Leadless semiconductor package and manufacturing method

Abstract

The present disclosure relates to a leadless packaged semiconductor device comprising opposing top and bottom major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further comprising: a leadframe structure comprising an array of two or more leadframe substructures each having a semiconductor die disposed thereon; terminals; and rails extending across the bottom surface of the semiconductor device, wherein the rails provide an area for interconnecting the semiconductor die and the terminals, wherein the rails are filled with an insulating material to isolate the leadframe substructures.

Description

Technical Field

[0001] The present invention relates to a method for forming a leadless packaged semiconductor device. The present invention also relates to a leadless packaged semiconductor device. Background Art

[0002] Leadless packaged semiconductor devices are known to offer advantages over leaded packages. These advantages include better electrical performance in terms of reduced lead inductance; improved heat dissipation to the printed circuit board (PCB) through the use of exposed thermal pads; reduced package thickness; and a smaller footprint that reduces the area occupied on the PCB. Examples of leadless packaged semiconductor devices include quad flat no-lead (QFN) devices and dual flat no-lead (DFN) devices. However, a disadvantage of leadless packaged semiconductor devices is that solder joint inspection is difficult when mounted on a PCB. Conventional inspection techniques utilize so-called automated optical inspection (AOI) systems, whereby a camera scans leadless packaged semiconductor devices mounted on a PCB for various defects such as open connections, shorts, thinning of solder connections, and misplaced devices. Because the input / output (I / O) terminals of semiconductor devices are arranged on the bottom of the device and are therefore hidden from view when the device is mounted on a PCB, AOI systems are generally not suitable for use with leadless semiconductor devices. Automated X-ray Inspection (AXI) systems may allow inspection of solder joints, however, AXI systems are expensive.

[0003] A solution that allows solder joints to pass AOI inspection includes metal side pads that extend at least partially upward from the device's I / O terminals on the bottom of the device to the device's outer sidewalls. Typically, the metal side pads can be formed from tin, lead, or a tin-lead alloy. During the soldering process of attaching the device to the PCB, the solder will wet the I / O terminals on the bottom of the device as well as the metal side pads. As a result, a portion of the solder joint will be visible, allowing inspection using AOI techniques. As long as the metal side pads are properly soldered, the solder joint can be considered good even if the I / O terminals are not properly soldered to the PCB.

[0004] In addition to facilitating inspection, the metal side pads reduce device tilt when mounted on the PCB and also improve shear and bending performance due to the increased soldering area.

[0005] Typically, the package structure will include an array of device wafers embedded in a packaging layer. The device wafers will be connected to a lead frame by any suitable means such as eutectic bonding. The process of forming such a leadless device involves separating the two-dimensional array of packaged integrated circuits into individual semiconductor device packages using a series of parallel row cuts and parallel column cuts. The first series of parallel separation cuts extend completely through the lead frame and packaging layer defining the rows of the array. In this process, the I / O terminals will be exposed, and since the I / O terminals are electrically connected to each other, the exposed I / O terminals can be electroplated to form metal side pads. It is necessary for the electrical connections to maintain electrical continuity so that the electroplating process can be implemented.

[0006] After plating the metal side pads, a second series of parallel separation cuts are made extending completely through the lead frame and package layers. This separates the columns of the array, providing singulated packages.

[0007] However, for a leadless semiconductor device having one or more functional chips and at least three I / O terminals positioned at one sidewall of the device and at least two I / O terminals positioned at an opposite sidewall, it is impossible to form side pads by electroplating according to the above process because the separation cutting process requires that the middle I / O terminals positioned at one sidewall of the device on a leadframe structure formed on a leadframe be electrically isolated.

[0008] FIG. 1 a shows a typical leadframe structure 10 formed from a series of leadframe substructures.

[0009] Prior to the first singulation cut process for defining the rows, as discussed above, the six I / O terminals 12, 14, and 16 for a particular device leadframe (three I / O terminals on two opposing sides of the device) are electrically interconnected because each of them will typically be formed from a single metal monolith by a photoetching process on a metal plate. Referring now to FIG. 1 b, after the first cut process (indicated by line A), the I / O terminals 12, 14 will be detached from the leadframe structure 10, and therefore it will not be possible to electroplate the I / O terminals 12, 14 to form metal side pads because they will be mechanically detached from the leadframe structure and electrically isolated from the leadframe structure.

[0010] After a second cutting process (indicated by line B) that is substantially orthogonal to the first cutting process, each individual sub-leadframe will be singulated from the leadframe structure 10 .

[0011] A disadvantage of the leadless packaged semiconductor device as described above is that it is limited to a maximum of four terminals having metal side pads. Summary of the Invention

[0012] Various exemplary embodiments address the disadvantages described above and / or other disadvantages that may become apparent from the following disclosure.

[0013] According to an embodiment of the present invention, a leadless packaged semiconductor device includes a top main surface and a bottom main surface relative to each other and a sidewall extending between the top surface and the bottom surface. It also includes a leadframe structure, which includes an array of two or more leadframe substructures, each of which has a semiconductor chip arranged thereon. In addition, the leadless packaged semiconductor device includes terminals and a track extending across the bottom surface of the semiconductor device. The track provides an area for interconnecting the semiconductor chip and the terminal during manufacturing. The track is filled with an insulating material to isolate the leadframe substructures.

[0014] According to an embodiment of the present invention, each of the terminals includes a respective metal side pad.

[0015] According to an embodiment of the present invention, a leadless packaged semiconductor device may include four or more terminals.

[0016] According to an embodiment of the invention, the insulating material is a solder mask or an encapsulant.

[0017] According to an embodiment of the present invention, a semiconductor die and corresponding terminals may be mechanically and electrically connected.

[0018] According to an embodiment of the present invention, the terminals are plated using a plating material such as tin, lead, or a tin-lead compound.

[0019] The invention also relates to an automotive component comprising a leadless packaged semiconductor device as specified in one of the preceding embodiments. This is particularly useful due to the use of AOI systems in the automotive industry.

[0020] One embodiment of the present invention relates to a method for forming a leadless packaged semiconductor device, the device comprising a leadframe structure including an array of leadframe substructures, each leadframe substructure having a semiconductor die disposed thereon. The method comprises the following steps:

[0021] electrical connections provided between terminals of the leadframe substructure and terminals of the leadframe structure;

[0022] providing an encapsulation layer to encapsulate the leadframe substructure and the individual semiconductor dies;

[0023] performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose side portions forming terminals;

[0024] Plating the terminals to form metal side pads;

[0025] forming a series of trenches in a leadframe structure, wherein the trenches extend across a bottom surface of a leadless packaged semiconductor device;

[0026] filling the trench with an insulating material; and

[0027] A second series of parallel cuts is performed at an angle relative to the first series of parallel cuts, the second series of parallel cuts extending through the leadframe structure and the package layer to singulate the leadless packaged semiconductor devices.

[0028] In another embodiment of the present invention, the method may further comprise a deburring step to remove any remaining encapsulation layer from the terminals. This deburring step is performed before the electroplating step. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order that the manner in which the features of the present disclosure may be understood in detail, a more particular description will be given with reference to some of the embodiments thereof illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments and are therefore not to be considered limiting of the scope thereof. The accompanying drawings are provided to facilitate understanding of the present disclosure and are not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art upon reading this specification in conjunction with the accompanying drawings, in which like reference numerals have been used to denote like elements, and in which:

[0030] FIG1a shows a known lead frame structure;

[0031] FIG1 b shows a known lead frame structure indicating the locations of the separation cuts;

[0032] Figure 2 shows a lead frame structure according to an embodiment;

[0033] Figure 3 shows a process flow chart for forming a leadless semiconductor device according to an embodiment;

[0034] Figures 4a to 4e shows process flow steps for forming a leadless semiconductor device according to an embodiment;

[0035] Figure 5a shows a bottom view of a single device in a lead frame structure after a slotting process; and

[0036] Figure 5b Respective bottom-side and top-side views of a completed leadless packaged semiconductor device according to an embodiment are shown. DETAILED DESCRIPTION

[0037] In the drawings and the following description, like reference numerals denote like features. Figure 2 , a leadframe structure 20, referred to as a unit structure, according to an embodiment is shown. The leadframe structure 20 is formed of a two-dimensional (2D) array of interconnected substructures, each of which constitutes a single leadframe 22, 28 for a semiconductor device of a leadless package when singulated. In this example, each leadframe includes two sets of three I / O terminals 25, however, those skilled in the art will understand that the number of I / O terminals can vary as required by the package type. Each of the leadframes 22, 28 also includes at least two die attach areas 27, the semiconductor device die ( Figure 2 A device wafer (not shown) can be attached to each of at least two die attach areas 27, as discussed below. Two sets of I / O terminals are associated with each of the die attach areas 27, allowing for appropriate connections to be made to the device wafer. Applications requiring two dies include dual transistor arrangements, such as cascode transistors or dual diodes.

[0038] The wafer attach area 27 is integrally connected to each of the I / O terminals 25, however, the wafer attach area 27 is configured and arranged to be disconnected from the I / O terminals 25 after the separation process, as discussed below. Before separation, each of the I / O terminals 25 is connected to the wafer by, for example, a tie bar.

[0039] The leadframe structure 20 is integrally connected to each die attach area 27 by means of a plurality of lead wires 29. As discussed below, the tie bars 29 connecting the die attach area 27 to the I / O terminals 25 are arranged to be cut or broken off during the separation process. The I / O terminals 25 are arranged so that they are formed along two parallel axes (referred to as lead side axes) to define an array or row in the leadframe 22, 28. The leadframe structure 20 is typically formed by a photolithographic process from a metal copper alloy plate coated with palladium gold.

[0040] Figure 3 A process flow chart for manufacturing a leadless packaged semiconductor device according to an embodiment is shown. Figures 4a to 4e Shown is the corresponding Figure 3 The process steps of the process flow. Figure 3 The process and Figures 4a to 4e In the process flow, after forming the lead frame structure 20 as discussed above, the device wafer 40 is attached to the wafer attachment area 27 ( Figure 2 ). Device wafer 40 can be attached to wafer attach area 27 by any suitable means, such as eutectic bonding 43 or adhesive 43 between wafer attach area 27 and the backside metallization of device wafer 40. In this manner, device wafer 40 is mechanically and electrically connected to various I / O terminals 25.

[0041] Also refer to Figure 4a After the wafer bonding step 30, the wire bonding member 41 is Figure 3 The wire bonding process step 32 connects the contacts of the device wafer 40 to the respective lead frames 22, 28 ( Figure 2 The wire bonding process may be any suitable wire bonding process using gold, copper, aluminum or silver wires or using metal clip bonding.

[0042] like Figure 4b As shown in , after line bonding, using Figure 3 The molding step 34 encapsulates the array of lead frames 22, 28 and the device wafer 40 in a molding compound 42. The encapsulation defines a first set of opposing sidewalls of the leadless packaged semiconductor device. The packaging process can be any suitable semiconductor packaging process as understood by those skilled in the art.

[0043] After packaging, use Figure 3 The chopper cutting step 35 performs a first series of parallel cuts in the lead frame structure 20, such as Figure 4b As shown in . Figure 2 A series of parallel cuts are separation cuts that are made along a horizontal or X-axis path (XX) along the line of I / O terminals 25 to define individual rows of lead frames 22, 28. These first separation cuts leave the lead frames in a row of lead frames 22, 28 electrically and mechanically connected. Because each row of lead frames is electrically connected, it is possible to utilize a separate wire for each of the individual lead frames that make up the row, as discussed below. Figure 3 The electroplating step 36 is for the I / O terminals 25 (such as Figure 2 Each of the metal side pads is electroplated.

[0044] The separation cut also removes the I / O terminals 25 (eg Figure 2 ) near the package, so that they can take advantage of Figure 3 The electroplating step 36 is to perform electroplating to form Figure 4c The metal side pads 44 shown in FIG. The electroplating can be achieved by any suitable process as understood by those skilled in the art. Typically, the metal side pads 44 will be plated using a plating material such as tin or alternatively lead or a tin-lead compound. Additionally, in this manner, the electroplating ( Figure 5a and Figure 5bAs will be appreciated by those skilled in the art, this electroplating step will also result in the bottom surface of the leadframe structure 20 being plated, such that the plating material will extend across the bottom surface between the I / O terminals 25. To ensure electrical isolation of the I / O terminals 25, such that there is no electrical continuity between the individual I / O terminals in the final device, the plating material and tie bars 29 should be severed.

[0045] Cut the plating material and tie rod 29 through Figure 3 The slotting step 37 is implemented so that Figure 4d As shown on the left side of FIG, one of the I / O terminals 25 is severed from the die attach area 27 by cutting through the leadframe 20 material to form a first trench 46 extending through the encapsulation material 42.

[0046] This slotting step makes use of the typical half-etched features in the tie bar 29 material. This is a common industrial design to reduce the workload of the sawing process. However, it is also possible not to perform the half-etch, but in that case, the sawing process must be cut deep into the package to completely remove the metal connection.

[0047] Optionally, another slotting step may be used to form a slot that partially passes through the tie rod 29a ( Figure 5a ) material, wherein the trench is formed in the wafer attachment area 27 ( Figure 2 Neutralization Figure 5a shown in ) and Figure 4d Between the second I / O terminals on the right side of the . An alternative design of tie bar 29 to tie bar 29a and may also be designed with or without half-etched features. Figure 5a In the exemplary embodiment shown in FIG, the tie rod 29 is completely cut off by the groove 46, so that Figure 5a is no longer visible and in this way, terminal 25 is isolated. Figure 5a The tie bars 29a in the circuit are partially cut, and the connection terminals 25a and the die pad 27 are kept.

[0048] Some metal side pads 44 (also called terminals, for example, in the two chip package examples) Figure 5a The terminal 25a) in can be connected to the chip attachment area, so that one bonding wire can be saved. Figure 4d Not all terminals on the right side are connected to the wafer attach area. Therefore, groove 48 (such as Figure 4d ) it is still necessary to isolate these terminals from the die attach pad.

[0049] In such Figure 3 After the trenching process of step 37 shown in FIG, the first trench 46 and the second trench 48 are then formed using the method shown in FIG. Figure 4eThe insulating material track 49 shown in FIG is backfilled using the backfill process step 38. The insulating material fills the trenches 46, 48 to cover the lead frame material exposed as a result of the slotting process. The exposed lead frame metal will appear stained due to the slotting, which will shorten the gap between the two exposed metals. There is a risk of creepage, especially in highly polluted environments in end-user applications. The backfill process step 38 ensures that the backfill covers the exposed metal to prevent such application problems. Figure 4e As shown in FIG, the insulating material track 49 extends across the width of the semiconductor device and never includes the I / O terminals 25 (e.g., Figure 2 The first side wall (shown in FIG) is substantially parallel to the second side wall not including the I / O terminal.

[0050] like Figure 3 As shown in FIG, in the process step final cutting 39, a final separation cut is performed to separate the semiconductor device from the lead frames 22, 28 (eg, Figure 2 The final separation cut is made orthogonal to the first horizontal separation cut. Figure 5b This final singulation cut produces the final leadless packaged semiconductor device 50 as shown in FIG.

[0051] Figure 5b Respective bottom and top side views of the completed leadless packaged semiconductor device are shown. Figure 5b A perspective bottom view of a completed leadless semiconductor device according to an embodiment is shown. Metal side pads 44 extend from each I / O terminal 25 (e.g., Figure 2 As will be appreciated by those skilled in the art, metal side pads (shown in FIG. Figure 5b The view in is obscured) is also provided on opposite side walls of the device. Figure 5b Also shown are trenches 46, 48 formed along the width of the bottom side of the semiconductor device (e.g., Figure 5a Insulating material 49 in FIG.

[0052] although Figure 5b A two die package is shown, but all embodiments of the present invention also apply to single die packages and / or packages with more than 2 dies that are common to any logic device.

[0053] Additional processing steps may include deburring to remove any potting compound from the I / O terminals, which can be performed before plating the metal side pads. After singulation, other cleaning steps can be used to remove material from the final device. A final visual inspection may also be performed.

[0054] Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent claims and / or independent claims may be combined as appropriate and not just as set out in the claims.

[0055] The scope of the present disclosure includes any novel feature or combination of features disclosed therein, whether explicitly or implicitly, or any generalization thereof, whether or not it relates to the claimed invention or alleviates any or all of the problems solved by the invention. The applicants hereby give notice that new claims may be formulated to such features during the prosecution of the present application or of any such further application derived therefrom. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from separate independent claims may be combined in any suitable manner and not merely in the specific combinations recited in the claims.

[0056] Features that are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination.

[0057] The term "comprising" does not exclude other elements or steps, and the term "a" or "an" does not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A method of forming a leadless packaged semiconductor device, the leadless packaged semiconductor device comprising a leadframe structure, the leadframe structure comprising an array of leadframe substructures, each leadframe substructure having a semiconductor die disposed thereon, the method comprising the steps of: electrical connections provided between terminals of the leadframe substructure and terminals of the leadframe structure; providing an encapsulation layer to encapsulate the lead frame substructure and each semiconductor die; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose side portions forming terminals; electroplating the terminals to form metal side pads; forming a trench in the leadframe structure, wherein the trench extends across a bottom surface of the leadless packaged semiconductor device; filling the trench with an insulating material; and A second series of parallel cuts is performed at an angle relative to the first series of parallel cuts, the second series of parallel cuts extending through the leadframe structure and the packaging layer to singulate the leadless packaged semiconductor devices.

2. The method for forming a leadless packaged semiconductor device according to claim 1, wherein: The method further comprises a deburring step to remove any remaining encapsulation layer from the terminals, wherein the deburring step is performed before the electroplating step.

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