Memory device and method of operating the same

Abstract

Embodiments of the present disclosure relate to memory devices and methods of operating the same. A memory device and a method of operating the same may be provided herein. The memory device may include: a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of programming states, and a control logic configured to control the peripheral circuit so that programming operations corresponding to the plurality of programming states are performed, wherein the control logic controls the peripheral circuit so that during a programming operation for a target programming state among the plurality of programming states, a memory cell to be programmed to a programming state immediately higher than the target programming state is programmed to the target programming state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2020-0032787, filed on Mar. 17, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to an electronic device, and more particularly, to a memory device and a method of operating a memory device. Background Art

[0004] Recently, the paradigm of computer environment has transitioned to ubiquitous computing, which enables computer systems to be used at any time and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras and notebook computers has increased rapidly. Typically, such portable electronic devices use a memory system that uses a memory device, in other words, a data storage device. The data storage device is used as a primary memory device or a secondary memory device of the portable electronic device.

[0005] Since there are no mechanical driving parts, data storage devices using memory devices provide advantages such as improved stability and durability, higher information access speed, and low power consumption. As examples of memory systems having such advantages, data storage devices include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSDs).

[0006] Memory devices may be classified into volatile memory devices and nonvolatile memory devices.

[0007] A nonvolatile memory device has a relatively low write and read speed, but retains the data stored therein even when the power supply is interrupted. Therefore, a nonvolatile memory device is used to store data to be retained regardless of whether the power supply is supplied. Representative examples of nonvolatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified into NOR type and NAND type. Summary of the invention

[0008] Various embodiments of the present disclosure are directed to a memory device and a method of operating the memory device, which may improve a range of threshold voltage distribution of memory cells during a program operation of the memory device.

[0009] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of programming states, and a control logic configured to control the peripheral circuit so that programming operations corresponding to the plurality of programming states are performed, wherein the control logic controls the peripheral circuit so that during a programming operation for a target programming state among the plurality of programming states, a memory cell to be programmed to a programming state immediately higher than the target programming state is programmed to the target programming state.

[0010] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of programming states, and a control logic configured to control the peripheral circuit so that programming operations corresponding to the plurality of programming states are performed, wherein the control logic controls the peripheral circuit so that during a programming operation for a target programming state among the plurality of programming states, a memory cell to be programmed to a programming state higher than the target programming state is programmed to a pre-programmed state.

[0011] Embodiments of the present disclosure may provide a method for operating a memory device. The method may include: programming a first memory cell to be programmed to a target programming state among a plurality of memory cells; and programming a second memory cell to be programmed to a programming state immediately higher than the target programming state among the plurality of memory cells to the target programming state. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 It's a picture. Figure 1 Schematic diagram of a memory device.

[0014] Figure 3 It's a picture. Figure 2 Schematic diagram of the memory block.

[0015] Figure 4 is a diagram illustrating an example of a memory block having a 3D structure.

[0016] Figure 5 A threshold voltage distribution graph used to describe the programmed state of a programmed memory cell.

[0017] Figure 6 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0018] Figure 7 is a threshold voltage distribution diagram of memory cells for describing a program operation for a first program state.

[0019] Figure 8 is a threshold voltage distribution diagram of memory cells for describing a program operation for a second program state.

[0020] Fig. 9 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0021] Fig.10 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0022] Fig.11 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0023] Fig.12 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0024] Fig.13 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0025] Fig.14 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0026] Fig.15 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0027] Fig.16 is a schematic diagram illustrating an embodiment of a memory system.

[0028] Fig.17 is a schematic diagram illustrating an embodiment of a memory system.

[0029] Fig.18 is a schematic diagram illustrating an embodiment of a memory system.

[0030] Fig.19 is a schematic diagram illustrating an embodiment of a memory system. DETAILED DESCRIPTION

[0031] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are merely examples for describing the embodiments of the present disclosure. Various embodiments of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0032] Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings so that those skilled in the art can easily practice the technical spirit of the present disclosure.

[0033] Figure 1 is a schematic diagram illustrating a memory system according to an embodiment.

[0034] Reference Figure 1 , the memory system 1000 may include a memory device 1100 storing data, and a memory controller 1200 controlling the memory device 1100 under the control of a host 2000 .

[0035] The host 2000 can communicate with the memory system 1000 using an interface protocol, such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). In addition, the interface protocol between the host 2000 and the memory system 1000 is not limited to the above examples, and may be one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0036] The memory controller 1200 may control the overall operation of the memory system 1000, and may control data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 may program or read data by controlling the memory device 1100 in response to a request received from the host 2000. During a program operation, the memory controller 1200 may transmit a command CMD, an address ADD, and data DATA to be programmed corresponding to the program operation to the memory device 1100. Further, during a read operation, the memory controller 1200 may receive data DATA read from the memory device 1100, may temporarily store the data DATA, and may transmit the temporarily stored data DATA to the host 2000.

[0037] The memory device 1100 may perform a program operation, a read operation, or an erase operation under the control of the memory controller 1200 .

[0038] In an embodiment, the memory device 1100 may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus DRAM (RDRAM), or a flash memory.

[0039] During a programming operation, the memory device 1100 according to an embodiment of the present disclosure may perform programming operations corresponding to a plurality of programming states in sequence. During a programming operation for a target programming state, the memory device 1100 may program a memory cell to be programmed to a programming state that is immediately higher than the target programming state to the target programming state, and may program a memory cell to be programmed to a further higher programming state to a pre-programmed state or pre-state. The pre-programmed state may be a programming state that is adjacent to and higher than the target programming state.

[0040] Figure 2 It's a picture. Figure 1 Schematic diagram of a memory device.

[0041] Reference Figure 2 , the memory device 1100 may include a memory cell array 100 storing data. The memory device 1100 may include a peripheral circuit 200 configured to perform a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 may include a control logic 300, which in a memory controller (e.g., Figure 1 The peripheral circuit 200 is controlled under the control of 1200).

[0042] The memory cell array 100 may include a plurality of memory blocks MB1 to MBk 110 (where k is a positive integer). A local line LL and a bit line BL1 to BLm (where m is a positive integer) may be coupled to each of the memory blocks MB1 to MBk 110. For example, the local line LL may include a first selection line, a second selection line, and a plurality of word lines arranged between the first and second selection lines. Moreover, the local line LL may include a virtual line arranged between the first selection line and the word line and between the second selection line and the word line. Here, the first selection line may be a source selection line, and the second selection line may be a drain selection line. For example, the local line LL may include a word line, a drain and source selection line, and a source line SL. For example, the local line LL may further include a virtual line. For example, the local line LL may further include a pipeline. The local line LL may be coupled to each of the memory blocks MB1 to MBk 110, and the bit lines BL1 to BLm may be commonly coupled to the memory blocks MB1 to MBk 110. The memory blocks MB1 to MBk 110 may each be implemented in a two-dimensional (2D) or three-dimensional (3D) structure. For example, the memory cells in the memory block 110 having a 2D structure may be arranged horizontally on a substrate. For example, the memory cells in the memory block 110 having a 3D structure may be stacked vertically on a substrate.

[0043] The peripheral circuit 200 may perform programming, reading, and erasing operations on the selected memory block 110 under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generating circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, a pass / fail check circuit 260, and a source line driver 270.

[0044] The voltage generating circuit 210 may generate various operating voltages Vop for programming, reading, and erasing operations in response to the operating signal OP_CMD. Further, the voltage generating circuit 210 may selectively discharge the local line LL in response to the operating signal OP_CMD. For example, the voltage generating circuit 210 may generate various voltages such as a programming voltage, a verification voltage, and a pass voltage under the control of the control logic 300.

[0045] The row decoder 220 may deliver the operation voltage Vop to the local line LL coupled to the selected memory block 110 in response to the row decoder control signal AD_signals. For example, during a programming operation, in response to the row decoder control signal AD_signals, the row decoder 220 may apply the program voltage generated by the voltage generating circuit 210 to a selected word line among the local lines LL, and may apply the pass voltage generated by the voltage generating circuit 210 to the remaining word lines, i.e., unselected word lines.

[0046] The page buffer group 230 may include a plurality of page buffers PB1 to PBm 231 coupled to the bit lines BL1 to BLm. The page buffers PB1 to PBm 231 may be operated in response to the page buffer control signal PBSIGNALS. For example, during a programming operation, the page buffers PB1 to PBm 231 may temporarily store data to be programmed, and may adjust the potential level of the bit lines BL1 to BLm based on the temporarily stored data to be programmed. In addition, during a read or program verification operation, the page buffers PB1 to PBm 231 may sense the voltage or current of the bit lines BL1 to BLm. The page buffers PB1 to PBm 231 may control the corresponding bit lines BL1 to BLm to a programming mode or a programming inhibit mode during a programming operation. Due to the programming voltage applied to the word line of the memory cell during the programming operation, the threshold voltage of the memory cell coupled to the bit line in the programming mode increases, and even if the programming voltage is applied to the word line of the memory cell during the programming operation, the threshold voltage of the memory cell coupled to the bit line in the programming inhibit mode does not increase. For example, page buffers PB1 to PBm 231 can control the potential levels of bit lines BL1 to BLm to the level of a programming permission voltage (e.g., a ground voltage) in a programming mode, and can control the potential levels of bit lines BL1 to BLm to a programming inhibition voltage (e.g., a power supply voltage) in a programming inhibition mode.

[0047] The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 may exchange data with the page buffer 231 through the data line DL, or may exchange data with the input / output circuit 250 through the column line CL.

[0048] The input / output circuit 250 can transfer the data from the memory controller (e.g., Figure 1 The input / output circuit 250 may transmit the command CMD and the address ADD received from the control logic 300 to the control logic 300, or may exchange the data DATA with the column decoder 240. The input / output circuit 250 may transmit the bad block information BB_info received from the control logic 300 to an external device (eg, Figure 1 Memory controller 1200).

[0049] During a read operation or a program verification operation, the pass / fail check circuit 260 may generate a reference current in response to the enable bit VRY_BIT<#>, and may compare the sensing voltage VPB received from the page buffer group 230 with the reference voltage generated by the reference current, and then output a pass signal PASS or a fail signal FAIL. The sensing voltage VPB may be a voltage controlled based on the number of memory cells determined to have passed the program verification operation.

[0050] The source line driver 270 may be coupled to the memory cells included in the memory cell array 100 through the source lines SL and may control a voltage to be applied to the source lines SL. The source line driver 270 may receive a source line control signal CTRL_SL from the control logic 300 and may control a source line voltage to be applied to the source lines SL in response to the source line control signal CTRL_SL.

[0051] The control logic 300 may control the peripheral circuit 200 by outputting an operation signal OP_CMD, a row decoder control signal AD_signals, a page buffer control signal PBSIGNALS, and an enable bit VRY_BIT<#> in response to a command CMD and an address ADD. The control logic 300 may control the peripheral circuit 200 so that programming operations corresponding to a plurality of programming states are sequentially executed during the programming operation. Moreover, the control logic 300 may control the peripheral circuit 200 so that during a programming operation for a target programming state, a memory cell to be programmed to a programming state immediately higher than the target programming state is programmed to the target programming state. Further, the control logic 300 may control the peripheral circuit 200 so that during a programming operation for a target programming state, a memory cell to be programmed to a programming state further higher than the programming state immediately higher is programmed to a pre-programmed state.

[0052] Figure 3 It's a picture. Figure 2 Schematic diagram of the memory block.

[0053] Reference Figure 3, a plurality of word lines arranged in parallel with each other between a first selection line and a second selection line may be coupled to the memory block 110. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. In an embodiment, the memory block 110 may include a plurality of strings ST coupled between the bit lines BL1 to BLm and the source line SL. The bit lines BL1 to BLm may be coupled to the strings ST, respectively, and the source line SL may be coupled to the string ST in common. The strings ST may be equally configured, and therefore, the string ST coupled to the first bit line BL1 will be described in detail by way of example.

[0054] The string ST may include a source selection transistor SST, a plurality of memory cells F1 to F16, and a drain selection transistor DST coupled to each other in series between a source line SL and a first bit line BL1. A single string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and more memory cells than the memory cells F1 to F16 illustrated in the drawings may be included in the string ST.

[0055] The source of the source select transistor SST may be coupled to the source line SL, and the drain of the drain select transistor DST may be coupled to the first bit line BL1. The memory cells F1 to F16 may be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be coupled to the source select line SSL, the gates of the drain select transistors DST included in different strings ST may be coupled to the drain select line DSL, and the gates of the memory cells F1 to F16 may be coupled to a plurality of word lines WL1 to WL16, respectively. A group of memory cells coupled to the same word line among the memory cells included in different strings ST may be referred to as a 'physical page (PPG)'. Therefore, the memory block 110 may include a plurality of physical pages PPGs the same as the number of word lines WL1 to WL16.

[0056] Figure 4 is a diagram illustrating an example of a memory block having a 3D structure.

[0057] Reference Figure 4 , the memory cell array 100 may include a plurality of memory blocks MB1 to MBk 110. Each memory block 110 may include a plurality of strings ST11 to ST1m and ST21 to ST2m. In an embodiment, each of the strings ST11 to ST1m and ST21 to ST2m may be formed in an 'I' shape or a 'U' shape. In the first memory block MB1, m strings may be arranged along a row direction (e.g., an X direction). Although in Figure 4In the embodiment, two strings are illustrated as being arranged along the column direction (eg, the Y direction), but this embodiment is given for ease of description, and in other embodiments three or more strings may be arranged along the column direction (eg, the Y direction).

[0058] Each of the strings ST11 to ST1m and ST21 to ST2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0059] The source select transistor SST of each string may be coupled between the source line SL and the memory cells MC1 to MCn. The source select transistors of the strings arranged in the same row may be coupled to the same source select line. The source select transistors of the strings ST11 to ST1m arranged in the first row may be coupled to the first source select line SSL1. The source select transistors of the strings ST21 to ST2m arranged in the second row may be coupled to the second source select line SSL2. In other embodiments, the source select transistors of the strings ST11 to ST1m and ST21 to ST2m may be commonly coupled to a single source select line.

[0060] The first to nth memory cells MC1 to MCn in each string may be coupled in series between source select transistors SST and drain select transistors DST. Gates of the first to nth memory cells MC1 to MCn may be coupled to first to nth word lines WL1 to WLn, respectively.

[0061] In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, a voltage or current of a corresponding string may be stably controlled. Therefore, the reliability of data stored in the memory block 110 may be improved.

[0062] The drain selection transistor DST of each string may be coupled between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors DST of the strings arranged along the row direction may be coupled to the drain selection lines extending along the row direction. The drain selection transistors DST of the strings ST11 to ST1m in the first row may be coupled to the first drain selection line DSL1. The drain selection transistors DST of the strings ST21 to ST2m in the second row may be coupled to the second drain selection line DSL2.

[0063] Figure 5 A threshold voltage distribution graph used to describe the programmed state of a programmed memory cell.

[0064] In an embodiment of the present disclosure, description will be made based on a triple-level cell (TLC) programming scheme, where the number of threshold voltage distributions of memory cells is eight (eg, PV0 to PV7 ) by way of example.

[0065] Reference Figure 5 During a program operation, each memory cell may be programmed to any one of an erase state PV0 and a plurality of program states PV1 to PV7. Before performing a program operation, memory cells included in a memory block may have a threshold voltage corresponding to the erase state PV0.

[0066] During the programming operation, the programming operation may be sequentially performed on the memory cells in the erase state PV0 starting from the programming state with the low threshold voltage distribution among the plurality of programming states PV1 to PV7. For example, the programming operation for the first programming state PV1, the programming operation for the second programming state PV2, the programming operation for the third programming state PV3, ..., the programming operation for the seventh programming state PV7 may be sequentially performed.

[0067] During a program operation, a selected program state is defined as a target program state, and a program state adjacent to the target program state and higher than the target program state is defined as a pre-program state.

[0068] For example, during a program operation for a first program state PV1, the target program state may be the first program state PV1, and the pre-program state may be the second program state PV2.

[0069] Figure 6 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0070] Will refer to Figures 1 to 6 A method of operating a memory device according to an embodiment of the present disclosure is described.

[0071] When receiving a request corresponding to a program operation from the host 2000, the memory controller 1200 may generate a program command CMD in response to the request from the host 2000. The memory device 1100 may receive the program command CMD, an address ADD, and data DATA to be programmed from the memory controller 1200 in operation S610.

[0072] The memory device 1100 can select a memory block (e.g., MB1) on which a programming operation is to be performed from a plurality of memory blocks MB1 to MBk in response to a received programming command CMD and an address ADD, program the selected memory block (e.g., MB1) sequentially on a page basis, and perform a programming operation on a first programming state PV1 having a lowest threshold voltage distribution among a plurality of programming states PV1 to PV7 using an incremental step pulse programming (ISPP) scheme during the programming operation on the selected page in operation S620.

[0073] The page buffer group 230 may temporarily store data to be programmed in response to a page buffer control signal PBSIGNALS generated by the control logic 300, and may adjust the potential levels of the bit lines BL1 to BLm based on the temporarily stored data to be programmed. For example, a program permission voltage may be applied to a bit line corresponding to a page buffer in which a plurality of data corresponding to the first to seventh program states PV1 to PV7 are temporarily stored, and a program inhibition voltage may be applied to a bit line corresponding to a page buffer in which a plurality of data corresponding to the erase state PV0 is temporarily stored.

[0074] The voltage generating circuit 210 may generate a program voltage and a pass voltage in response to the operation signal OP_CMD. The row decoder 220 may apply the program voltage generated by the voltage generating circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to the row decoder control signal AD_signals, and may apply the pass voltage generated by the voltage generating circuit 20 to the remaining word lines.

[0075] Thereafter, in operation S630, the peripheral circuit 200 may check whether the memory cells to be programmed to the first programming state PV1 have been normally programmed by performing a program verification operation for the first programming state PV1. In this case, the peripheral circuit 200 may check whether the memory cells to be programmed to the immediately higher programming state PV2 than the first programming state PV1 have been programmed to the first programming state PV1, and may check the memory cells to be programmed to the immediately higher programming state PV2 among the memory cells to be programmed to the further higher programming states PV3 to PV7.

[0076] For example, the peripheral circuit 200 may sequentially perform a program verification operation for the first program state PV1 and a program verification operation for a pre-program state, which is an operation of verifying memory cells to be programmed to further higher program states PV3 to PV7 .

[0077] During a program verification operation for a first program state PV1, the voltage generation circuit 210 may generate a first verification voltage and a pass voltage corresponding to the first program state PV1 in response to an operation signal OP_CMD. The row decoder 220 may apply the first verification voltage generated by the voltage generation circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to a row decoder control signal AD_signals, and may apply a pass voltage generated by the voltage generation circuit 20 to the remaining word lines. Further, during the program verification operation, the page buffers PB1 to PBm 231 may sense a voltage or current of the bit lines BL1 to BLm, and may then check whether a memory cell to be programmed to the first program state PV1 and a memory cell to be programmed to the second program state PV2 corresponding to an immediately higher program state have been programmed to the first program state PV1.

[0078] During a program verification operation for a pre-programmed state, the voltage generating circuit 210 may generate a second verification voltage and a pass voltage corresponding to an immediately higher program state PV2 in response to an operation signal OP_CMD. The row decoder 220 may apply the second verification voltage generated by the voltage generating circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to a row decoder control signal AD_signals, and may apply a pass voltage generated by the voltage generating circuit 20 to the remaining word lines. Further, during a program verification operation, the page buffers PB1 to PBm 231 may sense a voltage or current of the bit lines BL1 to BLm, and then check memory cells that have been programmed to an immediately higher program state PV2 among the memory cells to be programmed to the third to seventh program states PV3 to PV7.

[0079] In the above operation S630, when the threshold voltages of some of the memory cells to be programmed to the first programming state PV1 have not reached the first programming state PV1, or when the threshold voltages of some of the memory cells to be programmed to the second programming state PV2 have not reached the first programming state PV1 (failure), the control logic 300 may reset the programming voltage by increasing the programming voltage by a step voltage in operation S640, and the operation may be re-executed from the above operation S620. When re-executing operation S620, a program inhibition voltage may be applied to the bit lines BL1 to BLm corresponding to the memory cells determined to have passed the program verification operation for the first programming state PV1 and the program verification operation for the pre-programming state. Moreover, a program permission voltage may be applied to the bit lines BL1 to BLm corresponding to the memory cells determined to have failed the program verification operation for the first programming state PV1 and the program verification operation for the pre-programming state.

[0080] In the above operation S630, when the threshold voltage of the memory cell to be programmed to the first programming state PV1 and the second programming state PV2 has reached the first programming state PV1 (pass), the control logic 300 can determine in operation S650 whether the programming operation currently being performed is a programming operation for the last programming state PV7.

[0081] When it is determined in operation S650 that the currently executed program operation is not a program operation for the last program state PV7 (in the case of "No"), a program operation for an immediately higher program state is performed in operation S660. For example, when the above program operation is a program operation for the first program state PV1, a program operation for the second program state PV2 may be performed.

[0082] The page buffer group 230 may adjust the potential levels of the bit lines BL1 to BLm based on data to be programmed, which is temporarily stored in response to the page buffer control signal PBSIGNALS generated by the control logic 300. For example, a program permission voltage may be applied to a bit line corresponding to a page buffer temporarily storing a plurality of data corresponding to the second to seventh program states PV2 to PV7, and a program inhibition voltage may be applied to a bit line corresponding to a page buffer temporarily storing a plurality of data corresponding to the erase state PV0 and the first program state PV1.

[0083] The voltage generating circuit 210 may generate a program voltage and a pass voltage in response to the operation signal OP_CMD. The row decoder 220 may apply the program voltage generated by the voltage generating circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to the row decoder control signal AD_signals, and may apply the pass voltage generated by the voltage generating circuit 20 to the remaining word lines.

[0084] Thereafter, in operation S670, the peripheral circuit 200 may check whether the memory cells to be programmed to the second programming state PV2 have been normally programmed by performing a program verification operation for the second programming state PV2. In this case, the peripheral circuit 200 may check whether the memory cells to be programmed to the programming state PV3 that is immediately higher than the second programming state PV2 have been programmed to the second programming state PV2, and may check the memory cells that have been programmed to the immediately higher programming state PV3 among the memory cells to be programmed to the further higher programming states PV4 to PV7. For example, the peripheral circuit 200 may sequentially perform a program verification operation for the second programming state PV2 and a program verification operation for the pre-programmed state, which is a verification operation for the further higher programming states PV4 to PV7.

[0085] During a program verification operation for a second program state PV2, the voltage generation circuit 210 may generate a second verification voltage and a pass voltage corresponding to the second program state PV2 in response to the operation signal OP_CMD. The row decoder 220 may apply the second verification voltage generated by the voltage generation circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to the row decoder control signal AD_signals, and may apply the pass voltage generated by the voltage generation circuit 20 to the remaining word lines. Further, during the program verification operation, the page buffers PB1 to PBm 231 may sense the voltage or current of the bit lines BL1 to BLm, and then check whether the memory cells to be programmed to the second program state PV2 and the memory cells to be programmed to the immediately higher program state PV3 have been programmed to the second program state PV2.

[0086] During a program verification operation for a pre-programmed state, the voltage generating circuit 210 may generate a third verification voltage and a pass voltage corresponding to an immediately higher program state PV3 in response to the operation signal OP_CMD. The row decoder 220 may apply the third verification voltage generated by the voltage generating circuit 210 to a word line corresponding to a selected page among a plurality of word lines of a selected memory block (e.g., MB1) in response to the row decoder control signal AD_signals, and may apply the pass voltage generated by the voltage generating circuit 20 to the remaining word lines. Further, during a program verification operation, the page buffers PB1 to PBm 231 may sense a voltage or current of the bit lines BL1 to BLm, and then check the memory cells that have been programmed to the program state PV3 among the memory cells to be programmed to the fourth to seventh program states PV4 to PV7.

[0087] When the threshold voltages of some of the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the immediately higher programming state PV3 in the above-mentioned operation S670 have not reached the second programming state PV2 (failed), the control logic 300 may reset the programming voltage by increasing the programming voltage by a step voltage in operation S680, and the operation may be re-executed from operation S660. When re-executed operation S660, a program inhibition voltage may be applied to the bit lines BL1 to BLm corresponding to the memory cells determined to have passed the program verification operation for the second programming state PV2 and the program verification operation for the pre-programmed state. Moreover, a program permission voltage may be applied to the bit lines BL1 to BLm corresponding to the memory cells determined to have failed the program verification operation for the second programming state PV2 and the program verification operation for the pre-programmed state.

[0088] In the above operation S670, when the threshold voltage of the memory cell to be programmed to the second programming state PV2 has reached the second programming state PV2, and the threshold voltage of the memory cell to be programmed to the adjacent higher programming state PV3 has reached the second programming state PV2 (pass), the control logic 300 can re-execute the operation starting from operation S650 of determining whether the programming operation currently being performed is a programming operation for the last programming state PV7.

[0089] The aforementioned operations S650 to S680 may be repeated until it is determined in the aforementioned operation S650 that the currently being performed programming operation is the final programming state PV7. That is, the programming operations for the second to seventh programming states PV2 to PV7 may be completed by repeating the aforementioned operations S650 to S680. Here, during the programming operation for the final programming state PV7, the programming operation for the pre-programming state and the verification operation for the pre-programming state are not performed.

[0090] When it is determined in operation S650 that the program operation currently being performed is the program operation for the last program state PV7 , the aforementioned operations S620 to S680 may be performed by selecting the next page of the selected memory block.

[0091] Figure 7 is a threshold voltage distribution diagram of memory cells for describing a program operation for a first program state.

[0092] The following will refer to Figure 7 Threshold voltage distributions of memory cells during a program operation for a first program state PV1 are described.

[0093] Reference Figure 7 , during a programming operation for a first programming state PV1, a target memory cell (target MC) including a memory cell to be programmed to the first programming state PV1 and a memory cell to be programmed to a programming state PV2 that is immediately higher than the first programming state PV1 may be programmed to have a threshold voltage distribution corresponding to the first programming state PV1. For example, during a programming voltage application operation, the threshold voltage distribution may be increased by applying a programming voltage to a word line of the target memory cell (target MC). During a programming verification operation, after the first verification voltage Vver1 has been applied to the word line of the target memory cell (target MC), the potential level of the bit line may be sensed, and thus it may be determined whether the programming verification operation has passed / failed. When it is determined that the programming verification operation has failed due to the programming verification operation, the programming operation may be performed in such a manner that a programming voltage with an increased step voltage is reapplied to the word line of the target memory cell (target MC). As a result, the target memory cell (target MC) may have a threshold voltage distribution corresponding to the first programming state PV1 that is higher than the first verification voltage Vver1.

[0094] During the programming operation for the first programming state PV1, the remaining memory cells (i.e., other MCs) intended to be programmed to the third to seventh programming states PV3 to PV7 may be programmed to a pre-programmed state (i.e., pre-state). The pre-programmed state (pre-state) may be a state in which the threshold voltage distribution is higher than the threshold voltage distribution in the first programming state PV1. For example, until the above-mentioned target memory cell (target MC) passes the programming verification operation, the programming operation may be performed on the remaining memory cells (other MCs), and the memory cells in the remaining memory cells (other MCs) whose threshold voltage distribution is higher than the second verification voltage Vver2 corresponding to the immediately higher programming state PV2 may be operated in the programming inhibit mode. As a result, while the target memory cell (target MC) is programmed to the first programming state PV1, the remaining memory cells (other MCs) may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distribution is higher than the threshold voltage distribution in the first programming state PV1.

[0095] Figure 8 is a threshold voltage distribution diagram of memory cells for describing a program operation for a second program state.

[0096] The following will refer to Figure 8 Threshold voltage distributions of memory cells during a program operation for a second program state PV2 are described.

[0097] With the above Figure 7 Similarly, after the program operation for the first program state PV1 is completed, the program operation for the second program state PV2 is performed.

[0098] Reference Figure 8, during a programming operation for a second programming state PV2, a target memory cell (target MC) including a memory cell to be programmed to the second programming state PV2 and a memory cell to be programmed to an immediately higher programming state PV3 can be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. For example, during a programming voltage application operation, the threshold voltage distribution can be increased by applying a programming voltage to a word line of the target memory cell (target MC). During a programming verification operation, after the second verification voltage Vver2 has been applied to the word line of the target memory cell (target MC), the potential level of the bit line can be sensed, so it can be determined whether the programming verification operation is passed / failed. When it is determined that the programming verification operation fails due to the programming verification operation, the programming operation can be performed in such a way that a programming voltage with an increased step voltage is reapplied to the word line of the target memory cell (target MC). As a result, the target memory cell (target MC) can have a threshold voltage distribution corresponding to the second programming state PV2, which is higher than the second verification voltage Vver2. During the program voltage applying operation, a program inhibit voltage may be applied to bit lines of memory cells corresponding to the erase state PV0 and memory cells that have been programmed to the first program state PV1, thereby preventing threshold voltages of the memory cells from increasing.

[0099] During the programming operation for the second programming state PV2, the remaining memory cells (i.e., other MCs) intended to be programmed to the fourth to seventh programming states PV4 to PV7 may be programmed to a pre-programmed state (i.e., pre-state). The pre-programmed state (pre-state) may be a state in which the threshold voltage distribution is higher than the threshold voltage distribution in the second programming state PV2. For example, until the above-mentioned target memory cell (target MC) passes the programming verification operation, the programming operation may be performed on the remaining memory cells (other MCs), and the memory cells in the remaining memory cells (other MCs) whose threshold voltage distribution is higher than the third verification voltage Vver3 corresponding to the immediately higher programming state PV3 may be operated in the programming inhibit mode. As a result, while the target memory cell (target MC) is programmed to the second programming state PV2, the remaining memory cells (other MCs) may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distribution is higher than the threshold voltage distribution in the second programming state PV2.

[0100] Based on reference Figure 7 and Figure 8The programming method described, during the respective programming operations corresponding to the first to sixth programming states PV1 to P6, the remaining memory cells (other MCs) other than the target memory cell (target MC) can be programmed to the pre-programmed state. Finally, during the programming operation for the seventh programming state PV7, only the memory cells intended to be programmed to the seventh programming state PV7 can be set as the target memory cells (target MCs), and then the programming operation can be performed on the target memory cells.

[0101] According to an embodiment of the present disclosure, before performing a programming operation for a target programming state, the threshold voltage distribution of the target memory cell can be increased to a threshold voltage range adjacent to the target programming state. Therefore, during the programming operation for the target programming state, the magnitude of the increased threshold voltage can be reduced, thereby improving the threshold voltage distribution.

[0102] Further, during the programming operation, programming operations for the first to seventh programming states are performed sequentially, and thus, the programming verification operation performed after the programming voltage application operation can be simplified from the verification operation for the first to seventh programming states to the verification operation for the target programming state and the verification operation for the pre-programming state.

[0103] Fig. 9 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0104] Reference Fig. 9 During a program operation for a first program state PV1, a memory cell to be programmed to the first program state PV1 and a memory cell to be programmed to a second program state PV2 adjacent to the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV1. That is, the bit lines corresponding to the memory cell to be programmed to the first program state PV1 and the memory cell to be programmed to the second program state PV2 may be controlled to be a program mode (PGM MODE) in which a program permission voltage is applied.

[0105] Here, until the programming operation of the memory cells to be programmed to the first programming state PV1 and the memory cells to be programmed to the second programming state PV2 is terminated, the memory cells to be programmed to the remaining programming states PV3 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the first programming state PV1. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltages in the second programming state PV2 among the memory cells to be programmed to the remaining programming states PV3 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltages in the second programming state PV2. That is, among the memory cells to be programmed to the remaining programming states PV3 to PV7, the memory cells whose threshold voltages are lower than the threshold voltages in the second programming state PV2 may be controlled to the programming mode (PGM MODE).

[0106] When the programming operation for the first programming state PV1 is completed, the programming operation for the second programming state PV2 is performed. During the programming operation for the second programming state PV2, the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 adjacent to the second programming state PV2 may be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. That is, the bit lines corresponding to the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0107] Here, until the programming operation of the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 is terminated, the memory cells to be programmed to the remaining programming states PV4 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the second programming state PV2. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltages in the third programming state PV3 among the memory cells to be programmed to the remaining programming states PV4 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltages in the third programming state PV3. That is, among the memory cells to be programmed to the remaining programming states PV4 to PV7, the memory cells whose threshold voltages are lower than the threshold voltages in the third programming state PV3 may be controlled to the programming mode (PGM MODE).

[0108] When the programming operation for the second programming state PV2 is completed, the programming operation for the third programming state PV3 is performed. During the programming operation for the third programming state PV3, the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 adjacent to the third programming state PV3 may be programmed to have a threshold voltage distribution corresponding to the third programming state PV3. That is, the bit lines corresponding to the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 and the memory cells that have been programmed to the second programming state PV2 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0109] Here, until the programming operation of the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 is terminated, the memory cells to be programmed to the remaining programming states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the third programming state PV3. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 among the memory cells to be programmed to the remaining programming states PV5 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fourth programming state PV4. That is, among the memory cells to be programmed to the remaining programming states PV5 to PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 may be controlled to the programming mode (PGM MODE).

[0110] When the programming operation for the third programming state PV3 is completed, the programming operation for the fourth programming state PV4 is performed. During the programming operation for the fourth programming state PV4, the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 adjacent to the fourth programming state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth programming state PV4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 may be controlled to a programming mode (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third programming states PV1 to PV3 may be controlled to a program inhibition mode (INHIBIT MODE) in which a program inhibition voltage is applied.

[0111] Here, until the programming operation of the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 is terminated, the memory cells to be programmed to the remaining programming states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the fourth programming state PV4. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fifth programming state PV5 among the memory cells to be programmed to the remaining programming states PV6 and PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fifth programming state PV5. That is, among the memory cells to be programmed to the remaining programming states PV6 and PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the fifth programming state PV5 may be controlled to the programming mode (PGM MODE).

[0112] When the programming operation for the fourth programming state PV4 is completed, the programming operation for the fifth programming state PV5 is performed. During the programming operation for the fifth programming state PV5, the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 adjacent to the fifth programming state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth programming state PV5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth programming states PV1 to PV4 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0113] Here, until the programming operation of the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 is terminated, the memory cells to be programmed to the remaining programming states PV7 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the fifth programming state PV5. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltages in the sixth programming state PV6 among the memory cells to be programmed to the remaining programming state PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltages in the sixth programming state PV6. That is, among the memory cells to be programmed to the remaining programming state PV7, the memory cells whose threshold voltages are lower than the threshold voltages in the sixth programming state PV6 may be controlled to the programming mode (PGM MODE).

[0114] When the programming operation for the fifth programming state PV5 is completed, the programming operation for the sixth programming state PV6 is performed. During the programming operation for the sixth programming state PV6, the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 adjacent to the sixth programming state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth programming state PV6. That is, the bit lines corresponding to the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth programming states PV1 to PV5 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0115] When the programming operation for the sixth programming state PV6 is completed, the programming operation for the seventh programming state PV7 is performed. During the programming operation for the seventh programming state PV7, the bit lines corresponding to the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM mode) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth programming states PV1 to PV6 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0116] Although in the above-mentioned embodiments of the present disclosure, the description has been made based on a three-level cell (TLC) programming scheme, in which, by way of example, the number of threshold voltage distributions for programming memory cells is eight (i.e., PV0 to PV7), the present embodiments can also be applied to a multi-level cell (MLC) programming scheme in which the number of threshold voltage distributions is four and a quad-level cell (QLC) programming scheme in which the number of threshold voltage distributions is 16.

[0117] Fig.10 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0118] Reference Fig.10 During the programming operation for the first programming state PV1, the memory cells to be programmed to the first programming state PV1 may be programmed to have a threshold voltage distribution corresponding to the first programming state PV1. That is, the bit lines corresponding to the memory cells to be programmed to the first programming state PV1 may be controlled to a programming mode (PGM MODE) in which a program permission voltage is applied.

[0119] Here, until the programming operation of the memory cell to be programmed to the first programming state PV1 is terminated, the memory cells to be programmed to the remaining programming states PV2 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the first programming state PV1. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltage is lower than the threshold voltage in the second programming state PV2 among the memory cells to be programmed to the remaining programming states PV2 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltage is equal to or higher than the threshold voltage in the second programming state PV2. That is, among the memory cells to be programmed to the remaining programming states PV2 to PV7, the memory cells whose threshold voltage is lower than the threshold voltage in the second programming state PV2 may be controlled to the programming mode (PGM MODE).

[0120] When the programming operation for the first programming state PV1 is terminated, the programming operation for the second programming state PV2 is performed. During the programming operation for the second programming state PV2, the memory cells to be programmed to the second programming state PV2 may be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. That is, the bit lines corresponding to the memory cells to be programmed to the second programming state PV2 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0121] Here, until the programming operation of the memory cell to be programmed to the second programming state PV2 is terminated, the memory cells to be programmed to the remaining programming states PV3 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the second programming state PV2. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltage is lower than the threshold voltage in the third programming state PV3 among the memory cells to be programmed to the remaining programming states PV3 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltage is equal to or higher than the threshold voltage in the third programming state PV3. That is, among the memory cells to be programmed to the remaining programming states PV3 to PV7, the memory cells whose threshold voltage is lower than the threshold voltage in the third programming state PV3 may be controlled to the programming mode (PGM MODE).

[0122] When the programming operation for the second programming state PV2 is terminated, a programming operation for the third programming state PV3 is performed. During the programming operation for the third programming state PV3, the memory cells to be programmed to the third programming state PV3 may be programmed to have a threshold voltage distribution corresponding to the third programming state PV3. That is, the bit lines corresponding to the memory cells to be programmed to the third programming state PV3 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 and the memory cells that have been programmed to the second programming state PV2 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0123] Here, until the programming operation of the memory cell to be programmed to the third programming state PV3 is terminated, the memory cells to be programmed to the remaining programming states PV4 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the third programming state PV3. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltage is lower than the threshold voltage in the fourth programming state PV4 among the memory cells to be programmed to the remaining programming states PV4 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltage is equal to or higher than the threshold voltage in the fourth programming state PV4. That is, among the memory cells to be programmed to the remaining programming states PV4 to PV7, the memory cells whose threshold voltage is lower than the threshold voltage in the fourth programming state PV4 may be controlled to the programming mode (PGM MODE).

[0124] When the programming operation for the third programming state PV3 is terminated, a programming operation for the fourth programming state PV4 is performed. During the programming operation for the fourth programming state PV4, the memory cells to be programmed to the fourth programming state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth programming state PV4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth programming state PV4 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third programming states PV1 to PV3 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0125] Here, until the programming operation of the memory cell to be programmed to the fourth programming state PV4 is terminated, the memory cells to be programmed to the remaining programming states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the fourth programming state PV4. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltage is lower than the threshold voltage in the fifth programming state PV5 among the memory cells to be programmed to the remaining programming states PV5 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltage is equal to or higher than the threshold voltage in the fifth programming state PV5. That is, among the memory cells to be programmed to the remaining programming states PV5 to PV7, the memory cells whose threshold voltage is lower than the threshold voltage in the fifth programming state PV5 may be controlled to the programming mode (PGM MODE).

[0126] When the programming operation for the fourth programming state PV4 is terminated, the programming operation for the fifth programming state PV5 is performed. During the programming operation for the fifth programming state PV5, the memory cells to be programmed to the fifth programming state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth programming state PV5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth programming state PV5 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth programming states PV1 to PV4 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0127] Here, until the programming operation of the memory cell to be programmed to the fifth programming state PV5 is terminated, the memory cells to be programmed to the remaining programming states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the fifth programming state PV5. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the sixth programming state PV6 among the memory cells to be programmed to the remaining programming states PV6 and PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the sixth programming state PV6. That is, among the memory cells to be programmed to the remaining programming states PV6 and PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the sixth programming state PV6 may be controlled to the programming mode (PGM MODE).

[0128] When the programming operation for the fifth programming state PV5 is terminated, the programming operation for the sixth programming state PV6 is performed. During the programming operation for the sixth programming state PV6, the memory cells to be programmed to the sixth programming state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth programming state PV6. That is, the bit lines corresponding to the memory cells to be programmed to the sixth programming state PV6 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth programming states PV1 to PV5 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0129] Here, until the programming operation of the memory cell to be programmed to the sixth programming state PV6 is terminated, the memory cell to be programmed to the remaining programming state PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the sixth programming state PV6. For example, a program permission voltage may be applied to the bit lines of the memory cells to be programmed to the remaining programming state PV7 whose threshold voltage is lower than the threshold voltage in the seventh programming state PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltage is equal to or higher than the threshold voltage in the seventh programming state PV7. That is, among the memory cells to be programmed to the remaining programming state PV7, the memory cells whose threshold voltage is lower than the threshold voltage in the seventh programming state PV7 may be controlled to the programming mode (PGMMODE).

[0130] When the programming operation for the sixth programming state PV6 is terminated, the programming operation for the seventh programming state PV7 is performed. During the programming operation for the seventh programming state PV7, the bit lines corresponding to the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM mode) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth programming states PV1 to PV6 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0131] Fig.11 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0132] Reference Fig.11 During a program operation for the first program state PV1, memory cells to be programmed to the first program state PV1, and memory cells to be programmed to the second and third program states PV2 and PV3 adjacent to the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV1. That is, the bit lines corresponding to the memory cells to be programmed to the first to third program states PV1 to PV3 may be controlled to a program mode (PGM MODE) in which a program permission voltage is applied.

[0133] Here, until the programming operation of the memory cells to be programmed to the first programming state PV1 to the third programming state PV3 is terminated, the memory cells to be programmed to the remaining programming states PV4 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the first programming state PV1. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltages in the second programming state PV2 among the memory cells to be programmed to the remaining programming states PV4 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltages in the second programming state PV2. That is, among the memory cells to be programmed to the remaining programming states PV4 to PV7, the memory cells whose threshold voltages are lower than the threshold voltages in the second programming state PV2 may be controlled to the programming mode (PGM MODE).

[0134] When the programming operation for the first programming state PV1 is completed, the programming operation for the second programming state PV2 is performed. During the programming operation for the second programming state PV2, the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third and fourth programming states PV3 and PV4 adjacent to the second programming state PV2 may be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. That is, the bit lines corresponding to the memory cells to be programmed to the second to fourth programming states PV2 to PV4 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0135] Here, until the programming operation of the memory cells to be programmed to the second to fourth programming states PV2 to PV4 is terminated, the memory cells to be programmed to the remaining programming states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the second programming state PV2. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 among the memory cells to be programmed to the remaining programming states PV5 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the third programming state PV3. That is, among the memory cells to be programmed to the remaining programming states PV5 to PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 may be controlled to the programming mode (PGM MODE).

[0136] When the programming operation for the second programming state PV2 is completed, the programming operation for the third programming state PV3 is performed. During the programming operation for the third programming state PV3, the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth and fifth programming states PV4 and PV5 adjacent to the third programming state PV3 may be programmed to have a threshold voltage distribution corresponding to the third programming state PV3. That is, the bit lines corresponding to the memory cells to be programmed to the third to fifth programming states PV3 to PV5 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 and the memory cells that have been programmed to the second programming state PV2 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0137] Here, until the programming operation of the memory cells to be programmed to the third to fifth programming states PV3 to PV5 is terminated, the memory cells to be programmed to the remaining programming states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the third programming state PV3. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 among the memory cells to be programmed to the remaining programming states PV6 and PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fourth programming state PV4. That is, among the memory cells to be programmed to the remaining programming states PV6 and PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 may be controlled to the programming mode (PGM MODE).

[0138] When the programming operation for the third programming state PV3 is completed, the programming operation for the fourth programming state PV4 is performed. During the programming operation for the fourth programming state PV4, the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth and sixth programming states PV5 and PV6 adjacent to the fourth programming state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth programming state PV4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth to sixth programming states PV4 to PV6 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third programming states PV1 to PV3 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0139] Here, until the programming operation of the memory cells to be programmed to the fourth programming state PV4 to the sixth programming state PV6 is terminated, the memory cells to be programmed to the remaining programming state PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the fourth programming state PV4. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltages in the fifth programming state PV5 among the memory cells to be programmed to the remaining programming state PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltages in the fifth programming state PV5. That is, among the memory cells to be programmed to the remaining programming state PV7, the memory cells whose threshold voltages are lower than the threshold voltages in the fifth programming state PV5 may be controlled to the programming mode (PGM MODE).

[0140] When the programming operation for the fourth programming state PV4 is completed, the programming operation for the fifth programming state PV5 is performed. During the programming operation for the fifth programming state PV5, the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth and seventh programming states PV6 and PV7 adjacent to the fifth programming state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth programming state PV5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth to seventh programming states PV5 to PV7 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth programming states PV1 to PV4 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0141] When the programming operation for the fifth programming state PV5 is completed, the programming operation for the sixth programming state PV6 is performed. During the programming operation for the sixth programming state PV6, the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 adjacent to the sixth programming state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth programming state PV6. That is, the bit lines corresponding to the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth programming states PV1 to PV5 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0142] When the programming operation for the sixth programming state PV6 is completed, the programming operation for the seventh programming state PV7 is performed. During the programming operation for the seventh programming state PV7, the bit lines corresponding to the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM mode) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth programming states PV1 to PV6 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0143] Fig.12 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0144] Reference Fig.12During the programming operation for the first programming state PV1, the memory cells to be programmed to the first programming state PV1 may be programmed to have a threshold voltage distribution corresponding to the first programming state PV1. That is, the bit lines corresponding to the memory cells to be programmed to the first programming state PV1 may be controlled to a programming mode (PGM MODE) in which a program permission voltage is applied.

[0145] Here, until the programming operation of the memory cell to be programmed to the first programming state PV1 is terminated, the memory cells to be programmed to the remaining programming states PV2 to PV7 may be programmed to a pre-programmed state higher than the first programming state PV1. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the second programming state PV2 among the memory cells to be programmed to the second programming state PV2 and the third programming state PV3 adjacent to the first programming state PV1, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the second programming state PV2. Further, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 among the memory cells to be programmed to the remaining programming states PV4 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the third programming state PV3.

[0146] That is, among the memory cells to be programmed into the second and third programming states PV2 and PV3, the memory cells having a threshold voltage lower than the threshold voltage in the second programming state PV2 can be controlled into the programming mode (PGM MODE). Moreover, among the memory cells to be programmed into the programming states PV4 to PV7, the memory cells having a threshold voltage lower than the threshold voltage in the third programming state PV3 can be controlled into the programming mode (PGM MODE).

[0147] When the programming operation for the first programming state PV1 is terminated, a programming operation for the second programming state PV2 is performed. During the programming operation for the second programming state PV2, the memory cells to be programmed to the second programming state PV2 may be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. That is, the bit lines corresponding to the memory cells to be programmed to the second programming state PV2 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied.

[0148] Here, until the programming operation of the memory cell to be programmed to the second programming state PV2 is terminated, the memory cells to be programmed to the remaining programming states PV3 to PV7 may be programmed to a pre-programmed state higher than the second programming state PV2. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 among the memory cells to be programmed to the third and fourth programming states PV3 and PV4 adjacent to the second programming state PV2, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the third programming state PV3. Further, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 among the memory cells to be programmed to the remaining programming states PV5 to PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fourth programming state PV4.

[0149] That is, among the memory cells to be programmed into the third and fourth programming states PV3 and PV4, the memory cells having a threshold voltage lower than the threshold voltage in the third programming state PV3 may be controlled to be in the programming mode (PGM MODE). Also, among the memory cells to be programmed into the programming states PV5 to PV7, the memory cells having a threshold voltage lower than the threshold voltage in the fourth programming state PV4 may be controlled to be in the programming mode (PGM MODE).

[0150] When the programming operation for the second programming state PV2 is terminated, a programming operation for the third programming state PV3 is performed. During the programming operation for the third programming state PV3, the memory cells to be programmed to the third programming state PV3 may be programmed to have a threshold voltage distribution corresponding to the third programming state PV3. That is, the bit lines corresponding to the memory cells to be programmed to the third programming state PV3 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied.

[0151] Here, until the programming operation of the memory cell to be programmed to the third programming state PV3 is terminated, the memory cells to be programmed to the remaining programming states PV4 to PV7 may be programmed to a pre-programmed state higher than the third programming state PV3. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 among the memory cells to be programmed to the fourth and fifth programming states PV4 and PV5 adjacent to the third programming state PV3, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fourth programming state PV4. In addition, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fifth programming state PV5 among the memory cells to be programmed to the remaining programming states PV6 and PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fifth programming state PV5.

[0152] That is, among the memory cells to be programmed into the fourth and fifth programming states PV4 and PV5, the memory cells having a threshold voltage lower than the threshold voltage in the fourth programming state PV4 can be controlled to the programming mode (PGM MODE). Moreover, among the memory cells to be programmed into the programming states PV6 and PV7, the memory cells having a threshold voltage lower than the threshold voltage in the fifth programming state PV5 can be controlled to the programming mode (PGM MODE).

[0153] When the programming operation for the third programming state PV3 is terminated, a programming operation for the fourth programming state PV4 is performed. During the programming operation for the fourth programming state PV4, the memory cells to be programmed to the fourth programming state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth programming state PV4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth programming state PV4 may be controlled to a programming mode (PGMMODE) in which a program permission voltage is applied.

[0154] Here, until the programming operation of the memory cell to be programmed to the fourth programming state PV4 is terminated, the memory cells to be programmed to the remaining programming states PV5 to PV7 may be programmed to a pre-programmed state higher than the fourth programming state PV4. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fifth programming state PV5 among the memory cells to be programmed to the fifth and sixth programming states PV5 and PV6 adjacent to the fourth programming state PV4, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fifth programming state PV5. Further, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the sixth programming state PV6 among the memory cells to be programmed to the remaining programming state PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the sixth programming state PV6.

[0155] That is, among the memory cells to be programmed into the fifth and sixth programming states PV5 and PV6, the memory cells having a threshold voltage lower than the threshold voltage in the fifth programming state PV5 can be controlled into the programming mode (PGM MODE). Moreover, among the memory cells to be programmed into the programming state PV7, the memory cells having a threshold voltage lower than the threshold voltage in the sixth programming state PV6 can be controlled into the programming mode (PGM MODE).

[0156] When the programming operation for the fourth programming state PV4 is terminated, the programming operation for the fifth programming state PV5 is performed. During the programming operation for the fifth programming state PV5, the memory cells to be programmed to the fifth programming state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth programming state PV5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth programming state PV5 may be controlled to a programming mode (PGMMODE) in which a program permission voltage is applied.

[0157] Here, until the programming operation on the memory cell to be programmed to the fifth programming state PV5 is terminated, the memory cells to be programmed to the remaining programming states PV6 and PV7 may be programmed to a pre-programmed state higher than the fifth programming state PV5. For example, a program permission voltage may be applied to the bit lines of the memory cells having a threshold voltage lower than the threshold voltage in the sixth programming state PV6 among the memory cells to be programmed to the sixth and seventh programming states PV6 and PV7 adjacent to the fifth programming state PV5, and a program inhibition voltage may be applied to the bit lines of the memory cells having a threshold voltage equal to or higher than the threshold voltage in the sixth programming state PV6.

[0158] That is, among memory cells to be programmed into the sixth and seventh program states PV6 and PV7, memory cells having a threshold voltage lower than that in the sixth program state PV6 may be controlled into the program mode (PGM MODE).

[0159] When the programming operation for the fifth programming state PV5 is terminated, a programming operation for the sixth programming state PV6 is performed. During the programming operation for the sixth programming state PV6, the memory cells to be programmed to the sixth programming state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth programming state PV6. That is, the bit lines corresponding to the memory cells to be programmed to the sixth programming state PV6 may be controlled to a programming mode (PGMMODE) in which a program permission voltage is applied.

[0160] Here, until the programming operation on the memory cells to be programmed to the sixth programming state PV6 is terminated, the memory cells to be programmed to the remaining programming state PV7 may be programmed to a pre-programmed state higher than the sixth programming state PV6. For example, a program permission voltage may be applied to the bit lines of the memory cells to be programmed to the seventh programming state PV7 whose threshold voltages are lower than the threshold voltage in the seventh programming state PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the seventh programming state PV7.

[0161] That is, among memory cells to be programmed to the seventh program state PV7, memory cells having a threshold voltage lower than that in the seventh program state PV7 may be controlled to the program mode (PGM MODE).

[0162] When the programming operation for the sixth programming state PV6 is terminated, a programming operation for the seventh programming state PV7 is performed. During the programming operation for the seventh programming state PV7, the memory cells to be programmed to the seventh programming state PV7 may be programmed to have a threshold voltage distribution corresponding to the seventh programming state PV7. That is, the bit lines corresponding to the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied.

[0163] Fig.13 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0164] Reference Fig.13During a program operation for a first program state PV1, a memory cell to be programmed to the first program state PV1 and a memory cell to be programmed to a second program state PV2 adjacent to the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV1. That is, the bit lines corresponding to the memory cell to be programmed to the first program state PV1 and the memory cell to be programmed to the second program state PV2 may be controlled to a program mode (PGM MODE) in which a program permission voltage is applied.

[0165] Here, until the programming operations on the memory cells to be programmed to the first programming state PV1 and the memory cells to be programmed to the second programming state PV2 are terminated, the memory cells to be programmed to the remaining programming states PV3 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the first programming state PV1.

[0166] For example, among the remaining programming states PV3 to PV7, memory cells to be programmed to the third programming state PV3 and the fourth programming state PV4 with relatively low threshold voltage distribution and memory cells to be programmed to the fifth programming state PV5 to the seventh programming state PV7 with relatively high threshold voltage distribution can be programmed to have different threshold voltage distributions. For example, a program permission voltage can be applied to the bit lines of memory cells whose threshold voltages are lower than the threshold voltage in the second programming state PV2 among the memory cells to be programmed to the third programming state PV3 and the fourth programming state PV4, and a program inhibition voltage can be applied to the bit lines of memory cells whose threshold voltages are equal to or higher than the threshold voltage in the second programming state PV2. That is, among the memory cells to be programmed to the third and fourth programming states PV3 and PV4, the memory cells whose threshold voltages are lower than the threshold voltage in the second programming state PV2 can be controlled to the programming mode (PGM MODE). Further, a program permission voltage may be applied to the bit lines of memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 among the memory cells to be programmed into the fifth to seventh programming states PV5 to PV7, and a program inhibition voltage may be applied to the bit lines of memory cells whose threshold voltages are equal to or higher than the threshold voltage in the third programming state PV3. That is, among the memory cells to be programmed into the fifth to seventh programming states PV5 to PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 may be controlled to the programming mode (PGM MODE).

[0167] When the programming operation for the first programming state PV1 is completed, the programming operation for the second programming state PV2 is performed. During the programming operation for the second programming state PV2, the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 adjacent to the second programming state PV2 may be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. That is, the bit lines corresponding to the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0168] Here, until the programming operations on the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 are terminated, the memory cells to be programmed to the remaining programming states PV4 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the second programming state PV2.

[0169] For example, among the remaining programming states PV4 to PV7, memory cells to be programmed to the fourth programming state PV4 and the fifth programming state PV5 having relatively low threshold voltage distributions and memory cells to be programmed to the sixth programming state PV6 and the seventh programming state PV7 having relatively high threshold voltage distributions can be programmed to have different threshold voltage distributions. For example, a program permission voltage can be applied to the bit lines of memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 among the memory cells to be programmed to the fourth programming state PV4 and the fifth programming state PV5, and a program inhibition voltage can be applied to the bit lines of memory cells whose threshold voltages are equal to or higher than the threshold voltage in the third programming state PV3. That is, among the memory cells to be programmed to the fourth and fifth programming states PV4 and PV5, the memory cells whose threshold voltages are lower than the threshold voltage in the third programming state PV3 can be controlled to the programming mode (PGM MODE). Further, a program permission voltage may be applied to the bit lines of memory cells whose threshold voltages are lower than the threshold voltage in the fourth program state PV4 among the memory cells to be programmed into the sixth and seventh program states PV6 and PV7, and a program inhibition voltage may be applied to the bit lines of memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fourth program state PV4. That is, among the memory cells to be programmed into the sixth and seventh program states PV6 and PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the fourth program state PV4 may be controlled to the programming mode (PGM MODE).

[0170] When the programming operation for the second programming state PV2 is completed, the programming operation for the third programming state PV3 is performed. During the programming operation for the third programming state PV3, the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 adjacent to the third programming state PV3 may be programmed to have a threshold voltage distribution corresponding to the third programming state PV3. That is, the bit lines corresponding to the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 and the second programming state PV2 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0171] Here, until the programming operations on the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 are terminated, the memory cells to be programmed to the remaining programming states PV5 to PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the third programming state PV3.

[0172] For example, among the remaining programming states PV5 to PV7, memory cells to be programmed to the fifth and sixth programming states PV5 and PV6 with relatively low threshold voltage distributions and memory cells to be programmed to the seventh programming state PV7 with relatively high threshold voltage distributions can be programmed to different threshold voltage distributions. For example, a program permission voltage can be applied to the bit lines of memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 among the memory cells to be programmed to the fifth programming state PV5 and the sixth programming state PV6, and a program inhibition voltage can be applied to the bit lines of memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fourth programming state PV4. That is, among the memory cells to be programmed to the fifth and sixth programming states PV5 and PV6, memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 can be controlled to the programming mode (PGM MODE). Further, a program permission voltage may be applied to the bit lines of memory cells whose threshold voltages are lower than the threshold voltages in the fifth programming state PV5 among the memory cells to be programmed to the seventh programming state PV7, and a program inhibition voltage may be applied to the bit lines of memory cells whose threshold voltages are equal to or higher than the threshold voltages in the fifth programming state PV5. That is, among the memory cells to be programmed to the seventh programming state PV7, the memory cells whose threshold voltages are lower than the threshold voltages in the fifth programming state PV5 may be controlled to the programming mode (PGM MODE).

[0173] When the programming operation for the third programming state PV3 is completed, the programming operation for the fourth programming state PV4 is performed. During the programming operation for the fourth programming state PV4, the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 adjacent to the fourth programming state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth programming state PV4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 may be controlled to a programming mode (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third programming states PV1 to PV3 may be controlled to a program inhibition mode (INHIBIT MODE) in which a program inhibition voltage is applied.

[0174] Here, until the programming operation of the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 is terminated, the memory cells to be programmed to the remaining programming states PV6 and PV7 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the fourth programming state PV4. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fifth programming state PV5 among the memory cells to be programmed to the remaining programming states PV6 and PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fifth programming state PV5. That is, among the memory cells to be programmed to the remaining programming states PV6 and PV7, the memory cells whose threshold voltages are lower than the threshold voltage in the fifth programming state PV5 may be controlled to the programming mode (PGM MODE).

[0175] When the programming operation for the fourth programming state PV4 is completed, the programming operation for the fifth programming state PV5 is performed. During the programming operation for the fifth programming state PV5, the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 adjacent to the fifth programming state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth programming state PV5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth programming states PV1 to PV4 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0176] Here, until the programming operation of the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 is terminated, the memory cells to be programmed to the remaining programming states PV7 to PV7 may be programmed to a pre-programmed state (pre-state) in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the fifth programming state PV5. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltages in the sixth programming state PV6 among the memory cells to be programmed to the remaining programming state PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltages in the sixth programming state PV6. That is, among the memory cells to be programmed to the remaining programming state PV7, the memory cells whose threshold voltages are lower than the threshold voltages in the sixth programming state PV6 may be controlled to the programming mode (PGM MODE).

[0177] When the programming operation for the fifth programming state PV5 is completed, the programming operation for the sixth programming state PV6 is performed. During the programming operation for the sixth programming state PV6, the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 adjacent to the sixth programming state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth programming state PV6. That is, the bit lines corresponding to the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth programming states PV1 to PV5 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0178] When the programming operation for the sixth programming state PV6 is completed, the programming operation for the seventh programming state PV7 is performed. During the programming operation for the seventh programming state PV7, the bit lines corresponding to the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM mode) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth programming states PV1 to PV6 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0179] Fig.14 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0180] Reference Fig.14 During a program operation for a first program state PV1, a memory cell to be programmed to the first program state PV1 and a memory cell to be programmed to a second program state PV2 adjacent to the first program state PV1 may be programmed to have a threshold voltage distribution corresponding to the first program state PV1. That is, the bit lines corresponding to the memory cell to be programmed to the first program state PV1 and the memory cell to be programmed to the second program state PV2 may be controlled to a program mode (PGM MODE) in which a program permission voltage is applied.

[0181] Here, until the programming operations on the memory cells to be programmed to the first programming state PV1 and the memory cells to be programmed to the second programming state PV2 are terminated, the memory cells to be programmed to the remaining programming states PV3 to PV7 can be controlled to a programming mode (PGM MODE), so that the threshold voltage distribution of the memory cells can be increased.

[0182] When the programming operation for the first programming state PV1 is completed, the programming operation for the second programming state PV2 is performed. During the programming operation for the second programming state PV2, the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 adjacent to the second programming state PV2 may be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. That is, the bit lines corresponding to the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0183] Here, until the programming operations on the memory cells to be programmed to the second programming state PV2 and the memory cells to be programmed to the third programming state PV3 are terminated, the memory cells to be programmed to the remaining programming states PV4 to PV7 can be controlled to a programming mode (PGM MODE), so that the threshold voltage distribution of the memory cells can be increased.

[0184] When the programming operation for the second programming state PV2 is completed, the programming operation for the third programming state PV3 is performed. During the programming operation for the third programming state PV3, the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 adjacent to the third programming state PV3 may be programmed to have a threshold voltage distribution corresponding to the third programming state PV3. That is, the bit lines corresponding to the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 and the memory cells that have been programmed to the second programming state PV2 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0185] Here, until the programming operations on the memory cells to be programmed to the third programming state PV3 and the memory cells to be programmed to the fourth programming state PV4 are terminated, the memory cells to be programmed to the remaining programming states PV5 to PV7 can be controlled to a programming mode (PGM MODE), so that the threshold voltage distribution of the memory cells can be increased.

[0186] When the programming operation for the third programming state PV3 is completed, the programming operation for the fourth programming state PV4 is performed. During the programming operation for the fourth programming state PV4, the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 adjacent to the fourth programming state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth programming state PV4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 may be controlled to a programming mode (PGM MODE) in which a program permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third programming states PV1 to PV3 may be controlled to a program inhibition mode (INHIBIT MODE) in which a program inhibition voltage is applied.

[0187] Here, until the programming operations on the memory cells to be programmed to the fourth programming state PV4 and the memory cells to be programmed to the fifth programming state PV5 are terminated, the memory cells to be programmed to the remaining programming states PV6 and PV7 can be controlled to the programming mode PGM MODE, so that the threshold voltage distribution of the memory cells can be increased.

[0188] When the programming operation for the fourth programming state PV4 is completed, the programming operation for the fifth programming state PV5 is performed. During the programming operation for the fifth programming state PV5, the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 adjacent to the fifth programming state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth programming state PV5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth programming states PV1 to PV4 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0189] Here, until the programming operations on the memory cells to be programmed to the fifth programming state PV5 and the memory cells to be programmed to the sixth programming state PV6 are terminated, the memory cells to be programmed to the remaining programming state PV7 can be controlled to the programming mode (PGM MODE), so that the threshold voltage distribution of the memory cells can be increased.

[0190] When the programming operation for the fifth programming state PV5 is completed, the programming operation for the sixth programming state PV6 is performed. During the programming operation for the sixth programming state PV6, the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 adjacent to the sixth programming state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth programming state PV6. That is, the bit lines corresponding to the memory cells to be programmed to the sixth programming state PV6 and the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM MODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth programming states PV1 to PV5 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0191] When the programming operation for the sixth programming state PV6 is completed, the programming operation for the seventh programming state PV7 is performed. During the programming operation for the seventh programming state PV7, the bit lines corresponding to the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM mode) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth programming states PV1 to PV6 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0192] Fig.15 is a diagram for describing a program mode of a memory cell depending on a corresponding program state during a program operation according to an embodiment of the present disclosure.

[0193] Reference Fig.15 During the programming operation for the first programming state PV1, the memory cells to be programmed to the first programming state PV1 may be programmed to have a threshold voltage distribution corresponding to the first programming state PV1. That is, the bit lines corresponding to the memory cells to be programmed to the first programming state PV1 may be controlled to a programming mode (PGM MODE) in which a program permission voltage is applied.

[0194] Here, until the programming operation of the memory cell to be programmed to the first programming state PV1 is terminated, the memory cell to be programmed to the second programming state PV2 adjacent to the first programming state PV1 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the first programming state PV1. For example, a program permission voltage may be applied to the bit line of the memory cell having a threshold voltage lower than the threshold voltage in the second programming state PV2 among the memory cells to be programmed to the second programming state PV2, and a program inhibition voltage may be applied to the bit line of the memory cell having a threshold voltage equal to or higher than the threshold voltage in the second programming state PV2. That is, among the memory cells to be programmed to the second programming state PV2, the memory cell having a threshold voltage lower than the threshold voltage in the second programming state PV2 may be controlled to the programming mode (PGM MODE).

[0195] Also, until the program operation on the memory cells to be programmed to the first program state PV1 is terminated, the memory cells to be programmed to the remaining program states PV3 to PV7 may be controlled to a program mode (PGM MODE), and thus the threshold voltage distribution thereof may increase.

[0196] When the programming operation for the first programming state PV1 is completed, the programming operation for the second programming state PV2 is performed. During the programming operation for the second programming state PV2, the memory cells to be programmed to the second programming state PV2 may be programmed to have a threshold voltage distribution corresponding to the second programming state PV2. That is, the bit lines corresponding to the memory cells to be programmed to the second programming state PV2 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0197] Here, until the programming operation of the memory cell to be programmed to the second programming state PV2 is terminated, the memory cell to be programmed to the third programming state PV3 adjacent to the second programming state PV2 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the second programming state PV2. For example, a program permission voltage may be applied to the bit lines of the memory cells to be programmed to the third programming state PV3 whose threshold voltage is lower than the threshold voltage in the third programming state PV3, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltage is equal to or higher than the threshold voltage in the third programming state PV3. That is, among the memory cells to be programmed to the third programming state PV3, the memory cells whose threshold voltage is lower than the threshold voltage in the third programming state PV3 may be controlled to the programming mode (PGM MODE).

[0198] Also, until the program operation on the memory cells to be programmed to the second program state PV2 is terminated, the memory cells to be programmed to the remaining program states PV4 to PV7 may be controlled to a program mode (PGM MODE), and thus the threshold voltage distribution thereof may increase.

[0199] When the programming operation for the second programming state PV2 is completed, the programming operation for the third programming state PV3 is performed. During the programming operation for the third programming state PV3, the memory cells to be programmed to the third programming state PV3 may be programmed to have a threshold voltage distribution corresponding to the third programming state PV3. That is, the bit lines corresponding to the memory cells to be programmed to the third programming state PV3 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first programming state PV1 and the second programming state PV2 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0200] Until the programming operation of the memory cells to be programmed to the third programming state PV3 is terminated, the memory cells to be programmed to the fourth programming state PV4 adjacent to the third programming state PV3 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cells is higher than the threshold voltage distribution in the third programming state PV3. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 among the memory cells to be programmed to the fourth programming state PV4, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltage in the fourth programming state PV4. That is, among the memory cells to be programmed to the fourth programming state PV4, the memory cells whose threshold voltages are lower than the threshold voltage in the fourth programming state PV4 may be controlled to the programming mode (PGM MODE).

[0201] Also, until the program operation on the memory cells to be programmed to the third program state PV3 is terminated, the memory cells to be programmed to the remaining program states PV5 to PV7 may be controlled to a program mode (PGM MODE), and thus the threshold voltage distribution thereof may increase.

[0202] When the programming operation for the third programming state PV3 is completed, the programming operation for the fourth programming state PV4 is performed. During the programming operation for the fourth programming state PV4, the memory cells to be programmed to the fourth programming state PV4 may be programmed to have a threshold voltage distribution corresponding to the fourth programming state PV4. That is, the bit lines corresponding to the memory cells to be programmed to the fourth programming state PV4 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to third programming states PV1 to PV3 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0203] Here, until the programming operation of the memory cell to be programmed to the fourth programming state PV4 is terminated, the memory cell to be programmed to the fifth programming state PV5 adjacent to the fourth programming state PV4 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the fourth programming state PV4. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltages are lower than the threshold voltages in the fifth programming state PV5 among the memory cells to be programmed to the fifth programming state PV5, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltages are equal to or higher than the threshold voltages in the fifth programming state PV5. That is, among the memory cells to be programmed to the fifth programming state PV5, the memory cells whose threshold voltages are lower than the threshold voltages in the fifth programming state PV5 may be controlled to the programming mode (PGM MODE).

[0204] Also, until the program operation on the memory cells to be programmed to the fourth program state PV4 is terminated, the memory cells to be programmed to the remaining program states PV6 and PV7 may be controlled to the program mode (PGM MODE), and thus the threshold voltage distribution thereof may increase.

[0205] When the programming operation for the fourth programming state PV4 is completed, the programming operation for the fifth programming state PV5 is performed. During the programming operation for the fifth programming state PV5, the memory cells to be programmed to the fifth programming state PV5 may be programmed to have a threshold voltage distribution corresponding to the fifth programming state PV5. That is, the bit lines corresponding to the memory cells to be programmed to the fifth programming state PV5 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fourth programming states PV1 to PV4 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0206] Until the programming operation of the memory cell to be programmed to the fifth programming state PV5 is terminated, the memory cell to be programmed to the sixth programming state PV6 adjacent to the fifth programming state PV5 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the fifth programming state PV5. For example, a program permission voltage may be applied to the bit lines of the memory cells having a threshold voltage lower than the threshold voltage in the sixth programming state PV6 among the memory cells to be programmed to the sixth programming state PV6, and a program inhibition voltage may be applied to the bit lines of the memory cells having a threshold voltage equal to or higher than the threshold voltage in the sixth programming state PV6. That is, among the memory cells to be programmed to the sixth programming state PV6, the memory cells having a threshold voltage lower than the threshold voltage in the sixth programming state PV6 may be controlled to the programming mode (PGM MODE).

[0207] Also, until the program operation on the memory cells to be programmed to the fifth program state PV5 is terminated, the memory cells to be programmed to the remaining program state PV7 may be controlled to the program mode (PGM MODE), and thus the threshold voltage distribution thereof may increase.

[0208] When the programming operation for the fifth programming state PV5 is completed, the programming operation for the sixth programming state PV6 is performed. During the programming operation for the sixth programming state PV6, the memory cells to be programmed to the sixth programming state PV6 may be programmed to have a threshold voltage distribution corresponding to the sixth programming state PV6. That is, the bit lines corresponding to the memory cells to be programmed to the sixth programming state PV6 may be controlled to a programming mode (PGMMODE) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to fifth programming states PV1 to PV5 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0209] Until the programming operation of the memory cell to be programmed to the sixth programming state PV6 is terminated, the memory cell to be programmed to the seventh programming state PV7 adjacent to the sixth programming state PV6 may be programmed to a pre-programmed state in which the threshold voltage distribution of the memory cell is higher than the threshold voltage distribution in the sixth programming state PV6. For example, a program permission voltage may be applied to the bit lines of the memory cells whose threshold voltage is lower than the threshold voltage in the seventh programming state PV7 among the memory cells to be programmed to the seventh programming state PV7, and a program inhibition voltage may be applied to the bit lines of the memory cells whose threshold voltage is equal to or higher than the threshold voltage in the seventh programming state PV7. That is, among the memory cells to be programmed to the seventh programming state PV7, the memory cells whose threshold voltage is lower than the threshold voltage in the seventh programming state PV7 may be controlled to the programming mode (PGM MODE).

[0210] When the programming operation for the sixth programming state PV6 is completed, the programming operation for the seventh programming state PV7 is performed. During the programming operation for the seventh programming state PV7, the bit lines corresponding to the memory cells to be programmed to the seventh programming state PV7 may be controlled to a programming mode (PGM mode) in which a programming permission voltage is applied. Here, the bit lines corresponding to the memory cells that have been programmed to the first to sixth programming states PV1 to PV6 may be controlled to a programming inhibition mode (INHIBIT MODE) in which a programming inhibition voltage is applied.

[0211] Fig.16 is a schematic diagram illustrating an embodiment of a memory system.

[0212] Reference Fig.16 , the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 may control data access operations of the memory device 1100, such as a program operation, an erase operation, or a read operation, under the control of the processor 3100.

[0213] Data programmed to the memory device 1100 may be output via the display 3200 under the control of the memory controller 1200 .

[0214] The radio transceiver 3300 can exchange radio signals through the antenna ANT. For example, the radio transceiver 3300 can convert the radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300, and can transmit the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 can program the signal processed by the processor 3100 to the memory device 1100. Further, the radio transceiver 3300 can convert the signal output from the processor 3100 into a radio signal, and output the radio signal to an external device through the antenna ANT. The input device 3400 can be used to input a control signal to control the operation of the processor 3100 or the data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device, such as a touch pad, a computer mouse, a keypad or a keyboard. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 1200 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output via the display 3200 .

[0215] In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 or as a chip provided separately from the processor 3100. Further, the memory controller 1200 may be implemented as a part of the processor 3100 or as a chip provided separately from the processor 3100. Figure 1 The illustrated example of the memory controller 1200 is implemented, and the memory device 1100 may be implemented by Figure 2 The illustrated example of the memory device 1100 is implemented.

[0216] Fig.17 is a schematic diagram illustrating an embodiment of a memory system.

[0217] Reference Fig.17 , the memory system 40000 may be embodied in a personal computer, a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0218] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation of the memory device 1100 .

[0219] The processor 4100 may output data stored in the memory device 1100 via the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad, a computer mouse, a keypad, or a keyboard.

[0220] The processor 4100 may control the overall operation of the memory system 40000 and may control the operation of the memory controller 1200. In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or as a chip provided separately from the processor 4100. Further, the memory controller 1200 may be configured to control the operation of the memory device 1100. Figure 1 The illustrated example implementation of the memory controller 1200 and the memory device 1100 may be implemented by Figure 2 An example implementation of a memory device 1100 is illustrated.

[0221] Fig.18 is a schematic diagram illustrating an embodiment of a memory system.

[0222] Reference Fig.18 , the memory system 50000 may be implemented as an image processing device, for example, a digital camera, a mobile phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet PC provided with a digital camera.

[0223] The memory system 50000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation (eg, a program operation, an erase operation, or a read operation) of the memory device 1100 .

[0224] The schematic image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal, and the converted digital signal may be transmitted to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signal may be output via the display 5300, or may be stored in the memory device 1100 through the memory controller 1200. Further, under the control of the processor 5100 or the memory controller 1200, the data stored in the memory device 1100 may be output via the display 5300.

[0225] In an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 5100 or as a chip provided separately from the processor 5100. Further, the memory controller 1200 may be implemented as a part of the processor 5100 or as a chip provided separately from the processor 5100. Figure 1 The illustrated example of the memory controller 1200 is implemented, and the memory device 1100 may be implemented by Figure 2 The illustrated example of the memory device 1100 is implemented.

[0226] Fig.19 is a schematic diagram illustrating an embodiment of a memory system.

[0227] Reference Fig.19 The memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0228] The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In an embodiment, the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface. Figure 1 The illustrated example of the memory controller 1200 is implemented and the memory device 1100 may be implemented by Figure 2 The illustrated example of the memory device 1100 is implemented.

[0229] Further, the card interface 7100 can connect the data exchange between the host 60000 and the memory controller 1200 according to the protocol interface of the host 60000. In an embodiment, the card interface 7100 can support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. Here, the card interface 7100 can refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method executed by the hardware.

[0230] When the memory system 70000 is coupled to the host interface 6200 of the host 60000 (such as, a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box), the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0231] The present disclosure may improve the range of threshold voltage distribution of memory cells during a programming operation of a memory device, and may also increase the speed of a programming operation of the memory device.

[0232] In the embodiments discussed above, all operations may be selectively performed or skipped. In addition, the operations in each embodiment may not always be performed in order, and may be performed randomly. In addition, the embodiments disclosed in this specification and the accompanying drawings are intended to help those of ordinary skill in the art to more clearly understand the present disclosure, rather than to limit the limits of the present disclosure. In other words, those of ordinary skill in the art to which the present disclosure belongs will be able to easily understand that, based on the technical scope of the present disclosure, various modifications are possible.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells; a peripheral circuit configured to perform a plurality of programming operations to program the plurality of memory cells to a plurality of programming states; as well as control logic configured to control the peripheral circuit during a programming operation for a selected programming state among the plurality of programming states of the plurality of programming operations: programming a first memory cell of the plurality of memory cells targeted for the selected programming state to the selected programming state using a first verification voltage corresponding to the selected programming state; programming a second memory cell of the plurality of memory cells targeted at a first programming state immediately above the selected programming state to the selected programming state using the first verification voltage; as well as Third memory cells of the plurality of memory cells targeted for second program states each higher than the first program state are programmed to a pre-program state corresponding to the first program state using a second verification voltage corresponding to the first program state.

2. The memory device of claim 1, wherein the pre-programmed state is a program state adjacent to the selected program state.

3. The memory device of claim 1 , wherein the peripheral circuit performs the following operations in sequence during the programming operation: a verification operation for the selected programming state by applying the first verification voltage to the second memory cell, and a verification operation for the pre-programmed state by applying the second verification voltage to the third memory cell. 4 . The memory device of claim 1 , wherein the peripheral circuit sequentially performs the plurality of program operations corresponding to the plurality of program states in order starting from a program operation corresponding to a program state having a low threshold voltage distribution.

5. A memory device comprising: a memory cell array comprising a plurality of memory cells; a peripheral circuit configured to perform a plurality of programming operations to program the plurality of memory cells to a plurality of programming states; as well as control logic configured to control the peripheral circuit during a programming operation for a first programming state among the plurality of programming states of the plurality of programming operations: programming a first memory cell of the plurality of memory cells targeted for the first programming state to the first programming state using a first verification voltage corresponding to the first programming state; as well as programming second memory cells of the plurality of memory cells that target respective second programming states higher than the first programming state to a pre-programmed state higher than the first programming state using a second verification voltage corresponding to a second programming state of the second programming states that is immediately higher than the first programming state, The peripheral circuit sequentially performs the plurality of program operations corresponding to the plurality of program states in order starting from a program operation corresponding to a program state having a lower threshold voltage distribution. 6 . The memory device of claim 5 , wherein the pre-programmed state is a programmed state adjacent to the first programmed state.

7. The memory device of claim 5 , wherein the peripheral circuit performs the following operations in sequence during the programming operation: a verification operation for the first programming state by applying the first verification voltage to the first memory cell, and a verification operation for the pre-programmed state by applying the second verification voltage to the second memory cell.

8. A method of operating a memory device, comprising: programming a first memory cell of a plurality of memory cells targeted for the first programming state to the first programming state using a first verification voltage corresponding to the first programming state; programming a second memory cell of the plurality of memory cells targeted for a second programming state immediately higher than the first programming state to the first programming state using the first verification voltage; as well as Third memory cells of the plurality of memory cells targeting respective third program states higher than the second program state are programmed to a pre-program state using a second verification voltage corresponding to the second program state. 9 . The method of claim 8 , wherein a first program verification operation by applying the first verification voltage to the first memory cell and the second memory cell, and a second program verification operation by applying the second verification voltage to the third memory cell are sequentially performed.

10. The method of claim 8, wherein the first memory cell and the second memory cell are programmed together to the first programmed state.

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