Semiconductor device and semiconductor package

Abstract

The embodiment improves a semiconductor device and a semiconductor package with high reliability. The semiconductor device of the embodiment includes a first semiconductor chip, an organic insulating film, and a rewiring layer. The first semiconductor chip has a first pad and a second pad having a recessed portion. The organic insulating film is provided on the first semiconductor chip, covers the recessed portion, and does not cover at least a portion of the first pad. The lower portion of the rewiring layer is connected to the first pad, and the upper portion is arranged on the organic insulating film.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-45537 (filing date: March 16, 2020), and the present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device and a semiconductor package. Background Art

[0004] In the past, a semiconductor package has been developed in which a rewiring layer is formed on a semiconductor chip and the rewiring layer is bonded to a bump. By forming a rewiring layer, the bump can be arranged at any position, thereby improving the connectivity with the outside. In this semiconductor package, high reliability is also required. Summary of the invention

[0005] Embodiments provide a semiconductor device and a semiconductor package with high reliability.

[0006] A semiconductor device according to an embodiment includes a first semiconductor chip, an organic insulating film, and a rewiring layer. The first semiconductor chip has a first pad and a second pad having a recessed portion. The organic insulating film is provided on the first semiconductor chip, covers the recessed portion, and does not cover at least a portion of the first pad. The lower portion of the rewiring layer is connected to the first pad, and the upper portion is arranged on the organic insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a cross-sectional view showing a semiconductor package according to an embodiment.

[0008] Figure 2 FIG. 1 is a plan view showing a semiconductor device of a semiconductor package according to an embodiment.

[0009] Figure 3 Yes means Figure 2 A partial enlarged top view of area A.

[0010] Figure 4 Yes means Figure 3 A partial enlarged top view of area B.

[0011] Figure 5 yes Figure 4 The cross-sectional view along the CC' line is shown.

[0012] Figure 6 yes Figure 4 The cross-sectional view along the line DD' is shown.

[0013] Figure 7 yes Figure 4The cross-sectional view along the line EE' is shown.

[0014] Figure 8 (a) to (f) are cross-sectional views of a method for manufacturing a semiconductor package according to an embodiment.

[0015] Fig. 9 (a) to (f) are cross-sectional views of a method for manufacturing a semiconductor package according to a comparative example. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present invention will be described.

[0017] Figure 1 It is a cross-sectional view showing the semiconductor package according to the present embodiment.

[0018] Figure 2 It is a top view showing a semiconductor device of a semiconductor package according to the present embodiment.

[0019] Figure 3 Yes means Figure 2 A partial enlarged top view of area A.

[0020] Figure 4 Yes means Figure 3 A partial enlarged top view of area B.

[0021] Figure 5 yes Figure 4 The cross-sectional view along the CC' line is shown.

[0022] Figure 6 yes Figure 4 The cross-sectional view along the line DD' is shown.

[0023] Figure 7 yes Figure 4 The cross-sectional view along the line EE' is shown.

[0024] In addition, each figure is a schematic diagram and is appropriately enlarged and simplified. In addition, for the convenience of illustration, the components are appropriately omitted. Figure 2 as well as Figure 3 The redistribution layer is omitted.

[0025] like Figure 1 As shown, in the semiconductor package 1 of the present embodiment, a mounting substrate 10 , a semiconductor chip 20 , a semiconductor chip 30 , a plurality of bumps 40 , an underfill 50 , a resin member 60 , and a plurality of bumps 70 are provided.

[0026] The semiconductor chip 20 is mounted on the mounting substrate 10. The semiconductor chip 30 is provided on the semiconductor chip 20. A plurality of protrusions 40 are arranged between the semiconductor chip 20 and the semiconductor chip 30. The underfill 50 is provided between the semiconductor chip 20 and the semiconductor chip 30 and covers the protrusions 40. In addition, the underfill 50 is also arranged around the semiconductor chip 30. In addition, the underfill 50 may also be provided only in the area between the semiconductor chip 20 and the semiconductor chip 30. The resin member 60 is provided on the mounting substrate 10 and covers the semiconductor chip 20, the semiconductor chip 30, the protrusions 40 and the underfill 50. A plurality of protrusions 70 are provided on the lower surface of the mounting substrate 10.

[0027] For example, DRAM (Dynamic Random Access Memory) is formed on the semiconductor chip 20, and for example, a logic circuit is formed on the semiconductor chip 30. Each terminal of the semiconductor chip 30 is connected to each terminal of the semiconductor chip 20 via the bump 40. The resin member 60 is a sealing member made of a resin material.

[0028] The mounting substrate 10 is provided with an insulating base material 11, a via hole 12, an upper surface wiring layer 13, a lower surface wiring layer 14, an insulating film 15, and an insulating film 16. The via hole 12 penetrates the base material 11 in the thickness direction. The upper surface wiring layer 13 is provided on the upper surface of the base material 11, and the lower surface wiring layer 14 is provided on the lower surface of the base material 11. The upper surface wiring layer 13 is connected to the lower surface wiring layer 14 via the via hole 12. The insulating film 15 is provided on the peripheral portion of the upper surface of the base material 11. The insulating film 16 is provided on the region of the lower surface of the base material 11 where the lower surface wiring layer 14 is not provided, and covers the end of the lower surface wiring layer 14.

[0029] The upper surface wiring layer 13 is connected to a terminal of a part of the semiconductor chip 20 via the wire 41. The lower surface wiring layer 14 is connected to the bump 70. Furthermore, a bonding member 42 is provided between the mounting substrate 10 and the semiconductor chip 20. The bonding member 42 is made of, for example, an adhesive.

[0030] The semiconductor chip 20 includes a chip body 21 and pads 22 to 24 (see Figure 3 ), and a passivation film 26 as an inorganic insulating film. The pads 22 to 24 are provided on the upper surface of the chip body 21. The pads 22 to 24 are formed of, for example, aluminum (Al). In addition, the pads 22 to 24 are also collectively referred to as "pads".

[0031] The passivation film 26 is provided on the chip body 21. The passivation film 26 is formed of, for example, silicon nitride (SiN). However, the passivation film 26 may be formed of an inorganic material other than silicon nitride. A portion of the pads 22 to 24 is covered by the passivation film 26, and the remaining portion is exposed.

[0032] A polyimide film 27 as an organic insulating film and a rewiring layer 28 are provided on the semiconductor chip 20. The polyimide film 27 is formed of polyimide. However, the organic insulating film may be formed of an organic material other than polyimide. The rewiring layer 28 is formed of, for example, copper (Cu) and nickel (Ni). The rewiring layer 28 is connected to the bump 40. The semiconductor chip 20, the polyimide film 27, and the rewiring layer 28 constitute a semiconductor device 91 of this embodiment.

[0033] like Figure 2 As shown in the figure, a bump pad region 20a and a bonding pad region 20b are set on the upper surface of the semiconductor chip 20. The bump pad region 20a is arranged, for example, along a pair of end edges of the semiconductor chip 20 facing each other. The bonding pad region 20b is arranged, for example, along another pair of end edges of the semiconductor chip 20 facing each other. The polyimide film 27 exposes a portion of the bump pad region 20a, a portion of the bonding pad region 20b, and the end of the semiconductor chip 20, and covers the other portions. A bump pad (not shown) is provided in the bump pad region 20a.

[0034] like Figure 3 as well as Figure 4 As shown, a plurality of pads 22, pads 23, and pads 24 are provided in the bonding pad area 20b. As described later, the pads 22 also serve as inspection pads, wire bonding pads, and rewiring connection pads. The pads 23 are pads used in the semiconductor package 1. The pads 24 are pads not used in the semiconductor package 1. Although a plurality of pads are provided in the semiconductor chip 20, only a portion of the pads are connected to the outside and used according to the configuration of the semiconductor package in which the semiconductor chip 20 is assembled. Therefore, there are pads 23 used and pads 24 not used in the semiconductor chip 20.

[0035] like Figure 4 as well as Figure 5 As shown, a bonding area 22a for bonding the wire 41, a probe area 22b to which a probe (not shown) is pressed when inspecting electrical characteristics, and a rewiring area 22c connected to the rewiring layer 28 are set in the pad 22. In the semiconductor chip 20 after inspection, a probe mark P formed when the probe is pressed and abutted remains in the probe area 22b. The shape of the probe mark P is, for example, a crater, and a ring-shaped convex part P2 is formed around a concave part P1. In the probe mark P, there is a case where the convex part P2 is not formed, but at least the concave part P1 is formed.

[0036] The passivation film 26 covers the end of the pad 22, the end of the pad 23, and the end of the pad 24. In addition, the passivation film 26 is also arranged between the pads 22 to 24.

[0037] The polyimide film 27 is provided with a lower layer 27a and an upper layer 27b. The polyimide film 27 is arranged on the passivation film 26, and is also arranged on a part of the portion of the pad that is not covered by the passivation film 26. In more detail, the entire bump pad region 20a and the bonding pad region 20b of the semiconductor chip 20 are not covered by the upper layer 27b of the polyimide film 27. A part of the bump pad region 20a and a part of the bonding pad region 20b are covered by the lower layer 27a of the polyimide film 27. The lower layer 27a of the polyimide film 27 does not cover the bonding region 22a of the pad 22. The wire 41 is bonded to the upper surface of the bonding region 22a. In addition, the lower layer 27a of the polyimide film 27 covers the probe region 22b and the rewiring region 22c of the pad 22. Therefore, the lower layer 27a of the polyimide film 27 covers the probe mark P formed in the probe region 22b.

[0038] The rewiring layer 28 is provided with a contact portion 28a, a wiring portion 28b, a via portion 28c, and a pad portion 28d. The contact portion 28a penetrates the lower layer 27a of the polyimide film 27 and is connected to the rewiring region 22c of the pad 22. The wiring portion 28b is provided on the lower layer 27a of the polyimide film 27 and is connected to the contact portion 28a. The wiring portion 28b is led out to a region away from the region directly above the contact portion 28a. The upper layer 27b of the polyimide film 27 covers the wiring portion 28b.

[0039] The conductive portion 28c is provided on the wiring portion 28b, connected to the wiring portion 28b, and penetrates the upper layer 27b of the polyimide film 27. The pad portion 28d is provided on the upper layer 27b of the polyimide film 27 and connected to the conductive portion 28c. The conductive portion 28c and the pad portion 28d are provided in an area away from the area directly above the pad 22. The bump 40 is bonded to the upper surface of the pad portion 28d.

[0040] A barrier metal layer 29 is provided between the lower layer 27a of the polyimide film 27 and the rewiring layer 28. The barrier metal layer 29 contains, for example, copper (Cu) and titanium (Ti). In this way, the rewiring region 22c of the pad 22 is connected to the bump 40 via the barrier metal layer 29, the contact portion 28a of the rewiring layer 28, the wiring portion 28b, the conductive portion 28c, and the pad portion 28d.

[0041] like Figure 4 as well as Figure 6 As shown, the ends of the pads 23 used are covered by the passivation film 26, and the portions of the pads 23 other than the ends are exposed from the passivation film 26. In addition, the lower layer 27a of the polyimide film 27 does not cover the pads 23. Therefore, the resin member 60 is in contact with the pads 23. The wires 41 are bonded to the pads 23.

[0042] like Figure 4 as well as Figure 7 As shown in the figure, the end of the unused pad 24 is also covered by the passivation film 26, and the portion of the pad 24 other than the end is exposed from the passivation film 26. On the other hand, the pad 24 is entirely covered by the lower layer 27a of the polyimide film 27. Therefore, in the area directly above the pad 24, the resin member 60 is in contact with the lower layer 27a of the polyimide film 27, and is not in contact with the passivation film 26. In addition, the wire 41 is not bonded to the pad 24. Moreover, the pad 24 is not connected to the rewiring layer 28, and therefore, is not connected to the bump 40.

[0043] Next, a part of the method for manufacturing the semiconductor package according to the present embodiment will be described.

[0044] Figure 8 (a) to (f) are cross-sectional views showing a method for manufacturing a semiconductor package according to the present embodiment.

[0045] In addition, Figure 8 In (a) to (f), only the periphery of the pad 22 is shown.

[0046] like Figure 8 As shown in (a), a semiconductor chip 20 is prepared. In the semiconductor chip 20, pads 22 to 24 and a passivation film 26 are provided on a chip body 21. The pads 22 to 24 are formed of, for example, aluminum. The electrical properties of the semiconductor chip 20 have been inspected, and a probe mark P is formed in the probe area 22b of the pad 22. The shape of the probe mark P is, for example, a crater shape, and a ring-shaped convex portion P2 is formed around the concave portion P1.

[0047] The passivation film 26 covers the area between the pads in the upper surface of the chip body 21, the peripheral portion of the pad 22, the peripheral portion of the pad 23, and the peripheral portion of the pad 24. On the other hand, the passivation film 26 does not cover the portion other than the peripheral portion of the pad 22, the portion other than the peripheral portion of the pad 23, and the portion other than the peripheral portion of the pad 24.

[0048] Next, if Figure 8 As shown in (b), the lower layer 27a of the polyimide film 27 is formed. The lower layer 27a is formed on the passivation film 26. The lower layer 27a is also formed on the probe region 22b of the pad 22. Thus, the probe mark P is covered by the lower layer 27a.

[0049] Next, if Figure 8 As shown in (c), copper or titanium is deposited to form a barrier metal layer 29 on the entire surface.

[0050] Next, if Figure 8 As shown in (d) of FIG. 1 , a resist pattern 101 is formed. In the resist pattern 101 , an opening 101 a is formed in a region directly above the rewiring region 22 c of the pad 22 .

[0051] Next, if Figure 8 As shown in (e), the resist pattern 101 is used as a mask to deposit copper and nickel, thereby forming the contact portion 28a and the wiring portion 28b of the rewiring layer 28 in the opening 101a of the resist pattern 101. The contact portion 28a is formed in the lower layer 27a of the polyimide film 27, and the wiring portion 28b is formed on the lower layer 27a. The contact portion 28a is connected to the rewiring region 22c of the pad 22 via the barrier metal layer 29.

[0052] Next, if Figure 8 As shown in (f), for example, the resist pattern 101 is dissolved and removed by contact with a chemical solution. Originally, the pads 22 to 24 made of aluminum are susceptible to the chemical solution. However, since the bonding area 22a of the pad 22 is covered by the barrier metal layer 29, it will not be damaged by the chemical solution. In addition, since the probe area 22b of the pad 22 is covered by the lower layer 27a of the polyimide film 27, it will naturally not be damaged by the chemical solution. Moreover, the rewiring area 22c of the pad 22 is covered by the lower layer 27a of the polyimide film 27, the contact part 28a of the rewiring layer 28, and the wiring part 28b, so it will not be damaged by the chemical solution.

[0053] Next, if Figure 4 to Figure 7 As shown, etching is performed to remove the portion of the barrier metal layer 29 that is not covered by the rewiring layer 28. Next, the upper layer 27b of the polyimide film 27 is formed. Next, the conductive portion 28c and the pad portion 28d of the rewiring layer 28 are formed. The conductive portion 28c is formed in the upper layer 27b of the polyimide film 27, and the pad portion 28d is formed on the upper layer 27b.

[0054] Next, if Figure 1 , Figure 4 to Figure 7 As shown, the pad portion 28d of the rewiring layer 28 is bonded to the bump 40. In addition, the bump pad region 20a of the semiconductor chip 20 is also bonded to the bump 40. Thus, the bumps 40 are connected to each other via the pad and the rewiring layer 28. Next, the bump 40 is bonded to the semiconductor chip 30. Thus, the semiconductor chip 30 is connected to the semiconductor chip 20. Next, the bottom filler 50 is filled between the semiconductor chip 20 and the semiconductor chip 30 and around the semiconductor chip 30. In addition, the bottom filler 50 may be filled only between the semiconductor chip 20 and the semiconductor chip 30. Next, the semiconductor chip 20 is mounted on the mounting substrate 10 via the bonding component 42. Next, the bonding region 22a of the pad 22 and the pad 23 are bonded to one end of the wire 41. The other end of the wire 41 is bonded to the upper surface wiring layer 13 of the mounting substrate 10. Thus, each terminal of the semiconductor chip 20 is connected to each terminal of the mounting substrate 10.

[0055] Next, a liquid resin material is placed on the mounting substrate 10 to cover the semiconductor chip 20, the semiconductor chip 30, the bottom filler 50, the wire 41, the bump 40, etc. Next, the resin material is cured. Thus, the resin component 60 is formed. At this time, since most of the passivation film 26 is covered by the polyimide film 27, it does not contact the resin component 60. In this way, the semiconductor package 1 is manufactured.

[0056] Next, the effects of this embodiment will be described.

[0057] In this embodiment, Figure 8 In the step (b) shown in FIG. 1 , the probe mark P formed in the probe area 22b of the pad 22 is covered by the lower layer 27a of the polyimide film 27. Figure 8 In the process shown in (f), when a chemical solution is used to remove the resist pattern 101, the chemical solution is blocked by the lower layer 27a and does not contact the probe area 22b. As a result, the pad 22 can be prevented from being damaged by the chemical solution. Therefore, the reliability of the semiconductor device 91 of this embodiment is high.

[0058] In addition, in this embodiment, if Figure 7 As shown, the portion of the passivation film 26 disposed in the region directly above the pad 24 is covered by the polyimide film 27. In addition, the portion of the passivation film 26 disposed between the pads is also covered by the polyimide film 27. Therefore, in the above region, the resin member 60 does not contact the passivation film 26. Thus, the contact area between the resin member 60 and the passivation film 26 can be reduced.

[0059] The resin member 60 made of a resin material has low adhesion to the passivation film 26 made of an inorganic material. Therefore, if the contact area between the resin member 60 and the passivation film 26 is large, the resin member 60 is easily peeled off from the passivation film 26 when thermal stress is generated in the semiconductor package 1. If the resin member 60 is peeled off from the passivation film 26, the wire 41 may be pulled up by the resin member 60 and detached from the bonding area 22a of the pad 22 and the pad 23, resulting in a short circuit failure.

[0060] In this embodiment, since the resin member 60 is in contact with the polyimide film 27 in the region just above the pad 24 and the region just above the pads, the contact area between the resin member 60 and the passivation film 26 is small. The polyimide film 27 as an organic insulating film has good adhesion to the resin member 60. Therefore, it is possible to suppress the peeling of the resin member 60 from the passivation film 26 and suppress the occurrence of a short circuit fault.

[0061] Next, a comparative example will be described.

[0062] Fig. 9(a) to (f) are cross-sectional views showing a method for manufacturing a semiconductor package according to this comparative example.

[0063] like Fig. 9 As shown in (a) of FIG. 1 , a semiconductor chip 20 is prepared. The configuration of the semiconductor chip 20 is the same as that of the above-described embodiment, and a probe mark P is formed in the probe region 22 b of the pad 22 .

[0064] Next, if Fig. 9 As shown in (b), the lower layer 27a of the polyimide film 27 is formed. In this comparative example, the lower layer 27a is not formed on the probe region 22b of the pad 22. In addition, the lower layer 27a is not formed on the pad 24 that is not used.

[0065] Next, if Fig. 9 As shown in (c), the barrier metal layer 29 is formed on the entire surface. Although the barrier metal layer 29 is also formed on the probe mark P, due to the unevenness of the probe mark P, there may be a non-covered portion 29a that is not fully covered by the barrier metal layer 29.

[0066] Next, if Fig. 9 As shown in (d) of FIG. 1 , a resist pattern 101 is formed. An opening 101 a is formed in the resist pattern 101 . The resist pattern 101 is also in contact with the non-covered portion 29 a of the barrier metal layer 29 .

[0067] Next, if Fig. 9 As shown in FIG. 5 (e), the contact portion 28a and the wiring portion 28b of the rewiring layer 28 are formed in the opening portion 101a of the resist pattern 101.

[0068] Next, if Fig. 9 As shown in (f), the resist pattern 101 is dissolved and removed by contact with the chemical solution. At this time, the chemical solution contacts the pad 22 via the non-covered portion 29a of the barrier metal layer 29. As a result, the pad 22 is dissolved and damaged, resulting in damage 22d.

[0069] After that, the resin component 60 is formed by the same process as the above-mentioned embodiment. At this time, the resin component 60 contacts the passivation film 26 in the area just above the pad 24 and in the area between the pads. Therefore, the contact area between the resin component 60 and the passivation film 26 becomes larger. As a result, when thermal stress is generated in the semiconductor package after manufacturing, the resin component 60 is easily peeled off from the passivation film 26. As a result, the wire 41 covered by the resin component 60 is also displaced upward and easily detached from the bonding area 22a of the pad 22 and the pad 23. If the wire 41 detaches from the pad 22 or 23, a circuit breaker failure occurs.

[0070] In contrast, according to the above-described embodiment, since the polyimide film 27 as an organic insulating film covers the probe mark P and the pad 24, damage to the pad 22 caused by the chemical solution for removing the resist pattern 101 can be avoided, and a disconnection failure of the wire 41 can also be suppressed. As a result, a semiconductor package with high reliability can be manufactured.

[0071] According to the embodiments described above, a semiconductor device and a semiconductor package with high reliability can be realized.

[0072] The above describes the embodiments of the present invention, but the embodiments are shown as examples and are not intended to limit the scope of the invention. The new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are included in the scope of the invention and its equivalents recorded in the claims.

Claims

1. A semiconductor device comprising: A first semiconductor chip having a first pad and a second pad separated from the first pad and having a recess, wherein the second pad is provided with a bonding area for wire bonding, a probe area against which a probe is pressed when inspecting electrical characteristics, and a rewiring area connected to a rewiring layer; an organic insulating film, provided on the first semiconductor chip, covering the recessed portion but not covering the bonding region and the rewiring region of the second pad; and The rewiring layer has a lower portion connected to the rewiring region of the second pad and an upper portion disposed on the organic insulating film. A wire is bonded to the bonding area in the second pad, The first semiconductor chip further has a fourth pad, The organic insulating film covers the fourth pad, The fourth pad is not connected to the redistribution layer.

2. The semiconductor device according to claim 1, The first semiconductor chip further includes a third pad adjacent to the first pad, and an inorganic insulating film disposed between the first pad and the third pad. The organic insulating film is provided on the inorganic insulating film.

3. A semiconductor package comprising: The semiconductor device according to claim 1 or 2; a bump engaged with the redistribution layer; and A resin member covers the first semiconductor chip, the organic insulating film, an upper portion of the rewiring layer, and the bumps.

4. A semiconductor package comprising: A first semiconductor chip has a first pad and a second pad, wherein the first pad is set with a bonding area for wire bonding, a probe area to which a probe is pressed when inspecting electrical characteristics, and a rewiring area connected to a rewiring layer; an organic insulating film, not covering the bonding region and the rewiring region of the first pad, and covering the second pad; The rewiring layer has a lower portion connected to the rewiring region of the first pad and an upper portion disposed on the organic insulating film; a protrusion engaged with the redistribution layer; as well as a resin member covering the first semiconductor chip, the organic insulating film, an upper portion of the rewiring layer, and the bumps, A wire is bonded to the bonding area in the first pad, The first semiconductor chip further has a fourth pad, The organic insulating film covers the fourth pad, The fourth pad is not connected to the redistribution layer.

5. The semiconductor package according to claim 4, The second pad is not connected to the bump.

6. The semiconductor package according to any one of claims 3 to 5, further comprising a second semiconductor chip connected to the bump, The resin member also covers the second semiconductor chip.

7. The semiconductor package according to claim 6, A DRAM is formed on the first semiconductor chip. A logic circuit is formed on the second semiconductor chip.

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