Transistor with segmented epitaxial semiconductor layer

Abstract

The present invention relates to a transistor with a segmented epitaxial semiconductor layer, and discloses a structure of a field effect transistor and a method for forming the structure of the field effect transistor. A first and a second gate structure extend above a semiconductor body, and the second gate structure extends above the semiconductor body. A source / drain region is laterally located between the first gate structure and the second gate structure. The source / drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first segment and a second segment. The second semiconductor layer is laterally located between the first segment of the first semiconductor layer and the second segment of the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits, and more particularly to a structure of a field effect transistor and a method for forming the structure of a field effect transistor. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) process can be used to create a combination of p-type and n-type field effect transistors, which are used as devices to construct, for example, logic cells. A field effect transistor typically includes a source, a drain, a channel region between the source and the drain, and a gate electrode superimposed on the channel region. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and the drain, thereby generating a device output current. A field effect transistor may include multiple gates superimposed on multiple channel regions.

[0003] The source and drain of a field effect transistor can be formed simultaneously. One method is to implant ions containing n-type dopants or p-type dopants into regions of the semiconductor body to provide the source and drain. Another method is to epitaxially grow sections of semiconductor material from the semiconductor body to form the source and drain. The semiconductor material can be doped in situ with n-type dopants or p-type dopants during epitaxial growth.

[0004] Wide gate spacing in a multi-gate field effect transistor may cause underfilling of the semiconductor material epitaxially grown in the cavity to provide the source and drain. This underfilling may degrade device performance, for example, by reducing radio frequency performance indicators such as power gain. This underfilling may also degrade other performance indicators. For example, it may reduce the drain current (Idsat) when the transistor is biased in the saturation region and may increase contact resistance. This underfilling may also cause contact disconnection problems.

[0005] There is a need for improved field effect transistor structures and methods of forming field effect transistor structures. Summary of the invention

[0006] In one embodiment of the present invention, a structure for a field effect transistor is provided. The structure includes: a semiconductor body, a first gate structure extending above the semiconductor body, a second gate structure extending above the semiconductor body, and a source / drain region laterally located between the first gate structure and the second gate structure. The source / drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first section and a second section. The second semiconductor layer is laterally located between the first section of the first semiconductor layer and the second section of the first semiconductor layer.

[0007] In one embodiment of the present invention, a method of forming a structure for a field effect transistor is provided. The method includes: forming a first gate structure extending above a semiconductor body, forming a second gate structure extending above the semiconductor body, and forming a first semiconductor layer on the semiconductor body between the first gate structure and the second gate structure. The method also includes forming a first section of the second semiconductor layer laterally located between the first gate structure and the first semiconductor layer, and forming a second section of the second semiconductor layer laterally located between the second gate structure and the first semiconductor layer. The first semiconductor layer and the first and second sections of the second semiconductor layer are components of the source / drain region of the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of these embodiments made below, are used to explain these embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0009] Figure 1-6 A cross-sectional view showing the structure of a field effect transistor at successive manufacturing stages of a processing method according to an embodiment of the present invention.

[0010] Figure 7 Display in Figure 6 A cross-sectional view of the structure following a manufacturing stage of the process.

[0011] Fig. 7A , 7B 7C shows a vertical axis generally parallel to the gate structure. Figure 7 Cross-sectional views of different parts of the structure.

[0012] Figure 8 Display in Figure 7 A cross-sectional view of the structure following a manufacturing stage of the process. DETAILED DESCRIPTION

[0013] Please refer to Figure 1 According to an embodiment of the present invention, the field effect transistor structure 10 includes a fin 12 disposed above a substrate 14 and protruding upward from the substrate. The fin 12 and the substrate 14 may be composed of a single crystal semiconductor material, such as single crystal silicon. The fin 12 may be formed by patterning the substrate 14 using a photolithography and etching process, or by a self-aligned multi-patterning process. The shallow trench isolation 16 ( Fig. 7A , 7B, 7C) can surround the lower section 60 of the fin 12. The upper section 62 of the fin 12 is exposed above the top surface of the shallow trench isolation 16. The fin 12 defines a semiconductor body that can be used to form a field effect transistor. The upper section 62 of the fin 12 includes the top surface 11.

[0014] The gate structures 18 extend laterally above the fins 12 and across the fins 12 and the shallow trench isolations 16 along the corresponding longitudinal axes. Each gate structure 18 is aligned laterally with respect to the fins 12, overlapping and covering the top surface 11 and the side surfaces of the upper section 62 of the fins 12. Each gate structure 18 may include a dummy gate 20 composed of a conductor, such as polysilicon, and a dielectric layer 22 composed of an electrical insulator, such as silicon dioxide. A gate cap 21 may be disposed above each gate structure 18.

[0015] Sidewall spacers 24 are disposed adjacent to the side surfaces or sidewalls 19 of each gate structure 18. The sidewall spacers 24 may be formed by depositing a conformal layer of dielectric material (eg, low-k dielectric material) and etching the deposited conformal layer using an anisotropic etching process such as reactive ion etching.

[0016] Doped regions 26 and 28 may be formed in an upper section 62 of the fin 12 and disposed between side spacers 24 on the gate structure 18. The doped regions 26 and 28 contain a certain concentration of n-type or p-type dopants. The doped regions 26 and 28 may be formed by an ion implantation process that introduces energetic ions, as indicated by a single arrow, with the ion trajectory stopping within a depth range in the fin 12. The ions may be generated from a suitable source gas and implanted into the fin 12 using an ion implantation tool under given implantation conditions. The implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) may be selected to adjust the characteristics (e.g., depth distribution) of the doped regions 26 and 28. An implantation mask may be temporarily formed over other areas of the substrate 14 for forming different types of field effect transistors.

[0017] In one embodiment, doped regions 26, 28 may be formed simultaneously in fin 12 by implanting ions of a p-type dopant (e.g., boron) that provides p-type conductivity. In an alternative embodiment, doped regions 26, 28 may be formed simultaneously in fin 12 by implanting ions of an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type conductivity. In one embodiment, the dopant concentrations of doped regions 26, 28 may be equal or substantially equal. Gate structure 18 and sidewall spacers 24 may be used to self-align the ion implantation process.

[0018] In an alternative embodiment, doped regions 26 , 28 may be omitted from the device construction, thereby not changing the doping (if any) of fin 12 .

[0019] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1 In the next manufacturing stage, a conformal layer 30 is deposited as a liner over the gate cap 21, the sidewall spacers 24, and the doped regions 26 and 28 on the gate structure 18. The conformal layer 30 may be composed of, for example, amorphous carbon and may be deposited by, for example, atomic layer deposition. The material of the conformal layer 30 may be selected to be different from the material of the gate cap 21 and the sidewall spacers 24 to facilitate subsequent etching processes.

[0020] Please refer to Figure 3 , wherein similar reference numerals denote Figure 2 and in the next manufacturing stage, an anisotropic etching process is used to etch the conformal layer 30 ( Figure 2 ) to form spacers 34. The etching process may be a reactive ion etching process that selectively etches the material constituting the spacers 34 relative to the material of the gate cover 21, the side spacers 24, and the fins 12. The term "selective" as used herein when referring to a material removal process (e.g., etching) means that the material removal rate (i.e., etching rate) of the target material is higher than the material removal rate (i.e., etching rate) of at least another material exposed to the material removal process. The spacers 34 (which are temporary structural components) may have a height relative to the top surface 11 of the fin 12 that is substantially the same as the side spacers 24. The openings 32 are defined between the spacers 34 and extend in a vertical direction to the doped regions 26, 28. Since the conformal layer 30 is removed by the etching process, the top surface 11 of the fin 12 located above each doped region 26, 28 is exposed at the bottom of the opening 32.

[0021] Please refer to Figure 4 , wherein similar reference numerals denote Figure 3 and in the next manufacturing stage, from the top surface 11 ( Figure 7B ) epitaxially grows layer 36 in segments. Layer 36 may be composed of a semiconductor material. The material of semiconductor layer 36 may be selected relative to the material of fin 12 so that fin 12 may be selectively etched relative to semiconductor layer 36. In one embodiment, layer 36 may be composed of silicon-germanium. The material of semiconductor layer 36 may be selected relative to the material of fin 12 so that fin 12 and semiconductor layer 36 are not selectively etched. In an alternative embodiment, layer 36 may be composed of silicon or silicon-phosphorus.

[0022] The semiconductor layer 36 may be in direct contact with the top surface 11 of the fin 12 above each of the doped regions 26, 28. The epitaxial growth process may be selective because the material of the semiconductor layer 36 does not grow from dielectric surfaces such as the surface of the shallow trench isolation 16, the gate cap 21, the sidewall spacers 24, and the spacers 34. Due to the constraints provided during the epitaxial growth, the semiconductor layer 36 is formed in a segment having the same width as the opening 32.

[0023] The thickness of the semiconductor layer 36 (which may be measured in a vertical direction relative to a reference plane defined by the top surface 11 of the fin 12) relative to the same reference plane is less than the height of the spacers 34. Portions of the doped regions 26, 28 covered by the spacers 34 are not covered by the segments of the epitaxially grown semiconductor layer 36. Each segment of the semiconductor layer 36 may have a width w that is less than the spacing s between the side spacers 24 on adjacent gate structures 18.

[0024] Please refer to Figure 5 , wherein similar reference numerals denote Figure 4 3 and, at a next manufacturing stage, the spacers 34 are removed to expose portions of the doped regions 26, 28 that were previously covered by the spacers 34 and not covered by the segments of the semiconductor layer 36. The spacers 34 may be removed by an etching process that is selective with respect to the semiconductor material of the layer 36, thereby leaving the segments of the layer 36 intact and covering the corresponding portions of the doped regions 26, 28. The etching process may also selectively remove the spacers 34 with respect to the gate capping body 21 and the side spacers 24. The corresponding portions of the doped regions 26, 28 covered by the segments of the semiconductor layer 36 may be equidistant from the gate structures 18 of the adjacent pair.

[0025] Please refer to Figure 6 , wherein similar reference numerals denote Figure 5 , and in the next manufacturing stage, cavities 38, 40 are formed in the fins 12 between each adjacent pair of gate structures 18. The cavities 38, 40 may extend into the fins 12 to a given depth d. The cavities 38, 40 may be formed by an etching process that is selective to the gate cover 21 and the side spacers 24. The segments of the semiconductor layer 36 act as a protective cover during the etching process to mask and laterally maintain the portion 41 of the fin 12 between the cavities 38 and 40 in various cases. The segments of the semiconductor layer 36 may be corroded and shortened by the etching process, rather than consumed and removed. In one embodiment, the thickness of the segments of the semiconductor layer 36 may be greater than the depth of the cavities 38, 40. The segments of the semiconductor layer 36 are located above the portions 41 of the fins 12. In one embodiment, the segments of the semiconductor layer 36 have substantially the same width as the portions 41 of the fins 12. In one embodiment, the segments of the semiconductor layer 36 are in direct contact with the portions 41 of the fins 12.

[0026] The formation of cavities 38, 40 removes portions of doped regions 26, 28 adjacent to portion 41 of fin 12. Portions of doped regions 26 and portions of doped regions 28 remain intact in corresponding portions 41 of fin 12. In one embodiment, the depth of cavities 38, 40 may be equal to or substantially equal to the thickness of doped regions 26, 28.

[0027] Please refer to Figure 7 , 7A , 7B, 7C, wherein similar reference numerals denote Figure 6 1 and 12. The fin 12 is provided with a structure similar to that in the embodiment of the present invention, and in the next manufacturing stage, an epitaxial semiconductor material layer 42 is grown in the form of corresponding segments from the surface of the fin 12 bordering the cavities 38, 40, and in particular from the top surface 11 and the side surface 13 of the portion 41 of the fin 12 between the cavities 38, 40. The segments of the epitaxial semiconductor layer 42 are independently grown inside each cavity 38, 40, thereby providing a significantly larger surface area for epitaxial growth compared to a single large cavity. The epitaxial semiconductor layer 42 can extend laterally from the space between the gate structures 18 and provide a cladding on the segments of the semiconductor layer 36, and the segments of the semiconductor layer 36 are embedded in the epitaxial semiconductor layer 42. Each segment of the epitaxial semiconductor layer 42 is partially located in one of the cavities 38, 40 and partially extends above the top surface 11 of the fin 12. Different segments of the epitaxial semiconductor layer 42 merge over the associated segments of the semiconductor layer 36.

[0028] The epitaxial growth process may be selective in that the semiconductor material is not grown from dielectric surfaces, such as the surfaces of the shallow trench isolation 16, the gate cap 21, and the sidewall spacers 24. The epitaxial semiconductor layer 42 may be doped in situ during the epitaxial growth with a concentration of dopants. In one embodiment, the epitaxial semiconductor layer 42 may have the same conductivity type as the doped regions 26, 28. In one embodiment, the epitaxial semiconductor layer 42 may be doped in situ during the epitaxial growth with an n-type dopant, such as phosphorus and / or arsenic, that provides n-type conductivity. In an alternative embodiment, the epitaxial semiconductor layer 42 may be doped in situ during the epitaxial growth with a p-type dopant, such as boron, that provides p-type conductivity. The epitaxial semiconductor layer 42 may have a composition containing germanium and silicon, and in one embodiment, the epitaxial semiconductor layer 42 may be composed of silicon-germanium. In one embodiment, the epitaxial semiconductor layer 42 may be composed of silicon and may contain an n-type dopant, such as phosphorus. In an alternative embodiment, the epitaxial semiconductor layer 42 may be composed of silicon-germanium and may include a p-type dopant, such as boron.

[0029] The segments of the epitaxial semiconductor layer 42 in each pair of cavities 38, 40 contact the portions 41 of the fin 12 between the cavities 38 and 40. The semiconductor layer 42 is also in direct contact with the segments of the semiconductor layer 36 located on the respective portions 41 of the fin 12. The segments of the epitaxial semiconductor layer 42 located in each cavity 38 may be in direct contact with one side surface 13 of the portion 41 of the fin 12 and the overlying segments of the semiconductor layer 36, and the segments of the epitaxial semiconductor layer 42 located in each cavity 40 may be in direct contact with the opposite side surface 13 of the portion 41 of the fin 12 and the overlying segments of the semiconductor layer 36. Portions of the doped regions 26, 28 are respectively included in the portions 41 of the fin 12 below the segments of the semiconductor layer 36. The portions 41 of the fin 12 define the separation between the segments of the epitaxial semiconductor layer 42 in the cavities 38 and the segments of the epitaxial semiconductor layer 42 in the cavities 40. Portions 43 of fin 12 define a separation between a section of epitaxial semiconductor 42 in cavity 38 and a section of epitaxial semiconductor layer 42 in cavity 40 .

[0030] Please refer to Figure 8 , wherein similar reference numerals denote Figure 7 , and in the next manufacturing stage, a replacement gate process is performed to replace the gate structure 18 with gate structures 46, 47, 48 and complete the structure 10 of the field effect transistor. The gate structures 46, 47, 48 may include an electrode layer 64 composed of one or more metal gate materials (e.g., work function metals), and a gate dielectric layer 66 composed of a dielectric material (e.g., a high-k dielectric material such as hafnium oxide).

[0031] The structure 10 includes a source / drain region 50 provided by a doped region 26 in a segment of the semiconductor layer 42, a segment of the semiconductor layer 36, and a portion 41 of the fin 12. The structure 10 includes a source / drain region 52 provided by a doped region 28 in a segment of the semiconductor layer 42 and a portion 41 of the fin 12. The term "source / drain region" as used herein refers to a doped region of semiconductor material that can serve as a source or drain of a field effect transistor. In one embodiment, the source / drain region 50 can provide a source in the structure 10, and the source / drain region 52 can provide a drain in the structure 10. In an alternative embodiment, the source / drain region 50 can provide a drain in the structure 10, and the source / drain region 52 can provide a source in the structure 10. The source / drain regions 50, 52 are doped to have a conductivity type of the same polarity. The fin 12 provides a semiconductor body for forming the source / drain regions 50, 52, and the source / drain regions 50, 52 have a symmetrical arrangement.

[0032] The channel region 55 is disposed between the source / drain region 50 and the source / drain region 52 and in a portion of the fin 12 below the overlying gate structure 47. The segments of the semiconductor layer 36 included in the source / drain region 50 are laterally separated from the sidewall spacers 24 on the adjacent sidewalls 49 of the gate structures 46 and 47 by distances d1 and d2, respectively. In one embodiment, the distances d1 and d2 may be equal or substantially equal. Similarly, the segments of the semiconductor layer 36 included in the source / drain region 52 are laterally separated from the sidewall spacers 24 on the adjacent sidewalls 49 of the gate structures 47 and 48 by distances d1 and d2, respectively.

[0033] Then, the middle process and back-end process are performed, including forming contacts, vias, and interconnection structures coupled to the field effect transistor. Contacts 56 in the interlayer dielectric layer 58 of the interconnection structures are coupled to the source / drain regions 50 and 52 .

[0034] The source / drain regions 50, 52 may present improvements in filling with the epitaxial semiconductor material of the epitaxial semiconductor layer 42. Relying on smaller cavities 38, 40 rather than a single larger cavity provides a larger seed area and a smaller fill volume for epitaxial growth, and may compensate for a larger gate spacing to mitigate underfilling. Thus, the source / drain regions 50, 52 may include a larger overall volume of epitaxial semiconductor material. The presence of segments of the semiconductor layer 36 (embedded in segments of the epitaxial semiconductor layer 42) may be used to reduce contact resistance. The structure 10 may include additional gate structures with wider gate spacings, and the source / drain regions 52, 54 may be repeated for pairs of gate structures to form multi-gate field effect transistors for radio frequency integrated circuits.

[0035] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects or embedded interconnects). In any case, the chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product.

[0036] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0037] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0038] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intermediate feature.

[0039] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a field effect transistor, the structure comprising: Semiconductor substrate; A semiconductor fin protrudes from the semiconductor substrate, the semiconductor fin comprising a first section and a second section located between the first section and the semiconductor substrate, and the first section of the semiconductor fin comprises a first cavity and a second cavity; A first gate structure extending above the semiconductor fin; a second gate structure extending above the semiconductor fin; as well as A first source / drain region is laterally located between the first gate structure and the second gate structure, the first source / drain region includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer has a first segment located in the first cavity and a second segment located in the second cavity, and the second semiconductor layer is laterally located between the first segment of the first semiconductor layer and the second segment of the first semiconductor layer.

2. The structure of claim 1, wherein: The semiconductor fin includes a portion laterally located between the first cavity and the second cavity.

3. The structure of claim 2, wherein: The second semiconductor layer is located on the portion of the semiconductor fin.

4. The structure of claim 3, wherein: The second semiconductor layer directly contacts the portion of the semiconductor fin.

5. The structure of claim 2, wherein: The portion of the semiconductor fin includes a doped region containing a dopant.

6. The structure of claim 2, wherein: The portion of the semiconductor fin has substantially the same width as the second semiconductor layer.

7. The structure of claim 2, wherein: The first section of the first semiconductor layer located in the first cavity directly contacts the portion of the semiconductor fin, and the second section of the first semiconductor layer located in the second cavity directly contacts the portion of the semiconductor fin.

8. The structure of claim 1, wherein: The semiconductor fin has a top surface, and the first section and the second section of the first semiconductor layer include respective portions that merge above the top surface of the semiconductor fin.

9. The structure of claim 1, wherein: The semiconductor fin has a top surface, and the second semiconductor layer directly contacts the top surface of the semiconductor fin.

10. The structure of claim 1, further comprising: A contact is connected to the first source / drain region.

11. The structure of claim 1, wherein: The second semiconductor layer is composed of a semiconductor material containing germanium.

12. The structure of claim 1, wherein: The second semiconductor layer is composed of silicon-germanium.

13. The structure of claim 1, further comprising: The second source / drain region includes a third semiconductor layer and a fourth semiconductor layer, wherein the third semiconductor layer has a first section and a second section, and the fourth semiconductor layer is laterally located between the first section of the third semiconductor layer and the second section of the third semiconductor layer. The first gate structure is laterally located between the first source / drain region and the second source / drain region.

14. A method of forming a structure for a field effect transistor, the method comprising: forming a first gate structure extending above the semiconductor fin; forming a second gate structure extending above the semiconductor fin; forming a first cavity and a second cavity in a first section of the semiconductor fin, wherein the semiconductor fin includes a second section located between the first section and the semiconductor substrate; forming a first semiconductor layer on the semiconductor fin between the first cavity and the second cavity; forming a first section of a second semiconductor layer, wherein the first section of the second semiconductor layer is located in the first cavity; and forming a second section of the second semiconductor layer, wherein the second section of the second semiconductor layer is located in the second cavity, In which, the first semiconductor layer is laterally located between the first segment of the second semiconductor layer and the second segment of the second semiconductor layer, and the first semiconductor layer, the first segment of the second semiconductor layer, and the second segment of the second semiconductor layer are components of the source / drain region of the field effect transistor, and the source / drain region of the field effect transistor is laterally located between the first gate structure and the second gate structure.

15. The method of claim 14, wherein: The first section of the first semiconductor layer is epitaxially grown in the first cavity, and the second section of the first semiconductor layer is epitaxially grown in the second cavity.

16. The method of claim 15, wherein: The semiconductor fin includes a portion located between the first cavity and the second cavity, and the second semiconductor layer is located on the portion of the semiconductor fin.

17. The method of claim 16, wherein: The portion of the semiconductor fin includes a doped region containing a dopant.

18. The method of claim 16, wherein: The first section of the first semiconductor layer located in the first cavity is in direct contact with the portion of the semiconductor fin, and the second section of the first semiconductor layer is in direct contact with the portion of the semiconductor fin.

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