Integrated circuit and method of forming the same

Abstract

Embodiments disclosed herein relate to an integrated circuit including metal rails. In one aspect, the integrated circuit includes a first layer and a second layer, the first layer including a first metal rail, the second layer including a second metal rail, wherein the second layer is above the first layer along a first direction. In one aspect, the integrated circuit includes a third layer, the third layer including an active area of ​​a transistor, wherein the third layer is above the second layer along the first direction. In one aspect, the integrated circuit includes a fourth layer, the fourth layer including a third metal rail, wherein the fourth layer is above the third layer along the first direction. In one aspect, the integrated circuit includes a fifth layer, the fifth layer including a fourth metal rail, wherein the fifth layer is above the fourth layer along the first direction. Embodiments of the present invention also relate to methods of forming an integrated circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods of forming the same. Background Art

[0002] Recently, the trend of integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide more functionality at higher speeds. The miniaturization process has also brought more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize and verify standard cell layout patterns for integrated circuits while ensuring that standard cell layout design and manufacturing specifications are met. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, an integrated circuit is provided, comprising: a first layer, comprising a first metal rail; a second layer, comprising a second metal rail, the second layer being above the first layer along a first direction; a third layer, comprising an active area of ​​a transistor, the third layer being above the second layer along the first direction; a fourth layer, comprising a third metal rail, the fourth layer being above the third layer along the first direction; and a fifth layer, comprising a fourth metal rail, the fifth layer being above the fourth layer along the first direction.

[0004] According to another aspect of an embodiment of the present invention, a method for forming an integrated circuit is provided, the method comprising: forming a first layer including a first metal track; forming a second layer including a second metal track, the second layer being above the first layer along a first direction; forming a third layer, the third layer including an active area of ​​a transistor, the third layer being above the second layer along the first direction; forming a fourth layer including a third metal track, the fourth layer being above the third layer along the first direction; and forming a fifth layer including a fourth metal track, the fifth layer being above the fourth layer along the first direction.

[0005] According to another aspect of an embodiment of the present invention, an integrated circuit is provided, comprising: a first layer, comprising an active region of a transistor; a second layer, comprising a first metal rail, the first metal rail being directly coupled to a first side of the active region of the transistor, and the second layer being above the first layer along a first direction; a third layer, comprising a second metal rail, the second metal rail being coupled to a second side of the active region of the transistor through a first through-hole contact, the second side being away from the first side, and the first layer being above the third layer along the first direction; and a fourth layer, comprising a third metal rail, the third metal rail being coupled to the second metal rail through a second through-hole contact, and the third layer being above the fourth layer along the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1C is a top plan view of a layout design of a circuit including back side power rails and back side metal rails according to one embodiment.

[0008] Figure 2A According to one embodiment Figures 1A to 1C A cross-sectional view of an integrated circuit formed by the layout design along I-I'.

[0009] Figure 2B According to one embodiment Figures 1A to 1C A cross-sectional view of an integrated circuit formed by the layout design along II-II'.

[0010] Figure 3A and 3B is a top plan view of a layout design for an integrated circuit including backside metal tracks according to one embodiment.

[0011] Figure 4A and 4B is a top plan view of a layout design for an integrated circuit including backside metal tracks according to one embodiment.

[0012] Figure 5A and 5B is a top plan view of a layout design for an integrated circuit including backside metal tracks according to one embodiment.

[0013] Fig. 6A and 6B is a top plan view of a layout design for an integrated circuit including backside metal tracks according to one embodiment.

[0014] Figure 6C According to one embodiment Fig. 6A and Figure 6B A cross-sectional view of an integrated circuit formed by the layout design along the line AA'.

[0015] Fig.6D According to one embodiment Fig. 6A and Figure 6B A cross-sectional view of an integrated circuit formed by the layout design along the BB' line.

[0016] Figure 7 is a top plan view of a layout design for an integrated circuit including backside metal tracks according to one embodiment.

[0017] Fig. 8Ais a schematic diagram of an example multiplexer circuit according to one embodiment.

[0018] Figure 8B According to an embodiment Fig. 8A A top plan view of an example layout design for a multiplexer circuit.

[0019] 9A to 9C According to an embodiment Fig. 8A A top plan view of a layout design of an example multiplexer circuit including backside metal tracks.

[0020] FIG. 10A to FIG. 10C According to an embodiment Fig. 8A A top plan view of a layout design of an example multiplexer circuit including backside metal tracks.

[0021] FIG. 11A to FIG. 11C According to an embodiment Fig. 8A A top plan view of a layout design of an example multiplexer circuit including backside metal tracks.

[0022] Fig. 12A and Fig. 12B According to an embodiment Fig. 8A A top plan view of a layout design of an example multiplexer circuit including backside metal tracks.

[0023] Fig.13A is a schematic diagram of an example multiplexer circuit according to one embodiment.

[0024] Fig. 13B According to an embodiment Fig.13A A top plan view of an example layout design for a multiplexer circuit.

[0025] FIG. 13C to FIG. 13D According to an embodiment Fig.13A A top plan view of a layout design of an example multiplexer circuit including backside metal tracks.

[0026] FIG. 13E to FIG. 13F According to an embodiment Fig.13A A top plan view of a layout design of an example multiplexer circuit including backside metal tracks.

[0027] FIG. 13G to FIG. 13I According to an embodiment Fig.13A A top plan view of a layout design of an example multiplexer circuit including backside metal tracks.

[0028] Fig.14A is a schematic diagram of an example circuit according to one embodiment.

[0029] Fig. 14BAccording to an embodiment Fig.14A Top plan view of the layout design of an example circuit.

[0030] Fig.15 is a flow chart of a method of manufacturing an integrated circuit according to some embodiments.

[0031] Fig.16 is a block diagram of a system for generating an IC layout design according to some embodiments.

[0032] Fig.17 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0034] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0035] According to some embodiments, the disclosure herein relates to an integrated circuit including a backside power rail and a backside wiring rail. In one aspect, the integrated circuit includes an active region, the active region forming a large number of transistors, a multilayer metal rail on the front side of the active region, and at least two layers of metal rails on the back side of the active region. The active region is a semiconductor structure having n-type doping or p-type doping. The metal rail on the front side of the active region can be referred to as a "front side metal rail", wherein the metal rail on the front side of the active region for providing electrical signals or serving as local interconnects can be referred to as a "front side interconnect rail". In addition, the metal rail on the back side of the active region can be referred to as a "back side metal rail", wherein the metal rail on the back side of the active region for providing power supply voltage or power can be referred to as a "back side power rail", and the metal rail on the back side of the active region for providing electrical signals or serving as local interconnects can be referred to as a "back side interconnect rail".

[0036] In some embodiments, the first layer of metal rails on the back side of the active area can be arranged closer to the active area than the metal rails on the front side, and provide a more reliable power supply voltage (e.g., VDD or GND) to the active area than the metal rails on the front side. In addition, the second layer of metal rails on the back side of the active area provides flexibility for wiring or electrically connecting different components in the integrated circuit. By implementing at least two layers of metal rails on the back side of the active area, an integrated circuit can be formed on a smaller area because the number of contacts and front metal rails can be reduced. In addition, the use of back metal rails allows the elements used to form the transistor (e.g., the active area, the metal overdiffusion (MD) region, or the gate region) to have a more regular or consistent shape, so that the characteristics of the transistor can become more consistent.

[0037] refer to Figures 1A to 1C , top plan views 100A to 100C of a layout design including layout patterns for manufacturing an integrated circuit according to one embodiment are shown. In one aspect, the top plan views 100A to 100C of the layout design show layout patterns for elements in different layers of the integrated circuit. The circuit formed according to the layout design in the top plan views 100A to 100C can be an inverting circuit. In one aspect, Figure 1A Layout patterns 110A and 110B corresponding to the backside power rails are shown. In one aspect, Figure 1B Layout patterns 130A and 130B corresponding to active areas of transistors are shown. In one aspect, Figure 1C Layout patterns 170A to 170E corresponding to front metal rails (eg, M0 metal rails) are shown. In some embodiments, the layout designs shown in top plan views 100A to 100C include Figures 1A to 1CIn some embodiments, the layout patterns of the layout designs shown in the top plan views 100A to 100C are different from those shown in the top plan views 100A to 100C. Figures 1A to 1C According to the layout design shown in the top plan views 100A to 100C, an integrated circuit can be manufactured or formed.

[0038] exist Figure 1B In the embodiment, layout patterns 120B and 130B indicate the size and / or position of N-type transistors (e.g., NMOS, N-type fin field effect transistors (FinFETs)). On the one hand, the layout pattern 120B extending in the Y direction corresponds to the gate region of the N-type transistor, and the layout pattern 130B extending in the X direction corresponds to the active region to form the source region and drain region of the N-type transistor. The gate region is a structure including one or more conductive parts, and the one or more conductive parts include one or more other conductive materials substantially surrounded by one or more insulating materials, for example, polysilicon, one or more metals and / or one or more suitable materials, and the one or more conductive parts are thereby configured to control the voltage provided to the lower layer or adjacent dielectric layer. The source region or the drain region is a semiconductor structure within the active region and is configured to have a doping type opposite to that of other parts of the active region. Layout patterns 120A, 120C may correspond to the gate regions of other transistors. On the one hand, layout patterns 165B, 165C extending in the Y direction correspond to the MD region to supply power to the N-type transistor or absorb current from the N-type transistor. The MD region is a conductive region or conductive structure that directly contacts the source region or the drain region. In some embodiments, the MD region includes one or more of the following: polysilicon, copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low-resistance electrical connection component between IC structural elements. For example, the gate region of the N-type transistor is formed at the intersection of the layout patterns 120B and 130B; the source region of the N-type transistor is formed at the intersection of the layout patterns 165C and 130B; and the drain region of the N-type transistor is formed at the intersection of the layout patterns 165B and 130B.

[0039] In one embodiment, layout patterns 120B and 130A indicate the size and / or position of a P-type transistor (e.g., PMOS or P-type FinFET). On the one hand, layout pattern 120B extending in the Y direction corresponds to the gate region of the P-type transistor, and layout pattern 130A extending in the X direction corresponds to the active region to form the source region and drain region of the P-type transistor. On the one hand, layout patterns 165A, 165B extending in the Y direction correspond to the MD region to supply power to the P-type transistor or absorb current from the P-type transistor. For example, the gate region of the P-type transistor is formed at the intersection of layout patterns 120B and 130A; the source region of the P-type transistor is formed at the intersection of layout patterns 165C and 130A; and the drain region of the P-type transistor is formed at the intersection of layout patterns 165B and 130A. In this structure, the drain region of the N-type transistor and the drain region of the P-type transistor are coupled to each other, and the gate region of the N-type transistor and the gate region of the P-type transistor are coupled to each other to form an inverter.

[0040] In one embodiment, the layout patterns 160A to 160D indicate the size and / or location of the through-hole contacts, which are used to make electrical contact with the back metal rails below the active area. Through the through-hole contacts formed according to the layout patterns 160A to 160D, an electrical signal (e.g., voltage or current) can be provided to or from the transistor. In some embodiments, the through-hole contacts include one or more of the following: copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low resistance electrical connection between different layers.

[0041] exist Figure 1AIn one embodiment, layout patterns 140A to 140D indicate the size and / or position of the back metal rail. The back metal rail may include metal or any conductive material. The back metal rail formed according to layout patterns 140A to 140D may be in the M-1 layer and may be implemented as a back interconnect rail. The back metal rail may be electrically connected to a transistor (e.g., a source region, a drain region, or a gate region) through a through-hole contact formed according to layout patterns 160A to 160D. In one embodiment, layout patterns 110A, 110B indicate the size and / or position of the back power rail. The back power rail may include metal or any conductive material. The back metal rail may be on the M-2 layer or on a lower layer. The back power rail formed according to layout patterns 110A, 110B may be electrically connected to the back metal rail formed according to layout patterns 140A to 140D through a through-hole contact formed according to layout patterns 150A to 150D. The layout patterns 110A, 110B, 140A, 140B, and 140C may extend in the X direction, the Y direction, or any direction.

[0042] In one structure, the layout patterns 110A, 110B for the back power rail may have a larger area with a regular structure to provide a reliable power supply voltage (e.g., VDD, GND). In one example, the back power rail formed according to the layout pattern 110A may provide a power supply voltage (e.g., VDD or 1V) to the source region of the P-type transistor through the back metal rail formed according to the layout pattern 140A. Similarly, the back power rail formed according to the layout pattern 110B may provide a power supply voltage (e.g., GND or 0V) to the source region of the N-type transistor through the back metal rail formed according to the layout pattern 140C. At the same time, the back metal rails formed according to the layout patterns 140B, 140D may extend in any direction to electrically couple to other transistors or metal rails for local connection.

[0043] exist Figure 1CIn one embodiment, layout patterns 170A to 170E indicate the size and / or position of the front metal rail. In one aspect, layout patterns 170A to 170E extend in the X direction. The front metal rail may include metal or any conductive material. The front metal rail may be an M0 layer. The front metal rail may be electrically connected to a transistor (e.g., a source region, a drain region, or a gate region) through a through-hole contact formed according to layout patterns 175, 180. For example, a metal rail formed according to layout pattern 170A may be electrically coupled to a drain region of a P-type transistor through an MD region formed according to layout pattern 165B and a through-hole contact formed according to layout pattern 175. For example, a metal rail formed according to layout pattern 170D may be electrically coupled to a common gate region of an N-type transistor and a P-type transistor through a through-hole contact formed according to layout pattern 180. In some embodiments, according to Figures 1A to 1C The layout pattern shown forms an integrated circuit that includes additional layers (eg, M1 through M7) for front-side metal tracks.

[0044] In one aspect, the back power rails and back interconnect rails disclosed herein provide several advantages. In one example, an integrated circuit can be formed with a smaller area because the number of front metal rails and through-hole contacts can be reduced. For example, by implementing the back interconnect rails, the gate density can be increased by 4% or more compared to not implementing the back interconnect rails. In addition, in one example, the MD region or gate region used to form the transistor can have a more regular or more consistent shape, so that the characteristics of the transistor can be more consistent.

[0045] Figure 2A According to one embodiment Figures 1A to 1C The layout design forms a cross-sectional view 200A of an integrated circuit along II'. Figure 2B According to one embodiment Figures 1A to 1C The integrated circuit formed by the layout design is shown in a cross-sectional view 200B along II-II'.

[0046] refer to Figure 2A and Figure 2B, the integrated circuit includes a back power rail layer BM, the back power rail layer BM includes back power rails 210A, 210B formed according to layout patterns 110A and 110B. Along the Z direction, above the back power rail layer BM, a contact layer VB including via contacts 250A, 250C may be formed according to layout patterns 150A, 150C. Along the Z direction, above the contact layer VB, a back metal rail layer M-1 including back metal rails 240A to 240C may be formed according to layout patterns 140A to 140C. Along the Z direction, above the back metal rail layer M-1, a contact layer VDB including via contacts 260A to 260C may be formed according to layout patterns 160A to 160C. Along the Z direction, above the contact layer VDB, an epitaxial layer EPI including source / drain regions 262A to 262C may be formed at the intersection of the layout patterns 130A, 130B and the layout patterns 165A to 165C. Along the Z direction, above the epitaxial layer EPI, a conductive layer MD including MD regions 265A to 265C may be formed according to the layout patterns 165A to 165C. Along the Z direction, above the conductive layer MD, a contact layer VD including a via contact 275 may be formed according to the layout pattern 175. Along the Z direction, above the contact layer VD, a front metal layer M0 including a front metal track 270 may be formed according to the layout pattern 170A.

[0047] exist Figure 2A In one aspect, the back power rail 210A is configured to provide a power supply voltage VDD. A through-hole contact 250A is formed on the back power rail 210A along the Z direction. A back metal rail 240A is formed on the VB layer including the through-hole contact 250A along the Z direction. The back metal rail 240A can be implemented as a back interconnect rail below the source region 262A (e.g., in the opposite direction of the Z direction). A through-hole contact 260A is formed on the back metal rail 240A along the Z direction. A source region 262A of a P-type transistor is formed on the through-hole contact 260A along the Z direction. An MD region 265A is formed on the source region 262A along the Z direction. In one aspect, the MD region 265A is directly coupled to the source region 262A. In some embodiments, the MD region 265A can be used as a local interconnect rail for electrically connecting nearby elements (e.g., metal rails and / or source regions / drain regions / gate regions). In one aspect, the side or surface of the source region 262A facing the Z direction is directly coupled to the MD region 265A, and the side or surface of the source region 262A facing the opposite direction of the Z direction is directly coupled to the via contact 260A. In this structure, the power supply voltage VDD can be provided to the source region 262A and the MD region 265A through the via contact 250A, the back metal rail 240A, and the via contact 260A.

[0048] On the one hand, the back power rail 210B is configured to provide a power supply voltage GND. On the back power rail 210B along the Z direction, a through-hole contact 250C is formed. On the through-hole contact 250C along the Z direction, a back metal rail 240C is formed according to the layout pattern 140C. The back metal rail 240C can be implemented as a back interconnection rail. On the back metal rail 240C along the Z direction, a through-hole contact 260C is formed. On the through-hole contact 260C along the Z direction, a source region 262C of an N-type transistor is formed. On the source region 262C along the Z direction, an MD region 265C is formed. On the MD region 265C, a MD region 265C is directly coupled to the source region 262C. In some embodiments, the MD region 265C can be used as a local interconnection rail for electrically connecting nearby elements (e.g., metal rails and / or source / drain / gate regions).

[0049] exist Figure 2B In the integrated circuit, the gate region 220A to 220C is formed according to the layout patterns 120A to 120C. On the one hand, the gate region 220B is formed between the source region / drain region 262A and 262B and between the MD region 265A and 265B. A through-hole contact 260B is formed on the back metal track 240B along the Z direction. A drain region 262B is formed on the through-hole contact 260B along the Z direction. An MD region 265B is formed on the drain region 262B of the P-type transistor along the Z direction. Therefore, the drain region 262B is arranged between the through-hole contact 260B and the MD region 265B. In particular, the side or surface of the drain region 262B facing the Z direction is directly coupled to the MD region 265B, and the side or surface of the drain region 262B facing the opposite direction of the Z direction is directly coupled to the through-hole contact 260B. On the MD region 265B along the Z direction, a via contact 275 is formed according to the layout pattern 175. On the via contact 275 along the Z direction, a front metal track 270 is formed.

[0050] In this structure, the source region 262A is electrically coupled to the back power rail 210A for the power supply voltage VDD through the via contact 250A, the back metal rail 240A, and the via contact 260A. Therefore, the power supply voltage VDD can be provided to the transistor through the back power rail 210A and the back metal rail 240A. In addition, the drain region 262B is electrically coupled to the front metal rail 270 through the via contact 275 and the MD region 265B, and is electrically coupled to the back metal rail 240B through the via contact 260B. Therefore, an electrical signal can be provided through the front metal rail 270, through the back metal rail 240B, or through both.

[0051] Figure 3A and Figure 3B300A, 300B are top plan views of a layout design for an integrated circuit including backside metal rails according to one embodiment. In one aspect, the top plan views 300, 300B of the layout design show layout patterns for components at different layers of the integrated circuit. In one aspect, the top plan view 300A shows a layout pattern for the frontside metal rails of the integrated circuit, and the top plan view 300B shows a layout pattern for the backside metal rails of the integrated circuit. Figure 3A In the , the layout pattern 320 extending in the Y direction indicates the size and / or position of the gate region of the transistor, the layout pattern 330 extending in the X direction indicates the size and / or position of the active region, the layout pattern 365 extending in the Y direction indicates the size and / or position of the MD region, and the layout pattern 370 extending in the X direction indicates the size and / or position of the front metal rail (e.g., M0 rail). Figure 3B , a layout pattern 340 extending in the X direction indicates the size and / or location of a back metal rail (e.g., in the M-1 layer), and a layout pattern 350 indicates the size and / or location of a via contact between a transistor and a back interconnect (e.g., in the VDB layer). The back metal rail may be formed in a layer (e.g., the M-1 layer) between a first layer (e.g., the epitaxial layer EPI) and a second layer, wherein the transistor is formed in the first layer and the back power rail (e.g., the BM layer) is formed in the second layer, as shown in FIG. Figure 2A and Figure 2B In other embodiments, the layout design of the integrated circuit shown in the top plan views 300A and 300B may include layout patterns of more, fewer, or different layers.

[0052] On the one hand, the back metal rail and the back power rail allow the elements of the transistor to be formed with a regular or consistent structure. For example, the power supply voltage can be provided from the back power rail below, so that the ends or edges of the layout pattern 365 for the MD region can be aligned with similar shapes without extending to be connected to the front power rail. In addition, compared with the MD region with an irregular or inconsistent structure, the characteristics of the transistor can become more consistent. In addition, the back metal rail allows the number of front metal rails and through-hole connections to be reduced, so as to reduce the area of ​​the integrated circuit.

[0053] Figure 4A and Figure 4B400A, 400B are top plan views of a layout design of an integrated circuit including backside metal rails according to one embodiment. In one aspect, the top plan views 400A, 400B of the layout design show layout patterns of components at different layers of the integrated circuit. In one aspect, the top plan view 400A shows the layout pattern of the front side metal rails (e.g., at one or more of the MD layer, the M0 layer) of the integrated circuit, and the top plan view 400B shows the layout pattern of the back side metal rails (e.g., at the M-1 layer) of the integrated circuit. In one aspect, Figure 4A , Figure 4B The layout design shown is similar to FIG. 3A to FIG. 3B The layout design shown, except that the top plan view 400B includes a layout pattern 440 extending in the Y direction, wherein the layout pattern 440 indicates the size and / or position of the back metal rail. Therefore, for the sake of brevity, the detailed description of the repeated parts is omitted herein. In one aspect, the back metal rail extending in the Y direction helps to provide flexibility in routing or local interconnects. In other embodiments, the layout design of the integrated circuit shown in the top plan views 400A, 400B can include more, fewer, or layout patterns for different layers.

[0054] Figure 5A and Figure 5B 500A, 500B are top plan views of a layout design for an integrated circuit including backside metal rails (e.g., at the M-1 layer) according to one embodiment. In one aspect, the top plan views 500A, 500B of the layout design show layout patterns for components in different layers of the integrated circuit. In one aspect, the top plan view 500A shows the layout pattern for the frontside metal rails of the integrated circuit, and the top plan view 500B shows the layout pattern for the backside metal rails of the integrated circuit. In one aspect, Figure 5A , Figure 5B The layout design shown is similar to FIG. 3A to FIG. 3B The layout design shown, except that the top plan view 500B includes a layout pattern 540 extending in the X direction and the Y direction, wherein the layout pattern 540 indicates the size and / or position of the back metal track. Therefore, for the sake of brevity, the detailed description of the repeated parts is omitted herein. In one aspect, the back metal track extending in the X direction and the Y direction helps to provide flexibility in routing or local interconnects. In other embodiments, the layout design of the integrated circuit shown in the top plan views 500A, 500B can include more, fewer, or layout patterns for different layers.

[0055] Fig. 6A and Figure 6B600A, 600B are top plan views of a layout design for an integrated circuit including backside metal rails (e.g., in the M-1 layer) according to one embodiment. In one aspect, the top plan views 600A, 600B of the layout design show layout patterns for components at different layers of the integrated circuit. In one aspect, the top plan view 600A shows a layout pattern for the frontside metal rails of the integrated circuit, and the top plan view 600B shows a layout pattern for the backside metal rails of the integrated circuit. Fig. 6A , layout patterns 620A to 620F extending in the Y direction indicate the size and / or position of the gate region of the transistor, layout pattern 630 extending in the X direction indicates the size and / or position of the active region, layout patterns 665A to 665E extending in the Y direction indicate the size and / or position of the MD region, and layout patterns 670A to 670C extending in the X direction indicate the size and / or position of the front metal rail (e.g., M0 rail). Figure 6B , the layout patterns 640A to 640D extending in the X direction indicate the size and / or position of the back metal rails, and the layout patterns 650A to 650C indicate the size and / or position of the via contacts between the transistors and the back metal rails (e.g., M-1 rails). In one aspect, in the region corresponding to the cell, the layout design includes three layout patterns 670A to 670C for the front metal rails (e.g., M0 rails) and four layout patterns 640A to 640D for the back metal rails (e.g., M-1 rails). In other embodiments, the layout design of the integrated circuit shown in the top plan views 600A, 600B may include more, fewer, or layout patterns for different layers.

[0056] In some embodiments, source regions / drain regions and MD regions with different heights can be formed in an interlaced order according to layout patterns 665A to 665E. For example, source regions / drain regions and MD regions with a first height H1 can be formed according to layout patterns 665A, 665C, ​​and 665E, wherein source regions / drain regions and MD regions with a second height H2 less than the first height H1 can be formed according to layout patterns 665B and 665D. On the one hand, the source regions / drain regions and MD regions formed according to layout patterns 665A, 665C, ​​and 665E can be electrically connected through through-hole contacts formed according to layout patterns 650A to 650C and back metal tracks formed according to layout pattern 640B. This local connection through the back metal track can contribute to the flexibility of the position and size of the front metal track (e.g., M0 track) formed according to layout patterns 670A to 670C. For example, the front metal rail can be formed according to the layout pattern 670B so that the front metal rail can be close to the edge of the MD region or partially overlap the MD region. By implementing the back rail and the back power rail, a smaller number of front metal rails can be implemented to connect to the transistor. Therefore, by implementing the back metal rail, an integrated circuit can be formed with a smaller area.

[0057] Figure 6C According to one embodiment Fig. 6A and Figure 6B A cross-sectional view of the integrated circuit formed by the layout design along the line AA'. Fig.6D According to one embodiment Fig. 6A and Figure 6B A cross-sectional view of the integrated circuit formed by the layout design along the BB' line.

[0058] refer to Figure 6C and Fig.6D, the integrated circuit includes a back power rail layer BM, wherein the back power rail layer BM includes back power rails 698A, 698B for providing power supply voltages VDD, GND, respectively. A contact layer VB including via contacts 695A, 695B may be formed above the back power rail layer BM along the Z direction. A back metal rail layer M-1 including four back metal rails 690A to 690D may be formed above the contact layer VB along the Z direction according to the layout patterns 640A to 640D, respectively. On the one hand, the back metal rail 690A is used to provide the power supply voltage VDD, and the back metal rail 690D is used to provide the ground voltage GND, wherein the back metal rails 690B, 690C are used for local interconnects. A contact layer VDB including via contacts 688A to 688D may be formed above the back metal rail layer M-1 along the Z direction. For example, the via contact 688A may be formed according to the layout pattern 650A. An epitaxial layer EPI including source / drain regions 686A to 686D may be formed above the contact layer VDB along the Z direction. For example, a drain structure 686A of a P-type transistor may be formed at the intersection of the layout pattern 665A and the layout pattern 630, and a source region 686C of a P-type transistor may be formed at the intersection of the layout pattern 665B and the layout pattern 630. A conductive layer MD including MD regions 684A to 684D may be formed above the epitaxial layer EPI along the Z direction. For example, MD regions 684A, 684C may be formed according to the layout patterns 665A, 665B. A contact layer VD may be formed above the conductive layer MD along the Z direction. A front metal layer M0 including three front metal rails 682A to 682C may be formed according to the layout patterns 670A to 670C, respectively.

[0059] exist Figure 6CIn the embodiment, the back power rail 698B is configured to provide a power supply voltage GND. A through-hole contact 695A is formed on the back power rail 698B along the Z direction. A back metal rail 690D is formed on the through-hole contact 695A along the Z direction. The back metal rail 690D can be implemented as a back interconnection rail. A through-hole contact 688B is formed on the back metal rail 690D along the Z direction. A source region 686B of an N-type transistor is formed on the through-hole contact 688B along the Z direction. An MD region 684B is formed on the source region 686B along the Z direction. On one hand, the MD region 684B is directly coupled to the source region 686B. On one hand, the side or surface of the source region 686B facing the Z direction is directly coupled to the MD region 684B, and the side or surface of the source region 686B facing the opposite direction of the Z direction is directly coupled to the through-hole contact 688B. In this structure, the power supply voltage GND may be provided to the source region 686B and the MD region 684B through the via contact 695A, the back side power rail 690D, and the via contact 688B.

[0060] exist Fig.6D In one aspect, the back power rail 698A is configured to provide a power supply voltage VDD. On the back power rail 698A along the Z direction, a through-hole contact 695B is formed. On the VB layer including the through-hole contact 695B along the Z direction, a back metal rail 690A is formed. The back metal rail 690A can be implemented as a back interconnection rail below the source region 686C (e.g., in the opposite direction of the Z direction). On the back metal rail 690A along the Z direction, a through-hole contact 688C is formed. On the through-hole contact 688C along the Z direction, a source region 686C of a P-type transistor is formed. On the source region 686C along the Z direction, an MD region 684C is formed. On one hand, the MD region 684C is directly coupled to the source region 686C. In one aspect, the side or surface of the source region 686C facing the Z direction is directly coupled to the MD region 684C, and the side or surface of the source region 686C facing the direction opposite to the Z direction is directly coupled to the via contact 688C. In this structure, the power supply voltage VDD can be provided to the source region 686C and the MD region 684C through the via contact 695B, the back power rail 690A, and the via contact 688C.

[0061] Figure 77 is a top plan view 700 of a layout design of an integrated circuit including a back metal rail according to one embodiment. In one aspect, the top plan view 700 shows layout patterns 710 to 710E of the back metal rails of the integrated circuit. The back metal rails formed according to the layout patterns can be in the M-2 layer and disposed between a first layer (e.g., the M-1 layer) forming the back metal rails and a second layer (e.g., the BM layer) forming the back power rails. The back metal rails formed according to the layout patterns 710 to 710E can include metal or any conductive material. Figure 7 As shown, in some embodiments, the layout patterns 640A to 640D for the back metal rails in the M-1 layer may extend in the X direction, while the layout patterns 710A to 710E for the back metal rails in the M-2 layer may extend in the Y direction. In some embodiments, one or more through-hole contacts may be formed at the intersection of the layout pattern for the back metal rails in the M-1 layer and the layout pattern for the back metal rails in the M-2 layer to allow the back metal rails in different layers to be electrically coupled to each other. Although not shown for simplicity, one or more through-hole contacts may be formed at the intersection of the layout pattern for the back metal rails in the M-2 layer and the layout pattern for the back power rails to allow the back metal rails in the M-2 layer and the back power rails to be electrically coupled to each other. By using the back metal rails in the M-2 layer between the back metal rails in the M-1 layer and the back power rails in the BM layer, more flexibility in layout and routing is provided, and the integrated circuit is allowed to be designed in a compressed form.

[0062] Fig. 8Ais a schematic diagram of an example multiplexer circuit 800 according to one embodiment. In one structure, the multiplexer circuit 800 includes P-type transistors P1, P2 (e.g., PMOS transistors or P-type FinFETs) and N-type transistors N1, N2 (e.g., NMOS transistors or N-type FinFETs). In one structure, a first input port I1 of the multiplexer circuit 800 is coupled to the drain region (or source region) of transistor P1 and the drain region (or source region) of transistor N2. Similarly, a second input port I2 of the multiplexer circuit 800 is coupled to the drain region (or source region) of transistor P2 and the drain region (or source region) of transistor N2. In addition, an output port Z of the multiplexer circuit 800 is coupled to the source region (or drain region) of transistor P1, the source region (or drain region) of transistor P2, the source region (or drain region) of transistor N1, and the source region (or drain region) of transistor N2. Furthermore, the control port A of the multiplexer circuit 800 is coupled to the gate region of the transistor P1 and the gate region of the transistor N2, and the control port B of the multiplexer circuit 800 is coupled to the gate region of the transistor P2 and the gate region of the transistor N1. In this structure, when the voltage at the control port A is high (e.g., VDD) and the voltage at the control port B is low (e.g., GND), the electrical signal at the input port I2 can be transferred to the output port Z through the transistors P2, N2. Similarly, when the voltage at the control port A is low (e.g., GND) and the voltage at the control port B is high (e.g., VDD), the electrical signal at the input port I1 can be transferred to the output port Z through the transistors P1, N1.

[0063] Figure 8B According to an embodiment Fig. 8A A top plan view 805 of a layout design of an example multiplexer circuit 800. In one aspect, Figure 8B The layout design shown includes layout patterns 830A, 830B and layout patterns 820A to 820D, wherein the layout patterns 830A, 830B indicate the size and / or position of the active area, and the layout patterns 820A to 820D indicate the size and / or position of the gate area. Figure 1B As described, transistors may be formed at the intersection of layout patterns 830A, 830B for active regions and layout patterns 820A to 820D for gate regions. In one example, the gate regions formed according to layout patterns 820A, 820D may be assigned to or coupled to control port A of multiplexer circuit 800, and the gate regions formed according to layout patterns 820B, 820C may be assigned to or coupled to control port B of multiplexer circuit 800. To achieve the above Fig. 8AThe multiplexer circuit 800 shown in FIG. 8 may use cross-coupled connections 840A, 840B. In one aspect, as described below with respect to 9A to 9C , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C as well as FIG. 12A to FIG. 12B As described, backside metal tracks may be used to allow local interconnects.

[0064] 9A to 9C According to an embodiment Fig. 8A 900A to 900C of a layout design of an example multiplexer circuit 800 including backside metal tracks (e.g., in layer M-1). In one aspect, the top plan views 900A to 900C of the layout design illustrate layout patterns for components at different layers of an integrated circuit. In one aspect, Fig. 9A The illustrated layout design 900A includes layout patterns 970A to 970E extending in the X direction, and layout patterns 980A to 980B extending in the Y direction. Layout patterns 970A to 970E may indicate the size and location of the front metal rails (e.g., M0 rails), and layout patterns 980A, 980B may indicate the size and location of the front metal rails (e.g., M1 rails). In one aspect, Fig. 9B The illustrated layout design 900B includes layout patterns 920A to 920D extending in the Y direction, and layout patterns 925A to 925D. The layout patterns 920A to 920D may indicate the size and location of the gate region, and the layout patterns 925A to 925D may indicate the size and location of the via contacts between the gate region and the front metal rail (e.g., M0 rail). In one aspect, Fig. 9C The layout design 900C shown includes layout patterns 940A-940B extending in the X direction. The layout patterns 940A, 940B may indicate the size and location of the backside metal tracks (eg, M-1 layer). Figures 9A to 9C According to the layout design, cross-coupling connections 840A, 840B can be formed through front metal rails (e.g., M1 rail and M0 rail). In addition, the drain region or source region of the transistor can be locally wired through the back metal rails (e.g., M-1 rail).

[0065] FIG. 10A to FIG. 10C According to an embodiment Fig. 8A 1000A to 1000C of a layout design of an example multiplexer circuit 800 including backside metal tracks (e.g., at layer M-1). In one aspect, the layout designs shown in top plan views 1000A to 1000C illustrate layout patterns for components at different layers of an integrated circuit. In one aspect, the layout designs shown in top plan views 1000A to 1000C are similar to 9A to 9CThe layout designs shown in the top plan views 900A to 900C are different from those shown in the top plan views 900A to 900C except that FIG. 10A to FIG. 10C The layout design shown includes layout patterns 1070A to 1070D for replacing four front side metal rails (eg, M0 rails) with five front side metal rails. FIG. 10A to FIG. 10C The layout design shown can form cross-coupling connections 840A, 840B through front metal rails (eg, M1 rail and M0 rail). Also, drain regions or source regions of transistors can be locally wired through back metal rails (eg, M-1 rail).

[0066] FIG. 11A to FIG. 11C According to an embodiment Fig. 8A 1 . A top plan view of a layout design of an example multiplexer circuit 800 including backside metal tracks (e.g., at layer M-1) is shown. In one aspect, top plan views 1100A through 1100C of the layout design illustrate layout patterns for components in different layers of an integrated circuit. In one aspect, the layout design shown in top plan views 1100A through 1100C is similar to 9A to 9C The layout design shown in the top plan views 900A to 900C is shown with the exception of FIG. 11A to FIG. 11C The layout design shown includes layout patterns 1170A to 1170C for replacing three front side metal rails (eg, M0 rails) with five front side metal rails. FIG. 11A to FIG. 11C The layout design shown can form cross-coupling connections 840A, 840B through front metal rails (eg, M1 rail and M0 rail). Also, drain regions or source regions of transistors can be locally wired through back metal rails (eg, M-1 rail).

[0067] Fig. 12A and Fig. 12B According to an embodiment Fig. 8A 1200A-1200B of a layout design of an example multiplexer circuit 800 including backside metal tracks (e.g., at the M-1 layer). In one aspect, the top plan views 1200A-1200B of the layout design illustrate layout patterns for components at different layers of an integrated circuit. In one aspect, Fig. 12A The layout design shown includes layout patterns 1230A to 1230D and layout patterns 1220A to 1220C, wherein the layout patterns 1230A to 1230D indicate the size and / or position of the active area, and the layout patterns 1220A to 1220C indicate the size and / or position of the gate area. Figure 1BAs described above, transistors may be formed at intersections of the layout patterns 1230A to 1230D for active regions and the layout patterns 1220A to 1220C for gate regions. In one example, different transistors are formed along the Y direction according to the layout patterns 1220A to 1220C and the layout patterns 1220A to 1220B.

[0068] In one aspect, front and back metal tracks can be formed to route different components. In one example, Fig. 12A The illustrated layout design also includes layout patterns 1270A to 1270D and layout pattern 1280, wherein layout patterns 1270A to 1270D indicate the size and / or location of the front metal rail (e.g., M0 rail), and layout pattern 1280 indicates the size and / or location of the front metal rail (e.g., M1 rail). In one example, Fig. 12B The illustrated layout design also includes layout patterns 1240A to 1240D, wherein the layout patterns 1240A to 1240D indicate the size and / or location of the backside metal tracks (eg, the M-1 tracks). FIG. 12A to FIG. 12B The layout design shown can form cross-coupling connections 840A, 840B through front metal rails (eg, M1 rail and M0 rail). Also, drain regions or source regions of transistors can be locally wired through back metal rails (eg, M-1 rail).

[0069] Fig.13A is a schematic diagram of an example circuit 1300 according to one embodiment. In one configuration, the circuit 1300 is similar to Fig. 8A The multiplexer circuit 800 is similar to the multiplexer circuit 800 except that the dummy transistors D1 and D2 are added. Therefore, for the sake of brevity, the detailed description of the repeated parts is omitted herein. In one aspect, the dummy transistors D1 and D2 allow easy layout and routing of different components.

[0070] Fig. 13B According to an embodiment Fig.13A A top plan view 1305 of a layout design of an example circuit 1300. In one aspect, Fig. 13B The layout design shown includes layout patterns 1310A, 1310B and layout patterns 1320A to 1320E, wherein the layout patterns 1310A, 1310B indicate the size and / or position of the active area, and the layout patterns 1320A to 1320E indicate the size and / or position of the gate area. The layout patterns 1310A, 1310B may extend in the X direction, and the layout patterns 1320A to 1320E may extend in the Y direction. Figure 1BAs described above, transistors may be formed at intersections of the layout patterns 1310A and 1310B for active regions and the layout patterns 1320A to 1320E for gate regions.

[0071] In some embodiments, the front metal rail and / or the back metal rail can be used for local wiring. In one example, the drain region and the source region of the transistor formed according to the layout patterns 1330A and 1330B can be short-circuited or electrically coupled to each other through the local interconnect 1350 to form a pseudo transistor D1. In one example, the gate regions formed according to the layout patterns 1320B and 1320D can be short-circuited or electrically coupled to each other through the local interconnect 1352. The local interconnect 1352 can be assigned to or coupled to the control port B of the circuit 1300. In one example, the gate region or source region of the transistor formed according to the layout pattern 1330C, the drain region or source region of the transistor formed according to the layout pattern 1330D, can be short-circuited or electrically connected to each other through the local interconnect 1354. The local interconnect 1354 can be assigned to or coupled to the output port Z of the circuit 1300. Similarly, in one example, the drain region and the source region of the transistor formed according to the layout patterns 1330E, 1330F can be shorted or electrically coupled to each other through the local interconnect 1356 to form a pseudo transistor D2. The local interconnects 1350, 1352, 1354, 1356 can be metal tracks at the M-2 layer, the M-1 layer, the M0 layer, the M1 layer, or any combination thereof.

[0072] On the one hand, the back metal rail allows for flexibility in the layout and routing of the elements, so that the layout patterns 1320A to 1320E, the layout patterns 1330A to 1330F can have a regular or consistent shape. For example, the layout patterns 1320A to 1320E for forming the gate region can have the same or similar shape and extend across the layout patterns 1330A, 1330B for forming the active region. For example, the layout patterns 1330A to 1330E for forming the source region / drain region and / or the MD region can have the same or similar shape of edge alignment. Advantageously, such regular or consistent shapes of the layout patterns 1320A to 1320E, 1330A to 1330F allow the elements of the transistor (e.g., gate region, source region / drain region) to be formed in a consistent manner, so that the characteristics of the transistor can be more consistent. Moreover, the circuit 1300 can be formed in a compressed form because the number of the front metal rails and the through-hole contacts can be reduced.

[0073] FIG. 13C to FIG. 13D According to an embodiment Fig.13A1360A, 1360B of a layout design of an example multiplexer circuit 1300 including backside metal rails. In one aspect, the top plan views 1360A, 1360B of the layout design illustrate layout patterns for components at different layers of an integrated circuit. In one aspect, Fig. 13C The illustrated layout design includes layout patterns 1366A to 1366D and layout patterns 1364A to 1364E, wherein layout patterns 1366A to 1366D indicate the size and / or location of the active regions and layout patterns 1364A to 1364E indicate the size and / or location of the gate regions.

[0074] In one aspect, front and back metal tracks can be formed to route different components. In one example, Fig. 13C The illustrated layout design also includes layout patterns 1362A to 1362C, wherein the layout patterns 1362A to 1362C indicate the size and / or location of the front metal rail (eg, M0 rail). Fig.13D The illustrated layout design also includes layout patterns 1368A-1368B, wherein the layout patterns 1368A-1368B indicate the size and / or location of the backside metal tracks (eg, the M-1 tracks). FIG. 13C to FIG. 13D The layout design shown can form cross-coupling connections 1352, 1354 through front metal rails (e.g., M1 rail and M0 rail) and back metal rails (e.g., M-1 rail). In one example, the drain region or source region of the transistor formed according to the layout pattern 1366A can be electrically connected to the back metal rail (e.g., M-1 rail) formed according to the layout pattern 1368A through a via contact formed according to the layout pattern 1369A. Similarly, the source region or drain region of the transistor formed according to the layout pattern 1366A can be electrically connected to the back metal rail (e.g., M-1 rail) formed according to the layout pattern 1368A through a via contact formed according to the layout pattern 1369B. In one example, the drain region or source region of the transistor formed according to the layout pattern 1366C can be electrically connected to the back metal rail (e.g., M-1 rail) formed according to the layout pattern 1368B through a via contact formed according to the layout pattern 1369C. Similarly, the drain region or source region of the transistor formed according to layout pattern 1366D can be electrically connected to the back metal rail (e.g., M-1 rail) formed according to layout pattern 1368B through a through-hole contact formed according to layout pattern 1369D. Therefore, different transistors formed according to layout patterns 1366C and 1366D can be electrically connected to each other through the back metal rail formed according to layout pattern 1368B. Fig. 13C and Fig.13DIn the example shown, the layout patterns 1368A, 1368B may extend in the X-direction and the Y-direction to allow the layout patterns 1366A to 1366D for the source region and / or the drain region to have a regular or uniform structure.

[0075] FIG. 13E to FIG. 13F According to an embodiment Fig.13A 1370A, 1370B of a layout design of an example multiplexer circuit 1300 including backside metal rails. In one aspect, the top plan views 1370A, 1370B of the layout design illustrate layout patterns for components at different layers of an integrated circuit. In one aspect, Fig.13E and Fig.13F The layout design shown is similar to Fig. 13C and Fig.13D The layout design shown, except Fig.13E and Fig.13F The layout design shown includes layout patterns 1376A to 1376D indicating the size and / or location of source / drain regions having varying lengths and layout patterns 1378A to 1378C indicating the size and / or location of backside metal rails (e.g., M-1 rails) extending in the X direction. Fig.13E , layout patterns 1376C and 1376D extend in the Y direction to partially overlap with layout pattern 1378B extending in the X direction. In one aspect, the drain region or source region of the transistor formed according to layout pattern 1376C can be electrically connected to the back metal rail formed according to layout pattern 1378B through a via contact formed according to layout pattern 1379D. Similarly, the drain region or source region of the transistor formed according to layout pattern 1376D can be electrically connected to the back metal rail formed according to layout pattern 1378B through a via contact formed according to layout pattern 1379C. Therefore, when layout patterns 1378A to 1378C extend in one direction (e.g., the X direction), layout patterns 1376C to 1376D can have a varying structure.

[0076] FIG. 13G to FIG. 13I According to an embodiment Fig.13A 1380A to 1380C of a layout design of an example multiplexer circuit 1300 including backside metal rails. In one aspect, the top plan views 1380A to 1380C of the layout design illustrate layout patterns for components at different layers of an integrated circuit. In one aspect, FIG. 13G to FIG. 13I The layout design shown is similar to Fig. 13C and Fig.13D The layout design shown, except FIG. 13G to FIG. 13IThe layout design shown includes layout patterns 1388A-1388C and layout patterns 1395A-1398B for different back metal rails (e.g., M-2 rails) extending in the Y direction, where layout patterns 1388A-1388C indicate the size and / or position of back metal rails (e.g., M-1 rails) extending in the X direction. In one aspect, transistors can be connected through back metal rails (e.g., M-1 rails) formed according to layout patterns 1388A-1388C, back metal rails (e.g., M-2 rails) formed according to layout patterns 1395A-1395B, and through-hole contacts formed according to layout patterns 1389A-1389B and layout patterns 1398A-1398D. By using different layers of back metal rails, flexibility in routing or connecting different elements of the integrated circuit can be provided. Furthermore, the backside metal rail allows for flexibility in the layout and routing of components, so that the layout pattern used to form the transistor (e.g., drain region, source region, and gate region) can have a regular or consistent shape. Advantageously, such a regular or consistent shape of the layout pattern allows the components of the transistor (e.g., gate region, source region / drain region) to be formed in a consistent manner, so that the characteristics of the transistor can be more consistent.

[0077] Fig.14A is a schematic diagram of an example circuit 1400 according to one embodiment. Fig. 14B According to an embodiment Fig.14A A top plan view 1450 of a layout design of an example circuit of FIG. 1400 is shown. In one example, the circuit 1400 is implemented as a flip-flop circuit. In one aspect, the circuit 1400 includes a first portion 1410A and a second portion 1420B, wherein the first portion 1410A and the second portion 1420B have Fig.13A The circuit 1300 in FIG. 1 is similar in structure to the circuit 1300 in FIG. Fig. 14B As shown, the circuit 1300 can be formed with cross-coupling connections. Fig. 13B As described, the back metal rail can be used for local interconnects. This use of the back metal rail allows flexibility in the layout and routing of components, so that the layout pattern used to form transistors (e.g., drain regions, source regions, and gate regions) can have a regular or consistent shape. Advantageously, this regular or consistent shape of the layout pattern allows the components of the transistor (e.g., gate regions, source regions, drain regions) to be formed in a consistent manner, so that the transistor characteristics can be more consistent. Moreover, the circuit 1400 can be formed in a compressed form because the number of front metal rails and through-hole contacts can be reduced.

[0078] Fig.15 is a flow chart of a method 1500 of forming or manufacturing an integrated circuit according to some embodiments. Fig.15Additional operations are performed before, during, and / or after the illustrated method 1500. In some embodiments, the method 1500 may be used to form an integrated circuit according to various layout designs disclosed herein.

[0079] In step 1510 of method 1500, a layout design for an integrated circuit is generated. A processing device (e.g., Fig.16 The processor 1602 of the embodiment of the present invention is used to perform step 1510. In one method, the layout design is generated by placing the layout design of one or more standard cells through a user interface. In one method, the layout design is automatically generated by a processor executing a synthesis tool that converts the logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is expressed as a graphic database system (GDSII) file format.

[0080] In step 1520 of method 1500, an integrated circuit is manufactured based on the layout design. In some embodiments, step 1520 of method 1500 includes manufacturing at least one mask based on the layout design, and manufacturing the integrated circuit based on the at least one mask. In one method, step 1520 includes steps 1522, 1524, 1526, 1528. In step 1522, a first layer (e.g., a BM layer) including a first metal rail (e.g., a back power rail) is formed. In step 1524, a second layer (e.g., an M-2 layer or an M-1 layer) including a second metal rail (e.g., a back metal rail) is formed. In one aspect, the second layer is above the first layer along a direction (e.g., a Z direction). In one method, a first contact layer (e.g., a VB layer) including one or more via contacts can be formed between the first layer and the second layer. One or more via contacts in the first contact layer (e.g., the VB layer) can be electrically coupled to the first metal rail (e.g., the back power rail) and the second metal rail (e.g., the back metal rail). In step 1526, a third layer (e.g., an EPI layer) including an active region of a transistor is formed above the second layer along the direction (e.g., the Z direction). In one method, a second contact layer (e.g., a VDB layer) including one or more through-hole contacts may be formed between the second layer and the third layer. In one aspect, one or more contacts in the second contact layer (e.g., the VDB layer) may be electrically coupled to the transistor and the back metal track. In step 1528, a fourth layer (e.g., an MD layer) including a third metal track (e.g., an MD region) is formed above the third layer along the direction (e.g., the Z direction). In some embodiments, the MD region is directly coupled to the active region. In step 1530, a fifth layer (e.g., an M0 layer) including a metal track (e.g., an M0 track) is formed above the fourth layer along the direction (e.g., the Z direction). In one method, a third contact layer (e.g., a VD layer) including one or more through-hole contacts may be formed between the fourth layer and the fifth layer. One or more via contacts at a third contact layer (eg, VD layer) may be electrically coupled to the MD region and the M0 rail.

[0081] Advantageously, the back power rail and the back wiring rail allow for flexibility in the layout and routing of components, so that the layout pattern used to form the transistor (e.g., drain structure, source structure, and gate structure) can have a regular or consistent shape. Advantageously, such a regular or consistent shape of the layout pattern allows the components of the transistor (e.g., source region / drain region, gate region, etc.) to be formed in a consistent manner, so that the characteristics of the transistor can be more consistent. Moreover, the integrated circuit can be formed in a compressed form because the number of front metal rails and through-hole contacts can be reduced.

[0082] Fig.161 is a schematic diagram of a system 1600 for designing and manufacturing IC layout designs according to some embodiments. In some embodiments, the system 1600 generates or places one or more IC layout designs described herein. In some embodiments, the system 1600 manufactures one or more ICs based on one or more IC layout designs described herein. The system 1600 includes a hardware processor 1602 and a non-transitory computer-readable storage medium 1604 encoded (e.g., stored) with a computer program code 1606 (e.g., a set of executable instructions). The computer-readable storage medium 1604 is configured to be connected to a manufacturing machine for generating integrated circuits. The processor 1602 is electrically coupled to the computer-readable storage medium 1604 via a bus 1608. The processor 1602 is also electrically coupled to an I / O interface 1610 via the bus 1608. A network interface 1612 is also electrically connected to the processor 1602 via the bus 1608. The network interface 1612 is connected to a network 1614, thereby enabling the processor 1602 and the computer-readable storage medium 1604 to be connected to external components via the network 1614. The processor 1602 is configured to execute computer program code 1606 encoded in the computer-readable storage medium 1604 so that the system 1600 can be used to perform part or all of the operations described in the method 1500 .

[0083] In some embodiments, processor 1602 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0084] In some embodiments, computer readable storage medium 1604 is an electronic, magnetic, optical fiber, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, computer readable storage medium 1604 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disks, computer readable storage medium 1604 includes compact disk read-only memory (CD-ROM), compact disk read / write memory (CD-R / W), and / or digital video disk (DVD).

[0085] In some embodiments, storage medium 1604 stores computer program code 1606 configured to cause system 1600 to perform method 1500. In some embodiments, storage medium 1604 also stores information required for performing method 1500 and information generated during the execution of method 1500, such as layout design 1616 and user interface 1618 and manufacturing unit 1620, and / or a set of executable instructions for performing the operations of method 1500.

[0086] In some embodiments, storage medium 1604 stores instructions (e.g., computer program code 1606) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1606) enable processor 1602 to generate manufacturing instructions readable by the manufacturing machine to effectively implement method 1500 in a manufacturing process.

[0087] System 1600 includes an input / output (I / O) interface 1610. I / O interface 1610 is coupled to external circuitry. In some embodiments, I / O interface 1610 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to processor 1602.

[0088] The system 1600 also includes a network interface 1612 coupled to the processor 1602. The network interface 1612 allows the system 1600 to communicate with a network 1614 to which one or more other computer systems are connected. The network interface 1612 includes: a wireless network interface, such as Bluetooth, wireless local area network (WIFI), access control (WIMAX), general packet radio service (GPRS) or mobile communication (WCDMA); or a wired network interface, such as Ethernet, universal serial bus (USB) or Institute of Electrical and Electronics Engineers-13154 (IEEE-13154). In some embodiments, the method 1500 is implemented in two or more systems 1600, and information such as layout design, user interface and manufacturing unit is exchanged between different systems 1600 through the network 1614.

[0089] System 1600 is configured to receive information related to a layout design via I / O interface 1610 or network interface 1612. The information is transmitted to processor 1602 via bus 1608 to determine a layout design for generating an IC. The layout design is then stored in computer-readable medium 1604 as layout design 1616. System 1600 is configured to receive information related to a user interface via I / O interface 1610 or network interface 1612. The information is stored in computer-readable medium 1604 as user interface 1618. System 1600 is configured to receive information related to a manufacturing unit via I / O interface 1610 or network interface 1612. The information is stored in computer-readable medium 1604 as manufacturing unit 1620. In some embodiments, manufacturing unit 1620 includes manufacturing information utilized by system 1600.

[0090] In some embodiments, method 1500 is implemented as a standalone software application for execution by a processor. In some embodiments, method 1500 is implemented as a software application that is part of an additional software application. In some embodiments, method 1500 is implemented as a plug-in to a software application. In some embodiments, method 1500 is implemented as a software application that is part of an EDA tool. In some embodiments, method 1500 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer readable medium. In some embodiments, the layout design is generated by using a computer program such as available from CADENCEDESIGN SYSTEMS, Inc. , or another suitable layout generation tool. In some embodiments, the layout design is generated based on a netlist that is created based on a schematic design. In some embodiments, method 1500 is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system 1600. In some embodiments, system 1600 is a manufacturing device (e.g., manufacturing tool 1622) that manufactures integrated circuits using a set of masks manufactured based on one or more layout designs of the present invention. In some embodiments, Fig.16 The system 1600 produces a layout design for an IC that is smaller than other methods. In some embodiments, Fig.16 The system 1600 produces a layout design for an IC that occupies a smaller area than other methods.

[0091] Fig.17 is a block diagram of an integrated circuit (IC) manufacturing system 1700 and an IC manufacturing flow associated therewith in accordance with at least one embodiment of the present invention.

[0092] exist Fig.17In the present invention, the IC manufacturing system 1700 includes entities such as a design room 1720, a mask room 1730, and an IC manufacturer / fab ("fab") 1740, which interact with each other in the design, development and manufacturing cycle and / or services related to the manufacture of integrated circuit devices 1760. The entities in the system 1700 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired communication channels and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, a single larger company owns two or more of the design room 1720, the mask room 1730, and the IC fab 1740. In some embodiments, two or more of the design room 1720, the mask room 1730, and the IC fab 1740 coexist in a common facility and use common resources.

[0093] The design house (or design group) 1720 generates an IC design layout 1722. The IC design layout 1722 includes various geometric patterns designed for the IC device 1760. The geometric patterns correspond to the patterns of the metal layers, oxide layers, or semiconductor layers of the various elements constituting the IC device 1760 to be manufactured. The various layers are combined to form various IC components. For example, a portion of the IC design layout 1722 includes various IC components, such as active areas, gate structures, source structures, and drain structures, through-hole contacts of metal lines or interlayer interconnects, and openings for bonding pads, to be formed on a semiconductor substrate (such as a silicon wafer) and various metal layers arranged on the semiconductor substrate. The design house 1720 performs appropriate design processes to form the IC design layout 1722. The design process includes one or more of a logical design, a physical design, or a layout and routing. The IC design layout 1722 exists in one or more data files with information of the geometric patterns. For example, the IC design layout 1722 can be expressed in a layout data (GDSII) file format or a DFII file format.

[0094] The mask chamber 1730 includes data preparation 1732 and mask manufacturing 1734. The mask chamber 1730 uses the IC design layout 1722 to manufacture one or more masks for manufacturing various layers of the IC device 1760 based on the IC design layout 1722. The mask chamber 1730 performs mask data preparation 1732, wherein the IC design layout drawing 1722 is translated into a representation data file ("RDF"). The mask data preparation 1732 provides the RDF to the mask manufacturing 1734. The mask manufacturing 1734 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 1732 to comply with the specific performance of the mask writer and / or the requirements of the IC fab 1740. In Fig.17 , mask data preparation 1732 and mask manufacturing 1734 are illustrated as a single element. In some embodiments, mask data preparation 1732 and mask manufacturing 1734 can be collectively referred to as mask data preparation.

[0095] In some embodiments, mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image distortions, such as those caused by diffraction, interference, and other process effects, etc. OPC adjusts IC design layout 1722. In some embodiments, mask data preparation 1732 also includes resolution enhancement techniques (RET), such as off-axis illumination, resolution assist patterns, phase shift masks, and other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0096] In some embodiments, mask data preparation 1732 includes a mask rule checker (MRC) that checks the IC design layout with a set of mask creation rules, the IC design layout has been through the process in the OPC, the set of mask creation rules containing certain geometric constraints and / or connection constraints to ensure sufficient space, account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask manufacturing 1734, which can undo a portion of the modifications performed by the OPC to meet the mask creation rules.

[0097] In some embodiments, mask data preparation 1732 includes a lithography process check (LPC), which simulates a process to be performed by ICfab 1740 to manufacture IC device 1760. LPC simulates the process based on IC design layout 1722 to create a simulated manufactured device, such as IC device 1760. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), and other suitable factors, etc. or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1722.

[0098] It should be understood that the foregoing description of mask data preparation 1732 has been simplified for the purpose of clarity. In some embodiments, mask data preparation 1732 includes additional components, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. In addition, the processes applied to IC design layout 1722 during mask data preparation 1732 can be performed in a variety of different orders.

[0099] After mask data preparation 1732 and during mask manufacturing 1734, a mask or a set of masks are manufactured based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (photomask or intermediate mask) based on the modified IC design layout. The mask can be formed in various techniques. In some embodiments, the mask is formed by using a binarization technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., a photoresist) is blocked by the opaque area and transmitted through the transparent area, and the image sensitive material layer has been coated on the wafer. In one example, the binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, the mask is formed by using a phase shift technique. In a phase shift mask (PSM), various components in the pattern formed on the mask are configured to have a suitable phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The one or more masks generated by mask manufacturing 1734 are used in various processes. For example, such one or more masks are used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0100] IC fab 1740 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 1740 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end of line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end of line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services for foundry business.

[0101] IC fab 1740 uses one or more masks manufactured by mask chamber 1730 to manufacture IC device 1760. Therefore, ICfab 1740 at least indirectly uses IC design layout 1722 to manufacture IC device 1760. In some embodiments, semiconductor wafer 1742 is manufactured by IC fab 1740 using one or more masks to form IC device 1760. Semiconductor wafer 1742 includes a silicon substrate or other suitable substrate with multiple material layers formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric components, and multi-layer interconnects, etc. (formed in subsequent manufacturing steps).

[0102] System 1700 is shown with design room 1720, mask room 1730, or IC fab 1740 as separate elements or entities. However, it may be considered that one or more of design room 1720, mask room 1730, or IC fab 1740 are part of the same element or entity.

[0103] With respect to integrated circuit (IC) manufacturing systems (e.g., Fig.17 Details of the system 1700 and the IC manufacturing process associated therewith may be found, for example, in U.S. Patent No. 9,256,709, issued on February 9, 2016, U.S. Patent Application No. 20150278429, issued on October 1, 2015, U.S. Patent Application No. 20100040838, issued on February 6, 2014, and U.S. Patent No. 7,260,442, issued on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0104] One aspect of the specification relates to an integrated circuit. In some embodiments, the integrated circuit includes a first layer, the first layer including a first metal track. In some embodiments, the integrated circuit includes a second layer, the second layer including a second metal track, wherein the second layer is above the first layer along a first direction. In some embodiments, the integrated circuit includes a third layer, the third layer including active regions of transistors, wherein the third layer is above the second layer along the first direction. In some embodiments, the integrated circuit includes a fourth layer, the fourth layer including a third metal track, wherein the fourth layer is above the third layer along the first direction. In some embodiments, the integrated circuit includes a fifth layer, the fifth layer including a fourth metal track, wherein the fifth layer is above the fourth layer along the first direction.

[0105] In the above integrated circuit, the first metal rail is used to provide a power supply voltage to an active region of the transistor through the second metal rail.

[0106] In the above integrated circuit, the third metal rail is used to provide an electrical signal from or to the transistor.

[0107] In the above integrated circuit, the first metal rail is electrically coupled to the second metal rail through the first via contact, and the second metal rail is electrically coupled to the first side of the active region of the transistor through the second via contact.

[0108] In the above integrated circuit, the third metal rail is directly coupled to the second side of the active area of ​​the transistor.

[0109] In the above integrated circuit, the fourth layer includes: a fifth metal track directly coupled to another active region of the transistor.

[0110] In the above-mentioned integrated circuit, the third metal rail extends in a second direction perpendicular to the first direction, wherein the third metal rail includes a first end and a second end, and wherein the fifth metal rail extends in the second direction, wherein the fifth metal rail includes a third end and a fourth end, wherein the first end of the third metal rail and the third end of the fifth metal rail are aligned, wherein the second end of the third metal rail and the fourth end of the fifth metal rail are aligned.

[0111] In the above integrated circuit, the second layer includes: a sixth metal track coupled to another active region of the transistor.

[0112] In the above integrated circuit, the sixth metal rail is coupled to an active region of another transistor.

[0113] The integrated circuit further includes: a seventh metal rail of the transistor extending in the second direction, the seventh metal rail being arranged between an active region of the transistor and another active region of the transistor, and the seventh metal rail partially overlapping with the sixth metal rail.

[0114] In the above integrated circuit, the fourth metal track extends in a second direction perpendicular to the first direction, wherein the first metal track extends in the second direction.

[0115] In the above integrated circuit, the second metal track extends in a third direction, and the first direction is orthogonal to the second direction and the third direction.

[0116] In the above integrated circuit, the second metal track extends in the second direction.

[0117] In the above integrated circuit, it also includes: a sixth layer, including a fifth metal track between the first layer and the second layer, the second metal track extends in the second direction, and the fifth metal track extends in the third direction, and the first direction is orthogonal to the second direction and the third direction.

[0118] One aspect of the specification relates to a method for forming an integrated circuit. In some embodiments, the method includes forming a first layer including a first metal track. In some embodiments, the method includes forming a second layer, the second layer including a second metal track, wherein the second layer is above the first layer along a first direction. In some embodiments, the method includes forming a third layer, the third layer including an active area of ​​a transistor, wherein the third layer is above the second layer along the first direction. In some embodiments, the method includes forming a fourth layer, the fourth layer including a third metal track, wherein the fourth layer is above the third layer along the first direction. In some embodiments, the method includes forming a fifth layer, the fifth layer including a fourth metal track, wherein the fifth layer is above the fourth layer along the first direction.

[0119] In the above method, the first metal rail is used to provide a power supply voltage to an active region of the transistor through the second metal rail, wherein the third metal rail is used to provide an electrical signal from the transistor or to the transistor.

[0120] In the above method, it also includes: forming a first via contact to electrically couple the first metal rail to the second metal rail; and forming a second via contact to electrically couple the second metal rail to the active region of the transistor.

[0121] One aspect of the specification relates to an integrated circuit. In some embodiments, the integrated circuit includes a first layer, the first layer including an active region of a transistor. In some embodiments, the integrated circuit includes a second layer, the second layer including a first metal rail coupled to a first side of the active region of the transistor, wherein the second layer is above the first layer along a first direction. In some embodiments, the integrated circuit includes a third layer, the third layer including a second metal rail coupled to a second side of the active region of the transistor through a first via contact, wherein the second side faces away from the first side. In one aspect, the first layer is above the third layer along the first direction. In some embodiments, the integrated circuit includes a fourth layer, the fourth layer including a third metal rail coupled to the second metal rail through a second via contact, wherein the third layer is above the fourth layer along the first direction.

[0122] In some embodiments, the integrated circuit includes another active region of the transistor. In some embodiments, the second layer includes a fourth metal rail, the fourth metal rail directly coupled to a first side of the another active region of the transistor. In some embodiments, the third layer includes a fifth metal rail, the fifth metal rail coupled to a second side of the another active region of the transistor through a third via contact. The third metal rail may provide a supply voltage to the active region of the transistor through the second metal rail, wherein the fifth metal rail may provide an electrical signal to or from the another active region of the transistor.

[0123] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit, comprising: A first layer, including a first metal rail; a second layer including a second metal track, the second layer being above the first layer along a first direction; a third layer including an active region of the transistor, the third layer being above the second layer along the first direction; a fourth layer, comprising a third metal track, the fourth layer being above the third layer along the first direction; as well as a fifth layer, comprising a fourth metal track, the fifth layer being above the fourth layer along the first direction, a sixth layer, comprising a fifth metal track between the first layer and the second layer, the second metal track extending in a second direction, the fifth metal track extending in a third direction, the first direction being orthogonal to the second direction and the third direction, Wherein, the third metal rail is directly coupled only to the second side of the active region of the transistor.

2. The integrated circuit according to claim 1, wherein: The first metal rail is used to provide a power supply voltage to the active region of the transistor through the second metal rail.

3. The integrated circuit according to claim 1, wherein: The third metal rail is used to provide an electrical signal from or to the transistor.

4. The integrated circuit according to claim 1, wherein: The first metal rail is electrically coupled to the fifth metal rail through a first via contact, and the second metal rail is electrically coupled to a first side of the active region of the transistor through a second via contact.

5. The integrated circuit according to claim 1, wherein: The third metal rail includes polysilicon, copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn) or aluminum (Al).

6. The integrated circuit according to claim 5, wherein: The fourth layer includes: An eighth metal rail is directly coupled to another active region of the transistor.

7. The integrated circuit according to claim 6, in, The third metal rail extends in the third direction perpendicular to the first direction, wherein the third metal rail includes a first end and a second end, and Wherein, the eighth metal rail extends in the third direction, wherein the eighth metal rail includes a third end and a fourth end, wherein the first end of the third metal rail and the third end of the eighth metal rail are aligned, wherein the second end of the third metal rail and the fourth end of the eighth metal rail are aligned.

8. The integrated circuit according to claim 7, wherein: The second layer includes: A sixth metal rail is coupled to the other active region of the transistor.

9. The integrated circuit of claim 8, wherein: The sixth metal rail is coupled to an active region of another transistor.

10. The integrated circuit of claim 9, further comprising: The seventh metal rail of the transistor extends in the third direction, the seventh metal rail is arranged between the active region of the transistor and the another active region of the transistor, and the seventh metal rail partially overlaps with the sixth metal rail.

11. The integrated circuit of claim 1, wherein: The fourth metal rail extends in the third direction perpendicular to the first direction, wherein the first metal rail extends in the second direction.

12. The integrated circuit of claim 1, wherein: The fourth metal rail is close to the third metal rail or partially overlaps with the third metal rail.

13. The integrated circuit of claim 1, wherein: The second metal rail and the fifth metal rail are electrically connected to each other through a third through-hole.

14. The integrated circuit of claim 1, wherein: The first metal rail is used to provide a power supply voltage to the second metal rail through the fifth metal rail.

15. A method of forming an integrated circuit, the method comprising: forming a first layer including a first metal track; forming a second layer including a second metal track, the second layer being above the first layer in a first direction; forming a third layer, the third layer including an active region of a transistor, the third layer being above the second layer along the first direction; forming a fourth layer including a third metal track, the fourth layer being above the third layer along the first direction; as well as forming a fifth layer including a fourth metal track, the fifth layer being above the fourth layer along the first direction, forming a sixth layer including a fifth metal track between the first layer and the second layer, the second metal track extending in a second direction, the fifth metal track extending in a third direction, the first direction being orthogonal to the second direction and the third direction, and the second direction being orthogonal to the third direction, the fifth metal track and the second metal track being electrically connected to each other through a through hole, Wherein, the third metal rail is directly coupled only to the top side of the active region of the transistor.

16. The method according to claim 15, wherein: The first metal rail is used to provide a power supply voltage to the active region of the transistor through the second metal rail, wherein the third metal rail is used to provide an electrical signal from or to the transistor.

17. The method according to claim 15, further comprising: forming a first via contact to electrically couple the first metal rail to the second metal rail; as well as A second via contact is formed to electrically couple the second metal rail to the active region of the transistor.

18. An integrated circuit comprising: The first layer includes the active area of ​​the transistor; a second layer including a first metal rail, the first metal rail being directly coupled only to a first side of the active region of the transistor, the second layer being above the first layer along a first direction; a third layer including a second metal rail coupled to a second side of the active region of the transistor through a first via contact, the second side facing away from the first side, the first layer being above the third layer along the first direction; as well as a fourth layer, comprising a third metal track, the third metal track being coupled to the second metal track through a second through-hole contact, the third layer being above the fourth layer along the first direction, a fifth layer, comprising a sixth metal rail between the third layer and the fourth layer, wherein the second metal rail extends in a second direction, the sixth metal rail extends in a third direction, the first direction is orthogonal to the second direction and the third direction, and the second direction is orthogonal to the third direction, and the sixth metal rail and the second metal rail are electrically connected to each other through a through hole.

19. The integrated circuit of claim 18, further comprising: another active region of the transistor; wherein the second layer comprises a fourth metal rail directly coupled to a first side of the other active region of the transistor; and Wherein, the third layer comprises a fifth metal track, and the fifth metal track is coupled to the second side of the another active region of the transistor through a third through-hole contact.

20. The integrated circuit of claim 19, wherein: The third metal rail is used to provide a power supply voltage to the active area of ​​the transistor through the second metal rail, wherein the fifth metal rail is used to provide an electrical signal to or from the other active area of ​​the transistor.

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