Semiconductor device package and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer, and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed above the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed above the antenna layer. The second circuit layer has a third CTE. The difference between the first CTE and the second CTE is less than the difference between the first CTE and the third CTE.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including an antenna. Background Art

[0002] One or more semiconductor device packages having an antenna for signal (e.g., radio frequency (RF) signal) transmission may include an antenna layer and an RF routing layer electrically connected to the antenna layer. To improve the radiation efficiency of the antenna layer, the antenna layer typically has a substrate with a relatively low dielectric constant (Dk) and loss tangent or dissipation factor (Df), which is different from the substrate of the RF routing layer. Such an unbalanced structure will cause warping problems during the manufacturing process, and the warping problems may lead to failures of the semiconductor device package. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes an antenna layer, a first circuit layer, and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed on the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed on the antenna layer. The second circuit layer has a third CTE. The difference between the first CTE and the second CTE is less than the difference between the first CTE and the third CTE.

[0004] In one or more embodiments, a semiconductor device package includes a substrate, a first circuit layer, and a second circuit layer. The substrate has a first surface and a second surface opposite the first surface. The first circuit layer is disposed on the first surface of the substrate. The first circuit layer has a first conductive layer and a first dielectric layer at least partially covering the first conductive layer. The second circuit layer is disposed on the first surface of the substrate. The second circuit layer has a second conductive layer and a second dielectric layer at least partially covering the second conductive layer. The dielectric constant (Dk) of the first dielectric layer is less than the Dk of the second dielectric layer.

[0005] In one or more embodiments, a method of manufacturing a semiconductor device package includes: (a) providing an antenna substrate having a first surface and a second surface opposite the first surface; (b) connecting a first circuit layer to the first surface of the substrate; (c) connecting a second circuit layer to the first surface of the substrate; and (d) forming a package body to cover the first circuit layer and the second circuit layer, wherein the package body further extends between the first circuit layer and the second layer. Brief Description of the Drawings

[0006] As will be readily understood from the following detailed description when read in conjunction with the accompanying drawings, aspects of the present disclosure can be easily understood. It should be noted that the various features may not necessarily be drawn to scale. For the sake of clarity in discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 1B A top view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0009] Figure 1C A top view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0010] Figure 1D A top view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0011] Figure 2A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0012] Figure 2B A top view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0013] Figure 2C A top view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0014] Figure 2D A top view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0015] Figure 2E A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0016] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0017] Figure 4A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0018] Figure 4B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0019] Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5DShows one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure.

[0020] Figure 6A 、 Figure 6B and Figure 6C Shows one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure.

[0021] Throughout the drawings and the detailed description, common reference numerals are used to indicate the same or similar elements. The present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings. Detailed Description

[0022] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, references to forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that may be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0024] Figure 1A Shows a cross-sectional view of a semiconductor device package 1 in accordance with some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10, an antenna layer 11, circuit layers 12, 13, electronic components 14, and a package body 15.

[0025] The substrate 10 has a surface 101 and a surface 102 opposite to the surface 101. The substrate 10 can be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. In some embodiments, the substrate 10 can be a multi-layer substrate including a core layer and conductive materials and / or structures. For example, the substrate 10 includes a core portion and can be of a wafer type, a panel type, or a strip type. The substrate 10 can include one or more conductive layers 10p1, 10p2 that are close to, adjacent to, or embedded in and exposed at two surfaces (e.g., surface 101 and surface 102) of the substrate 10. In some embodiments, the substrate 10 includes vias 10v that penetrate the substrate 10 to electrically connect the conductive layer 10p1 to the conductive layer 10p2. In some embodiments, a protective layer 10d (e.g., a leveling layer) can be disposed on the surface 101 of the substrate 10 to cover the conductive layer 10p1. For example, the side surfaces and the upper surface of the conductive layer 10p1 can be covered by and in contact with the protective layer 10d.

[0026] In some embodiments, the substrate 10 or a part of the substrate 10 and the antenna layer 11 can act as an antenna region. In some embodiments, the via 10v of the substrate 10 can act as a feedthrough via (or a feed port) of the antenna region. The thickness of the substrate 10 can act as the height of a resonator (or a resonant cavity) for RF signals transmitted from or received by the antenna region.

[0027] The antenna layer 11 is disposed on the surface 102 of the substrate 10. In some embodiments, the antenna layer 11 is in contact with the substrate 10. For example, the antenna layer 11 is in contact with the surface 102 of the substrate 10. The antenna layer 11 includes one or more conductive layers 11c1, 11c2 and one or more dielectric layers 11d. A part of the conductive layer 11c is covered or encapsulated by the dielectric layer 11d, while another part of the conductive layer 11c is exposed from the dielectric layer 11d. In some embodiments, the dielectric layer 11d can cover the conductive layer 10p2 of the substrate 10. For example, the conductive layer 10p2 is in contact with the dielectric layer 11d. In some embodiments, the conductive layers 11c1, 11c2 define or include an antenna pattern. The conductive layers 11c1, 11c2 can be electromagnetically coupled to the substrate 10 (e.g., coupled to the conductive layer 10p2) for signal transmission. In some embodiments, a protective layer 11s (e.g., a solder mask) is disposed on the surface of the dielectric layer 11d facing away from the substrate 10 to cover a part of the conductive layer 11c2.

[0028] In some embodiments, the dielectric layer 11d may comprise pre-impregnated composite fibers (e.g., prepregs), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination of two or more of the foregoing, etc. Examples of prepregs may include, but are not limited to, multi-layer structures formed by stacking or laminating multiple pre-impregnated materials / sheets. In some embodiments, the conductive layers 11c1, 11c2 are or comprise a conductive material such as a metal or a metal alloy. Examples of conductive materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), one or more other metals or one or more alloys, or a combination of two or more of the foregoing. Depending on different design specifications, any number of dielectric layers 11d and conductive layers 11c1, 11c2 may be present.

[0029] The circuit layer 12 is disposed on the surface 101 of the substrate 10. In some embodiments, the circuit layer 12 is connected to the protective layer 10d through an adhesive layer 10h (e.g., a tape or a die attach film (DAF)). The circuit layer 12 includes one or more conductive layers 12c and one or more dielectric layers 12d. A portion of the conductive layer 12c is covered or encapsulated by the dielectric layer 12d, while another portion of the conductive layer 12c is exposed from the dielectric layer 12d. In some embodiments, the circuit layer 12 may include conductive vias 12v (e.g., through-holes) that penetrate the dielectric layer 12d, the adhesive layer 10h, and the protective layer 10d to electrically connect to the conductive layer 10p1. For example, the conductive via 12v is in contact with the conductive layer 10p1. In some embodiments, the conductive layer 12c defines or comprises an antenna pattern. The conductive layer 12c may be electrically connected to the substrate 10 (e.g., electrically connected to the conductive layer 10p1) through the conductive via 12v for signal transmission.

[0030] In some embodiments, the dielectric layer 12d may comprise pre-impregnated composite fibers (e.g., prepregs), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination of two or more of the foregoing, etc. Examples of prepregs may include, but are not limited to, multi-layer structures formed by stacking or laminating multiple pre-impregnated materials / sheets. In some embodiments, the dielectric layer 12d and the dielectric layer 11d may comprise the same material. Alternatively, the dielectric layer 12d and the dielectric layer 11d may comprise different materials. In some embodiments, the conductive layer 12c and the conductive via 12v are or comprise a conductive material such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, one or more other metals or one or more alloys, or a combination of two or more of the foregoing. Depending on different design specifications, any number of dielectric layers 12d and conductive layers 12c may be present.

[0031] In some embodiments, such as Figure 1AAs shown, a part of the antenna layer 11 of the substrate 10 surrounded by the dashed square and a part of the conductive layer 10p2 can define an antenna A1, and another part of the antenna layer 11 and the circuit layer 12 surrounded by another dashed square can define another antenna A2. In some embodiments, antenna A1 and antenna A2 can include different types of antennas. Alternatively, antenna A1 and antenna A2 can include the same type of antenna. In some embodiments, antenna A1 and antenna A2 can include different operating frequencies or bandwidths. Alternatively, antenna A1 and antenna A2 can include the same operating frequency or bandwidth.

[0032] The circuit layer 13 (or routing layer) is disposed on the surface 101 of the substrate 10. The circuit layer 13 is disposed adjacent to the circuit layer 12. For example, as Figure 1B (which shows a top view of the semiconductor device package 1 according to some embodiments of the present disclosure as shown in Figure 1A ) shows, the circuit layer 13 and the circuit layer 12 are disposed side by side on the surface 101 of the substrate 10. For example, as Figure 1C (which shows a top view of the semiconductor device package 1 according to some embodiments of the present disclosure as shown in Figure 1A ) shows, the circuit layer 12 surrounds the circuit layer 13. For example, as Figure 1D (which shows a top view of the semiconductor device package 1 according to some embodiments of the present disclosure as shown in Figure 1A ) shows, the circuit layer 13 is disposed between the circuit layers 12. In other words, the circuit layer 13 is sandwiched between the circuit layers 12. In some embodiments, the circuit layer 12 and the circuit layer 13 are disposed at the same height relative to the substrate 10 (or the antenna layer 11).

[0033] Referring to Figure 1A , the circuit layer 13 is connected to the protective layer 10d through the adhesive layer 10h. The circuit layer 13 includes one or more conductive layers 13c and one or more dielectric layers 13d. A part of the conductive layer 13c is covered or encapsulated by the dielectric layer 13d, while another part of the conductive layer 13c is exposed from the dielectric layer 13d. In some embodiments, the circuit layer 13 can include conductive vias 13v that penetrate the dielectric layer 13d, the adhesive layer 10h, and the protective layer 10d to electrically connect to the conductive layer 10p1. The conductive layer 13c can be electrically connected to the substrate 10 (e.g., electrically connected to the conductive layer 10p1) through the conductive vias 13v for signal transmission. In some embodiments, the circuit layer 13 is electrically connected to the circuit layer 12 through the substrate 10 (e.g., through the conductive layer 10p1).

[0034] In some embodiments, the dielectric layer 13d may comprise a polymer or any other suitable material. In some embodiments, the Dk and Df of the dielectric layer 13d are higher than those of the dielectric layers 11d, 12d. For example, the Dk of the dielectric layers 11d, 12d is less than about 5. The Dk of the dielectric layers 11d, 12d is less than about about 3. The Df of the dielectric layers 11d, 12d is less than about 0.005. The Df of the dielectric layers 11d, 12d is less than about 0.003.

[0035] In some embodiments, the stiffness of the dielectric layer 13d is higher than that of the dielectric layers 11d, 12d. In some embodiments, the coefficient of thermal expansion (CTE) of the dielectric layers 11d, 12d is greater than that of the dielectric layer 13d. For example, the CTE of the dielectric layers 11d, 12d is about 120K -1 to about 150K -1 and the CTE of the dielectric layer 13d is about 20K -1 to about 50K -1 . In some embodiments, the dielectric layer 13d may comprise fibers, and the dielectric layers 11d and 12d do not comprise fibers.

[0036] In some embodiments, the conductive layer 13c is or comprises a conductive material such as a metal or a metal alloy. Examples of conductive materials include Au, Ag, Cu, Pt, Pd, one or more other metals or one or more alloys or a combination of two or more of them. Depending on different design specifications, any number of dielectric layers 13d and conductive layers 13c may be present. In some embodiments, the line / space (L / S or pitch or density) of the conductive layer 12c of the circuit layer 12 is higher than the L / S of the conductive layer 13c of the circuit layer 13.

[0037] In some embodiments, the thickness of the circuit layer 13 is substantially the same as the thickness of the circuit layer 12. Alternatively, the thickness of the circuit layer 13 is different from the thickness of the circuit layer 12. In some embodiments, the number of dielectric layers 13d and conductive layers 13c of the circuit layer 13 is the same as the number of dielectric layers 12d and conductive layers 12c of the circuit layer 12. Alternatively, the number of dielectric layers 13d and conductive layers 13c of the circuit layer 13 is different from the number of dielectric layers 12d and conductive layers 12c of the circuit layer 12.

[0038] The electronic component 14 is disposed on the circuit layer 13 and electrically connected to the circuit layer 13, and the electrical connection can be achieved by flip-chip or wire bonding technology. The electronic component 14 may be a chip or a die, and the chip or die comprises a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnect structures therein. The integrated circuit devices may comprise active devices such as transistors and / or passive devices such as resistors, capacitors, inductors or a combination thereof.

[0039] The package 15 is disposed on the circuit layer 12 and the circuit layer 13, and encapsulates the electronic component 14. In some embodiments, the package 15 comprises an epoxy resin with fillers dispersed therein.

[0040] In some comparative embodiments, an antenna layer having a dielectric layer with a relatively low Dk and Df is directly disposed on a circuit layer having a dielectric layer with a relatively high Dk and Df. However, such an unbalanced structure will cause warping problems (e.g., warping greater than 5 mm) during the manufacturing process, which may lead to failures of semiconductor device packages. According to an embodiment, as Figures 1A to 1D shown, two circuit layers (or routing layers) are disposed above the antenna layer 11. One circuit layer (i.e., the circuit layer 12) has a dielectric layer 12d with a Dk and Df similar to or the same as those of the dielectric layer 11d of the antenna layer 11, and the other circuit layer (i.e., the circuit layer 13) has a relatively high Dk and Df to provide higher stiffness for the semiconductor device package 1. The warping problem can be eliminated or alleviated.

[0041] In addition, in some embodiments of the present disclosure, since the dielectric layer 12d of the circuit layer 12 does not have fibers, the pitch of the conductive vias 12v of the circuit layer 12 is smaller than the pitch of the conductive vias 13v of the circuit layer 13. Therefore, the density (or L / S) of the conductive layer 12c of the circuit layer 12 is higher than the density of the conductive layer 13c of the circuit layer 13. This will reduce the number of the conductive layers 13c of the circuit layer 13 required for signal transmission, and the thickness of the semiconductor device package 1 can also be reduced. In some embodiments, when the ratio of the area of the circuit layer 12 to the area of the circuit layer 13 is about 2:3, the number of the conductive layers 13c of the circuit layer 13 can be reduced by 1 layer. When the ratio of the area of the circuit layer 12 to the area of the circuit layer 13 is about 1:1, the number of the conductive layers 13c of the circuit layer 13 can be reduced by 2 layers. In some embodiments, the ratio of the area of the circuit layer 12 to the area of the circuit layer 13 is in the range of about 2:3 to about 7:3. In some embodiments, the thickness of the semiconductor device package 1 is equal to or less than 950 microns.

[0042] Figure 2A A cross-sectional view of a semiconductor device package 2A according to some embodiments of the present disclosure is shown. The semiconductor device package 2A is similar to Figure 1A the semiconductor device package 1 shown in Figure 2A except that, in

[0043] as Figure 2B (which shows as Figure 2AAs shown in the top view of semiconductor device package 2A according to some embodiments of the present disclosure), the circuit layer 13 and the circuit layer 12 are arranged side by side on the surface 101 of the substrate 10. As Figure 2C (which shows the Figure 2A top view of semiconductor device package 2A according to some embodiments of the present disclosure as shown in Figure 2D (which shows the Figure 2A top view of semiconductor device package 2A according to some embodiments of the present disclosure as shown in

[0044] Figure 2E shows a cross-sectional view of semiconductor device package 2E according to some embodiments of the present disclosure. Semiconductor device package 2E is similar to Figure 2A semiconductor device package 2A as shown in Figure 2A , except that in

[0045] Figure 3 shows a cross-sectional view of semiconductor device package 3 according to some embodiments of the present disclosure. Semiconductor device package 3 is similar to Figure 1A semiconductor device package 1 as shown in

[0046] As Figure 3 shown, the portion 15a of the package body 15 is arranged between the circuit layer 12 and the circuit layer 13. For example, the circuit layer 12 and the circuit layer 13 are spaced apart from each other by the package body 15. For example, the side surface of the circuit layer 12 facing the circuit layer 13 contacts the portion 15a of the package body 15. For example, the side surface of the circuit layer 13 facing the circuit layer 12 contacts the portion 15a of the package body 15. Using the package body 15 that covers the circuit layer 12 and the circuit layer 13 and extends between the circuit layer 12 and the circuit layer 13 can prevent the circuit layer 12 from peeling off from the circuit layer 13 (e.g., delamination problem). In some embodiments, the thickness of the portion 15a of the package body 15 is equal to or greater than 150 micrometers. For example, the distance between the circuit layer 12 and the circuit layer 13 is equal to or greater than 150 micrometers.

[0047] Figure 4A shows a cross-sectional view of semiconductor device package 4A according to some embodiments of the present disclosure. Semiconductor device package 4A is similar to Figure 3 semiconductor device package 3 as shown in

[0048] A protective layer 30d (e.g., a planarization layer) is disposed on the surface 102 of the substrate 10 to cover the conductive layer 10p2. For example, the side surfaces and the upper surface of the conductive layer 10p2 may be covered by and in contact with the protective layer 30d.

[0049] The antenna layer 11 is connected to the protective layer 30d by an adhesive layer 30h (e.g., a tape or DAF). The antenna layer 11 may include conductive vias 11v (e.g., through vias) that penetrate the dielectric layer 11d, the adhesive layer 30h, and the protective layer 30d to electrically connect to the conductive layer 10p2. For example, the conductive vias 11v are in contact with the conductive layer 10p2. The conductive layer 11c1 may be electrically connected to the substrate 10 (e.g., electrically connected to the conductive layer 10p2) through the conductive vias 11v for signal transmission. In other embodiments, the conductive vias 11v may be omitted, and signal transmission may be achieved by magnetic coupling.

[0050] Figure 4B A cross-sectional view of a semiconductor device package 4B according to some embodiments of the present disclosure is shown. The semiconductor device package 4B is similar to Figure 4B the semiconductor device package 4A shown in

[0051] The package body 15 further covers the side surfaces of the circuit layers 12, 13, the substrate 10, and the antenna layer 11. In some embodiments, the distance between the side surfaces of the circuit layer 12 or 13 and the side surface of the package body 15 is in the range of about 2 millimeters to about 3 millimeters.

[0052] Figure 5A 、 Figure 5B 、 Figure 5C and 5D are cross-sectional views of semiconductor device packages at different manufacturing stages according to some embodiments of the present disclosure. At least some of these drawings have been simplified for a better understanding of aspects of the present disclosure. In some embodiments, Figure 5A 、 Figure 5B 、 Figure 5C and 5D the methods shown can be used to manufacture Figure 1A the semiconductor device package 1 shown in

[0053] Referring to Figure 5A , a substrate 10 (or a core) is provided. Conductive layers 10p1 and 10p2 are disposed on the surfaces 101 and 102, respectively. One or more vias 10v penetrate the substrate 10 to electrically connect the conductive layer 10p1 to the conductive layer 10p2.

[0054] Referring to Figure 5B, an antenna layer 11 including conductive layers 11c1, 11c2, a dielectric layer 11d, and a protective layer 11s (e.g., solder mask) is formed on the surface 102 of the substrate 10. In some embodiments, the antenna layer 11 can be formed on the surface 102 of the substrate 10 by, for example, lamination or any other suitable process. A protective layer 10d (e.g., planarization layer) is formed on the surface 101 of the substrate 10 to cover the conductive layer 10p1.

[0055] Reference Figure 5C , a circuit layer 12 including one or more conductive layers 12c, conductive vias 12v1, and a dielectric layer 12d is connected to the protective layer 10d through an adhesive layer 10h (e.g., tape or DAF). The conductive vias 12v1 are electrically connected to the conductive layers 12c at different layers. A circuit layer 13 including a conductive layer 13c, conductive vias 13v1, and a dielectric layer 13d is connected to the protective layer 10d through the adhesive layer 10h. The conductive vias 13v1 are electrically connected to the conductive layer 13c at different layers.

[0056] Reference Figure 5D , one or more conductive vias (e.g., through-holes) 12v are formed, and the one or more conductive vias penetrate the dielectric layer 12d, the adhesive layer 10h, and the protective layer 10d to be electrically connected to the conductive layer 10p1. One or more conductive vias (e.g., through-holes) 13v are formed, and the one or more conductive vias penetrate the dielectric layer 13d, the adhesive layer 10h, and the protective layer 10d to be electrically connected to the conductive layer 10p1.

[0057] An electronic component 14 is placed on the circuit layer 13 and electrically connected to the circuit layer 13. Then, an encapsulation body 15 is formed on the circuit layers 12 and 13 by, for example, molding or any other suitable technique to cover the electronic component 14.

[0058] Figure 6A , Figure 6B and 6C are cross-sectional views of semiconductor device packages at different manufacturing stages according to some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of aspects of the present disclosure. In some embodiments, Figure 6A , Figure 6B and 6C The methods shown in can be used to manufacture Figure 4A The semiconductor device package 4A shown in. In some embodiments, Figure 6A The operations in can be performed after Figure 5A The operations shown in.

[0059] Reference Figure 6A, a protective layer 30d (e.g., a planarization layer) is formed on the surface 102 of the substrate 10 to cover the conductive layer 10p2. An antenna layer 11 including conductive layers 11c1, 11c2, a dielectric layer 11d, and a protective layer 11s (e.g., a solder resist) is connected to the protective layer 30d through an adhesive layer 30h (e.g., a tape or DAF). A protective layer 10d (e.g., a planarization layer) is formed on the surface 101 of the substrate 10 to cover the conductive layer 10p1.

[0060] Reference Figure 6B , a circuit layer 12 including one or more conductive layers 12c, conductive vias 12v1, and a dielectric layer 12d is connected to the protective layer 10d through an adhesive layer 10h (e.g., a tape or DAF). The conductive vias 12v1 are electrically connected to the conductive layers 12c at different layers. A circuit layer 13 including conductive layers 13c, conductive vias 13v1, and a dielectric layer 13d is connected to the protective layer 10d through the adhesive layer 10h. The conductive vias 13v1 are electrically connected to the conductive layers 13c at different layers. The circuit layer 12 and the circuit layer 13 are spaced apart from each other. For example, a gap 15h exists between the circuit layer 12 and the circuit layer 13.

[0061] Reference Figure 6C , one or more conductive vias (e.g., through vias) 12v are formed, and the one or more conductive vias penetrate the dielectric layer 12d, the adhesive layer 10h, and the protective layer 10d to be electrically connected to the conductive layer 10p1. One or more conductive vias (e.g., through vias) 13v are formed, and the one or more conductive vias penetrate the dielectric layer 13d, the adhesive layer 10h, and the protective layer 10d to be electrically connected to the conductive layer 10p1.

[0062] An electronic component 14 is placed on the circuit layer 13 and electrically connected to the circuit layer 13. Then, an encapsulation 15 is formed on the circuit layers 12 and 13 through, for example, molding or any other suitable technique to cover the electronic component 14. The encapsulation 15 is further formed in the gap 15h between the circuit layer 12 and the circuit layer 13. For example, a portion 15a of the encapsulation 15 is disposed between the circuit layer 12 and the circuit layer 13. For example, the side surface of the circuit layer 12 facing the circuit layer 13 contacts the portion 15a of the encapsulation 15, and the side surface of the circuit layer 13 facing the circuit layer 12 contacts the portion 15a of the encapsulation 15.

[0063] In this document, spatial relative terms such as "below", "beneath", "lower", "above", "upper", "left", "right", etc. may be used for ease of description to describe the relationship of one element or feature to another or other elements or features as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it may be directly connected to or coupled to the other element, or there may be intervening elements.

[0064] As used herein, the terms "about", "substantially", "essentially", and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where it approximately occurs. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another endpoint or as between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified. The term "substantially coplanar" may refer to a positional difference between two surfaces positioned in the same plane within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm of being positioned in the same plane. When a numerical value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the value.

[0065] The foregoing outlines the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be readily used as a basis for designing or modifying other processes and structures so as to facilitate the implementation of the same or similar purposes and / or achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device package, comprising: An antenna layer having a first CTE; A first circuit layer disposed above the antenna layer, the first circuit layer having a second CTE; And A second circuit layer disposed above the antenna layer, the second circuit layer having a third CTE, Wherein the difference between the first CTE and the second CTE is less than the difference between the first CTE and the third CTE, Wherein the first circuit layer is disposed adjacent to the second circuit layer, and the first circuit layer and the second circuit layer are disposed at the same height relative to the antenna layer.

2. The semiconductor device package according to claim 1, wherein the first circuit layer surrounds the second circuit layer.

4. The semiconductor device package according to claim 1, further comprising:

3. The semiconductor device package according to claim 1, wherein the first circuit layer is in contact with the second circuit layer. A package covering the first circuit layer and the second circuit layer.

6. The semiconductor device package according to claim 1, further comprising:

5. The semiconductor device package according to claim 4, wherein the package further extends between the first circuit layer and the second circuit layer. A substrate having a first surface and a second surface opposite the first surface, wherein the first circuit layer and the second circuit layer are disposed on the first surface of the substrate, the antenna layer is disposed on the second surface of the substrate, and at least a portion of the antenna layer and the substrate defines an antenna region.

7. The semiconductor device package according to claim 6, wherein the substrate comprises: A first conductive layer disposed on the first surface of the substrate; A second conductive layer disposed on the second surface of the substrate; And A feedthrough via penetrating the substrate and electrically connecting the first conductive layer and the second conductive layer.

8. The semiconductor device package according to claim 7, wherein the first circuit layer comprises: A third conductive layer; A first dielectric layer at least partially covering the third conductive layer; And 9. The semiconductor device package according to claim 8, further comprising: A first via penetrating the first dielectric layer and the first leveling layer to electrically connect to the first conductive layer.

10. The semiconductor device package according to claim 9, further comprising: A first leveling layer disposed on the first surface of the substrate and covering the first conductive layer. A first adhesive layer connecting the first circuit layer to the first leveling layer, wherein the first via further penetrates the first adhesive layer.

11. The semiconductor device package according to claim 9, wherein the second circuit layer comprises: A fourth conductive layer; A second dielectric layer at least partially covering the fourth conductive layer; And A second via penetrating the second dielectric layer and the first leveling layer to electrically connect to the first conductive layer.

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