Semiconductor device and method for forming the same

Abstract

A semiconductor device according to an embodiment of the present invention includes a gate-all-around (GAA) transistor in a first device region and a fin field effect transistor (FinFET) in a second device region. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure above and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure above the fin-shaped channel member. The fin-shaped channel member includes a semiconductor layer interlaced by a sacrificial layer. An embodiment of the present application also provides a method for forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCE). A multi-gate device generally refers to a device in which a gate structure or a portion thereof is arranged over multiple sides of a channel region. Fin-type field effect transistors (FinFETs) and gate-all-around (GAA) transistors (both also referred to as non-planar transistors) are examples of multi-gate devices that have become popular candidates for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). This structure provides better control over the channel and greatly reduces SCE (particularly by reducing subthreshold leakage (i.e., coupling between the source and drain of a FinFET in the "off" state)) compared to planar transistors. A GAA transistor has a gate structure that can extend partially or completely around a channel region to provide access to a channel region on two or more sides. The channel region of the GAA transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. In some embodiments, such a channel region includes a plurality of nanostructures stacked vertically (which extend horizontally, thereby providing a horizontally oriented channel). Such a GAA transistor can be referred to as a vertically stacked horizontal GAA (VGAA) transistor.

[0004] GAA transistors and FinFETs can be fabricated on the same substrate to take advantage of the advantages of both types of multi-gate devices. Traditionally, because the fabrication of GAA transistors and the fabrication of FinFETs require different epitaxial layer arrangements and involve different process steps, it may be challenging or expensive to fabricate GAA transistors and FinFETs on the same substrate. Therefore, although conventional devices and methods have generally been adequate for their intended purposes, they are unsatisfactory in various aspects. Summary of the invention

[0005] In some embodiments, a semiconductor device includes: a first transistor in a first device region, the first transistor including: a plurality of vertically stacked channel components, and a first gate structure located above and around the plurality of vertically stacked channel components; and a second transistor located in a second device region, the second transistor including: a fin-shaped channel component, and a second gate structure located above the fin-shaped channel component, wherein the fin-shaped channel component includes a semiconductor layer interleaved by a sacrificial layer, wherein the semiconductor layer includes a first semiconductor material and the sacrificial layer includes a second semiconductor material or a dielectric material, wherein the first semiconductor material is different from the second semiconductor material, and wherein the plurality of vertically stacked channel components include the first semiconductor material.

[0006] In some embodiments, a semiconductor device includes: a fin-shaped channel component located in a first region; and a first gate structure located above the fin-shaped channel component, wherein the fin-shaped channel component includes multiple semiconductor layers interleaved by multiple sacrificial layers, wherein each of the multiple semiconductor layers includes a first semiconductor material, and each of the multiple sacrificial layers includes a second semiconductor material or a dielectric material, wherein the first semiconductor material is different from the second semiconductor material.

[0007] In some embodiments, a method includes: forming a stack of multiple semiconductor layers interlaced with multiple sacrificial layers on a substrate; forming a first fin element from the stack in a first region of the substrate, and forming a second fin element from the stack in a second region of the substrate; forming a first dummy gate stack above the first fin element, and forming a second dummy gate stack above the second fin element; depositing a gate spacer layer above the first dummy gate stack and the second dummy gate stack; forming a first source / drain groove in the first region, and forming a second source / drain groove in the second region; selectively and partially etching the multiple sacrificial layers in the first region to form multiple internal spacer grooves; forming multiple internal spacer components in the multiple internal spacer grooves in the first region; and forming a first source / drain component in the first source / drain groove, and forming a second source / drain component in the second source / drain groove.

[0008] Embodiments of the present application provide methods for forming different types of devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various functional components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various functional components may be arbitrarily enlarged or reduced for clarity of discussion.

[0010] Figure 1 A flow chart of a method for forming a semiconductor device having multiple device regions according to one or more aspects of the present invention is shown.

[0011] Figures 2 to 17 According to one or more aspects of the present invention, Figure 1 A partial cross-sectional view of a workpiece during the manufacturing process of the method. DETAILED DESCRIPTION

[0012] The following invention provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Further, for ease of description, as shown in the figures, spatially relative terms such as "under", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) elements or components. In addition to the orientation shown in the figures, the spatially relative terms are intended to cover different orientations of the device being used or operated. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Further, when "about", "approximately", etc. are used to describe a number or a range of numbers, the term is intended to cover numbers within + / -10% of the described number, unless otherwise specified. For example, the term "approximately 5nm" covers a size range from 4.5nm to 5.5nm.

[0014] The present invention relates generally to multi-gate transistors and methods of fabrication, and more particularly to the fabrication of gate-all-around (GAA) transistors and fin field effect transistors (FinFETs) in different device regions of a semiconductor device.

[0015] Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of the channel region. These multi-gate devices may include p-type metal oxide semiconductor devices or n-type metal oxide semiconductor devices. Examples of multi-gate transistors include FinFETs because of their fin-shaped structures and all-around gate (GAA) devices. Gallium arsenide devices include any device whose gate structure or a portion thereof is formed on the 4 sides of the channel region (e.g., a portion surrounding the channel region). Embodiments of the present invention may have channel regions arranged in nanowire channels, nanosheet channels, nanostructure channels, columnar channels, post-shaped channels, and / or other appropriate channel configurations. Devices according to the present invention may have one or more channel regions (e.g., nanowires, nanosheets, nanostructures) associated with a single continuous gate structure. However, however, a person of ordinary skill will recognize that the teachings in the present invention may be applicable to a single channel (e.g., a single nanowire, a single nanosheet, a single nanostructure) or any number of channels. A person of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from various aspects of the present invention.

[0016] As the proportion of fin width in FinFET decreases, the change in channel width may cause undesirable changes and mobility loss. GAA transistors are being studied as an alternative to FinFET. In a GAA transistor, the gate of the transistor is formed around the entire channel so that the channel is surrounded or wrapped by the gate. The advantage of this transistor is the improved electrostatic control of the gate over the channel, which also mitigates leakage current. Although GAA transistors have advantages over FinFETs, the reduced size of the channel components of GAA transistors makes them less suitable for high current applications. For this and other reasons, it may be desirable to manufacture GAA transistors and FinFETs on the same substrate to take advantage of the different properties of GAA transistors and FinFETs. In some conventional schemes, different epitaxial layer regions are formed above the substrate so that GAA transistors are formed in certain regions and FinFETs are formed in other regions. For example, a stack of alternating layers of two different semiconductor materials can be deposited on a substrate. Then, the stack of alternating layers of two different semiconductor materials is selectively removed from a first region of the substrate, while the stack remains in place in a second region of the substrate. The semiconductor layer is then epitaxially deposited in the first region. FinFETs are fabricated over and from a first region, and GAA transistors are fabricated over and from a second region. Forming different epitaxial regions in these conventional schemes involves additional steps, which may increase cost and reduce yield. The present invention provides a method for fabricating GAA transistors and FinFETs on the same substrate without the need to form different epitaxial layer regions over the substrate. FinFETs fabricated according to the method of the present invention include alternating layers of two semiconductor materials that are conventionally suitable for forming GAA transistors. Therefore, FinFETs fabricated according to the method of the present invention may be referred to as layered FinFETs.

[0017] Figure 1 1 is a method 100 for forming a semiconductor device having multiple device regions of a multi-gate device. As used herein, the term "multi-gate device" is used to describe a device (i.e., a semiconductor device) having at least some gate material arranged on multiple sides of at least one channel of the device. In some instances, the multi-gate device can be a GAA device having gate material arranged on at least four sides of at least one channel member of the device, or a FinFET having gate material arranged on three sides of a fin-shaped channel region. The channel member in a GAA transistor can be referred to as a nanowire, a nanosheet, a nanostructure, a channel member, or a semiconductor channel member. The channel member in a GAA transistor can have various geometries (e.g., cylindrical, bar, sheet) and various sizes.

[0018] The following will be combined Figures 2 to 16The operations of method 100 or other method embodiments are described by referring to the partial cross-sectional view of workpiece 200 shown in . Some operations may be described only briefly herein. At the end of the operations of method 100, workpiece 200 will be manufactured into semiconductor device 200. In this sense, workpiece 200 may be referred to as semiconductor device 200 as the context requires. In addition, the exemplary semiconductor device may include various other devices and components, such as other types of devices, including additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, SRAM and / or other logic circuits, etc., but they are simplified for a better understanding of the inventive concepts of the present invention. In some embodiments, the exemplary device includes a plurality of semiconductor devices (e.g., transistors) that may be interconnected, the plurality of semiconductor devices including n-type GAA transistors, p-type GAA transistors, PFETs, NFETs, etc. In addition, it should be noted that the process steps of method 100 include reference to Figures 2 to 16 Any description given, together with the rest of the method and the exemplary appendices provided in this invention Figure 1 The present invention is intended to be illustrative only and is not intended to be limiting beyond the scope of the invention as specifically described in the following claims.

[0019] refer to Figure 1 and Figure 2 , the method 100 includes a block 102 in which a stack 204 is formed over a substrate 202. The stack 204 includes semiconductor layers 206 and sacrificial layers 208 vertically stacked in an alternating manner. Figure 2 , a workpiece 200 having a first device region 10 and a second device region 20 is shown. The workpiece 200 includes a substrate 202, which may be a semiconductor substrate such as a silicon substrate. The substrate 202 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. As is known in the art, depending on the design requirements, the substrate 202 may include various doping configurations. For example, in regions designed for different device types (e.g., n-type GAA transistors, p-type GAA transistors), different doping profiles (e.g., n-wells, p-wells) may be formed on the substrate 202. Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. In an embodiment of the method 100, an anti-punch-through (APT) implant is performed. For example, an APT implant may be performed in a region below the channel region of the device to prevent breakdown or unnecessary diffusion.

[0020] The stack 204 includes a semiconductor layer 206 interposed by a sacrificial layer 208. The stack 204 may also be referred to as a layer stack 204 or an epitaxial stack 204. Figure 2As shown, the semiconductor layer 206 and the sacrificial layer 208 are alternately deposited along the Z direction so that they are staggered. The components of the semiconductor layer 206 and the sacrificial layer 208 are different to allow the sacrificial layer 208 to be selectively removed in subsequent operations. In some embodiments, the semiconductor layer 206 can be formed of silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), or a combination thereof, while the sacrificial layer 208 can be formed of a semiconductor material or a dielectric material. In some embodiments, the semiconductor material for the sacrificial layer 208 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), or a combination thereof. In some embodiments, the dielectric material for the sacrificial layer 208 may include silicon oxide, silicon nitride, or silicon oxide. For the avoidance of doubt, although the material selection of the semiconductor layer 206 and the sacrificial layer 208 may overlap, the selected components of the semiconductor layer 206 and the sacrificial layer 208 are different in terms of etching selectivity or oxidation rate in the presence of an oxidant. When both the semiconductor layer 206 and the sacrificial layer 208 are formed of a semiconductor material, they may also be formed of a semiconductor material selected from silicon carbide (SiC), gallium phosphide (GaP), indium phosphide (InP), indium antimonide (InSb), gallium arsenide (GaAsP), aluminum indium arsenide (AlInAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP) and / or gallium indium arsenide (GaInAsP) or a combination thereof. In an embodiment, the semiconductor layer 206 may be formed of silicon (Si), and the sacrificial layer 208 may be formed of silicon germanium (SiGe).

[0021] The stack 204 may be formed using an epitaxial growth process such as a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor layer 206 includes the same material as the substrate 202. In some embodiments where both the semiconductor layer 206 and the sacrificial layer 208 are formed of semiconductor materials, the semiconductor layer 206 and the sacrificial layer 208 may be substantially dopant-free (i.e., having approximately 0 cm -3 to about 1x10 17 cm -3 of extrinsic dopant concentration), where, for example, no intentional doping is performed during its epitaxial growth.

[0022] Note that Figure 2As shown in other figures, three (3) layers of semiconductor layer 206 and three (3) layers of sacrificial layer 208 are arranged alternately, which is for exemplary purposes only and is not intended to limit the content beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers can be formed in the epitaxial stack 204. The number of layers depends on the number of channel components required for the device 200. In some embodiments, the number of semiconductor layers 206 can be between 2 and 10. It should also be noted that although in Figure 2 The first device region 10 and the second device region 20 of the workpiece 200 are shown respectively, but Figure 2 The first device region 10 and the second device region 20 shown in FIG. 2 are snapshots of different device regions on the workpiece 200. With respect to the substrate 202, the first device region 10 and the second device region 20 also represent different regions above the substrate 202.

[0023] In such Figure 2 In some embodiments shown, each semiconductor layer 206 has a substantially identical first thickness (T1), and each sacrificial layer 208 has a substantially identical second thickness (T2). Here, substantially identical means that there is no intentional thickness variation. The first thickness T1 and the second thickness T2 can be selected based on different considerations, such as the channel width of the resulting GAA transistor and the difficulty of forming various layers in the gate structure. As will be described in more detail below, the semiconductor layer 206 or a portion thereof will become a channel member of the subsequently formed GAA transistor. For this reason, the semiconductor layer 206 may also be referred to as a channel layer 206. A larger first thickness T1 of the semiconductor layer 206 will result in a larger channel width. The sacrificial layer 208 from between the semiconductor layers 206 can eventually be removed to release the channel member formed by the semiconductor layer 206. The larger second thickness T2 of the sacrificial layer 208 is used to define the vertical distance between adjacent channel regions. As a result, when a larger channel width is desired, the first thickness T1 can be greater than the second thickness T2. When the difficulty of forming the gate structure is concerned, the second thickness T2 can be equal to or less than the first thickness T1.

[0024] refer to Figure 1 , Figure 3 and Figure 4, the method 100 includes a frame 104, wherein a first fin element 210A is formed from a stack 204 in a first device region 10, and a second fin element 210B is formed from a stack 204 in a second device region 20. Although not shown in detail, in some exemplary processes, a fin top hard mask layer may be deposited over the workpiece 200, including over the stack 204. The fin top hard mask layer may be a single layer or multiple layers. In some embodiments, the fin top hard mask layer may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or a combination thereof. In an embodiment where the fin top hard mask layer is a multilayer, the multilayer may include a silicon oxide layer deposited on the stack 204 and a silicon nitride layer deposited on the silicon oxide layer. The fin top hard mask layer is used to pattern the fin top hard mask layer in a pattern process. Then, the patterned fin top hard mask layer is used as an etching mask to form the first fin element 210A and the second first fin element 210B. For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. The patterning process may be performed on the workpiece 200 until the first fin element 210A and the second fin element 210B extend from the substrate 202. In some embodiments, the patterning is also etched into the substrate 202 so that each of the first fin element 210A and the second fin element 210B includes a lower portion formed by the substrate 202 and an upper portion formed by the stack 204. The upper portion includes each of the semiconductor layer 206 and the sacrificial layer 208 in the stack 204. In some embodiments, the first fin element 210A and the second fin element 210B may be manufactured using a double patterning or multiple patterning process. Typically, a double patterning or multiple patterning process combines photolithography and self-aligned processes, thereby allowing for the production of patterns having, for example, smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial dummy layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial dummy layer using a self-aligned process. The sacrificial dummy layer is then removed, and the remaining spacers or mandrels can then be used to pattern the first fin element 210A and the second fin element 210B by etching the stack 204. As shown in FIG. Figure 3 As shown, the first fin element 210A and the second fin element 210B extend longitudinally along the Y direction (ie, into or out of the Figure 3 ).

[0025] Reference now Figure 4. After forming the first fin element 210A and the second fin element 210B, an isolation feature 212 is formed between adjacent fin elements, such as, between two adjacent first fin elements 210A (only one is shown in the first device region 10) or between two adjacent second fin elements 210B (only one is shown in the second device region 20). The isolation feature 212 may also be referred to as a shallow trench isolation (STI) feature 212. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202, and the trench between the first fin element 210A and the second fin element 210B is filled with a dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric layer, a combination thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed by a dry etching process, a wet etching process, and / or a combination thereof to form the STI feature 212. After the recessing, at least the upper portions of the first fin element 210A and the second fin element 210B are higher than the STI feature 212. In some embodiments, the dielectric layer (and subsequently formed STI feature 212) may include a multi-layer structure, for example, with one or more liner layers. To better illustrate various embodiments of the present invention, Figure 4 Initially, each of the first fin element 210A in the first device region 10 and the second fin element 210B in the second device region 20 is shown above in the longitudinal direction (Y direction) and in the width direction (X direction).

[0026] refer to Figure 1 and Figure 5 , the method 100 includes block 106, in which a dummy gate stack 224 is formed over the channel region 10C of the first fin element 210A and the channel region 20C of the second fin element 210B. Although the dummy gate stack 224 does not appear in the cross-sectional view along the Y direction, Figure 5 The dummy gate stack 224 is shown in dashed lines. For simplicity, the dummy gate stack 224 is not shown in dashed lines in subsequent figures. In some embodiments, a gate replacement process (or gate last process) is used, in which the dummy gate stack 224 is used as a placeholder for a functional gate structure and is removed and replaced by a functional gate structure in a subsequent process. Other processes and structures are possible. Figure 5As shown in , a pseudo dielectric layer 214, which may be formed of silicon oxide, silicon nitride, or other suitable dielectric materials, is first deposited on the workpiece 200 by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, or an ALD process, including a first fin element 210A and a second fin element 210B. The pseudo dielectric layer 214 can be used to prevent damage to the fin element by subsequent processes. Then, a pseudo gate electrode layer 216, which may be formed of polysilicon, is deposited on the pseudo dielectric layer 214. For patterning, a gate top hard mask 218 may be deposited on the pseudo gate electrode layer 216. The gate top hard mask 218 may be a single layer or multiple layers, and may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, or a combination thereof. In the case where the gate top hard mask 218 is multilayer, the gate top hard mask 218 includes a silicon oxide layer 220 deposited on the pseudo gate electrode layer 216 and a silicon nitride layer 222 deposited on the silicon oxide layer 220. The gate top hard mask 218, the dummy gate electrode layer 216 and the dummy dielectric layer 214 are patterned into a patterning process, which may include a photolithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods.

[0027] After forming the dummy gate stack 224 over the channel region 10C of the first fin element 210A, a source / drain (S / D) region 10SD adjacent to the channel region 10C is further defined. Similarly, after forming the dummy gate stack 224 over the channel region 20C of the second fin element 210B, a source / drain (S / D) region 20SD adjacent to the channel region 20C is further defined.

[0028] refer to Figure 1 and Figure 6 , the method 100 includes a frame 108, in which a gate spacer layer 226 is deposited over the workpiece 200, including over the dummy gate stack 224, the first fin element 210A and the second fin element 210B. In some embodiments, the material used to form the gate spacer layer 226 is conformally deposited on the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 224. To facilitate describing a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. The gate spacer layer 226 may have a single layer structure or include multiple layers. Figure 6In some of the illustrated embodiments, the gate spacer layer 226 includes a single layer structure. The gate spacer layer 226 may include silicon oxide, silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, silicon oxide, other suitable dielectric materials, or combinations thereof. The spacer material may be deposited on the dummy gate stack 224 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, or other suitable process. The gate spacer material is then etched back in an anisotropic etching process to form the gate spacer layer 226. The anisotropic etching process exposes portions of the first fin element 210A and the second fin element 210B that are adjacent to but not covered by the dummy gate stack 224 (e.g., above the source / drain regions 10SD and 20SD). Although in Figure 6 Although not explicitly shown, in some alternative embodiments, a portion of the gate spacer material directly above the dummy gate stack 224 may be partially or completely removed by the anisotropic etching process, while the gate spacer layer 226 remains on the sidewalls of the dummy gate stack 224 .

[0029] refer to Figure 1 and Figure 7 , the method 100 includes a frame 110, in which a source / drain recess 228 is formed in the first fin element 210A and the second fin element 210B using the gate spacer 226 and the dummy gate stack 224 as an etching mask. In some embodiments, the source / drain region 10SD of the first fin element 210A and the source / drain region 20SD of the second fin element 210B in the first device region 10 are recessed to form the source / drain recess 228. The formation of the source / drain recess 228 may be formed using a dry etching process or a wet etching process. For example, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases, and / or plasma, and / or combinations thereof. Figure 7 In some embodiments shown in FIG. 1 , the upper portions of the first fin element 210A and the second fin element 210B are recessed to expose the sidewalls of the semiconductor layer 206 and the sacrificial layer 208. In some embodiments, at least a portion of the lower portions of the first fin element 210A and the second fin element 210B are also recessed. That is, the source / drain recess 228 can extend below the bottommost sacrificial layer 208 in the first device region 10 and the second device region 20. At the end of the operation in box 110, the source / drain regions 10SD and 20SD of the first fin element 210A and the second fin element 210B can become flush with or lower than the top surface of the STI feature 212.

[0030] refer to Figures 1 to 8 The method 100 includes block 112, in which an inner spacing recess 232 is selectively formed in the first fin element 210 in the first device region 10. Figure 8 In some embodiments shown in , the second device region 20 may be masked by a first mask layer 230 to facilitate selective formation of internal spacing grooves 232 in the first fin element 210A in the first device region 10. In some embodiments, the first mask layer 230 may include one or more photoresists or one or more dielectric layers. The first mask layer 230 may be deposited using spin coating, CVD, or a suitable deposition technique. As described above with respect to the stack 204, the composition of the semiconductor layer 206 is different from the composition of the sacrificial layer 208. At block 112, the different composition allows the sacrificial layer 208 in the first fin element 210A exposed in the source / drain groove 228 to be selectively and partially recessed to form the internal spacing groove 232 while substantially not etching the exposed semiconductor layer 206. In embodiments where the semiconductor layer 206 is substantially composed of Si and the sacrificial layer 208 is substantially composed of SiGe, the selective recessing of the sacrificial layer 208 may include a SiGe oxidation process followed by removal of the SiGe oxide. In those embodiments, the SiGe oxidation process may include the use of ozone. In some embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 208 is recessed is controlled by the duration of the etching process. In some embodiments, the selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Figure 8 As shown, the inner spacing recess 232 extends inwardly along the Y direction from the source / drain recess 228 in the first device region 10. In some embodiments, the selective wet etching process may include hydrogen fluoride (HF) or NH4OH etchant.

[0031] refer to Figure 1 , Fig. 9 and Fig.10 The method 100 includes a block 114 in which an inner spacer 236 is formed in the inner spacer groove 232. Fig.10). In some embodiments, the internal spacer layer 234 can be deposited on the workpiece 200 by CVD, PECVD, LPCVD, ALD, or other suitable methods. The internal spacer layer 234 can be formed of aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, silicon oxide, silicon carbonitride, silicon oxide, silicon carbide, low potassium materials, other suitable metal oxides, or combinations thereof. In some embodiments, the internal spacer layer 234 can be conformally deposited on the top surface of the gate top hard mask 218, the top surface and sidewalls of the gate spacer layer 226, the portion of the substrate 202 exposed in the source / drain recess 228, and the top surface of the STI feature 212. Subsequently, as Fig.10 As shown in FIG. 1 , the deposited inner spacer layer 234 may be etched back to form an inner spacer member 236 in the inner spacer groove 232 in the first device region 10 . In the etch-back process, the inner spacer layer 234 outside the inner spacer groove 232 is removed. Fig.10 In some embodiments shown in , the internal spacer member 236 is recessed so that a portion of the semiconductor layer 206 is suspended above the internal spacer member 236. In other words, the side of the internal spacer member 236 may not be flush with the sidewall of the semiconductor layer 206. The operations of frame 112 and frame 114 are performed while the second device region 20 remains protected and masked by the first mask layer 230. That is, the internal spacer recess 232 and the internal spacer member 236 are only formed in the first device region 10 and completely disappear from the second device region 20. After the internal spacer member 236 is formed, the first mask layer 230 can be removed from the second device region 20 using etching, ashing, or a suitable method.

[0032] refer to Figures 1 to 11 The method 100 includes block 116, where an epitaxial source / drain feature 238 is formed in the source / drain recess 228. Since the formation of the source / drain feature 238 is substantially the same throughout the workpiece 200, Fig.1120 . The formation of source / drain features 238 in the first device region 10 and the second device region 20 is shown together in FIG. Although not shown separately in the drawings of the present invention, the source / drain features 232 may include n-type source / drain features for n-type devices and p-type source / drain features for p-type devices. In some embodiments, n-type epitaxial source / drain features of n-type devices in the workpiece 200 may be formed together, and p-type epitaxial source / drain features of p-type devices in the workpiece 200 may be formed together in a previous or subsequent process. The source / drain features 238 may be formed using a suitable epitaxial process, such as CVD deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. Exemplary n-type epitaxial source / drain features may include Si, GaAs, GaAsP, SiP, or other suitable materials. The n-type epitaxial source / drain component can be in-situ doped during the epitaxial process by introducing a doping substance including an n-type dopant (such as phosphorus or arsenic) and / or other suitable dopants including combinations thereof. If the n-type epitaxial source / drain component is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the n-type epitaxial source / drain component. Exemplary p-type epitaxial source / drain components may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable materials. The p-type epitaxial source / drain component can be in-situ doped during the epitaxial process by introducing a doping substance including a p-type dopant (e.g., boron or BF2) and / or other suitable dopants (including combinations thereof). If the p-type epitaxial source / drain component is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the p-type epitaxial source / drain component.

[0033] refer to Figures 1 to 12, the method 100 includes a block 118, wherein a dielectric layer 242 is formed over the source / drain features 238. In some cases, the dielectric layer 242 may be referred to as an interlayer dielectric (ILD) layer 242. The ILD layer 242 may be substantially the same throughout the first device region 10 and the second device region 20 of the workpiece 200. In some embodiments, a contact etch stop layer (CESL) 240 is first deposited over the source / drain features 238. In some examples, the CESL 240 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 240 may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. Then, the ILD layer 242 is deposited over the CESL 240. In some embodiments, the ILD layer 242 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials). The ILD layer 242 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 242, the workpiece 200 may be annealed to improve the integrity of the ILD layer 242. Fig.12 As shown, after deposition and annealing of the ILD layer 242 , the workpiece 200 is planarized by, for example, a chemical mechanical polishing (CMP) process to form a level top surface for further processing.

[0034] refer to Figure 1 , Fig.13 and Fig.14, the method 100 includes a block 120, in which the dummy gate stack 224 is removed to form a first gate opening 244A in the first device region 10 and a second gate opening 244B in the second device region 20. Since the removal of the dummy gate stack 224 is substantially the same throughout the workpiece 200, the removal of the dummy gate stack 224 in the first device region 10 and the second device region 20 can be performed simultaneously. In the depicted embodiment, a planarization process can be performed to remove the gate top hard mask 218 so that the top surface of the dummy gate electrode layer 216 is exposed in both the first device region 10 and the second device region 20. Then, an etching process completely removes the dummy gate electrode layer 216 and the dummy dielectric layer 214 to expose the semiconductor layer 206 and the sacrificial layer 208 in the channel region 10C or the channel region 20C. At this point, the dummy gate stack 224 is substantially removed from the workpiece 200. The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. The etching process may be selected to be selective to the dummy gate stack 224 and not substantially etch the CESL 240 and the ILD layer 242. Fig.14 In some embodiments shown in , the dummy gate stack 224 and the dummy dielectric layer 214 are removed from the channel region 10C or the channel region 20C to expose the semiconductor layer 206 and the sacrificial layer 208 in the channel region 10C or the channel region 20C.

[0035] refer to Figure 1 and Fig.15, the method 100 includes a block 122, wherein the sacrificial layer 208 exposed in the first gate opening 244A is selectively removed so that the semiconductor layer 206 in the channel region 10C is selectively released in the first device region 10 to become a channel member. In some embodiments, the second device region 20 is masked by a second mask layer 246, which can be similar to the first mask layer 230. In the depicted embodiment, the etching process selectively etches the exposed sacrificial layer 208, with minimal or no etching of the semiconductor layer 206, and in some embodiments, minimal or no etching of the gate spacer layer 226 and the internal isolation feature 236. Various etching parameters can be adjusted to achieve selective etching of the sacrificial layer 208, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. For example, an etchant is selected for the etching process that etches the material of the sacrificial layer 208 (silicon germanium in the depicted embodiment) at a higher rate than the material of the semiconductor layer 206 (silicon in the depicted embodiment). The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, a dry etching process (such as an RIE process) utilizes a fluorine-containing gas (e.g., SF6) to selectively etch the sacrificial layer 208. In some embodiments, the ratio of the fluorine-containing gas to the oxygen-containing gas (e.g., O2 or O3), the etching temperature, and / or the RF power can be adjusted to selectively etch silicon germanium or silicon. In some embodiments, the wet etching process utilizes an etching solution including ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the sacrificial layer 208. In some embodiments, a chemical vapor etching process using hydrochloric acid (HCl) selectively etches the sacrificial layer 208. After the operation at block 122 is completed, the semiconductor layer 206 in the channel region 10C becomes suspended on the space 248 left by removing the sacrificial layer 208 in the first fin element 210A. The released semiconductor layer 206 in the channel region 10C can be referred to as a channel member 206'. The space 248 is in fluid communication with the first gate opening 244A. After releasing the channel member 206' in the first device region 10 at block 122, the second mask layer 246 can be removed from the second device region 20 using etching, ashing, or a suitable method.

[0036] refer to Figure 1 and Fig.16, the method 100 includes a frame 124, wherein a first gate element 250A is formed over a channel region 10C in a first device region 10, and a second gate element 250B is formed over a channel region 20C in a second device region 20. In some embodiments, the processes and components of the first gate structure 250A and the second gate structure 250B are substantially the same, and the formation of the first gate structure 250A and the second gate structure 250B can be performed simultaneously. In some alternative embodiments not specifically shown in the figures of the present invention, the first gate structure 250A and the second gate structure 250B can be formed separately by using a selective mask of a mask layer. Each of the first gate structure 250A and the second gate structure 250B can include an interface layer, a gate dielectric layer, one or more work function layers, and a metal filling layer. An example process is described below. An interface layer can be formed on the channel member 206' in the channel region 10C in the first device region 10 and in the channel region 10C of the second fin element 210B in the second device region 20 to provide adhesion of the gate dielectric layer formed subsequently. In some embodiments, the interfacial layer may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. Then, a gate dielectric layer is deposited over the channel member 206' in the channel region 10C in the first device region 10 and the channel region 10C of the second fin element 210B in the second device region 20. The gate dielectric layer may include one or more high-k dielectric materials. High-k dielectric materials as used and described herein include dielectric materials having a high dielectric constant, for example, a dielectric constant greater than that of thermally oxidized silicon (~3.9). Example high-k dielectric materials may include TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HftO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiN), other high-k dielectric materials, or combinations thereof. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0037] One or more work function layers may then be deposited on the gate dielectric layer. In some embodiments, different work function layers may be formed in the n-type device region and the p-type device region. In those embodiments, although the n-type device region and the p-type device region may share certain common work function layers, the n-type device region may include one or more work function layers that are not present in the p-type device region. Similarly, in alternative embodiments, the p-type device region may include one or more work function layers that are not present in the n-type device region. The p-type work function layer includes any suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function materials, or combinations thereof. The n-type work function layer includes any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function materials, or combinations thereof. Note that the p-type work function layer is not limited to use in the p-type device region, and the n-type work function layer is not limited to use in the n-type device region. P-type work function layers and n-type work function layers can be applied in the n-type device region and the p-type device region to achieve the desired threshold voltage. In some embodiments, the metal gate stack 244 may include one or more metal fill layers. For example, a CVD process or a PVD process deposits one or more metal fill layers on the n-type work function layer and the p-type work function layer so that the metal fill layer fills any remaining portion of the first gate opening 244A (including space 248) and the second gate opening 244B. The metal fill layer may include a suitable conductive material, such as Al, W and / or Cu. The metal fill layer may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof.

[0038] Still reference Fig.16 After the operation at block 124 is completed, a first transistor 260 is formed in the first device region 10 and a second transistor 270 is formed in the second device region 20. Fig.16As shown, the first gate structure 250A of the first transistor 260 is arranged above each channel member 206' in the channel region 10C in the first device region 10 and surrounds each channel member 206' in the channel region 10C in the first device region 10. That is, the first transistor 260 in the first device region 10 is a full-surround gate (GAA) transistor 260. The second gate structure 250B of the second transistor 270 is arranged above the channel region 20C of the second fin element 210B. Note that the sacrificial layer 208 in the channel region 20C of the second fin element 210B is not removed and the semiconductor layer 206 in the channel region 20C is not released to form the channel member. That is, the second transistor 270 in the second device region 20 is a FinFET 270, wherein the second gate structure 250B does not extend into the channel region 20C of the second fin element 210B. Due to the presence of the semiconductor layer 206 and the sacrificial layer 208 in the channel region 20C of the second fin element 210B, the FinFET 270 may be referred to as a layered or layered FinFET. Fig.16 As shown, source / drain features 238 in first transistor 260 in first device region 10 directly contact sidewalls of channel member 206' and internal isolation features 236. Source / drain features 238 in second transistor 270 in second device region 20 directly contact sidewalls of semiconductor layer 206 and sacrificial layer 208.

[0039] Fig.17 2 shows a cross-sectional view of a first transistor 260 and a second transistor 270 according to some alternative embodiments of the present invention. In some embodiments, Figure 3 The sidewalls of the first fin element 210A and the second fin element 210B shown in FIG. 2 may not be vertical. Alternatively, the sidewalls of the first fin element 210A and the second fin element 210B may be tapered such that each of them has a wider bottom and a narrower top. The tapered sidewalls of the first fin element 210A and the second fin element 210B may appear in the first transistor 260 and the second transistor 270. Fig.17 In the first transistor 260 shown in FIG. 1 , when viewed along the longitudinal direction (Y direction) of the channel member 206 ′, the topmost channel member 206 ′ has a first width W1, and the bottommost channel member 206 ′ has a second width W2 greater than the first width. Fig.17In the second transistor 270, when viewed along the longitudinal direction (Y direction) of the second fin element 210B, the second fin element 210 has a top surface with a third width W3 and a bottom surface with a fourth width W4. The fourth width W4 is greater than the third width W3. In some other embodiments, the first fin element 210A and the second fin element 210B may have different widths. For example, when the circuit design requires a wider channel component to improve the on-state current, the first fin element 210A may be wider than the second fin element 210B. Different fin element widths may also be used in Fig.17 For example, the first width W1 may be greater than the third width W3, and the second width W2 may be greater than the fourth width W4.

[0040] Since a GAA transistor (such as, Fig.16 or Fig.17 The first transistor 260 in the device region and the layered FinFET (such as, Fig.16 or Fig.17 In one aspect, the second transistor 270 includes a thicker channel region than the first transistor 260, making it suitable for high current applications. In some embodiments, the first device region 10 is a logic device region, and the second device region 20 is an input / output (I / O) device region, wherein the layer FinFET is used as an I / O transistor. In another aspect, when the sacrificial layer 208 is formed of silicon germanium (SiGe), the sacrificial layer 208 in the channel region 20C can be strained by the semiconductor layer 206 when the semiconductor layer 206 is formed of silicon (Si). The strained sacrificial layer 208 in the second transistor 270 can become a high hole mobility channel region suitable for a p-type transistor. In some embodiments where a six-transistor (6T) static random access memory (SRAM) cell is desired, the first transistor 260 can be used as an n-type pull-down (PD) transistor or an n-type pass-gate (PG) transistor, while the second transistor 270 formed using a method similar to method 100 can be used as a p-type pull-up (PU) transistor. In another aspect, the first transistor 260 and the second transistor 270 formed using the method of the present invention can be used as two types of transistors with different threshold voltages. The first transistor 260 whose channel member 206' is formed by the semiconductor layer 206 can have a first threshold voltage (VT1), and the second transistor 270 whose channel region includes both the semiconductor layer 206 and the sacrificial layer 208 can have a second threshold voltage (VT2) different from the first threshold voltage (VT1).

[0041] refer to Figure 1, the method 100 includes block 126, at which further processing is performed. Fabrication may continue to continue fabricating the semiconductor device 200. For example, various contacts may be formed to facilitate operation of the first transistor 260 and the second transistor 270 in the semiconductor device 200. For example, one or more ILD layers (similar to the ILD layer 242) and / or CESL layers (similar to the CESL 240) may be formed over the substrate 202 (specifically, over the ILD layer 242, the first gate structure 250A, and the second gate structure 250B). Contacts may then be formed in the ILD layer 242 and / or an ILD layer disposed over the ILD layer 242. For example, the contacts are electrically and / or physically coupled to the gate structures (including the first gate structure 250A and the second gate structure 250B), respectively, and the contacts are electrically and / or physically coupled to the source / drain features 238, respectively. The contact includes a conductive material, such as aluminum, an aluminum alloy (such as an aluminum / silicon / copper alloy), copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, a metal silicide, other suitable metals, or a combination thereof. In some embodiments, a metal silicide layer can be formed at the interface between the source / drain component 238 and the source / drain contact. The metal silicide can include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or a combination thereof. In some embodiments, an ILD layer disposed above the ILD layer 242 and the contact (e.g., extending through the ILD layer 242 and / or other ILD layers) is part of a multi-layer interconnect (MLI) structure.

[0042] In one exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes a first transistor in a first device region and a second transistor in a second device region. The first transistor includes a plurality of vertically stacked channel components and a first gate structure located above and around the plurality of vertically stacked channel components. The second transistor includes a fin-shaped channel component and a second gate structure above the fin-shaped channel component. The fin-shaped channel component includes a semiconductor layer interlaced by a sacrificial layer. The semiconductor layer includes a first semiconductor material, and the sacrificial layer includes a second semiconductor material or a dielectric material. The first semiconductor material is different from the second semiconductor material. The plurality of vertically stacked channel components include a first semiconductor material.

[0043] In some embodiments, the first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) or indium arsenide (InAs), and the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn). The dielectric material includes silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, the first transistor includes a plurality of internal spacer components arranged between a plurality of vertically stacked channel components, and the second gate structure does not extend into the fin-shaped channel component. In some cases, the first transistor also includes a first source / drain component, the second transistor also includes a second source / drain component, the first source / drain component contacts the plurality of internal spacer components, and the first source / drain component and the drain component contact the semiconductor layer and the sacrificial layer of the fin-shaped channel component. In some embodiments, the first device region is a logic device region, and the second device region is an input / output device region. In some embodiments, the first transistor includes a first threshold voltage and the second transistor includes a second threshold voltage different from the first threshold voltage. In some cases, the semiconductor device is a static random access memory (SRAM) cell. In some embodiments, the first transistor is used as a pull-down transistor or a pass-gate transistor, and the second transistor is used as a pass-gate transistor.

[0044] In another exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes a fin-shaped channel member in a first region and a first gate structure above the fin-shaped channel member. The fin-shaped channel member includes a plurality of semiconductor layers interlaced by a plurality of sacrificial layers, each of the plurality of semiconductor layers includes a first semiconductor material, and each of the plurality of sacrificial layers includes a second semiconductor material or a dielectric material. The first semiconductor material is different from the second semiconductor material. In some embodiments, the first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or indium arsenide (InAs), and the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn). The dielectric material may include silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the semiconductor device may further include: a plurality of vertically stacked channel members in a second region different from the first region; and a second gate structure above and around each of the plurality of vertically stacked channel members. The plurality of vertically stacked channel members include a first semiconductor material. In some embodiments, the semiconductor device further includes a plurality of internal spacing components arranged between the plurality of vertically stacked channel members. The first gate structure does not extend into the fin-shaped channel member. In some embodiments, the semiconductor device further includes a first source / drain component in contact with the plurality of semiconductor layers and the plurality of sacrificial layers in the fin-shaped channel member and a second source / drain component in contact with the plurality of vertically stacked channel members. The second source / drain component contacts the plurality of internal spacing components.

[0045] In yet another exemplary aspect, the present invention is directed to a method. The method includes: forming a stack on a substrate, the stack including a plurality of semiconductor layers interleaved by a plurality of sacrificial layers; forming a first fin element from the stack in a first region of the substrate, and forming a second fin element from the stack in a second region of the substrate; forming a first dummy gate stack over the second fin element, and forming a second dummy gate stack over the second fin element; depositing a gate spacer layer over the first dummy gate stack and the second dummy gate stack; forming a first source / drain recess in the first region, and forming a second source / drain recess in the second region, selectively and partially etching a plurality of sacrificial layers in the first region to form a plurality of spacer recesses; forming a plurality of internal spacer components in a plurality of internal spacer recesses in the first region; and forming a first source / drain component in the first source / drain recess, and forming a second source / drain component in the second source / drain recess.

[0046] In some embodiments, the plurality of semiconductor layers include silicon (Si), and the plurality of sacrificial layers include silicon germanium (SiGe). In some embodiments, the plurality of semiconductor layers include a first semiconductor material, the plurality of sacrificial layers include a second semiconductor material or a dielectric material, and the first semiconductor material is different from the second semiconductor material. In some cases, the first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) or indium arsenide (InAs), the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), and the dielectric material includes silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, the formation of the plurality of internal spacer components includes: blanket depositing an internal spacer layer over the first fin element, the first dummy gate stack, the second fin element, and the second dummy gate stack; and etching back the internal spacer layer to expose the gate spacer layer, while arranging the plurality of internal spacer components in the plurality of internal spacer grooves. In some embodiments, the method may further include: depositing a dielectric layer over the first region and the second region; planarizing the dielectric layer to expose the first dummy gate stack and the second dummy gate stack; removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench, respectively; selectively removing a plurality of sacrificial layers exposed in the first trench while the second trench is masked, thereby releasing a plurality of vertically stacked channel members; and simultaneously forming a first gate structure over and around the plurality of vertically stacked channel members and forming a second gate structure in the second trench. In some cases, simultaneously forming the first gate structure and the second gate structure includes: forming an interface layer; forming a gate dielectric layer over the interface layer; depositing a work function layer over the gate dielectric layer; and depositing a metal fill layer over the work function layer.

[0047] In some embodiments, a semiconductor device includes: a first transistor in a first device region, the first transistor including: a plurality of vertically stacked channel components, and a first gate structure located above and around the plurality of vertically stacked channel components; and a second transistor located in a second device region, the second transistor including: a fin-shaped channel component, and a second gate structure located above the fin-shaped channel component, wherein the fin-shaped channel component includes a semiconductor layer interleaved by a sacrificial layer, wherein the semiconductor layer includes a first semiconductor material and the sacrificial layer includes a second semiconductor material or a dielectric material, wherein the first semiconductor material is different from the second semiconductor material, and wherein the plurality of vertically stacked channel components include the first semiconductor material. In some embodiments, the first semiconductor material comprises silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or indium arsenide (InAs), wherein the second semiconductor material comprises silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), wherein the dielectric material comprises silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first transistor comprises a plurality of internal spacer components arranged between the plurality of vertically stacked channel components, wherein the second gate structure does not extend into the fin-shaped channel component. In some embodiments, the first transistor further comprises a first source / drain component, wherein the second transistor further comprises a second source / drain component, wherein the first source / drain component contacts the plurality of internal spacer components, wherein the first source / drain component contacts the semiconductor layer and the sacrificial layer of the fin-shaped channel component. In some embodiments, the first device region is a logic device region, and the second device region is an input / output device region. In some embodiments, the first transistor includes a first threshold voltage, wherein the second transistor includes a second threshold voltage different from the first threshold voltage. In some embodiments, the semiconductor device is a static random access memory (SRAM) cell. In some embodiments, the first transistor is used as a pull-down transistor or a pass-gate transistor, wherein the second transistor is used as a pull-up transistor.

[0048] In some embodiments, a semiconductor device includes: a fin-shaped channel component located in a first region; and a first gate structure located above the fin-shaped channel component, wherein the fin-shaped channel component includes a plurality of semiconductor layers interleaved by a plurality of sacrificial layers, wherein each of the plurality of semiconductor layers includes a first semiconductor material, and each of the plurality of sacrificial layers includes a second semiconductor material or a dielectric material, wherein the first semiconductor material is different from the second semiconductor material. In some embodiments, the first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or indium arsenide (InAs), wherein the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), wherein the dielectric material includes silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the present invention further includes: a plurality of vertically stacked channel members in a second region different from the first region; and a second gate structure above and around each of the plurality of vertically stacked channel members, wherein the plurality of vertically stacked channel members include the first semiconductor material. In some embodiments, the present invention further includes: a plurality of internal spacing components arranged between the plurality of vertically stacked channel members, wherein the first gate structure does not extend into the fin-shaped channel member. In some embodiments, the present invention further includes: a first source / drain component in contact with the plurality of semiconductor layers and the plurality of sacrificial layers in the fin-shaped channel member; and a second source / drain component in contact with the plurality of vertically stacked channel members, wherein the second source / drain component is in contact with the plurality of internal spacing components.

[0049] In some embodiments, a method includes: forming a stack of semiconductor layers interleaved with multiple sacrificial layers on a substrate; forming a first fin element from the stack in a first region of the substrate, and forming a second fin element from the stack in a second region of the substrate; forming a first dummy gate stack over the first fin element, and forming a second dummy gate stack over the second fin element; depositing a gate spacer layer over the first dummy gate stack and the second dummy gate stack; forming a first source / drain recess in the first region, and forming a second source / drain recess in the second region; selectively and partially etching the multiple sacrificial layers in the first region to form multiple inner spacer recesses; forming multiple inner spacer features in the multiple inner spacer recesses in the first region; and forming a first source / drain feature in the first source / drain recess, and forming a second source / drain feature in the second source / drain recess. In some embodiments, the multiple semiconductor layers include silicon (Si), wherein the multiple sacrificial layers include silicon germanium (SiGe). In some embodiments, the multiple semiconductor layers include a first semiconductor material, wherein the multiple sacrificial layers include a second semiconductor material or a dielectric material. Wherein, the first semiconductor material is different from the second semiconductor material. In some embodiments, the first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) or indium arsenide (InAs), wherein the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), wherein the dielectric material includes silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, the forming of the plurality of internal spacer components includes: blanket depositing an internal spacer layer over the first fin element, the first dummy gate stack, the second fin element and the second dummy gate stack; and etching back the internal spacer layer to expose the gate spacer layer, while arranging the plurality of internal spacer components in the plurality of internal spacer grooves. In some embodiments, it also includes: depositing a dielectric layer over the first region and the second region; planarizing the dielectric layer to expose the first dummy gate stack and the second dummy gate stack; removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench, respectively; selectively removing the multiple sacrificial layers exposed in the first trench while the second trench is masked, thereby releasing a plurality of vertically stacked channel components; and simultaneously forming a first gate structure over and around the plurality of vertically stacked channel components, and forming a second gate structure in the second trench.In some embodiments, the first gate structure and the second gate structure are simultaneously formed including: forming an interface layer; forming a gate dielectric layer above the interface layer; depositing a work function layer above the gate dielectric layer; and depositing a metal filling layer above the work function layer.

[0050] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art can better understand aspects of the present invention. It will be appreciated by those skilled in the art that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, include: A first transistor in a first device region, the first transistor comprising: a plurality of vertically stacked channel members, vertically stacked in a first direction, and a first gate structure disposed over and around the plurality of vertically stacked channel members; and A second transistor is located in the second device region, wherein the second transistor comprises: a fin-shaped channel member, and a second gate structure located above the fin-shaped channel member, wherein the fin-shaped channel member comprises semiconductor layers interleaved by sacrificial layers, wherein the semiconductor layer comprises a first semiconductor material, and the sacrificial layer comprises a second semiconductor material or a dielectric material, wherein the first semiconductor material is different from the second semiconductor material, wherein the plurality of vertically stacked channel members include the first semiconductor material, wherein the first transistor comprises a plurality of internal spacing features arranged between the plurality of vertically stacked channel members, and wherein the internal spacing features are recessed from respective ones of the plurality of vertically stacked channel members such that a portion of the respective channel member is suspended above an exterior of the internal spacing features, Wherein, in a second direction perpendicular to the first direction, a width of the inner spacing component at a position close to the corresponding channel member is smaller than a width at a center position of the inner spacing component.

2. The semiconductor device according to claim 1, in, The first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) or indium arsenide (InAs), Wherein, the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), Wherein, the dielectric material includes silicon oxide, silicon nitride or silicon oxynitride.

3. The semiconductor device according to claim 1, in, The second gate structure does not extend into the fin-shaped channel member.

4. The semiconductor device according to claim 3, in, The first transistor further includes a first source / drain component, Wherein, the second transistor further comprises a second source / drain component, wherein the first source / drain feature is in contact with the plurality of inner spacer features, Wherein, the first source / drain feature is in contact with the semiconductor layer and the sacrificial layer of the fin-shaped channel component.

5. The semiconductor device according to claim 1, in, The first device region is a logic device region, and the second device region is an input / output device region.

6. The semiconductor device according to claim 1, in, the first transistor comprising a first threshold voltage, The second transistor includes a second threshold voltage different from the first threshold voltage.

7. The semiconductor device according to claim 1, the semiconductor device being a static random access memory (SRAM) cell.

8. The semiconductor device according to claim 7, in, The first transistor functions as a pull-down transistor or a pass-gate transistor, The second transistor is used as a pull-up transistor.

9. A semiconductor device, include: a fin-shaped channel member located in the first region; as well as a first gate structure located above the fin-shaped channel member, wherein the fin-shaped channel member comprises a plurality of semiconductor layers interleaved by a plurality of sacrificial layers, wherein each of the plurality of semiconductor layers comprises a first semiconductor material, and each of the plurality of sacrificial layers comprises a second semiconductor material or a dielectric material, wherein the first semiconductor material is different from the second semiconductor material, Wherein, the semiconductor device further includes: a plurality of vertically stacked channel members located in a second region different from the first region; and a plurality of internal spacing members disposed between the plurality of vertically stacked channel members, wherein the plurality of vertically stacked channel members are vertically stacked in a first direction, the internal spacing members being recessed from respective ones of the plurality of vertically stacked channel members such that a portion of the respective channel members is suspended above an exterior of the internal spacing members, Wherein, in a second direction perpendicular to the first direction, a width of the inner spacing component at a position close to the corresponding channel member is smaller than a width at a center position of the inner spacing component.

10. The semiconductor device according to claim 9, in, The first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) or indium arsenide (InAs), Wherein, the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), Wherein, the dielectric material includes silicon oxide, silicon nitride or silicon oxynitride.

11. The semiconductor device according to claim 9, further comprising: include: a second gate structure over and around each channel member of the plurality of vertically stacked channel members, Wherein, the plurality of vertically stacked channel members include the first semiconductor material.

12. The semiconductor device according to claim 11, in, The first gate structure does not extend into the fin-shaped channel member.

13. The semiconductor device according to claim 12, further comprising a first source / drain feature contacting the plurality of semiconductor layers and the plurality of sacrificial layers in the fin-shaped channel member; and a second source / drain feature in contact with the plurality of vertically stacked channel members, in, The second source / drain feature is in contact with the plurality of inner spacer features.

14. A method of forming a semiconductor device, include: forming a stack composed of a plurality of semiconductor layers interlaced with a plurality of sacrificial layers on a substrate, wherein the stack is vertically stacked in a first direction; forming a first fin element from the stack in a first region of the substrate, and forming a second fin element from the stack in a second region of the substrate; forming a first dummy gate stack over the first fin element, and forming a second dummy gate stack over the second fin element; depositing a gate spacer layer over the first dummy gate stack and the second dummy gate stack; forming a first source / drain recess in the first region and forming a second source / drain recess in the second region; selectively and partially etching the plurality of sacrificial layers in the first region to form a plurality of inner spaced grooves; forming a plurality of inner spacing members in the plurality of inner spacing grooves in the first region, wherein the inner spacing members are recessed from channel portions of corresponding semiconductor layers of the plurality of semiconductor layers such that a portion of the channel portions of the corresponding semiconductor layers is suspended over an exterior of the inner spacing members; and forming a first source / drain feature in the first source / drain recess and forming a second source / drain feature in the second source / drain recess, Wherein, in a second direction perpendicular to the first direction, a width of the inner spacing component at a position close to the corresponding semiconductor layer is smaller than a width at a center position of the inner spacing component.

15. The method according to claim 14, in, The plurality of semiconductor layers include silicon (Si), Wherein, the plurality of sacrificial layers include silicon germanium (SiGe).

16. The method according to claim 14, wherein: in, The plurality of semiconductor layers include a first semiconductor material, Wherein, the plurality of sacrificial layers include a second semiconductor material or a dielectric material, The first semiconductor material is different from the second semiconductor material.

17. The method according to claim 16, in, The first semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) or indium arsenide (InAs), Wherein, the second semiconductor material includes silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), Wherein, the dielectric material includes silicon oxide, silicon nitride or silicon oxynitride.

18. The method according to claim 14, in, The forming of a plurality of internal spacer components comprises: blanket depositing an inner spacer layer over the first fin element, the first dummy gate stack, the second fin element, and the second dummy gate stack; and The inner spacer layer is etched back to expose the gate spacer layer while the plurality of inner spacer members are arranged in the plurality of inner spacer grooves.

19. The method according to claim 14, further comprising: include: depositing a dielectric layer over the first region and the second region; planarizing the dielectric layer to expose the first dummy gate stack and the second dummy gate stack; removing the first dummy gate stack and the second dummy gate stack to form a first trench and a second trench, respectively; selectively removing the plurality of sacrificial layers exposed in the first trench while the second trench is masked, thereby releasing a plurality of vertically stacked channel members; as well as A first gate structure is simultaneously formed over and around the plurality of vertically stacked channel members, and a second gate structure is formed in the second trench.

20. The method according to claim 19, in, The first gate structure and the second gate structure are formed simultaneously including: forming an interface layer; forming a gate dielectric layer over the interface layer; depositing a work function layer over the gate dielectric layer; and A metal filling layer is deposited over the work function layer.

Images