A photodetector array and a method for preparing the same

Abstract

The present disclosure provides a photodetector array that can be used in the field of high-quality and high-resolution imaging, including: a plurality of photodetector units, each photodetector unit including a transistor and a photodetector connected in series with the transistor, the transistors in each row of photodetector units share a gate and a drain, and the transistors in each column of photodetector units share a source; wherein the photodetector is used to detect light signals; the transistor is used to control the enabling state of the photodetector connected thereto, so that each photodetector unit is an independent photodetector unit. The present disclosure also provides a method for preparing a photodetector array.

Description

Technical Field

[0001] The present disclosure relates to the field of photoelectric detection technology, and in particular to a photoelectric detector array and a preparation method thereof. Background Art

[0002] Solar-blind photodetectors working in the solar-blind ultraviolet band (wavelength range of 200-280nm) have outstanding advantages such as avoiding solar radiation and low background interference, and have broad application prospects in the fields of warning, guidance, environmental monitoring and confidential communication. With the continuous innovation of semiconductor technology, a variety of wide-bandgap inorganic semiconductor materials such as Al x Ga 1-x N, Zn x Mg 1-x O.Ga 2 O 3 and diamond have been developed for the preparation of solar-blind photodetectors. The bandgap width of gallium oxide is as high as 4.8-5.1eV, which directly corresponds to the solar-blind band, and it has important application value in the field of solar-blind photodetectors. Gallium oxide-based devices have demonstrated excellent performance in solar-blind detection, providing a reliable foundation for solar-blind imaging technology based on gallium oxide materials. Among the gallium oxide-based detections of different structures, MSM-structured photodetectors have received special attention due to their simple preparation, easy integration with readout circuits, and the potential to achieve high gain and high quantum efficiency. The sensing unit composed of a highly responsive photodetector is an important component of the imaging system. At the same time, the array integration technology of the photodetector unit is the key to its practical application in the imaging system.

[0003] Although there is information about Ga 2 O 3 Photodetector arrays have been reported, but due to the Ga 2 O 3The limitations of photodetectors (crosstalk) mean that the devices cannot be actually applied to imaging systems. Conventional array integration design is to connect electrodes S (source electrode) and D (drain electrode) in series in a way that each row of detection units in the cross array of the detector shares the same word line and each column of detectors shares the same bit line. Although this array design can achieve high integration, it inevitably has the problem of crosstalk, that is, when the external circuit reads data from the array unit, the state of the units around the unit being tested has a great influence on the data reading, especially when the unit being tested is in a dark state and the surrounding units are illuminated, the test error will be the largest, and the read data will even be equivalent to the data when it is illuminated. The more leakage current paths there are, the more serious the misreading will be. Therefore, this design cannot be applied to the actual imaging field. The crosstalk problem is one of the major challenges faced by detectors at the circuit and architecture levels. Designing and preparing a new type of crosstalk-resistant gallium oxide array so that each detection unit has rectification and selection characteristics to eliminate the misreading caused by crosstalk is crucial for high-quality solar blind imaging. Summary of the invention

[0004] In order to solve the above-mentioned problems in the prior art, the present disclosure provides a photodetector array and a preparation method thereof, and designs a detector cross array by connecting crystal triodes in series with detectors, thereby realizing high integration of the detectors; by introducing crystal triodes, the detectors can be selected when reading data, avoiding the crosstalk problem of the detector array, and improving the accuracy of data reading of the detection unit, so that the design of this highly integrated anti-crosstalk array can be applied to high-quality day-blind imaging.

[0005] A first aspect of the present disclosure provides a photodetector array, comprising: a plurality of photodetector units, each photodetector unit comprising a transistor and a photodetector connected in series with the transistor, the transistors in each row of photodetector units sharing a gate and a drain, and the transistors in each column of photodetector units sharing a source; wherein the photodetector is used to detect light signals; and the transistor is used to control the enable state of the photodetector connected thereto, so that each photodetector unit is an independent photodetector unit.

[0006] Furthermore, each photodetector includes a gallium oxide layer and a pair of interdigital electrodes located on the gallium oxide layer, wherein the first interdigital electrode and the second interdigital electrode of each photodetector are respectively connected to the corresponding transistor and the drain of the transistor.

[0007] Furthermore, each photodetector unit is distributed in parallel and at equal intervals.

[0008] Furthermore, the gate and the drain are arranged in parallel, the source is arranged vertically to the gate and the drain, and the vertical contact is isolated by an electrode insulating layer.

[0009] Furthermore, the gallium oxide layer has a square structure, a circular structure, or a polygonal structure.

[0010] The second aspect of the present disclosure provides a method for preparing a photodetector array, comprising: S1, growing a detector material layer on a substrate, and etching to form a detector material layer array; S2, laterally depositing a gate and a drain between the detector material layer arrays; S3, growing an oxide layer on the wafer obtained in S2, and etching the oxide layer to form a transistor dielectric layer; S4, growing an indium gallium zinc oxide layer on the transistor dielectric layer and patterning to form a transistor channel layer; S5, growing an electrode insulating layer on one side of the transistor channel layer and on the gate and the drain; S6, vertically depositing a source between the gallium oxide layer arrays and on the electrode insulating layer, and growing interdigitated electrodes and electrode wires connecting the detector array and the transistor dielectric layer on the detector array.

[0011] Furthermore, the method further includes: S7, growing a passivation layer on the wafer obtained in S6; S8, growing a light shielding layer on the passivation layer corresponding to the transistor channel layer.

[0012] Furthermore, in S1, a gallium oxide layer is grown on the substrate by using a radio frequency magnetron sputtering method, a metal organic chemical vapor deposition method, a molecular beam epitaxy method, or an atomic layer deposition method.

[0013] Furthermore, in S1, the gallium oxide layer is etched by dry etching or wet etching to obtain a patterned gallium oxide layer array.

[0014] Furthermore, in S5, an electrode insulating layer is grown on one side of the channel layer of the transistor and on the gate by using an atomic layer deposition method, and the electrode insulating layer is etched by using a reactive ion beam etching method to pattern it.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects:

[0016] (1) The detectors prepared by the design scheme disclosed in the present invention can achieve high integration while avoiding the crosstalk problem, so that the highly integrated detector array has high resolution and can be used for high-quality and high-resolution imaging.

[0017] (2) By introducing transistors as switching devices of the detection unit, the detector to be read can be accurately selected, avoiding crosstalk problems and realizing accurate reading of device data. When reading data from a certain detection unit, the transistor connected in series with it is in the turned-on state to read the detector data, while the transistors of other detection units (different gate lines) remain in the turned-off state, thereby avoiding crosstalk problems and realizing accurate reading of detector array data.

[0018] (3) Isolate the devices (patterning of gallium oxide) to reduce the errors caused by wires and adjacent devices when reading data.

[0019] (4) The simultaneous production of transistors and detectors greatly reduces the complexity of the process. The present invention does not separate the production of detectors and transistors, but optimizes the process to produce them simultaneously, thus avoiding repeated processes and greatly reducing the complexity of the process.

[0020] (5) The device is passivated to ensure its stability. After the transistor and detector are manufactured, the surface defects of the device are passivated through passivation technology. In particular, the surface defects of gallium oxide increase after multiple etching treatments. Effective passivation treatment reduces the surface defects of gallium oxide and improves the stability of the device.

[0021] (6) The crystal triode is shielded from light to avoid long-term ultraviolet light exposure, which will weaken the gate control performance of the crystal triode. The IGZO material is sensitive to solar-blind ultraviolet light, and light will change the carrier concentration of the channel. The shielding treatment avoids the influence of ultraviolet light on the crystal triode. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] For a more complete understanding of the present disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 Schematically shows a top view of a photodetector array according to an embodiment of the present disclosure;

[0024] Figure 2 Schematically shows a left view of a photodetector array according to an embodiment of the present disclosure;

[0025] Figure 3 A flow chart schematically shows a method for preparing a photodetector array according to an embodiment of the present disclosure;

[0026] Figures 4A to 4J The schematic diagrams of the wafer structures corresponding to the method for preparing the photodetector array according to an embodiment of the present disclosure are schematically shown respectively. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0029] Figure 1 and 2 The top view and left view of a photodetector array according to an embodiment of the present disclosure are schematically shown.

[0030] like Figure 1 and 2 As shown, the photodetector array of the embodiment of the present disclosure includes:

[0031] Multiple photodetector units, each photodetector unit includes a transistor 101 and a photodetector 102 connected in series with the transistor 101, the transistors 101 in each row of photodetector units share a gate 3 and a drain 4, and the transistors 101 in each column of photodetector units share a source 9.

[0032] Each photodetector 102 is used to detect light signals, and each transistor 101 is used to control the enabling state of the photodetector 102 connected thereto, so that each photodetector unit is an independent photodetector unit.

[0033] In the embodiments of the present disclosure, Figure 1 and 2 As shown, each photodetector 102 includes a gallium oxide layer 2 and an interdigitated electrode pair 10 located on the gallium oxide layer 2, and the interdigitated electrode pair 10 includes a first interdigitated electrode and a second interdigitated electrode; wherein the first interdigitated electrode and the second interdigitated electrode of each photodetector 102 are respectively connected to the corresponding transistor 101 and the drain 4 of the transistor 101 through the electrode wire 8, and the other end of the transistor 101 is connected to the source 9 through the electrode wire 8.

[0034] Among them, Figure 2As shown, a passivation layer 11 and a light shielding layer 12 are also provided above each photodetector unit, wherein the light shielding layer 12 is provided on the corresponding passivation layer 11 above each transistor 101, and is used to shield light and prevent the influence of external light sources on the transistor 101. In the embodiment of the present disclosure, the preparation method and components of the photodetector array are described in detail in another embodiment of the preparation method of the present disclosure, and will not be repeated here.

[0035] like Figure 1 As shown, the transistor 101 and the photodetector 102 in each photodetector unit are parallel to the transistors and photodetectors in other photodetector units and are arranged at equal intervals, wherein the gate 3 and the drain 4 are also arranged parallel to each other, the source 9 and the gate 3 and the drain 4 are all arranged vertically, and the vertical contact is isolated by the electrode insulating layer 7 to avoid short circuit between the source 9, the gate 3 and the drain 4. Figure 1 The gallium oxide layer 2 in each photodetector shown is a square structure. In some other embodiments, it can also be a circular structure or a polygonal structure, etc. The embodiments of the present disclosure do not limit the material layer structure of the photodetector.

[0036] A photodetector array provided by an embodiment of the present disclosure can accurately select the photodetector to be read by introducing a transistor as a switching device of the photodetector unit, thereby avoiding the crosstalk problem and realizing accurate reading of the photodetector data. When reading data from a certain detection unit, the transistor connected in series with it is in the on state to read the detector data, while the transistors of other detection units (different gate lines) remain in the off state, thereby avoiding the crosstalk problem and realizing accurate reading of the detector array data. The array device has highly integrated and high-resolution characteristics and can be used for high-quality and high-resolution imaging.

[0037] Figure 3 A flow chart of a method for preparing a photodetector array according to an embodiment of the present disclosure is schematically shown.

[0038] like Figure 3 As shown, the preparation method of the photodetector array includes:

[0039] S1, growing a detector material layer 2 on a substrate 1, and etching to form a detector material layer array.

[0040] In the embodiments of the present disclosure, the substrate 1 may be a sapphire substrate or a silicon substrate or a quartz substrate with different crystal planes, and the detector material layer 2 may be a gallium oxide layer.

[0041] like Figure 4A4A(a) and 4A(b) are respectively the left view and the top view of the wafer obtained after the detector material layer 2 is grown. It should be noted that the following appendix Figure 4B to Figure 4J The figure (a) is a left view of the wafer obtained after the corresponding steps, and the figure (b) is a top view of the wafer obtained after the corresponding steps. The following steps will not be described. 2 O 3 ) as an example, specifically, the gallium oxide layer 2 is grown on the sapphire substrate 1 by adopting radio frequency magnetron sputtering, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or atomic layer deposition (ALD), and the thickness of the grown gallium oxide layer 2 is preferably 5 to 500 nm.

[0042] In the embodiment of the present disclosure, the gallium oxide layer 2 includes gallium oxide with different crystal orientations and doped gallium oxide materials, and the doping concentration is 1×10 16 1×10 20 cm- 3 , doping elements include but are not limited to silicon or germanium or tin or aluminum or nitrogen or magnesium, etc., to form a single crystal or polycrystalline or amorphous gallium oxide material layer. It should be noted that in addition to the gallium oxide layer, the detector material layer can also be optoelectronic materials of any wavelength band and other wide bandgap semiconductor materials, such as GaN, AlN, ZnO, etc.

[0043] like Figure 4B As shown, the gallium oxide layer 2 is etched by dry etching or wet etching, such as by plasma etching process (BCl 3 The gallium oxide layer is etched by using an etching device including an ICP and a RIE. The etching gas includes but is not limited to BCl 3 and Ar to obtain a patterned gallium oxide layer array. Figure 4B It can be seen that each gallium oxide layer unit in the gallium oxide layer array is distributed in parallel and at equal intervals, and the shape is a square structure. In some other embodiments, the shape includes but is not limited to a circular structure or a polygonal structure, etc. The present disclosure does not limit the shape of each gallium oxide layer unit in the gallium oxide layer array.

[0044] Specifically, when BCl 3 When the gas is used for etching, its concentration is preferably 1-50 sccm, and the etching rate is 90-95 nm / min; when Ar gas is used for etching, its concentration is preferably 1-20 sccm, and the etching rate is 90-95 nm / min.

[0045] S2, depositing a gate 3 and a drain 4 laterally between the detector material layer arrays.

[0046] In the embodiments of the present disclosure, Figure 4C As shown, a gate 3 and a drain 4 are deposited between the gallium oxide layer arrays. Figure 4C It can be seen that the gate 3 and the drain 4 are respectively located at the upper and lower sides of each row of gallium oxide layer units in the gallium oxide layer array, and are both in the shape of long strips and are distributed parallel to each other.

[0047] Specifically, standard photolithography and electron beam evaporation are used to deposit metal titanium / gold, with the thickness of the titanium / gold layer being 20nm / 80nm respectively, and the thickness of the gate 3 and the drain 4 layer being within 500nm. It should be noted that other metals can also be deposited to obtain electrode layers, such as Ti, Ni, Al, Cu, Au, Ag, Pt, Cr, Pb, etc.

[0048] S3, growing an oxide layer 5 on the wafer obtained in S2, and etching the oxide layer to form a transistor dielectric layer.

[0049] In the embodiments of the present disclosure, Figure 4D As shown, an oxide layer 5 is grown on the wafer obtained in S2 by plasma enhanced chemical vapor deposition (PECVD). The oxide layer 5 includes but is not limited to silicon dioxide, aluminum oxide, etc. The thickness of the oxide layer is preferably 10 to 500 nm.

[0050] In the embodiments of the present disclosure, Figure 4E As shown, the oxide layer 5 is patterned by etching with a reactive ion beam, that is, the oxide layer 5 is formed only on the gate 3 as a transistor dielectric layer. 2 O or mixed gas 5% SiH 4 / N 2 Etching is performed, where N 2 The O gas flow rate range is preferably 100-2000 sccm, and the mixed gas is 5% SiH 4 / N 2 The gas flow rate range is preferably 10 to 1000 sccm.

[0051] S4, growing an indium gallium zinc oxide layer 6 on the transistor dielectric layer and patterning it to form a transistor channel layer.

[0052] In the embodiments of the present disclosure, Figure 4F As shown, a standard photolithography process is adopted to grow an indium gallium zinc oxide layer 6 (IGZO) on the transistor dielectric layer by radio frequency magnetron sputtering, and a metal lift-off process is used to pattern it to form a transistor channel layer. The thickness of the indium gallium zinc oxide layer 6 is preferably 10 to 500 nm.

[0053] It should be noted that the transistor dielectric layer can not only be of IGZO back-gate type, but also of top-gate type, and its constituent material can also be realized by other transistor materials, such as ZnO, GaN, etc.

[0054] S5 , growing an electrode insulating layer 7 on one side of the transistor channel layer and on the gate 3 and the drain 4 .

[0055] In the embodiments of the present disclosure, Figure 4G As shown, in order to prevent the short circuit between the array gate 3, the drain 4 and the source 9, the electrode insulating layer Al is deposited by ALD. 2 O 3 , and reactive ion beam etching of Al 2 O 3 The electrode insulating layer is preferably 1 to 1000 nm thick and includes but is not limited to Al 2 O 3 、SiO 2 、SI 3 N 4 etc.

[0056] S6, depositing source electrodes 9 vertically between the detector material layer arrays and on the electrode insulating layer 7, and growing interdigitated electrodes 10 and electrode wires 8 connecting the detector material layer arrays and the transistor dielectric layer on the detector material layer arrays.

[0057] In the embodiments of the present disclosure, Figure 4H As shown, standard photolithography and electron beam evaporation are used to grow metal titanium / gold, with layer thicknesses of 20nm / 80nm respectively, and the layer thickness range of the source electrode 9, the interdigital electrode 10 and the electrode wire 8 is preferably within 500nm. Figure 4H It can be seen that the source electrode 9 is grown longitudinally on the left and right sides of the detector material layer array and on the electrode insulating layer 7 by electron beam evaporation coating, and the forked electrode 10 and the electrode wire 8 of the detector material layer array and the transistor dielectric layer are grown on the detector material layer array, so that the detector material layer array and the crystal triode are connected in series one by one, wherein one forked electrode of the forked electrode 10 is connected to the drain 4 of the crystal triode through the electrode wire 8, the other forked electrode of the forked electrode 10 is connected to the crystal triode through the electrode wire 8, and the other end of the crystal triode is also connected to the source electrode 9 through the electrode wire 8.

[0058] In the embodiment of the present disclosure, the photodetector array structure is completely prepared. In order to further optimize the device structure and prevent the external environment and external light source from affecting the photodetector array, as shown in FIG. Figure 3 As shown, the method also includes: S7-S8.

[0059] S7, growing a passivation layer 11 on the wafer obtained in S6.

[0060] In the embodiments of the present disclosure, Fig. 4IAs shown, an ALD method is used to grow a passivation layer 11 on the wafer obtained in S6. The passivation layer 11 includes but is not limited to silicon oxide, hafnium oxide, aluminum oxide, aluminum nitride, silicon nitride, etc., and the layer thickness is preferably 5 to 500 nm.

[0061] S8 , growing a light shielding layer 12 on the passivation layer 11 corresponding to the transistor channel layer 6 .

[0062] In the embodiments of the present disclosure, Figure 4J As shown, in order to prevent ultraviolet light from irradiating the crystal triode and avoid failing to realize the good on and off function of the crystal triode, a standard photolithography process and electron beam evaporation are used to deposit a shading layer 12 on the passivation layer 11 corresponding to the transistor channel layer 6. The shading layer 12 is composed of metal titanium / gold, and the thickness of the metal titanium / gold is 20nm / 80nm respectively, and the layer thickness range is within 500nm. The deposited metals include but are not limited to Ti, Ni, Al, Cu, Au, Ag, Pt, Cr, Pb, etc. The setting of the shading layer 12 can ensure high stability of the device during operation.

[0063] Depend on Figures 4A-4J As shown, the transistor includes: a gate 3, a drain 4, a source 9, an oxide layer 5 and a transistor channel layer 6, and the photodetector includes: a gallium oxide layer 2 and interdigital electrodes 10. Figure 4J As shown, each transistor and its corresponding photodetector are connected in series, one end of each row of photodetectors in the array is connected in series with the drain 4, and the other end of the photodetector is connected in series with the transistor, and then each column of transistors is connected in series through the source 9, and the connections between them are all connected through the electrode wire 8. This integration method avoids the error of the external circuit in the detector reading, ensures the accurate reading of each photodetector unit, and solves the crosstalk problem.

[0064] It should be noted that the process methods and materials used in the above steps in the embodiments of the present disclosure are only exemplary descriptions, and do not mean that the above semiconductor layer is grown only by the above method. For example, other thin film growth methods such as MOCVD, MBE, PLD, etc. may also be used to obtain high-quality gallium oxide epitaxial thin films; other metals such as nickel, gold, etc. may also be used as electrode and electrode wire materials; other insulating materials such as SiO 2 It can also be used as an electrode isolation line oxide layer, etc.; other types of transistors can also be used for gallium oxide detector integration to avoid crosstalk problems; other substrates such as silicon-based substrates and quartz substrates can also be used as experimental substrates; other detection materials can also be used for detection in other bands, etc.

[0065] The embodiments of the present disclosure disclose a photodetector array and a preparation method thereof, which can achieve high integration while avoiding crosstalk problems, so that the highly integrated detector array has high resolution and can be used for high-quality and high-resolution imaging; by introducing a transistor as a switching device of a detection unit, the detector to be read can be accurately selected, avoiding crosstalk problems and realizing accurate reading of device data; when reading data from a certain detection unit, the transistor connected in series with it is in an open state to read the detector data, while the transistors of other detection units (different gate lines) remain in a closed state, thereby avoiding crosstalk problems and realizing accurate reading of detector array data; the device is isolated (patterning of gallium oxide) to reduce the error caused by the wires and adjacent devices when reading data; the transistor The transistor and the detector are manufactured at the same time, which greatly reduces the complexity of the process. The present invention does not separate the manufacturing of the detector and the crystal triode, but optimizes the process and manufactures them at the same time, thus avoiding repeated processes and greatly reducing the complexity of the process. The device is passivated to ensure the stability of the device. After the crystal triode and the detector are manufactured, the surface defects of the device are passivated by passivation technology, especially the surface defects of gallium oxide increase after multiple etching treatments. Effective passivation treatment reduces the surface defects of gallium oxide and improves the stability of the device. The crystal triode is shielded to avoid the weakening of the gate control performance of the crystal triode when it is exposed to ultraviolet light for a long time. The IGZO material is sensitive to day-blind ultraviolet light, and the light will change the carrier concentration of the channel. The shading treatment avoids the influence of ultraviolet light on the crystal triode.

[0066] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive.

[0067] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of scopes, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of scopes without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0068] Although the present disclosure has been shown and described with reference to specific exemplary embodiments of the present disclosure, it should be understood by those skilled in the art that various changes in form and details may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims, but also by the equivalents of the appended claims.

Claims

1. A method for preparing a photodetector array, characterized in that: include: S1, growing a detector material layer on a substrate, and etching to form a detector material layer array; S2, depositing a gate and a drain laterally between the detector material layer arrays; S3, growing an oxide layer on the wafer obtained in S2, and etching the oxide layer to form a transistor dielectric layer; S4, growing an indium gallium zinc oxide layer on the transistor dielectric layer and patterning it to form a transistor channel layer; S5, growing an electrode insulating layer on one side of the transistor channel layer and on the gate and drain; S6, vertically depositing a source electrode between the detector material layer arrays and on the electrode insulating layer, and growing interdigitated electrodes and electrode wires connecting the detector material layer arrays and the transistor dielectric layer on the detector material layer arrays.

2. The method for preparing a photodetector array according to claim 1, characterized in that: The method further includes: S7, growing a passivation layer on the wafer obtained in S6; S8, growing a light shielding layer on the passivation layer corresponding to the transistor channel layer.

3. The method for preparing a photodetector array according to claim 1, characterized in that: In S1, a gallium oxide layer is grown on the substrate by radio frequency magnetron sputtering, metal organic chemical vapor deposition, molecular beam epitaxy or atomic layer deposition.

4. The method for preparing a photodetector array according to claim 3, characterized in that: In S1, the gallium oxide layer is etched by dry etching or wet etching to obtain a patterned gallium oxide layer array.

5. The method for preparing a photodetector array according to claim 1, characterized in that: In S5, an atomic layer deposition method is used to grow an electrode insulating layer on one side of the transistor channel layer and on the gate, and a reactive ion beam etching method is used to etch the electrode insulating layer to pattern it.

6. A photodetector array prepared by the method for preparing a photodetector array according to any one of claims 1 to 5, characterized in that: include: A plurality of photodetector units, each of which comprises a transistor and a photodetector connected in series with the transistor, the transistors in each row of the photodetector units share a gate and a drain, and the transistors in each column of the photodetector units share a source; wherein, The photodetector is used to detect light signals; the transistor is used to control the enabling state of the photodetector connected thereto, so that each photodetector unit is an independent photodetector unit.

7. The photodetector array according to claim 6, characterized in that: Each photodetector includes a gallium oxide layer and a pair of interdigital electrodes on the gallium oxide layer, wherein the first interdigital electrode and the second interdigital electrode of each photodetector are respectively connected to the corresponding transistor and the drain of the transistor.

8. The photodetector array according to claim 6, characterized in that: Each photodetector unit is distributed in parallel and at equal intervals.

9. The photodetector array according to claim 6, characterized in that: The gate electrode is parallel to the drain electrode, the source electrode is perpendicular to the gate electrode and the drain electrode, and the vertical contact points are isolated by an electrode insulating layer.

10. The photodetector array according to claim 7, characterized in that: The gallium oxide layer has a square structure, a circular structure or a polygonal structure.

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