Methods for forming semiconductor structures and methods for forming bonded semiconductor wafers

Abstract

A method for forming a semiconductor structure and a method for forming a bonded semiconductor wafer includes edge trimming of a front periphery region of a first wafer by performing a first pre-bonding edge trimming process. A second wafer is provided to be bonded to the first wafer. Optionally, the front periphery region of the second wafer can be edge trimmed by performing a second pre-bonding edge trimming process. The front surface of the first wafer is bonded to the front surface of the second wafer to form a bonding assembly. The back side of the first wafer is thinned by performing at least one wafer thinning process. The front periphery regions of the first and second wafers can be edge trimmed by performing a post-bonding edge trimming process. The bonding assembly can then be diced into bonded semiconductor wafers.

Description

Technical Field

[0001] This disclosure relates to methods for forming semiconductor structures and methods for forming bonded semiconductor wafers. Background Technology

[0002] Wafer thinning is used in conjunction with wafer bonding to provide a vertically stacked semiconductor wafer comprising at least two semiconductor wafers. A first wafer including a first semiconductor element can be bonded to a second wafer including a second semiconductor element. One of the two bonded wafers can be thinned after bonding. The bonded and thinned semiconductor wafer can then be diced to form multiple semiconductor wafers, which can have higher density, more functions, and / or faster operating speeds provided by the vertical bonding of at least two semiconductor wafers. The wafer edge regions excluding the bonding portions of the semiconductor wafers can be edge-trimmed during the wafer thinning process to prevent the bonded wafer assembly from peeling off. Existing methods for edge trimming typically use multiple edge trimming processes after grinding the back side of one of the two wafers in the bonding assembly. Multiple edge trimming processes use sequentially decreasing edge offsets to minimize wafer kerf. This wafer edge trimming method can result in more sources of film peeling and has additional problems such as short trimming lifetime, long edge trimming process duration, high processing costs, and high requirements for the capabilities of edge trimming tools. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes edge trimming of the front periphery region of a first wafer by performing a pre-bonding edge trimming process; bonding the front surface of the first wafer to the front surface of a second wafer; thinning the back side of the first wafer by performing at least one wafer thinning process; and edge trimming of the front periphery regions of the first wafer and the second wafer by performing a post-bonding edge trimming process.

[0004] According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes edge trimming of a front periphery region of a first wafer by performing a first pre-bonding edge trimming process; edge trimming of a front periphery region of a second wafer by performing a second pre-bonding edge trimming process; forming a bonding assembly by bonding the front surface of the first wafer to the front surface of the second wafer; removing an untrimmed portion of the first wafer by thinning the back side of the first wafer in the bonding assembly using at least one thinning process, wherein the back side surface of the first wafer is adjacent to a cylindrical sidewall formed during the first pre-bonding edge trimming process; and edge trimming of the bonding assembly by performing a post-bonding edge trimming process that trims the front periphery regions of the first and second wafers.

[0005] According to one embodiment of the present disclosure, a method of forming a bonded semiconductor wafer includes providing a first wafer comprising a first two-dimensional array of first semiconductor wafers; providing a second wafer comprising a second two-dimensional array of second semiconductor wafers having the same two-dimensional periodicity as the first two-dimensional array of the first semiconductor wafers; edge-trimming a front periphery region of the first wafer by performing a pre-bonding edge trimming process; forming a bonding assembly by bonding the front surface of the first wafer to the front surface of the second wafer, wherein each of the first semiconductor wafers is bonded to a corresponding one of the second semiconductor wafers; thinning the back side of the first wafer by performing at least one wafer thinning process; edge-trimming the front periphery regions of the first wafer and the second wafer by performing a post-bonding edge trimming process; and dicing the bonding assembly into a plurality of bonded semiconductor wafers, wherein each of the bonded semiconductor wafers comprises a bonding pair of two: a corresponding one of the first semiconductor wafers and a corresponding one of the second semiconductor wafers. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A This is a vertical cross-sectional view of the first wafer according to the first embodiment of this disclosure;

[0008] Figure 1B yes Figure 1A A top view of the first wafer;

[0009] Figure 1C yes Figure 1A Enlarged vertical cross-sectional view of region C;

[0010] Figure 2A This is a vertical cross-sectional view of the first wafer after the first edge trimming process according to the first embodiment of this disclosure;

[0011] Figure 2B yes Figure 2A A top view of the first wafer;

[0012] Figure 3A This is a vertical cross-sectional view of the second wafer according to the first embodiment of this disclosure;

[0013] Figure 3B yes Figure 3A A top view of the first wafer;

[0014] Figure 4AThis is a vertical cross-sectional view of a first exemplary structure after bonding a first wafer to a second wafer, according to a first embodiment of the present disclosure;

[0015] Figure 4B yes Figure 4A A top view of the first exemplary structure;

[0016] Figure 5A This is a vertical cross-sectional view of a first exemplary structure after a first thinning process on the back side of a first wafer, according to the first embodiment of this disclosure.

[0017] Figure 5B yes Figure 5A A top view of the first exemplary structure;

[0018] Figure 6A This is a vertical cross-sectional view of the first exemplary structure according to the first embodiment of the present disclosure after a second thinning process of thinning the first wafer;

[0019] Figure 6B yes Figure 6A A top view of the first exemplary structure;

[0020] Figure 7A This is a vertical cross-sectional view of a first exemplary structure after performing an end-edge trimming process according to a first embodiment of the present disclosure;

[0021] Figure 7B yes Figure 7A A top view of the first exemplary structure;

[0022] Figure 7C yes Figure 7A and Figure 7B An enlarged vertical cross-sectional view of the area surrounding the first exemplary structure;

[0023] Figure 8 This is an enlarged vertical cross-sectional view of a first exemplary structure after forming a through-hole cavity through the substrate, according to a first embodiment of the present disclosure;

[0024] Figure 9 This is an enlarged vertical cross-sectional view of a first exemplary structure after forming a through-hole structure through the substrate and a back-side bonding pad, according to the first embodiment of this disclosure.

[0025] Figure 10A This is a vertical cross-sectional view of a first exemplary structure in the wafer dicing process according to a first embodiment of the present disclosure;

[0026] Figure 10B yes Figure 10A A top view of the first exemplary structure;

[0027] Figure 11A This is a vertical cross-sectional view of the second wafer after the second edge trimming process according to the second embodiment of this disclosure;

[0028] Figure 11B yes Figure 11A A top view of the first wafer;

[0029] Figure 12A This is a vertical cross-sectional view of a second exemplary structure after the first wafer is bonded to the second wafer, according to a second embodiment of the present disclosure;

[0030] Figure 12B yes Figure 12A A top view of the second exemplary structure;

[0031] Figure 13A This is a vertical cross-sectional view of a second exemplary structure following a first thinning process on the back side of a first wafer, according to a second embodiment of this disclosure.

[0032] Figure 13B yes Figure 13A A top view of the second exemplary structure;

[0033] Figure 14A This is a vertical cross-sectional view of the second exemplary structure according to the second embodiment of the present disclosure after the second thinning process of thinning the first wafer;

[0034] Figure 14B yes Figure 14A A top view of the second exemplary structure;

[0035] Figure 15A This is a vertical cross-sectional view of a second exemplary structure after performing an end-edge trimming process according to a second embodiment of the present disclosure;

[0036] Figure 15B yes Figure 15A A top view of the second exemplary structure;

[0037] Figure 16 This is a first flowchart illustrating the steps for forming an exemplary structure according to an embodiment of the present disclosure;

[0038] Figure 17 This is a second flowchart illustrating the steps for forming an exemplary structure according to an embodiment of the present disclosure;

[0039] Figure 18 This is a third flowchart illustrating the steps for forming an exemplary structure according to an embodiment of the present disclosure.

[0040] [Symbol Explanation]

[0041] 12: Shallow trench isolation structure

[0042] 14: Active Zone

[0043] 15: Semiconductor Channel

[0044] 18: Metal-Semiconductor Alloy Region

[0045] 20: Grid structure

[0046] 22: Gate dielectric

[0047] 24: Gate electrode

[0048] 26: Dielectric grid spacer

[0049] 28: Dielectric gate capping layer

[0050] 30: Interconnection layer dielectric layer

[0051] 31A: Planarized dielectric layer

[0052] 31B: First interconnect layer dielectric layer

[0053] 32: Second interconnect layer dielectric layer

[0054] 33: Third interconnect layer dielectric layer

[0055] 34: Fourth interconnect layer dielectric layer

[0056] 35: Fifth interconnect layer dielectric layer

[0057] 36: Sixth interconnect layer dielectric layer

[0058] 37: Bonding pad level dielectric layer

[0059] 41L: First metal wire

[0060] 41V: Contact through-hole structure

[0061] 42L: Second metal wire

[0062] 43L: Third metal wire

[0063] 43V: Second metal through-hole structure

[0064] 44L: Fourth Metal Wire

[0065] 44V: Third metal through-hole structure

[0066] 45L: Fifth Metal Wire

[0067] 46V: Fifth Metal Through-Hole Structure

[0068] 47B: Metal bonding pad

[0069] 47V: Terminal metal through-hole structure

[0070] 100: First Wafer

[0071] 108: First Semiconductor Substrate

[0072] 130: Encapsulation dielectric layer

[0073] 139: Through-hole cavity through the substrate

[0074] 160: Joining pad

[0075] 200: Second wafer

[0076] 208: Second semiconductor substrate

[0077] 300: Semiconductor wafers

[0078] 330: Semiconductor components

[0079] 1610: Steps

[0080] 1620: Steps

[0081] 1630: Steps

[0082] 1640: Steps

[0083] 1710: Steps

[0084] 1720: Steps

[0085] 1730: Steps

[0086] 1740: Steps

[0087] 1750: Steps

[0088] 1810: Steps

[0089] 1820: Steps

[0090] 1830: Steps

[0091] 1840: Steps

[0092] 1850: Steps

[0093] 1860: Steps

[0094] 1870: Steps Detailed Implementation

[0095] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference elements and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0096] Furthermore, spatially relative terms such as “below,” “under,” “lower than,” “above,” and “above” may be used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the figures. The spatially relative terms are intended to cover different orientations of the device in use or operation, other than those illustrated in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0097] This disclosure relates generally to semiconductor devices, and more specifically to methods for edge trimming of wafers in wafer bonding and dicing processes.

[0098] Generally, the method disclosed herein minimizes the volume of the edge-trimmed portion of the semiconductor substrate during wafer bonding processes. The front periphery of the first semiconductor substrate can be edge-trimmed during a pre-bonding edge-trimming process, without edge-trimming the back periphery of the first semiconductor substrate. Compared to prior art methods where the entire periphery of the semiconductor substrate is edge-trimmed after bonding to another substrate and before thinning the semiconductor substrate, the depth of edge trimming into the first semiconductor substrate can be significantly smaller, such as less than 50 micrometers. Thus, the volume of the periphery of the first semiconductor substrate removable during the pre-bonding edge-trimming process disclosed herein can be significantly reduced. For example, in a typical prior art edge-trimming process performed on a pair of 450 mm diameter bonded wafers with an edge-trimming width of approximately 3 mm, for one of the two bonded wafers, it can have... The volume removed. In contrast, according to the illustrative example of the embodiments disclosed herein, the pre-bonded edge trimming process on a 450 mm diameter wafer with 30 micrometer deep edge trimming and 3 mm wide edge trimming only removes the volume. Thus, the method disclosed herein can reduce the amount of trimmed material on the wafer. This reduction in the amount of trimmed material shortens the processing time and reduces processing costs of the wafer edge trimming process used in the bonding process, and increases the lifespan of the edge trimming tool.

[0099] Furthermore, in various embodiments, the periphery of the material layer located on the wafer bonding side can be effectively removed before bonding a pair of wafers. In one embodiment, the second semiconductor substrate to be bonded to the first semiconductor substrate can optionally be edge-trimmed before bonding with the first semiconductor substrate. Material portions located around the semiconductor wafer and having weak adhesion to the semiconductor substrate can be removed before bonding during a pre-bonding edge trimming process. Therefore, the pre-bonding edge trimming process can reduce material peeling or detachment during or after the wafer bonding process. Various features and configurations of the disclosed method will now be described in detail with reference to the accompanying drawings.

[0100] See Figures 1A to 1C The illustration depicts a first wafer 100 according to an embodiment of the present disclosure. The first wafer 100 includes a first semiconductor substrate 108, which may include commercially available semiconductor substrates, such as monocrystalline silicon substrates with diameters of 200 mm, 300 mm, or 450 mm and thicknesses ranging from 600 micrometers to 1 mm, but smaller or larger thicknesses may also be used. The first semiconductor substrate 108 may have a flat front surface and a flat back surface parallel to each other. The edges of the first semiconductor substrate 108 may have rounded edges. In other words, a convex surface changing direction by 180 degrees in a vertical cross-sectional view may extend around the entire circumference of the first semiconductor substrate 108. The convex surface may connect the flat front surface and the flat back surface of the first semiconductor substrate 108 such that the first semiconductor substrate 108 has no sharp edges. In one embodiment, the first semiconductor substrate 108 may include a corresponding commercially available monocrystalline silicon substrate having the same diameter.

[0101] The first wafer 100 can be provided by forming semiconductor elements on a first semiconductor substrate 108 and by forming a first interconnect hierarchy (L0-L6) and a first bonding pad hierarchy LP. The semiconductor elements formed on the first semiconductor substrate 108 are referred to herein as first semiconductor elements. The first interconnect hierarchy (L0-L6) can be formed on the first semiconductor substrate 108 and incorporated into the first wafer 100. This disclosure describes an embodiment having the first interconnect hierarchy (L0-L6). However, those skilled in the art will understand that more or fewer interconnect hierarchy structures are possible within the scope of this disclosure. The first interconnect hierarchy (L0-L6) and the first bonding pad hierarchy LP can be laterally offset from the outermost periphery of the first wafer 100 by a lateral offset distance, which can range from 0.2 mm to 1 mm, but smaller and larger distances are also possible. The lateral offset between the first interconnect hierarchy (L0-L6) and the outermost periphery of the first wafer 100 is referred to as the edge removal distance.

[0102] The first interconnect hierarchy (L0-L6) includes dielectric material layers, referred to herein as first interconnect level dielectric layers. Metal interconnect structures are formed within the first interconnect level dielectric layers, referred to herein as first metal interconnect structures. Therefore, the first wafer 100 includes first metal interconnect structures formed within the first interconnect level dielectric layers. The first bonding pad hierarchy LP includes a bonding pad hierarchy dielectric layer and bonding pads formed within the first bonding pad hierarchy dielectric layer. The first bonding pad hierarchy LP may be formed on top of the first wafer interconnect hierarchy (L0-L6).

[0103] Figure 1C The illustration shows a semiconductor element 330 and an interconnect layer structure (L0-L6) that can be formed on a first semiconductor substrate 108. In an illustrative example, the first semiconductor substrate 108 may include a monolithic semiconductor substrate, such as a silicon substrate, wherein a semiconductor material layer extends continuously from the top surface of the first semiconductor substrate 108 to the bottom surface of the first semiconductor substrate 108, or includes a semiconductor material layer as a semiconductor-on-insulator layer covering a buried insulating layer (such as a silicon oxide layer) and a semiconductor top layer that carries the semiconductor substrate.

[0104] Semiconductor elements 330, such as field-effect transistors, may be formed on and / or in the first semiconductor substrate 108. For example, a shallow trench isolation structure 12 may be formed on the upper part of the first semiconductor substrate 108 by forming shallow trenches and subsequently filling the shallow trenches with a dielectric material such as silicon oxide. Various doped wells (not explicitly shown) may be formed in various regions on the upper part of the first semiconductor substrate 108 by performing a masking ion implantation process.

[0105] Gate structures 20 can be formed on the top surface of a first semiconductor substrate 108 by depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate capping dielectric layer. Each gate structure 20 may include a vertical stack of a gate dielectric 22, a gate electrode 24, and a dielectric gate capping layer 28, referred to herein as a gate stack (22, 24, 28). Ion implantation processes can be performed to form extended implantation regions, which may include source extension regions and drain extension regions. Dielectric gate spacers 26 may be formed around the gate stacks (22, 24, 28). Each component of the gate stacks (22, 24, 28) and the dielectric gate spacers 26 constitutes a gate structure 20. The gate structure 20 can be used as a self-aligned implantation mask to perform additional ion implantation processes to form deep active regions, which may include deep source regions and deep drain regions. The upper portion of the deep active region may partially overlap with the extended implantation region. Each combination of the extended injection region and the deep active region constitutes an active region 14, which may be a source region or a drain region with respect to electrical bias. A semiconductor channel 15 may be formed beneath each gate stack (22, 24, 28) between a pair of adjacent active regions 14. A metal-semiconductor alloy region 18 may be formed on the top surface of each active region 14. A field-effect transistor may be formed on the first semiconductor substrate 108. Each field-effect transistor may include a gate structure 20, a semiconductor channel 15, a pair of active regions 14 (one serving as a source region and the other as a drain region), and an optional metal-semiconductor alloy region 18. Complementary metal-oxide-semiconductor (CMOS) circuitry may be provided on the first semiconductor substrate 108, which may include surrounding circuitry for an array of resistive memory elements to be subsequently formed. Although this disclosure provides only a complementary metal-oxide-semiconductor (CMOS) element as the first semiconductor element, it should be understood that any other semiconductor element (such as a memory element, a radio frequency element, an image sensing element, a passive element, etc.) may be added to or replace the CMOS element in the first wafer 100.

[0106] Various interconnect hierarchy structures can then be formed. In an illustrative example, the interconnect hierarchy structures (L0-L6) may include a contact hierarchy structure L0, a first interconnect hierarchy structure L1, a second interconnect hierarchy structure L2, a third interconnect hierarchy structure L3, a fourth interconnect hierarchy structure L4, a fifth interconnect hierarchy structure L5, and a sixth interconnect hierarchy structure L6. The contact hierarchy structure L0 may include a planarized dielectric layer 31A and various contact via structures 41V. The planarized dielectric layer 31A includes a planarizable dielectric material such as silicon oxide, while the contact via structures 41V contact a corresponding one of the active region 14 or the gate electrode 24 and are formed within the planarized dielectric layer 31A. The first interconnect hierarchy structure L1 may include a first interconnect hierarchy dielectric layer 31B and a first metal line 41L formed within the first interconnect hierarchy dielectric layer 31B. The first interconnect hierarchy dielectric layer 31B is also referred to as a first line hierarchy dielectric layer. The first metal line 41L may contact a corresponding one of the contact via structures 41V. The second interconnect layer structure L2 may include a second interconnect layer dielectric layer 32. The second interconnect layer dielectric layer 32 may include a first via layer dielectric material layer and a second line layer dielectric material layer, or a stack of line and via layer dielectric material layers. Second interconnect layer metal interconnect structures (42V, 42L) are formed in the second interconnect layer dielectric layer 32. These structures may include a first metal via structure 42V and a second metal line 42L. The top surface of the second metal line 42L may be coplanar with the top surface of the second interconnect layer dielectric layer 32.

[0107] The third interconnect layer metal interconnect structure (43V, 43L) may include a second metal via structure 43V and a third metal line 43L formed within the third interconnect layer dielectric layer 33. Subsequent additional interconnect layer structures (L4, L5, L6) may be formed. For example, the additional interconnect layer structures (L4, L5, L6) may include a fourth interconnect layer structure L4, a fifth interconnect layer structure L5, and a sixth interconnect layer structure L6. The fourth interconnect layer structure L4 may include a fourth interconnect layer dielectric layer 34 in which fourth interconnect layer metal interconnect structures (44V, 44L) are formed, these fourth interconnect layer metal interconnect structures may include a third metal via structure 44V and a fourth metal line 44L. The fifth interconnect layer structure L5 may include a fifth interconnect layer dielectric layer 35 in which fifth interconnect layer metal interconnect structures (45V, 45L) are formed, these fifth interconnect layer metal interconnect structures may include a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnect layer structure L6 may include a sixth interconnect layer dielectric layer 36 in which sixth interconnect layer metal interconnect structures (46V, 46L) are formed, and these sixth interconnect layer metal interconnect structures may include a fifth metal via structure 46V and a sixth metal line 46L.

[0108] A bonding pad level structure LP can be formed on top of the interconnect level structure (L0-L6), which is referred to in this disclosure as the second bonding pad level structure. The bonding pad level structure LP may include a bonding pad level dielectric layer 37, in which terminal metal via structures 47V and metal bonding pads 47B are formed. The metal bonding pads 47B can be configured for metal-to-metal bonding (such as copper-copper bonding).

[0109] Each interconnect-level dielectric layer may be referred to as an interconnect-level dielectric (ILD) layer 30. Each interconnect-level metal interconnect structure may be referred to as a metal interconnect structure 40. Each combination of a metal via structure and an upper metal line located within the same interconnect-level structure (L1-L6) can be sequentially formed into two different structures using two single damascene processes, or simultaneously formed into a single structure using a dual damascene process. Each of the metal interconnect structures 40 may include its own metal liner (such as a TiN, TaN, or WN layer with a thickness ranging from 2 nm to 20 nm) and its own metal filler material (such as tungsten, copper, cobalt, molybdenum, ruthenium, other elemental metals or alloys, or combinations thereof). Various etch-stop dielectric layers and dielectric capping layers may be inserted between vertically adjacent pairs of interconnect-level dielectric layers 30, or may be incorporated into one or more interconnect-level dielectric layers 30.

[0110] Although this disclosure is described using an embodiment forming a set of seven interconnect hierarchy structures (L0-L6), this disclosure explicitly contemplates embodiments using different numbers of interconnect hierarchy structures in the first wafer 100. For example, the number of interconnect hierarchy structures (L0-L6) within the first wafer 100 may range from 1 to 20, such as from 2 to 10, but fewer and more interconnect hierarchy structures may also be used. Typically, the first wafer 100 may include a first two-dimensional array of first semiconductor wafers. The first semiconductor wafers may be arranged in a periodic two-dimensional array and may be laterally spaced from each other by diced channels.

[0111] See Figure 2A and Figure 2BA first pre-bonded edge trimming process can be performed to trim the front periphery region of the first wafer 100. An edge trimming process typically refers to a process that removes an edge portion of a substrate along its entire circumference. The first pre-bonded edge trimming process removes an annular periphery of the first wafer 100, located within a first edge trimming width tw1 from the outermost edge of the first wafer 100 and within a first edge trimming depth td1 from a horizontal plane including the top surface of the first wafer 100. A commercially available wafer edge trimming tool can be used to perform the first pre-bonded edge trimming process. The first pre-bonded edge trimming process forms an annular horizontal edge trimming surface within a horizontal plane located at a first edge trimming depth td1 from the front surface of the first wafer 100. Furthermore, the first pre-bonded edge trimming process forms a first cylindrical sidewall on the first wafer 100 at a position laterally offset from the outermost edge of the first wafer 100 to a position reaching the first edge trimming width tw1. In one embodiment, the first edge trimming width tw1 may range from 0.1 mm to 5.0 mm, but smaller and larger first edge trimming widths may also be used. The first edge trimming width tw1 may be greater than the edge removal distance and less than the end edge trimming width of the post-bonding edge trimming process to be used. In one embodiment, the first edge trimming depth td1 may range from 10 micrometers to 50 micrometers, but smaller and larger first edge trimming depths may also be used. The first edge trimming depth td1 is greater than the thickness to which the first wafer 100 is thinned during the post-bonding thinning process and less than 50% of the thickness of the first wafer 100, such as less than 15%.

[0112] See Figure 3A and Figure 3B These figures illustrate a second wafer 200 with a second lateral offset according to an embodiment of the present disclosure. The second wafer 200 includes a second semiconductor substrate 208, which may include commercially available semiconductor substrates, such as monocrystalline silicon substrates with diameters of 200 mm, 300 mm, or 450 mm and thicknesses ranging from 600 micrometers to 1 mm, but smaller or larger thicknesses may also be used. The second semiconductor substrate 208 has a flat front surface and a flat back surface parallel to each other. The edges of the second semiconductor substrate 208 may be rounded. In one embodiment, the second semiconductor substrate 208 may include a corresponding commercially available monocrystalline silicon substrate having the same diameter.

[0113] The second wafer 200 can be provided by forming semiconductor elements on the second semiconductor substrate 208 and by forming a second interconnect layer structure (L0-L6) and a second bonding pad layer structure LP. The semiconductor elements formed on the second semiconductor substrate 208 are referred to herein as second semiconductor elements. The second interconnect layer structure (L0-L6) can be formed on the second semiconductor substrate 208 and bonded to the second wafer 200. The second interconnect layer structure (L0-L6) and the second bonding pad layer structure LP can be laterally offset from the outermost periphery of the second wafer 200 by a lateral offset distance, which can be in the range of 0.2 mm to 1 mm, but smaller and larger lateral offset distances can also be used. The lateral offset between the second interconnect layer structure (L0-L6) and the outermost periphery of the second wafer 200 is an edge removal distance.

[0114] The second interconnect hierarchy (L0-L6) includes dielectric material layers, referred to herein as second interconnect level dielectric layers. Metal interconnect structures are formed within the second interconnect level dielectric layers, referred to herein as second metal interconnect structures. Therefore, the second wafer 200 includes second metal interconnect structures formed within the second interconnect level dielectric layers. The second bonding pad hierarchy LP includes a bonding pad hierarchy dielectric layer and bonding pads formed within the second bonding pad hierarchy dielectric layer. The second bonding pad hierarchy LP may be formed on top of the second wafer interconnect hierarchy (L0-L6).

[0115] The second wafer 200 may include complementary metal-oxide-semiconductor (CMOS) devices and / or any other semiconductor devices (such as memory devices, radio frequency devices, image sensing devices, passive devices, etc.) as second semiconductor devices. Although this disclosure is described using an embodiment in which a set of seven interconnect layers (L0-L6) is formed in the second wafer 200, embodiments using different numbers of interconnect layers are explicitly contemplated in this disclosure. In one embodiment, the second wafer 200 includes a second two-dimensional array of second semiconductor wafers having the same two-dimensional periodicity as the first two-dimensional array of first semiconductor wafers in the first wafer 100.

[0116] See Figure 4A and Figure 4BThe first wafer 100 and the second wafer 200 can be bonded to each other by bonding the front surface of the first wafer 100 to the front surface of the second wafer 200. For example, a second bonding pad formed in a second bonding pad level dielectric layer of the second wafer 200 can be bonded to a first bonding pad formed in a first bonding pad level dielectric layer of the first wafer 100. Metal-to-metal bonding (such as copper-copper bonding) can be used. For example, the components of the first wafer 100 and the second wafer 200 can be annealed at a high temperature in the range of 250 degrees Celsius to 450 degrees Celsius to induce metal-to-metal bonding between the first bonding pad and the second bonding pad. In one embodiment, the first bonding pad level dielectric layer and the second bonding pad level dielectric layer may include silicon oxide, and the assembly of the first wafer 100 and the second wafer 200 may be annealed at a high temperature in the range of 150 degrees Celsius to 350 degrees Celsius, while the first metal bonding pad contacts the second metal bonding pad and the first bonding pad level dielectric layer contacts the second bonding pad level dielectric layer, thereby inducing oxide-to-oxide bonding between the first bonding pad level dielectric layer and the second bonding pad level dielectric layer before metal-to-metal bonding.

[0117] See Figure 5A and Figure 5B The back side of the first wafer 100 can be thinned by performing at least one wafer thinning process. For example, a first wafer thinning process can be performed to thin the first wafer 100 to a first thickness t1 greater than the first edge trimming depth td1. In one embodiment, the first wafer thinning process may include and / or may consist of a wafer grinding process that grinds the back side of the first wafer 100. In one embodiment, the first thickness t1 may be in the range of 10 micrometers to 60 micrometers, such as from 15 micrometers to 50 micrometers, but smaller and larger thicknesses may also be used. Choosing a first thickness t1 greater than the first edge trimming depth td1 provides the advantage of avoiding grinding portions of the first wafer 100 including the annular horizontal surface, which is vertically offset from the bonding interface by the first edge trimming depth td1 (i.e., the annular horizontal surface formed by the first pre-bonding edge trimming process). Therefore, chipping and frizzing near the annular flat surface formed during the first pre-bonding edge trimming process can be avoided at the edge portions of the first wafer 100.

[0118] See Figure 6A and Figure 6BA second thinning process can be performed to further thin the first wafer 100. The second wafer thinning process uses a thinning process that is less likely to cause wafer frizz than a grinding process to thin the first wafer 100 to a second thickness t2 less than the first edge trimming depth td1. For example, the second wafer thinning process can use an isotropic etching process to etch the material on the back side of the remaining portion of the first wafer 100, and / or can use a chemical mechanical polishing (CMP) process. In one embodiment, the second wafer thinning process may include an isotropic etching process using an "HNA" etchant, which comprises a mixture of hydrofluoric acid, nitric acid, and acetic acid. In an illustrative example, the HNA etchant may comprise a 1:3:8 volume ratio mixture of hydrofluoric acid, nitric acid, and acetic acid, which, depending on the temperature of the etchant and the doping of the monocrystalline silicon, can provide an etching rate of 1 micrometer / minute to 3 micrometers / minute for the monocrystalline silicon. In one embodiment, the second thickness t2 can be in the range of 2 micrometers to 10 micrometers, but smaller and larger thicknesses can also be used.

[0119] Typically, at least one wafer thinning process can be performed to remove the untrimmed portion of the first wafer 100, i.e., the portion of the first wafer 100 that was not laterally trimmed during the first pre-bonding edge trimming process. Specifically, the untrimmed portion of the first wafer 100 may be a portion of the first wafer 100 vertically spaced from a horizontal plane, which includes the bonding interface between the first wafer 100 and the second wafer 200, with the vertical spacing being greater than the first edge trimming depth td1. Therefore, at least one wafer thinning process forms the back side of the first semiconductor substrate 108 within the horizontal plane, which may be vertically offset from the bonding interface between the first wafer 100 and the second wafer 200 by a vertical spacing less than the first edge trimming depth td1. In other words, the second thickness t2 is less than the first trimming depth td1. Thus, the annular horizontal surface of the first wafer 100 formed during the first pre-bonding edge trimming process can be removed during the second thinning process without causing the portion of the first wafer 100 adjacent to the annular horizontal surface to break or curl. Since a first pre-bonding edge trimming process can be performed on the first wafer 100 prior to bonding, the sidewalls of the first wafer 100 can be laterally offset inward from the sidewalls of the second wafer 200, which abut the horizontal plane of the bonding interface between the first wafer 100 and the second wafer 200.

[0120] See Figures 7A to 7CThis process can perform an end-edge trimming process, also known as a post-bonding edge trimming process. The post-bonding edge trimming process trims the edges of the front periphery of the first wafer 100 and the second wafer 200. A portion of the first wafer 100 and the second wafer 200 located within an end-edge trimming width twt from the outermost edge of the bonding assembly of the first wafer 100 and the second wafer 200 (the outermost edge of the second wafer 200) and within an end-edge trimming depth tdt from a horizontal plane including the back surface of the first wafer 100 can be removed during the post-bonding edge trimming process.

[0121] The post-bonding edge trimming process forms a cylindrical end sidewall at a location on the front peripheral region of the first wafer 100 and the second wafer 200, which is laterally offset from the outermost periphery of the second wafer 200 by an end edge trimming width twt. The end trimming width twt is greater than the first trimming width tw1. For example, the end edge trimming width twt can be in the range of 1.0 mm to 10.0 mm, but smaller and larger widths can also be used. Furthermore, the post-bonding edge trimming process can form an annular horizontal surface on the second wafer 200. The annular horizontal surface can be formed within a horizontal plane, which can be vertically separated from the horizontal plane including the bonding interface between the first wafer 100 and the second wafer 200 by a vertical spacing, in the range of 5 micrometers to 100 micrometers, but smaller and larger vertical spacings can also be used. In other words, the end edge trimming depth tdt can be the sum of a second thickness t2 and an additional depth ranging from 10 micrometers to 50 micrometers, but smaller and larger depths can also be used.

[0122] The post-bonding edge trimming process only removes the thinner peripheral portions of the first wafer 100 and the second wafer 200. Therefore, as... Figure 7C As schematically illustrated in the illustration, the trimmed sidewalls and trimmed annular horizontal surfaces of the joining components can achieve a very smooth profile. In other words, the trimmed sidewalls and trimmed annular horizontal surfaces can have very small surface roughness, such as a root mean square surface roughness of less than 10 nanometers, or less than 3 nanometers.

[0123] See Figure 8The upper portion of an exemplary first wafer 100 is shown in an enlarged view. An encapsulation dielectric layer 130 may subsequently be formed on the back surface of the first wafer 100. The encapsulation dielectric layer 130 may include a dielectric material that protects the bonding components (100, 200) in a subsequent dicing process, in which each bonding pair of a first semiconductor wafer in the first wafer 100 and a second semiconductor wafer in the second wafer 200 is diced into discrete structures. The encapsulation dielectric layer 130 may include silicon nitride or a high dielectric constant dielectric material (such as alumina, hafnium oxide, tantalum oxide, titanium oxide, etc.) with a dielectric constant greater than 7.9. Other suitable materials are also within the scope of this disclosure. The thickness of the encapsulation dielectric layer 130 may range from 50 nanometers to 500 nanometers, but smaller or larger thicknesses may also be used.

[0124] A photoresist layer (not shown) may be applied to a horizontal portion of the packaging dielectric layer 130 covering the first semiconductor substrate 108 and may be photolithographically patterned to form openings therethrough. An anisotropic etching process may be performed to etch unmasked portions through a subset of the packaging dielectric layer 130, the first semiconductor substrate 108, and the interconnect-level dielectric layer 30, thereby solidly exposing the horizontal surface of the underlying metal pad structure. The metal pad structure may include one of the metal lines of the second wafer 200 (such as first metal line 41L, second metal line 42L, third metal line 43L, etc.). Through-hole cavities 139 may be formed through the first semiconductor substrate 108 in each wafer region of the first wafer 100.

[0125] See Figure 9 Dielectric materials such as silicon oxide can be conformally deposited and subsequently anisotropically etched to form insulating spacers 146 penetrating the substrate. While smaller or larger thicknesses can also be used, the lateral thickness of each insulating spacer 146 penetrating the substrate can range from 100 nanometers to 500 nanometers. At least one conductive material can be deposited in the via cavity 139 penetrating the substrate and on the top surface of the encapsulation dielectric layer 130. For example, a metal pad material (such as TiN, TaN, and / or WN) and at least one metal filler material (such as copper, molybdenum, ruthenium, tungsten, aluminum, or combinations thereof) can be deposited in the remaining volume of the via cavity 139 penetrating the substrate and on the top surface of the encapsulation dielectric layer 130. At least one metal filler material can fill the via cavity 139 penetrating the substrate. An underbump metallurgy (UBM) layer stack can be deposited on the at least one metal filler material. Layer stacks that can be used for under-bump metallurgical layer stacking include, but are not limited to, chromium / chromium-copper / copper / gold, chromium / chromium-copper / copper, titanium-tungsten / chromium / copper, titanium / nickel / gold, and chromium / copper / gold stacks. Other suitable materials are also within the scope of this disclosure.

[0126] The under-bump metallurgical layer stack and at least one conductive material can then be patterned, for example, by coating and patterning a photoresist layer, and transferring the pattern in the photoresist layer through a horizontal portion of the under-bump metallurgical layer stack and at least one conductive material. Each remaining portion of the at least one conductive material is located within a corresponding via cavity 139 through the substrate, this remaining portion forming a via structure 148 through the substrate. Each remaining portion of the at least one conductive material and the under-bump metallurgical layer stack covering a horizontal surface including the distal horizontal surface of the encapsulation dielectric layer 130 includes a bonding pad 160, which may be an external bonding pad to which solder balls may be attached for wire bonding or C4 bonding. In an alternative embodiment, the under-bump metallurgical layer stack may be omitted, and the at least one conductive material may include copper or a copper alloy as a metal filler material. In this embodiment, the bonding pad 160 may have a copper surface, which may subsequently be used for copper-copper bonding, where the copper bonding pad is formed within another wafer in a subsequent wafer-to-wafer bonding process that forms a bonding assembly of three wafers.

[0127] See Figure 10A and Figure 10B An exemplary structure includes a bonding assembly (100, 200) comprising a first wafer 100 bonded to a second wafer 200 at a bonding interface. Cylindrical straight sidewalls may extend vertically from the back surface of the first wafer 100 around the bonding interface to a region surrounding the second wafer 200.

[0128] In one embodiment, a first wafer 100 may include a first two-dimensional array of first semiconductor wafers having a two-dimensional periodicity, and a second wafer 200 may include a second two-dimensional array of second semiconductor wafers having the same two-dimensional periodicity as the first two-dimensional array of first semiconductor wafers. In this case, the bonding assembly of the first wafer 100 and the second wafer 200 may be diced along a dicing channel DC into a plurality of bonded semiconductor wafers. For example, the bonding assembly (100, 200) may be diced along the dicing channel DC using a dicing saw. The dicing channel DC may include a first dicing channel that is parallel to each other and extends laterally in a first horizontal direction, and a second dicing channel that is parallel to each other and extends laterally in a second horizontal direction perpendicular to the first horizontal direction. Each dicing channel DC may be located between adjacent pairs of semiconductor wafers within the first wafer 100 and between adjacent pairs of semiconductor wafers within the second wafer 200.

[0129] Each semiconductor wafer 300, which can be cut into pieces via a dicing process, may include a first semiconductor wafer as a diced portion of a first wafer 100 and a second semiconductor wafer as a diced portion of a second wafer 200. Thus, each semiconductor wafer 300 may include a stack of first and second semiconductor wafers bonded to each other by metal-to-metal bonding between a first bonding pad in a first bonding pad level dielectric layer of the first semiconductor wafer and a second bonding pad in a second bonding pad level dielectric layer of the second semiconductor wafer. Typically, each of the bonded semiconductor wafers formed by the dicing bonding assemblies (100, 200) may include a bonding pair of a corresponding first semiconductor wafer and a corresponding second semiconductor wafer. Additional bonding pads 160 may be provided on the back side of the second semiconductor wafer; these bonding pads may be external bonding pads including a corresponding under-bump metallurgical layer stack.

[0130] See Figure 11A and Figure 11B These figures illustrate a second wafer 200 according to a second embodiment of the present disclosure, which is derived from [the present invention] by performing a second pre-bonded edge trimming process. Figure 3A and Figure 3B The second wafer 200 of the first embodiment. A second pre-bonding edge trimming process trims the edges of the front periphery region of the second wafer 200. The second pre-bonding edge trimming process removes an annular periphery portion of the second wafer 200 located within a second edge trimming width tw2 from the outermost edge of the second wafer 200 and within a second edge trimming depth td2 from a horizontal plane including the top surface (i.e., the bonding side surface) of the second wafer 200. A commercially available wafer edge trimming tool can be used to perform the second pre-bonding edge trimming process. The second pre-bonding edge trimming process forms an annular horizontal edge trimming surface in a horizontal plane located at a distance of the second edge trimming depth td2 from the front surface of the second wafer 200. In addition, the second pre-bonding edge trimming process forms a second cylindrical sidewall on the second wafer 200 at a position laterally offset from the outermost edge of the second wafer 200 to the second edge trimming width tw2. In one embodiment, the second trimming width tw2 may be in the range of 0.1 mm to 5.0 mm, but smaller and larger second trimming widths may also be used. The second edge trimming width tw2 can be greater than the edge removal distance of the second wafer 200, but less than the end edge trimming width of the post-bonding edge trimming process to be used. In one embodiment, the second edge trimming depth td2 can be in the range of 5 micrometers to 20 micrometers, but smaller and larger second edge trimming depths can also be used.

[0131] In the second embodiment, the first wafer 100 can be fabricated using the same method as in the first embodiment. Therefore, the first pre-bonding edge trimming process can be performed on the first wafer 100 in the same manner as in the first embodiment. Thus, the second pre-bonding edge trimming process can be an additional pre-bonding edge trimming process performed on the second wafer 200 before bonding the front surface of the first wafer 100 to the front surface of the second wafer 200. Typically, the second pre-bonding edge trimming process forms a second cylindrical sidewall on the second wafer 200 at a position laterally offset from the outermost periphery of the second wafer 200 to a second edge trimming width tw2.

[0132] See Figure 12A and Figure 12B The first wafer 100 and the second wafer 200 can be bonded to each other by bonding the front surface of the first wafer 100 to the front surface of the second wafer 200. For example, a second bonding pad formed in a second bonding pad level dielectric layer of the second wafer 200 can be bonded to a first bonding pad formed in a first bonding pad level dielectric layer of the first wafer 100. Metal-to-metal bonding (such as copper-copper bonding) can be used. The same bonding process as in the first embodiment can be used.

[0133] See Figure 13A and Figure 13B The back side of the first wafer 100 can be thinned by performing at least one wafer thinning process. For example, a first wafer thinning process can be performed to thin the first wafer 100 to a first thickness t1 greater than a first edge trimming depth td1. In one embodiment, the first wafer thinning process may include and / or may consist of a wafer grinding process that grinds the back side of the first wafer 100. In one embodiment, the first thickness t1 may be in the range of 10 micrometers to 60 micrometers, such as 15 micrometers to 50 micrometers. Choosing a first thickness t1 greater than the first edge trimming depth td1 provides the advantage of avoiding grinding to portions of the first wafer 100 including annular horizontal surfaces (i.e., annular horizontal surfaces formed by the first pre-bonding trimming process) that are vertically offset from the bonding interface to the first edge trimming depth td1. Therefore, chipping and frizzing near the annular flat surface formed during the first pre-bonding edge trimming process can be avoided at the edge portions of the first wafer 100.

[0134] See Figure 14A and Figure 14BA second thinning process can be performed to further thin the first wafer 100. The second wafer thinning process uses a thinning process that is less likely to cause wafer frizz than a grinding process to thin the first wafer 100 to a second thickness t2 less than the first edge trimming depth td1. For example, the second wafer thinning process can use an isotropic etching process to etch the material on the back side of the remaining portion of the first wafer 100, and / or can use a chemical mechanical polishing (CMP) process. In one embodiment, the second wafer thinning process may include an isotropic etching process using the aforementioned HNA etchant. In one embodiment, the second thickness t2 may be in the range of 2 micrometers to 10 micrometers.

[0135] Typically, at least one wafer thinning process can be performed to remove the untrimmed portion of the first wafer 100, which is the portion of the first wafer 100 that was not laterally edge-trimmed during the first pre-bonding edge trimming process. This at least one wafer thinning process forms the back surface of the first semiconductor substrate 108 in a horizontal plane, which is vertically offset from the bonding interface between the first wafer 100 and the second wafer 200 by a vertical distance less than the first edge trimming depth td1. The annular horizontal surface of the first wafer 100 formed during the first pre-bonding edge trimming process can be removed during the second thinning process without causing the portion of the first wafer 100 adjacent to the annular horizontal surface to chip or curl.

[0136] See Figure 15A and Figure 15B This process, also known as post-bonding edge trimming, performs an edge trimming process on the front periphery of the first wafer 100 and the second wafer 200. The portions of the first wafer 100 and the second wafer 200 located within the edge trimming width twt from the outermost edge of the bonding assembly (the outermost edge of the second wafer 200) and the edge trimming depth tdt from the horizontal plane including the back surface of the first wafer 100 are removed during the post-bonding edge trimming process.

[0137] The post-bonding edge trimming process forms a cylindrical end sidewall at a location on the first wafer 100 and the front periphery of the second wafer 200, laterally offset from the outermost edge of the second wafer 200 by an end edge trimming width twt. The end trimming width twt is greater than the first trimming width tw1 and greater than the second trimming width tw2. For example, the end edge trimming width twt can be in the range of 1.0 mm to 10.0 mm. Furthermore, the post-bonding edge trimming process can form an annular horizontal surface on the second wafer 200. This annular horizontal surface can be formed within a horizontal plane, vertically spaced from the horizontal plane including the bonding interface between the first wafer 100 and the second wafer 200 by a vertical distance greater than the second edge trimming depth td2. For example, an annular horizontal surface formed on the second wafer 200 by a post-bonding edge trimming process can be formed in a horizontal plane, which is vertically spaced from the horizontal plane including the bonding interface between the first wafer 100 and the second wafer 200 by a vertical distance ranging from 5 micrometers to 100 micrometers. In other words, the end edge trimming depth tdt can be the sum of the second thickness t2 and an additional depth ranging from 10 micrometers to 50 micrometers.

[0138] Subsequently, it can be executed Figure 8 , Figure 9 and Figure 10A and Figure 10B The processing steps are to cut the bonding assembly of the first wafer 100 and the second wafer 200 into a plurality of bonded semiconductor wafers, including a corresponding pair of first semiconductor wafers and second semiconductor wafers.

[0139] refer to Figure 16 The first flowchart illustrates the steps that can be used to form one of the exemplary structures disclosed herein. In step 1610, the front periphery region of the first wafer 100 can be prepared by performing a pre-bonded edge trimming process (such as...). Figure 2A and Figure 2B The first pre-bonding edge trimming process is used to trim the edges. In step 1620, the front surface of the first wafer 100 can be bonded to the front surface of the second wafer 200. Referring to step 1630, the back side of the first wafer 100 can be thinned by performing at least one wafer thinning process. Referring to step 1640, the areas surrounding the front sides of the first wafer 100 and the second wafer 200 can be edge-trimmed by performing a post-bonding edge trimming process.

[0140] refer to Figure 17The second flowchart illustrates steps that can be used to form one of the exemplary structures disclosed herein. In step 1710, the front periphery region of the first wafer 100 can be edge-trimmed by performing a first pre-bonding edge trimming process. In step 1720, the front periphery region of the second wafer 200 can be edge-trimmed by performing a second pre-bonding edge trimming process. In step 1730, a bonding assembly (100, 200) can be formed by bonding the front surface of the first wafer 100 to the front surface of the second wafer 200. In step 1740, an untrimmed portion of the first wafer 100 can be removed by thinning the back side of the first wafer 100 in the bonding assembly (100, 200) using at least one thinning process. The back side surface of the first wafer 100 abuts a cylindrical sidewall formed during the first pre-bonding edge trimming process. In step 1750, the edge trimming of the bonding assemblies (100, 200) can be performed by executing a post-bonding edge trimming process that trims the front periphery of the first wafer 100 and the second wafer 200 (but does not trim the back periphery of the second wafer 200).

[0141] refer to Figure 18 The third flowchart illustrates the steps that can be used to form one of the exemplary structures disclosed herein. In step 1810, a first wafer 100 comprising a first two-dimensional array of first semiconductor wafers can be provided. In step 1820, a second wafer 200 can be provided, comprising a second two-dimensional array of second semiconductor wafers having the same two-dimensional periodicity as the first two-dimensional array of first semiconductor wafers. In step 1830, the front periphery region of the first wafer can be processed by performing a pre-bonded edge trimming process (e.g., Figure 2A and Figure 2B In step 1840, edge trimming is performed using a first pre-bonding edge trimming process. In step 1850, the back side of the first wafer 100 is thinned by performing at least one wafer thinning process. In step 1860, the areas surrounding the front sides of the first wafer 100 and the second wafer 200 are edge-trimmed by performing a post-bonding edge trimming process. In step 1870, the bonding assembly (100, 200) is diced into multiple bonded semiconductor wafers. Each bonded semiconductor wafer comprises a bond pair of two: a corresponding first semiconductor wafer and a corresponding second semiconductor wafer.

[0142] The various structures and methods disclosed herein can be used to provide effective edge trimming for two wafers being bonded to form a bonded assembly. The vertical range of a first pre-bonding edge trimming process is limited to the upper periphery of the first wafer 100 and may have a first edge trimming depth td1 ranging from 10 micrometers to 50 micrometers, thus less than 10% of the total thickness of the first wafer. When using a second pre-bonding edge trimming process, the vertical range of the second pre-bonding edge trimming process is limited to the upper periphery of the second wafer 200 and may have a second edge trimming depth td2 ranging from 5 micrometers to 20 micrometers. The vertical range of the post-bonding edge trimming process is limited to the end edge trimming depth tdt, which may be equal to the second thickness t2 and the sum of the vertical depths ranging from 10 micrometers to 50 micrometers. Each edge trimming process may have a vertical range significantly smaller than the pre-thinning wafer thickness, ranging from 725 micrometers to 825 micrometers. Therefore, the method disclosed herein reduces the total processing time and cost of the edge trimming process, and provides high wafer processing capability for the edge trimming process with appropriate processing tools. Furthermore, before and / or after bonding the first wafer 100 and the second wafer 200, the method disclosed herein effectively reduces the stripping of interconnect hierarchy structures (L0-L6) and bonding pad hierarchy structures LP in the first wafer 100 and the second wafer 200. Therefore, the effectiveness of edge trimming continues throughout the bonding and dicing processes. Thus, the method disclosed herein provides cost-effective and reliable edge trimming during bonding and wafer dicing.

[0143] According to one embodiment of this disclosure, a method of forming a semiconductor structure includes edge trimming of a front periphery region of a first wafer by performing a pre-bonding edge trimming process; bonding the front surface of the first wafer to the front surface of a second wafer; thinning the back side of the first wafer by performing at least one wafer thinning process; and edge trimming of the front periphery regions of the first and second wafers by performing a post-bonding edge trimming process. In some embodiments, the pre-bonding edge trimming process forms an annular horizontal edge trimming surface in a horizontal plane. The horizontal plane is located at a first edge trimming depth from the front surface of the first wafer. In some embodiments, at least one wafer thinning process forms the back side surface of the first wafer in the horizontal plane. The horizontal plane is vertically offset from the bonding interface between the first and second wafers by a vertical distance less than the first edge trimming depth. In some embodiments, at least one wafer thinning process includes: a first wafer thinning process, thinning the first wafer to a first thickness greater than a first edge trimming depth; and a second wafer thinning process, thinning the first wafer to a second thickness less than the first edge trimming depth. In some embodiments, the first wafer thinning process includes a wafer grinding process; and the second wafer thinning process includes an isotropic etching process. In some embodiments, the first thickness is in the range of 10 micrometers to 60 micrometers; and the second thickness is in the range of 2 micrometers to 10 micrometers. In some embodiments, a pre-bonding edge trimming process forms a first cylindrical sidewall at a location on the first wafer. The location is laterally offset from the outermost edge of the first wafer by a first edge trimming width. In some embodiments, a post-bonding edge trimming process forms an end cylindrical sidewall at a location on the first wafer and in a region surrounding the front side of the second wafer. The location is laterally offset from the outermost edge of the second wafer by an end edge trimming width. The end edge trimming width is greater than the first edge trimming width. In some embodiments, the first trimming width is in the range of 0.1 mm to 5.0 mm; and the end trimming width is in the range of 1.0 mm to 10.0 mm. In some embodiments, a post-bonding trimming process forms an annular horizontal surface on the second wafer; and the annular horizontal surface is formed within a horizontal plane. The horizontal plane is vertically spaced from the horizontal plane including the bonding interface between the first wafer and the second wafer by a vertical spacing in the range of 5 micrometers to 100 micrometers. In some embodiments, the method further includes trimming the edge of the area surrounding the front side of the second wafer by performing an additional pre-bonding edge trimming process before bonding the front surface of the first wafer to the front surface of the second wafer. In some embodiments, the first wafer includes a first two-dimensional array of first semiconductor wafers; the second wafer includes a second two-dimensional array of second semiconductor wafers having the same two-dimensional periodicity as the first two-dimensional array of the first semiconductor wafers; and the method includes dicing bonding assemblies of the first wafer and the second wafer along dicing channels.

[0144] According to one embodiment of this disclosure, a method of forming a semiconductor structure includes edge trimming a front periphery region of a first wafer by performing a first pre-bonding edge trimming process; edge trimming a front periphery region of a second wafer by performing a second pre-bonding edge trimming process; forming a bonding assembly by bonding the front surface of the first wafer to the front surface of the second wafer; removing an untrimmed portion of the first wafer by thinning the back side of the first wafer in the bonding assembly using at least one thinning process, wherein the back side surface of the first wafer abuts a cylindrical sidewall formed during the first pre-bonding edge trimming process; and edge trimming the bonding assembly by performing a post-bonding edge trimming process that trims the front periphery regions of the first and second wafers. In some embodiments, the pre-bonding edge trimming process forms an annular horizontal edge trimming surface in a horizontal plane located at a first edge trimming depth from the front surface of the first wafer; and the annular horizontal edge trimming surface is removed during the thinning of the back side of the first wafer. In some embodiments, after the back side of the first wafer in the bonding assembly is thinned, the thickness of the first wafer is less than the first edge trimming depth. In some embodiments, the back side of the first wafer in the bonding assembly is thinned by performing the following steps: a first wafer thinning process to thin the first wafer to a first thickness greater than a first edge trimming depth; and a second wafer thinning process to thin the first wafer to a second thickness less than the first edge trimming depth. In some embodiments, a first pre-bonding edge trimming process forms a first cylindrical sidewall on the first wafer at a position laterally offset from the outermost edge of the first wafer by a first edge trimming width; a second pre-bonding edge trimming process forms a second cylindrical sidewall on the second wafer at a position laterally offset from the outermost edge of the second wafer by a second edge trimming width; and a post-bonding edge trimming process forms an end cylindrical sidewall at a position on the first wafer and in the front periphery region of the second wafer, the position being laterally offset from the outermost edge of the second wafer by an end edge trimming width, the end edge trimming width being greater than the first edge trimming width and greater than the second edge trimming width.

[0145] According to one embodiment of the present disclosure, a method of forming a bonded semiconductor wafer includes providing a first wafer comprising a first two-dimensional array of first semiconductor wafers; providing a second wafer comprising a second two-dimensional array of second semiconductor wafers having the same two-dimensional periodicity as the first two-dimensional array of the first semiconductor wafers; edge-trimming a front periphery region of the first wafer by performing a pre-bonding edge trimming process; forming a bonding assembly by bonding the front surface of the first wafer to the front surface of the second wafer, wherein each of the first semiconductor wafers is bonded to a corresponding one of the second semiconductor wafers; thinning the back side of the first wafer by performing at least one wafer thinning process; edge-trimming the front periphery regions of the first wafer and the second wafer by performing a post-bonding edge trimming process; and dicing the bonding assembly into a plurality of bonded semiconductor wafers, wherein each of the bonded semiconductor wafers comprises a bonding pair of two: a corresponding one of the first semiconductor wafers and a corresponding one of the second semiconductor wafers. In some embodiments, the method further includes edge trimming of the area surrounding the front side of the second wafer by performing an additional pre-bonding edge trimming process before bonding the front surface of the first wafer to the front surface of the second wafer.

[0146] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations to this disclosure without departing from its spirit and scope.

Claims

1. A method of forming a semiconductor structure, comprising: comprises a first semiconductor substrate, first semiconductor elements on the first semiconductor substrate, a first interconnect level structure on the first semiconductor elements, a first bond pad level dielectric layer on the first interconnect level structure, and first metal bond pads within the first bond pad level dielectric layer; performing a first pre-bond edge trim process on the first wafer, wherein the first pre-bond edge trim process removes a first annular peripheral portion of the first wafer, the first annular peripheral portion is within a first edge trim width from an outermost periphery of the first wafer, and the first annular peripheral portion is within a first edge trim depth from a first horizontal plane comprising a first top surface of the first wafer, the first pre-bond edge trim process forms a first annular horizontal edge trim surface within the first horizontal plane at the first edge trim depth from a front surface of the first wafer, the first pre-bond edge trim process forms a first cylindrical sidewall at a location on the first wafer laterally offset from the outermost periphery of the first wafer by the first edge trim width; comprises a second semiconductor substrate, second semiconductor elements on the second semiconductor substrate, a second interconnect level structure on the second semiconductor elements, a second bond pad level dielectric layer on the second interconnect level structure, and second metal bond pads within the second bond pad level dielectric layer; performing a second pre-bond edge trim process on the second wafer, wherein the second pre-bond edge trim process removes a second annular peripheral portion of the second wafer, the second annular peripheral portion is within a second edge trim width from an outermost periphery of the second wafer, and the second annular peripheral portion is within a second edge trim depth from a second horizontal plane comprising a second top surface of the second wafer, the second pre-bond edge trim process forms a second annular horizontal edge trim surface within the second horizontal plane at the second edge trim depth from a front surface of the second wafer, the second pre-bond edge trim process forms a second cylindrical sidewall at a location on the second wafer laterally offset from the outermost periphery of the second wafer by the second edge trim width; bonding the first metal bond pads of the first wafer to the second metal bond pads of the second wafer by a metal-to-metal bond; thinning a backside of the first wafer by performing at least one wafer thinning process; and edge trimming a front side peripheral region of the first wafer and the second wafer by performing a post-bond edge trim process. The metal-to-metal bond is a copper-to-copper bond. The at least one wafer thinning process forms a backside surface of the first wafer within a horizontal plane vertically offset from a bond interface between the first wafer and the second wafer by a vertical spacing, the vertical spacing is less than the first edge trim depth.

2. The method of claim 1, wherein, The at least one wafer thinning process comprises:

3. The method of claim 2, wherein, a first wafer thinning process that thins the first wafer to a first thickness that is greater than the first edge trim depth; and 4. The method of claim 3, wherein, a second wafer thinning process that thins the first wafer to a second thickness that is less than the first edge trim depth. ​ a second wafer thinning process that thins the first wafer to a second thickness that is less than the first edge trim depth.

5. The method of claim 4, wherein: the first wafer thinning process comprises a wafer grinding process; and the second wafer thinning process comprises an isotropic etching process.

6. The method of claim 4, wherein: the first thickness is in a range from 10 microns to 60 microns; and the second thickness is in a range from 2 microns to 10 microns.

7. The method of claim 1, wherein, the number of the first interconnect levels is in a range from 1 to 20.

8. The method of claim 1, wherein, the post-bond edge trim process forms an end cylindrical sidewall on the first wafer and on the front side peripheral region of the second wafer at a location that is laterally offset from the outermost periphery of the second wafer by an end edge trim width that is greater than the first edge trim width.

9. The method of claim 8, wherein: the first edge trim width is in a range from 0.1 mm to 5.0 mm; and the end edge trim width is in a range from 1.0 mm to 10.0 mm.

10. The method of claim 1, wherein: the post-bond edge trim process forms an annular horizontal surface on the second wafer; and the annular horizontal surface is formed in a horizontal plane that is vertically spaced from a horizontal plane that includes a bonding interface between the first wafer and the second wafer by a vertical separation that is in a range from 5 microns to 100 microns.

11. The method of claim 1, wherein, inducing an oxide-to-oxide bonding between the first bonding pad level dielectric layer and the second bonding pad level dielectric layer prior to the metal-to-metal bonding.

12. The method of claim 1, wherein: the first wafer comprises a first two-dimensional array of first semiconductor dies; the second wafer comprises a second two-dimensional array of second semiconductor dies that have a same two-dimensional periodicity as the first two-dimensional array of the first semiconductor dies; and the method comprises dicing the bonded assembly of the first wafer and the second wafer along dicing streets. comprises:

13. A method of forming a semiconductor structure, comprising: providing a first wafer, wherein the first wafer comprises a first semiconductor substrate, first semiconductor elements on the first semiconductor substrate, first interconnect levels on the first semiconductor elements, first bonding pad level dielectric layers on the first interconnect levels, and first metal bonding pads in the first bonding pad level dielectric layers; ​ performing a first pre-bond edge trim process on the first wafer, wherein the first pre-bond edge trim process removes a first annular peripheral portion of the first wafer, the first annular peripheral portion is within a first edge trim width from an outermost periphery of the first wafer, and the first annular peripheral portion is within a first edge trim depth from a first horizontal plane including a first top surface of the first wafer, the first pre-bond edge trim process forms a first annular horizontal edge trim surface within the first horizontal plane at the first edge trim depth from a front surface of the first wafer, the first pre-bond edge trim process forms a first cylindrical sidewall on the first wafer laterally offset from the outermost periphery of the first wafer by the first edge trim width; providing a second wafer, wherein the second wafer includes a second semiconductor substrate, second semiconductor elements on the second semiconductor substrate, second interconnect level structures on the second semiconductor elements, second bond pad level dielectric layers on the second interconnect level structures, and second metal bond pads within the second bond pad level dielectric layers; performing a second pre-bond edge trim process on the second wafer, wherein the second pre-bond edge trim process removes a second annular peripheral portion of the second wafer, the second annular peripheral portion is within a second edge trim width from an outermost periphery of the second wafer, and the second annular peripheral portion is within a second edge trim depth from a second horizontal plane including a second top surface of the second wafer, the second pre-bond edge trim process forms a second annular horizontal edge trim surface within the second horizontal plane at the second edge trim depth from a front surface of the second wafer, the second pre-bond edge trim process forms a second cylindrical sidewall on the second wafer laterally offset from the outermost periphery of the second wafer by the second edge trim width; forming a bonded assembly by bonding the first metal bond pads at the front surface of the first wafer to the second metal bond pads at the front surface of the second wafer using a metal-to-metal bonding; removing untrimmed portions of the first wafer by thinning a backside of the first wafer in the bonded assembly using at least one thinning process, wherein a backside surface of the first wafer is contiguous with a cylindrical sidewall formed during the first pre-bond edge trim process; and edge trimming the bonded assembly by performing a post-bond edge trim process that trims a front side peripheral region of the first wafer and the second wafer.

14. The method of claim 13, wherein: during the thinning of the backside of the first wafer, the first annular horizontal edge trim surface is removed.

15. The method of claim 14, wherein, after the backside of the first wafer in the bonded assembly is thinned, a thickness of the first wafer is less than the first edge trim depth.

16. The method of claim 15, wherein, the backside of the first wafer in the bonded assembly is thinned by performing: a first wafer thinning process that thins the first wafer to a first thickness that is greater than the first edge trim depth; and a second wafer thinning process that thins the second wafer to a second thickness that is greater than the second edge trim depth. a second wafer thinning process that thins the first wafer to a second thickness that is less than the first edge trim depth.

17. The method of claim 13, wherein: the post-bond edge trim process forms a terminal cylindrical sidewall on the first wafer and on the front side peripheral region of the second wafer at a location that is laterally offset from an outermost periphery of the second wafer by a terminal edge trim width, the terminal edge trim width being greater than the first edge trim width and greater than the second edge trim width.

18. The method of claim 13, wherein: the annular horizontal surface is formed in a horizontal plane that is vertically spaced from a horizontal plane of a bonding interface included between the first wafer and the second wafer by a vertical spacing, the vertical spacing being in a range of 5 microns to 100 microns.

19. A method of forming bonded semiconductor wafers, comprising: comprises: providing a first wafer comprising a first two-dimensional array of first semiconductor dies, wherein the first wafer comprises a first semiconductor substrate, first semiconductor elements on the first semiconductor substrate, first interconnect level structures on the first semiconductor elements, first bond pad level dielectric layers on the first interconnect level structures, and first metal bond pads within the first bond pad level dielectric layers; providing a second wafer comprising a second two-dimensional array of second semiconductor dies having a same two-dimensional periodicity as the first two-dimensional array of second semiconductor dies, wherein the second wafer comprises a second semiconductor substrate, second semiconductor elements on the second semiconductor substrate, second interconnect level structures on the second semiconductor elements, second bond pad level dielectric layers on the second interconnect level structures, and second metal bond pads within the second bond pad level dielectric layers; performing a first pre-bond edge trim process on the first wafer, wherein the first pre-bond edge trim process removes a first annular peripheral portion of the first wafer that is within a first edge trim width from an outermost periphery of the first wafer and that is within a first edge trim depth from a first horizontal plane that includes a first top surface of the first wafer, the first pre-bond edge trim process forming a first annular horizontal edge trim surface in the first horizontal plane at a location that is at the first edge trim depth from a front surface of the first wafer, the first pre-bond edge trim process forming a first cylindrical sidewall on the first wafer at a location that is laterally offset from the outermost periphery of the first wafer by the first edge trim width; performing a second pre-bond edge trim process on the second wafer, wherein the second pre-bond edge trim process removes a second annular peripheral portion of the second wafer, the second annular peripheral portion being within a second edge trim width from an outermost periphery of the second wafer and the second annular peripheral portion being within a second edge trim depth from a second horizontal plane including a second top surface of the second wafer, the second pre-bond edge trim process forming a second annular horizontal edge trim surface within the second horizontal plane at the second edge trim depth from a front surface of the second wafer, the second pre-bond edge trim process forming a second cylindrical sidewall at a location on the second wafer laterally offset from the outermost periphery of the second wafer by the second edge trim width; bonding the first metal bond pads of the first wafer to the second metal bond pads of the second wafer by a metal-to-metal bonding to form a bonded assembly, wherein each of the first semiconductor dies is bonded to a respective one of the second semiconductor dies; thinning a backside of the first wafer by performing at least one wafer thinning process; edge trimming a front side peripheral region of the first wafer and the second wafer by performing a post-bond edge trim process; and dicing the bonded assembly into a plurality of bonded semiconductor dies, wherein each of the bonded semiconductor dies includes a bonded pair of a respective one of the first semiconductor dies and a respective one of the second semiconductor dies.

20. The method of claim 19, wherein, further comprising forming a via structure through the first semiconductor substrate. performing a second pre-bond edge trim process on the second wafer, wherein the second pre-bond edge trim process removes a second annular peripheral portion of the second wafer, the second annular peripheral portion being within a second edge trim width from an outermost periphery of the second wafer and the second annular peripheral portion being within a second edge trim depth from a second horizontal plane including a second top surface of the second wafer, the second pre-bond edge trim process forming a second annular horizontal edge trim surface within the second horizontal plane at the second edge trim depth from a front surface of the second wafer, the second pre-bond edge trim process forming a second cylindrical sidewall at a location on the second wafer laterally offset from the outermost periphery of the second wafer by the second edge trim width; bonding the first metal bond pads of the first wafer to the second metal bond pads of the second wafer by a metal-to-metal bonding to form a bonded assembly, wherein each of the first semiconductor dies is bonded to a respective one of the second semiconductor dies; thinning a backside of the first wafer by performing at least one wafer thinning process; edge trimming a front side peripheral region of the first wafer and the second wafer by performing a post-bond edge trim process; and dicing the bonded assembly into a plurality of bonded semiconductor dies, wherein each of the bonded semiconductor dies includes a bonded pair of a respective one of the first semiconductor dies and a respective one of the second semiconductor dies. further comprising forming a via structure through the first semiconductor substrate.

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