Package, semiconductor device and method for forming the same

Abstract

Disclosed herein is a method for forming an ultra-high density metal-insulator-metal (SHDMIM) capacitor and a semiconductor device. The method comprises: depositing a first insulating layer above a semiconductor substrate, and depositing a series of conductive layers separated by a series of dielectric layers above the first insulating layer, the series of conductive layers comprising device electrodes and pseudo metal plates. A first group of contact plugs passing through a series of conductive layers contacts one or more conductive layers in a first portion of a series of conductive layers. A second group of contact plugs passing through a series of dielectric layers avoids contacting a second portion of a series of conductive layers, and the second portion of a series of conductive layers is electrically floating. Embodiments of the present application provide a package, a semiconductor device, and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to packages, semiconductor devices, and methods of forming the same. Background Art

[0002] Metal-insulator-metal (MIM) capacitors have been widely used in functional circuits such as mixed-signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM), embedded DRAM, and logic operation circuits. In system-on-chip applications, different capacitors for different functional circuits must be integrated on the same chip to serve different purposes. For example, in mixed-signal circuits, capacitors are used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillators and phase shift networks for coupling and / or bypass purposes. For microprocessors, capacitors are used for decoupling. The traditional way to combine these capacitors on the same chip is to manufacture these capacitors in different metal layers.

[0003] Decoupling capacitors are used to decouple certain parts of an electrical network from other parts. Noise caused by certain circuit elements is shunted by decoupling capacitors, thereby reducing the effect of the noise-generating circuit elements on adjacent circuits. In addition, decoupling capacitors are also used in power supplies so that the power supply can adapt to changes in current consumption, thereby minimizing changes in the supply voltage. When the current consumption in a device changes, the power supply itself cannot respond to the change immediately. Therefore, the decoupling capacitor can be used as a power storage device to maintain the supply voltage in response to the current consumption.

[0004] Integrated circuit packages are becoming more complex, packaging more device dies in the same package to achieve more functions. For example, a system on an integrated chip (SoIC) has been developed to include multiple device dies, such as a processor and a memory cube, in the same package. A SoIC can include device dies formed using different technologies and having different functions bonded to the same device die to form a system. This can save manufacturing costs and optimize device performance. Summary of the invention

[0005] In some embodiments, a method includes: depositing a first insulating layer over a semiconductor substrate; depositing a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates; depositing a second insulating layer over the series of conductive layers and the dielectric layers; forming a first group of contact plugs through the series of conductive layers, each of the first group of contact plugs contacting one or more conductive layers in a first portion of the series of conductive layers; forming a second group of contact plugs through the series of dielectric layers, each of the second group of contact plugs avoiding contacting a second portion of the series of conductive layers, the second portion of the series of conductive layers being electrically floating.

[0006] In some embodiments, a package includes: a first die, the first die including an integrated device structure disposed above an interconnect structure, the integrated device structure including: a first capacitor electrode, the first capacitor electrode being formed on a first layer of the integrated device structure; a second capacitor electrode, the second capacitor electrode being formed on a second layer of the integrated device structure; a first capacitor insulator layer being inserted between the first capacitor electrode and the second capacitor electrode; and a first dummy metal plate and a second dummy metal plate, the first dummy metal plate being formed on the first layer of the integrated device structure, the second dummy metal plate being formed on the second layer of the integrated device structure, wherein the first dummy metal plate and the second dummy metal plate are electrically floated from the first capacitor electrode and the second capacitor electrode; and a second die, a connector of the second die contacting a connector of the first die.

[0007] In some embodiments, a device includes: an embedded device; an interconnect structure disposed above the embedded device; a first passivation structure disposed above the interconnect structure, the first passivation structure including an integrated device layer, the integrated device layer including a first capacitor and a first pseudo-metal plate; a second passivation structure disposed above the first passivation structure, the second passivation structure having a bonding pad disposed on its upper surface; a first connector coupled to the interconnect structure and coupled to the first capacitor; and a second connector coupled to the interconnect structure, the second connector passing through the integrated device layer and away from the first capacitor and the first pseudo-metal plate.

[0008] Embodiments of the present application provide structures and methods for integrating high-density MIM capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When with Figure 1 When read together, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0010] Figure 1 A perspective view is shown of two package components coupled together in accordance with some embodiments.

[0011] Figure 2 A top view of a wafer is shown in accordance with some embodiments.

[0012] Figure 3A and FIG. 3B to FIG. 20A and Fig. 20B An intermediate view of a formed packaged device is shown in accordance with some embodiments.

[0013] Fig.21A , Fig.21B , Fig. 21C and Fig.21D A diagram illustrating a dummy metal plate layer according to some embodiments.

[0014] Figure 22 to Figure 24 Various configurations of packaged devices according to some embodiments are shown.

[0015] Figure 25 to Figure 27 A second package component and bonding of the second package component to the first package component are shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may again be used to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] According to some embodiments, a semiconductor die / wafer including a capacitor and a method of forming the same are provided. Intermediate stages of forming a capacitor are shown. Various variations of various embodiments are discussed. Throughout the various figures and illustrative embodiments, similar reference numerals are used to indicate similar elements.

[0019] Disclosed herein is a method for forming ultra-high density metal-insulator-metal (MIM) (MIM-SHD or SHDMIM) capacitors and semiconductor devices. When SHDMIM is formed in some areas of the device die and not in other areas of the device die, when the cover layer is formed, the cover layer may not have a horizontal upper surface. Therefore, a subsequently formed through-hole and platform with an uneven upper surface may be formed. This unevenness may further propagate into the dielectric bonding layer and cause bonding failure due to the non-planar bonding surface. An embodiment advantageously includes a pseudo metal plate to fill the SHDMIM layer as needed to prevent uneven coverage. The process of forming the pseudo metal plate includes: depositing a series of metal layers and alternating dielectric layers for the SHDMIM device, and after each metal layer, patterning the first metal layer into a metallization layer of the SHDMIM device and a metallization layer of the pseudo metal plate. The pseudo metal plate can be patterned to include a keep-away zone (KOZ) for a subsequently formed landing pad via and / or bonding pad via. Other landing pad vias and / or bond pad vias formed through the SHDMIM device couple the metal layer of the SHDMIM device to one or more active devices of the semiconductor substrate.

[0020] Figure 1 A perspective view of a SoIC packaged device at an intermediate step according to some embodiments is shown. The device die 105 may be a logic die, such as a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input output (IO) die, a baseband (BB) die, an application processor (AP) die, etc. The device die 105 may also be a memory die, such as a dynamic random access memory (DRAM) die or a static random access memory (SRAM) die, etc. The device die 105 may be part of a wafer (see Figure 2 ). Device die 405 is electrically bonded to device die 105. Device die 405 may be a logic die, which may be a CPU die, an MCU die, an IO die, a baseband die, or an AP die. Device die 405 may also be a memory die. Multiple of device dies 405 may be bonded to device die 105, each device die 405 having a different function.

[0021] Figure 2A package component 100 (which may be a wafer, as shown) is shown having a plurality of device dies 105 defined therein. The device dies 105 may all have the same design and function, or may have different designs and functions. The dashed lines represent cut lines 106 where the device dies 105 will be separated from one another in a subsequent singulation process.

[0022] Figure 3A and FIG. 3B to FIG. 20A and Fig. 20B A cross-sectional view of an intermediate stage in the formation of a packaged device such as a SoIC package is shown in accordance with some embodiments of the present invention. Figure 3A A cross-sectional view showing the formation of package component 100 is shown. Figure 3B A top view (or plan view) showing the formation of package component 100 is shown. Figure 3A The view is along Figure 3B BB. According to some embodiments of the present invention, the package component 100 is part of a device wafer including an integrated circuit device 122, which is, for example, an active device 102 such as a transistor and / or a diode, and may be a passive device such as a capacitor, an inductor, a resistor, etc. The active device 102 is represented by a single transistor. However, as will be appreciated by those skilled in the art, a variety of active devices may be used to produce the desired structural and functional requirements of the semiconductor device design. The active device 102 may be formed in or on the surface of the semiconductor substrate 120 using any suitable method. A plurality of device dies 105 may be included in the package component 100, of which a portion of the device die 105 is shown. It should be understood that these views are merely illustrative and not restrictive. The components shown may not be shown to scale in order to enhance or simplify details as needed.

[0023] According to other embodiments of the present invention, the package component 100 includes passive devices (no active devices). In some embodiments, and as referenced in the following discussion, the package component 100 can be a device wafer. Embodiments of the present invention can also be applied to other types of package components, such as interposer wafers.

[0024] According to some embodiments of the present invention, the wafer 100 includes a semiconductor substrate 120 and components formed on the top surface of the semiconductor substrate 120. The semiconductor substrate 120 may be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, and / or a III-V compound semiconductor, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 120 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. A shallow trench isolation (STI) region (not shown) may be formed in the semiconductor substrate 120 to isolate active regions in the semiconductor substrate 120. Although not shown, a through hole extending into the semiconductor substrate 120 may be formed and used to electrically couple with components located on opposite sides of the wafer 100.

[0025] According to some embodiments of the present invention, wafer 100 includes integrated circuit devices 122 formed on a top surface of semiconductor substrate 120. Example integrated circuit devices 122 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, and / or diodes, etc. Details of integrated circuit devices 122 are not shown herein. According to other embodiments, wafer 100 is used to form an interposer, wherein semiconductor substrate 120 may be a semiconductor substrate or a dielectric substrate.

[0026] An interlayer dielectric (ILD) 124 is formed over the semiconductor substrate 120 and fills a space between gate stacks of transistors (not shown) in the integrated circuit device 122. According to some embodiments, the ILD 124 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide formed of tetraethyl orthosilicate (TEOS), etc. The ILD 124 may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0027] Contact plug 128 is formed in ILD 124 and is used to electrically connect integrated circuit device 122 to overlying metal line 134 and via 136. According to some embodiments of the present invention, contact plug 128 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of contact plug 128 may include: forming a contact opening in ILD 124, filling the contact opening with a conductive material, and performing planarization (such as a chemical mechanical polishing (CMP) process) to make the top surface of contact plug 128 flush with the top surface of ILD 124.

[0028] There is an interconnect structure 130 above the ILD 124 and the contact plug 128. The interconnect structure 130 includes a dielectric layer 132 and a metal line 134 and a via 136 formed in the dielectric layer 132. The dielectric layer 132 is optionally referred to as an intermetallic dielectric (IMD) layer 132 hereinafter. According to some embodiments of the present invention, at least the lower dielectric layer in the dielectric layer 132 is formed of a low-k dielectric material having a dielectric constant (k value) lower than about 3.0 or about 2.5. The dielectric layer 132 may be formed of Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to an optional embodiment of the present invention, some or all of the dielectric layer 132 are formed of non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), etc. According to some embodiments of the present invention, the formation of the dielectric layer 132 includes: depositing a dielectric material containing a porogen, and then performing a curing process to exhaust the porogen, and thus the remaining dielectric layer 132 becomes porous. An etch stop layer (not shown) that may be formed of silicon carbide, silicon nitride, etc. is formed between the IMD layers 132, and is not shown for simplicity.

[0029] Metal lines 134 and vias 136 are formed in dielectric layer 132. Hereinafter, metal lines 134 at the same level are collectively referred to as metal layers. According to some embodiments of the present invention, interconnect structure 130 includes multiple metal layers interconnected by vias 136. Metal lines 134 and vias 136 may be formed of copper or copper alloys, or may be formed of other metals. The formation process may include a single inlay process and a dual inlay process. In a single inlay process, a trench is first formed in one layer of dielectric layer 132, and then the trench is filled with a conductive material. A planarization process such as a CMP process is then performed to remove excess conductive material above the top surface of the dielectric layer, thereby leaving a metal line in the trench. In a dual inlay process, a trench and a via opening are simultaneously formed in the IMD layer, wherein the via opening is located below the trench and connected thereto. Conductive material is then filled into the trench and the via opening to form a metal line and a via, respectively.

[0030] The conductive material may include a diffusion barrier layer (e.g., diffusion barrier layer 133) and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer 133 is formed in the dielectric layer 132, for example, during a damascene process or a dual damascene process for forming a metal line 134 in the dielectric layer 132. For example, during the damascene process, a groove is formed in the dielectric layer 132 to a desired depth and shape of a conductive feature to be formed therein. In this way, the surface of the dielectric layer 132 becomes a waveform by the contour of the groove formed in the dielectric layer 132. Once the opening is formed, the diffusion barrier material is deposited over and conforms to the waveform surface of the dielectric layer 132. In some embodiments, the material of the diffusion barrier layer 133 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and may be formed to a thickness of about About However, any suitable material and any suitable thickness may be used for the diffusion barrier layer 133 .

[0031] Once the diffusion barrier layer 133 has been deposited, a conductive fill material (e.g., copper (Cu)) is deposited over the diffusion barrier layer 133, and in some embodiments, the conductive fill material may be deposited such that the remaining portion of the trench is overfilled to a level above the planar surface of the dielectric layer 132. Once deposited, a planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to remove excess portions of the diffusion barrier layer 133 and excess portions of the conductive fill material extending above the planar surface of the dielectric layer 132. In this manner, a metal line 134 including the diffusion barrier layer 133 is formed within the dielectric layer 132 of the interconnect structure 130, as shown in FIG. 3. The diffusion barrier layer 133 has the function of preventing the conductive material (e.g., copper (Cu)) of the metal line 134 from diffusing into the dielectric layer 132. In some embodiments, a dielectric layer 132 having a thickness of about 100 mm may be formed. About However, any suitable material and any suitable thickness may be used for the metal line 134.

[0032] The metal lines 134 include metal lines 134A, which may be referred to as top metal lines. The top metal lines 134A are also collectively referred to as top metal layers. Each top dielectric layer 132A may be formed of a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc. The top dielectric layer 132A may also be formed of a low-k dielectric material, which may be selected from similar materials of the underlying IMD layer 132.

[0033] exist Figure 4A and Figure 4BIn accordance with some embodiments, an optional etch stop layer 138 can be formed over the interconnect structure 130. In such embodiments, the etch stop layer 138 can be formed as a blanket layer of dielectric material over the top layer of the interconnect structure 130, thereby isolating the metal line 134 from any subsequently formed layers. The etch stop layer 138 can be deposited using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc. However, any suitable materials and processes can be used to form the etch stop layer 138. According to some embodiments, the etch stop layer 138 includes a thickness of about 100 Å to about 500 Å. About However, any suitable material and any suitable thickness may be used for etch stop layer 138. For simplicity, etch stop layer 138 is omitted from the views of subsequent figures.

[0034] Figure 5A and FIG. 5B to FIG. 12A and Fig. 12B A passivation structure (eg, Fig. 12A The passivation structure 200 is an intermediate step. Figure 5A and Figure 5B In the interconnect structure 130 (or Figure 4A Insulating layer 219 is formed over optional etch stop layer 138. In some embodiments, insulating layer 219 may be formed as plasma enhanced oxide undoped silicon glass (PEOX-USG) having a thickness of about 100 Å. About In some embodiments, the insulating layer 219 is a silicon oxide layer formed of tetraethyl orthosilicate (TEOS). The insulating layer 219 can be formed as a capping layer using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc. However, the insulating layer 219 can be formed using any suitable material, any suitable thickness, and any suitable process.

[0035] exist Fig. 6A and Figure 6B In the embodiment, a bottom electrode layer 221 is formed as a capping metal layer over the insulating layer 219. According to some embodiments, the bottom electrode layer 221 is deposited by a technique including one of chemical vapor deposition (CVD) and atomic layer deposition (ALD). However, any suitable technique may be used to form the bottom electrode layer 221. According to some embodiments, the bottom electrode layer 221 is formed of a metal nitride such as titanium nitride (TiN) and is formed to be approximately About However, the bottom electrode layer 221 may be formed using any suitable material and any suitable thickness.

[0036] refer to Fig. 7A and Figure 7B In some embodiments, an etching process may be performed after forming the bottom electrode layer 221 to remove the undesired portion of the bottom electrode layer 221, thereby forming the bottom electrode 223 and the dummy metal plate 225 (which may also be referred to as the bottom dummy metal plate 225). For example, a photoresist layer may be deposited as a capping layer over the bottom electrode layer 221. Once deposited, the photoresist layer may be patterned to expose a portion of the bottom electrode layer 221 to be removed. The exposed portion of the bottom electrode layer 221 may be removed by a suitable etching process (e.g., in some embodiments, wet or dry etching using a second process gas including hydrofluoric acid (HF)). However, any suitable etching process may be used and any suitable etchant may be used to remove the undesired portion of the bottom electrode layer 221. Depending on the etching process used to remove the exposed portion of the bottom electrode layer 221, the photoresist layer may be consumed in its entirety, in part, or not consumed during etching. Any remaining material of the photoresist layer may be removed from the remaining portion of the bottom electrode layer 221, for example, by an ashing process. However, any suitable process may be used to remove the remaining material of the photoresist layer.

[0037] In some embodiments, the bottom electrodes 223 may be etched to each have a total length L1 between about 10 μm and about 250 μm and a total width W1 between about 10 μm and about 250 μm. Based on the functional design of each MIM device, each bottom electrode 223 will have a length L1 and a width W1. Thus, any suitable length and width may be used for each bottom electrode 223.

[0038] The dummy metal plates 225 may be etched to each have an overall length L2 between about 10 μm and about 250 μm and an overall width W2 between about 10 μm and about 250 μm. Because the dummy metal plates 225 are non-functional, the sizes of the dummy metal plates 225 may each be set to approximately the same size, except that some of the dummy metal plates 225 may be etched or positioned to avoid the keep-out zones (e.g., Fig.13A and Fig. 13B KOZ 310 or FIG. 21A to FIG. 21D KOZ 360) to avoid subsequent formation of bond pad vias (e.g. Fig. 20A and Fig. 20B The bonding pad via 380) and / or the landing pad via (eg Fig.16A and Fig. 16B Landing pad through hole 345).

[0039] The spacing S1 between each bottom electrode 223 can be between about 0.5 μm and about 2 μm. Similarly, the spacing S2 between each dummy metal plate 225 can be between about 0.5 μm and about 2 μm. The spacing S3 between the bottom electrode 223 and the nearest dummy metal plate 225 can be between about 0.5 μm and about 2 μm. In each case, the spacing S1, S2 and / or S3 should not be greater than about 2 μm. The purpose of the dummy metal plate 225 is to fill the bottom electrode layer so that the unevenness caused by the gap between the electrodes will not propagate to the bonding interface (discussed below). If the spacing S1, S2 and / or S3 is too large, such a gap may be formed.

[0040] The spacing S1 between the bottom electrodes 223 can vary based on the functional requirements of the bottom electrodes. Because the dummy metal plate 225 does not work, the spacing S2 between the dummy metal plates 225 can be regular, except that the avoidance zone described above is avoided. The density of the dummy metal plate 225 in the area in which the dummy metal plate 225 is formed can be between 70% and about 99.5%, with the remainder being composed of the spacing between the dummy metal plates 225. The density must be large enough to provide sufficient vertical filling. The spacing S2 and density of the dummy metal plates 235 and dummy metal plates 245 discussed below can be similar to the spacing S2 and density of the dummy metal plate 225.

[0041] refer to Fig. 8A and Figure 8B , the first capacitor insulator layer 230 is deposited over the bottom electrode 223 and the dummy metal plate 225. The first capacitor insulator layer 230 may be deposited as a high-K dielectric layer by one or more deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and combinations thereof. The first capacitor insulating layer 230 is formed as a capping insulating layer (e.g., a dielectric film layer) over the bottom electrode 223 and the dummy metal plate 225, such that the capping insulating layer conforms to the planar surfaces of the bottom electrode 223, the dummy metal plate 225, and the insulating layer 219. In this way, the first capacitor insulating layer 230 is formed to include a planar region disposed over the planar surfaces of the insulating layer 219, the bottom electrode 223, and the dummy metal plate 225, and is formed to include a vertical region or a corner region, wherein the first capacitor insulating layer 230 transitions from the insulating layer 219 to the bottom electrode 223 or the dummy metal plate 225, and transitions from the bottom electrode 223 or the dummy metal plate 225 to the insulating layer 219.

[0042] In some embodiments, the first capacitor insulator layer 230 is formed as a composite layer of stacked dielectric layers. For example, the first capacitor insulator layer 230 can be formed as a layered stack of ZrO2 / Al2O3 / ZrO2 (ZAZ), which includes a first zirconium oxide (ZrO2) layer, an aluminum oxide (Al2O3) layer above the first ZrO2 layer, and a second ZrO2 layer above the Al2O3 layer. The advantage of ZAZ is that the equivalent oxide thickness is low, so the capacitance value of the resulting capacitor is high. According to other embodiments of the present invention, the first capacitor insulator layer 230 is formed as a single layer of a homogeneous dielectric material such as zirconium oxide (ZrO2). It can be formed with a thickness of about About A first capacitor insulator layer 230 is provided therebetween.

[0043] In some embodiments where the bottom electrode 223 is close to another bottom electrode 223 or a dummy metal plate 225, for example, if the bottom electrode 223 is less than about 0.5 μm from the adjacent bottom electrode 223 or dummy metal plate 225, the first capacitor insulating layer 230 may have a portion with an upper surface and a lower surface, the upper surface of the portion being higher than the upper surface of the bottom electrode 223, and the lower surface of the portion being flush with the lower surface of the bottom electrode 223, such as shown at portion 230A. In other words, the thickness of the first capacitor insulating layer 230 between two bottom electrodes 223 close together, two dummy metal plates 225 close together, or one of each of the parts close together (such as at portion 230A) may be greater than the thickness of the portion of the first capacitor insulating layer 230 above the bottom electrode 223 or above the dummy metal plate 225. Similar situations may occur for each electrode layer and corresponding capacitor insulating layer.

[0044] Fig. 9A and Fig. 9B The formation of an intermediate electrode layer over the first capacitor insulator layer 230 and patterning of the intermediate electrode layer into an intermediate electrode 233 and a dummy metal plate 235 (also referred to as an intermediate dummy metal plate 235) are shown. The intermediate electrode layer may be deposited as a capping metal layer over the first capacitor insulator layer 230 using the materials and processes described above with respect to the bottom electrode layer 221. However, in particular, the intermediate electrode layer is formed to substantially conform to the first capacitor insulator layer 230. The intermediate electrode layer may be made of the same material as the bottom electrode layer 221 or a different material. In some embodiments, a thickness of about 1000 nm may be formed. About However, any suitable material and any suitable thickness may be used for the intermediate electrode layer.

[0045] Once deposited, the capping metal layer of the middle electrode layer may be etched to remove one or more portions of the capping metal layer above the first capacitor insulator layer 301, thereby forming the middle electrode 233 and the middle dummy metal plate 235. The etching may be accomplished using processes and materials such as those described above with respect to etching the bottom electrode layer 221. The middle electrode layer may be etched using the same etching technique as used to etch the bottom electrode layer 221 or a different etching technique may be used.

[0046] The length, width, and spacing of the middle electrode 233 and the middle dummy metal plate 235 may be within the same ranges as described above with respect to the bottom electrode 223 and the bottom dummy metal plate 225. However, any suitable dimensions may be used for the middle electrode 233 and the middle dummy metal plate 235.

[0047] The intermediate electrode 233 may overlap the edge of the bottom electrode 223 by a distance Ov1 between about 0.2 μm and about 1.0 μm. In addition, according to some embodiments, a first end of the first intermediate electrode 233 covers a first one of the bottom electrodes 223 and a second end of the first intermediate electrode 233 covers a second one of the bottom electrodes 223. The intermediate dummy metal plate 235 may overlap one or more bottom electrodes 233.

[0048] refer to Fig. 10A and Fig. 10B , the second capacitor insulator layer 240 is deposited over the middle electrode 233, the middle dummy metal plate 235, and the first capacitor insulator layer 230. The second capacitor insulator layer 240 may be deposited as a high-K dielectric layer using one or more deposition processes as discussed above with respect to the first capacitor insulator layer 230. As such, the second capacitor insulator layer 240 is formed to include a planar region disposed over the planar surfaces of the first capacitor insulator layer 230, the middle electrode 233, and the middle dummy metal plate 235, and is formed to include a vertical region or an angled region where the second capacitor insulator layer 240 transitions from the first capacitor insulator layer 230 to the middle electrode 233 or the middle dummy metal plate 235, and from the middle electrode 233 or the middle dummy metal plate 235 to the first capacitor insulator layer 230.

[0049] The second capacitor insulator layer 240 may be deposited using the same materials and the same processes used to deposit the first capacitor insulator layer 230. However, the materials and processes used to deposit the second capacitor insulator layer 240 may be different from the materials and processes used to deposit the first capacitor insulator layer 230.

[0050] In some embodiments, the second capacitor insulator layer 240 is formed as a composite layer of stacked dielectric layers (e.g., ZAZ). According to other embodiments of the present invention, the second capacitor insulator layer 240 is formed as a single layer of a homogeneous dielectric material (e.g., ZrO2). The second capacitor insulator layer 240 may be formed to a thickness of about About A second capacitor insulator layer 240 is provided therebetween.

[0051] Fig.11A and Fig. 11B The top electrode layer is formed over the second capacitor insulator layer 240 and patterned into a top electrode 243 and a top dummy metal plate 245 (also referred to as a top dummy metal plate 245). The top electrode layer may be deposited as a capping metal layer over the second capacitor insulator layer 240 using materials and processes as described above with respect to the bottom electrode layer 221. However, in particular, a top electrode layer is formed that substantially conforms to the second capacitor insulator layer 240. The top electrode layer may be made of the same material as the bottom electrode layer 221, the middle electrode 233, or a different material. In some embodiments, a top electrode layer having a thickness of about 1000 nm may be formed. About However, any suitable material and any suitable thickness may be used for the top electrode layer.

[0052] Once deposited, the capping metal layer of the top electrode layer may be etched to remove one or more portions of the capping metal layer above the second capacitor insulator layer 240, thereby forming a top electrode 243 and a top dummy metal plate 245. The etching may be accomplished using processes and materials such as those described above with respect to etching the bottom electrode layer 221. The top electrode layer may be etched using the same etching technique as used to etch the bottom electrode layer 221, the intermediate electrode 233, or a different etching technique may be used.

[0053] The length, width, and spacing of the top electrode 243 and the top dummy metal plate 245 may be within the same ranges as described above with respect to the bottom electrode 223 and the bottom dummy metal plate 225. However, any suitable dimensions may be used for the top electrode 243 and the top dummy metal plate 245.

[0054] The top electrode 243 may overlap an edge of the middle electrode 233 by a distance Ov2 between about 0.2 μm and about 1.0 μm. In addition, according to some embodiments, a first end of the first top electrode 243 covers the middle electrode 233, and a second end of the first top electrode 243 covers the second middle electrode 233. The top dummy metal plate 245 may overlap one or more middle electrodes 233 and / or the bottom electrode 223.

[0055] like Fig.11AAs shown in , the bottom electrode 223, the middle electrode 233 and the top electrode 243 are arranged in a stack, wherein the first capacitor insulating layer 230 and the second capacitor insulating layer 240 separate the middle electrode 233 from each bottom electrode 223 and the top electrode 243. The stack of electrode layers separated by the insulating layer is arranged to form a super high density metal-insulator-metal (SHDMIM) capacitor 250 above the top metal line 134A of the interconnect structure 130. Each electrode layer is vertically filled by the dummy metal plates 225, 235 and 245. Therefore, when no dummy metal plates 225, 235 and 245 will appear, the subsequently deposited insulating layer can have a substantially flat upper surface, rather than a stepped, layered or wavy upper surface. It should be understood that any number of SHDMIM capacitors 250 can be formed.

[0056] The total thickness of the SHDMIM capacitor layer 248 as measured from the uppermost surface of the top electrode 243 to the bottom surface of the bottom electrode 223 may be about 1000 Å. About In the absence of dummy metal plates 225, 235, and 245, the thickness of the area without electrodes from the SHDMIM capacitor 250 will be between and In embodiments where the first capacitor insulating layer 230 and the second capacitor insulating layer 240 do not extend across the insulating layer 219, the thickness in such a region will be In the embodiment where the first capacitor insulating layer 230 and the second capacitor insulating layer 240 extend across the insulating layer 219, the thickness in this region will be approximately The thickness can fluctuate across the insulating layer 219. This variation can propagate to the upper surface of the capping insulating layer 260 (see Fig. 12A ), thereby causing a stepped vertical gap in the upper surface. However, due to the inclusion of dummy metal plates such as dummy metal plates 225, 235, and 245, the total thickness of the SHDMIM capacitor layer 248 is relatively uniform.

[0057] See also Fig. 12A and Fig. 12B A capping insulating layer 260 is formed over the top electrode 243, the top dummy metal plate 245, and the exposed portion of the second capacitor insulating layer 240. According to some embodiments, the capping insulating layer 260 is formed over these layers as a plasma enhanced oxide undoped silicon glass (PEOX-USG) having a thickness of about 100 Å. About The capping insulating layer 260 may be formed as a capping layer using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc., which is over the top electrode 243, the top dummy metal plate 245, and the exposed portion of the second capacitor insulating layer 240. However, the capping insulating layer 260 may be formed using any suitable material, any suitable thickness, and any suitable method.

[0058] As such, the insulating layer 219 and the capping insulating layer 260, along with the SHDMIM capacitor 250 and the various layers of dummy metal plates 225, 235, and 245, collectively form the passivation structure 200 having an integrated SHDMIM capacitor device and dummy metal plates formed therein.

[0059] Next, in Fig.13A and Fig. 13B In the embodiment of the present invention, a via opening 305 may be formed in the capping insulating layer 260 and through the top electrode 243, the second capacitor insulating layer 240, the middle electrode 233, the first capacitor insulating layer 230, the bottom electrode 223, the insulating layer 219, and the etch stop layer 138 (if used). One or more photolithography processes (e.g., a damascene process or a dual damascene process) are performed to form the via opening 305, thereby exposing the contact area of ​​the top metal line 134A of the interconnect structure 130. However, any number and any suitable photolithography processes may be used to form the via opening.

[0060] In some embodiments, the via opening 305 may be formed using a photolithography process using, for example, a photoresist and / or hard mask formed and patterned over the capping insulating layer 260. Anisotropic etching may be used to form these trenches through the photoresist and / or hard mask in each successive layer using an appropriate etchant until the top metal line 134A is exposed in the via opening 305. In some embodiments, after forming the via opening 305 as shown in FIG. Fig.13A When the particular opening 305 is shown, one or more of the top electrode 243, the middle electrode 233, and the bottom electrode 223 may not be etched. The positions of the via opening 305 and the dummy metal plates 225, 235, and 245 are such that the via opening 305 is not etched through the dummy metal plates 225, 235, and 245. A first keep out zone (KOZ) 310 may be established to keep the dummy metal plates 225, 235, and 245 away from the via opening 305. The KOZ 310 may be circular or square (or any suitable shape) and establishes a minimum distance d between the via opening 305 and the nearest dummy metal plate 225, 235, and 245. l The distance d1 may be between 0.5 μm and about 5 μm. The dummy metal plates 225 , 235 , and 245 are disposed outside the KOZ 310 .

[0061] exist Fig.14A and Fig. 14B In the embodiment, a plug diffusion barrier layer 315 is formed above the passivation structure 200, which conforms to the flat surface of the capping insulating layer 260 and is opposite to the sidewalls of the through-hole opening 305 and conforms to the exposed contact area of ​​the top metal line 134A. Due to the dummy metal plates 225, 235 and 245, the upper surface of the plug diffusion barrier layer 315 is substantially flat, rather than stepped, wavy or layered. In some embodiments, the plug diffusion barrier layer 315 is formed of one or more layers of conductive materials, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. In some embodiments, the plug diffusion barrier layer 315 is formed of a thin layer of tantalum nitride (TaN) deposited by chemical vapor deposition technology. According to some embodiments, a thickness of about 100 Å can be formed. About However, any suitable material, any suitable deposition method, and any suitable thickness may be used for the plug diffusion barrier layer 315 .

[0062] Fig.15A and FIG. 15B to FIG. 16A and Fig. 16B The conductive plug 340 and the conductive platform 345 ( Fig.16A and Fig. 16B ) is formed. Fig.15A and Fig. 15B In the embodiment, once the plurality of via openings 305 have been formed, a photoresist 330 is applied over the plug diffusion barrier layer 315. After the photoresist is applied, the photoresist 330 can be patterned and developed to form openings 335 of various shapes according to the upper portions of the conductive plugs 340 and the conductive platforms 345. Fig. 15B As shown, the shape can be a line, square, circle, ellipse, rounded rectangle, etc. Fig. 15B The view of the plug diffusion barrier layer 315 is omitted in order to show the details below the plug diffusion barrier layer 315 .

[0063] exist Fig.16A and Fig. 16B In the embodiment, the via opening 305 and the opening 335 can be filled with the conductive filling material to a certain thickness by, for example, performing a deposition process, so that the conductive filling material fills the via opening 305 and overfills the via opening 305, so that the conductive layer of the conductive filler extends over the via opening 305 and fills at least a portion of the opening 335 above the plug diffusion barrier layer 315, so that the conductive layer of the conductive filler extends over the via opening 305 and fills at least a portion of the opening 335 above the plug diffusion barrier layer 315, thereby Fig.14A and Fig. 14B ) to form a conductive plug 340 (in Fig. 16B) and at the opening 335 ( Fig.15A and Fig. 15B ) forms a conductive platform 345 within the passivation structure 200 and extends above the passivation structure 200 and extends horizontally above the upper surface of the passivation structure 200. The conductive fill material includes a metal, an elemental metal, a transition metal, etc. In some embodiments, the conductive fill material includes one or more of copper, aluminum, tungsten, cobalt, or an alloy thereof (e.g., aluminum-copper alloy (AlCu)). The conductive fill material can be formed using a selective plating technique such as chemical plating. In some embodiments, the conductive fill material can be formed by depositing a seed layer (not shown) and performing an electrochemical plating process. However, any suitable material and any suitable technique can be used for the conductive fill material.

[0064] In some embodiments, once deposited, the conductive fill material may be subjected to a planarization process such as a chemical mechanical process (CMP) to planarize the surface and remove excess deposits of the conductive fill material used to form the conductive platform 345. Some embodiments may omit the planarization process because the dummy metal plates 225, 235, and 245 create a substantially horizontal upper surface of the passivation structure 200, which creates a substantially horizontal upper surface of the conductive platform 345. In an embodiment, the thickness of the conductive platform 345 is about About However, any suitable thickness may be used. In an embodiment, the thickness of the conductive plug 340 passing through the passivation structure 200 is between about About However, any suitable thickness may be used and will depend on the thickness of the passivation structure 200 .

[0065] Fig.16A and Fig. 16B It is also shown that the photoresist 330 can be removed and an etching process can be performed to remove the undesired portion of the plug diffusion barrier layer 315 exposed from the conductive platform 345. Therefore, a conductive plug 340 is formed through the passivation structure 200, and a conductive platform 345 is formed over the passivation structure 200 continuous with the conductive plug 340. The conductive plug 340 and the conductive platform 345 extend through the passivation structure 200 including the SHDMIM capacitor 250 and are electrically coupled to the top metal line 134A. As such, the conductive platform 345 forms a contact for an electrode of the SHDMIM capacitor 250.

[0066] In some embodiments, the conductive platform 345 can be directly probed to perform a chip probe (CP) test on the wafer 100. Optionally, a solder area (e.g., a solder ball or solder bump) can be set on the conductive platform 345, and the solder area can be used to perform a CP test on the wafer 100. The CP test can be performed on the wafer 100 to determine whether each device die 105 of the wafer 100 is a known good die (KGD). Therefore, only the device die 105 that is a KGD is subjected to subsequent processing for packaging, and the die that fails the CP test is not packaged. After the test, the solder area (if any) can be removed in a subsequent processing step.

[0067] exist Fig.17A and Fig. 17B , a second passivation structure 350 may then be formed over the passivation structure 200 and the conductive platform 345. The second passivation structure 350 may be deposited as a capping layer over the top of the conductive platform 345 and over the exposed portion of the capping insulating layer 260 of the passivation structure 200. According to some embodiments, the material of the second passivation structure 350 may include plasma enhanced oxide undoped silicon glass (PEOX-USG), an oxide (such as silicon oxide), a nitride (such as silicon nitride), a carbide, an oxycarbide, etc., or a combination thereof, with a thickness of about 1000 Å. About Between. The second passivation structure 350 can be formed as a capping layer using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc. In some embodiments, the second passivation structure 350 can be made of multiple layers of the same or different materials. In some embodiments, a planarization process (e.g., CMP) can be used to planarize the surface of the second passivation structure 350. In some embodiments, since the pseudo metal plates 225, 235 and 245 provide a more horizontal conductive platform 345, and therefore provide a more horizontal upper surface of the second passivation structure 350, the planarization process can be omitted or the planarization time can be reduced. However, the second passivation structure 350 can be formed using any suitable material, any suitable thickness, and any suitable method.

[0068] exist Fig.18A and Fig.18B, a contact opening 355 is formed through the second passivation structure 350 and the passivation structure 200 to expose a portion of the top metal line 134A for the subsequently formed bonding pad via 375. The contact opening 355 may be formed using any suitable photolithographic mask and etching process. For example, the passivation structure 200 and the second passivation structure 350 may be patterned using any suitable photolithographic process. In an embodiment, a photoresist layer may be deposited as a capping layer over the second passivation structure 350 and patterned to expose the area of ​​the second passivation structure 350 where the contact opening 355 is to be formed. The exposed area of ​​the second passivation structure 350 is subjected to an etching process [for example, in some embodiments, a wet or dry etching using a suitable etchant (such as using gaseous phosphoric acid (H3PO4), chlorine (Cl2) (or a compound of chlorine))] to remove the material of the second passivation structure 350 so that the area of ​​the passivation structure 200 is exposed through the contact opening 355 in the second passivation structure 350.

[0069] Once the area of ​​the passivation structure 200 is exposed through the contact opening 355, the exposed area of ​​the passivation structure 200 is subjected to an etching process (e.g., plasma enhanced etching using a suitable etchant including the above-mentioned gases and / or tetrafluoromethane (CF4)) until a portion of the top metal line 134A of the interconnect structure 130 is exposed through the contact opening 355. This includes etching the first capacitor insulating layer 230 and the second capacitor insulating layer 240. In some embodiments, the etching may include etching through one or more of the bottom electrode 223, the middle electrode 233, and / or the top electrode 243, for example, to expose them for connection with them in the contact opening 355 through a subsequently formed bonding pad via 375. However, due to a keep out zone (KOZ) 360 disposed around the contact opening 355, the etching does not include etching the dummy metal plates 225, 235, or 245. The dummy metal plates 225, 235, and 245 are disposed outside the KOZ 360.

[0070] like Fig.18B As shown, KOZ 360 can be any suitable shape, such as a square or a circle. KOZ 360 establishes a minimum distance d2 between contact opening 355 and the nearest dummy metal plate 225, 235, and 245. Distance d2 can be between 0.5 μm and about 5 μm. Dummy metal plates 225, 235, and 245 are disposed outside KOZ 360.

[0071] During etching of the second passivation structure 350 and the passivation structure 200, the photoresist layer is consumed completely, consumed partially, or not consumed, and any remaining photoresist material can be removed, for example, by an ashing process. However, any suitable material, any suitable deposition, and any suitable removal process can be used for the photoresist, and any suitable etching process can be used to form the contact opening 355.

[0072] exist Fig.19A and Fig.19B In the embodiment, the bonding pad opening 365 can be formed in the upper portion of the second passivation structure 350. The bonding pad opening 365 can be formed using any suitable photolithography mask and etching process. In an embodiment, a photoresist layer can be deposited as a capping layer over the second passivation structure 350 and patterned to expose the area of ​​the second passivation structure 350 where the bonding pad opening 365 is to be formed. The exposed area of ​​the second passivation structure 350 is subjected to an etching process (for example, in some embodiments, wet or dry etching using a suitable etchant) to remove the material of the second passivation structure 350. In some embodiments, the etching process can stop on an etch stop layer disposed below the bonding pad layer of the second passivation structure 350. In other embodiments, the etching process can be a time-based etching process. As in Fig.19A As noted in , a bonding pad opening 365 may be formed around an upper portion of the contact opening 355 .

[0073] exist Fig. 20A and Fig. 20B In the embodiment, a bonding pad via 375 and a bonding pad 380 may be formed. First, a diffusion barrier layer 370 may be formed. Fig.14A and Fig. 14B The diffusion barrier layer 370 is formed by similar processes and materials as those discussed above for the plug diffusion barrier layer 315 of the second passivation structure 350. Next, the bonding pad via 375 and the bonding pad 380 can be formed by filling the contact opening 355 and the bonding pad opening 365 with a conductive filler. The conductive filler may include any suitable material, such as a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. In some embodiments, the conductive filler includes copper or a copper alloy. The conductive filler may be deposited using any suitable process, such as by electroplating or chemical plating techniques, or by using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), etc. In some embodiments, the conductive filler may be deposited above the surface of the second passivation structure 350. The conductive filler material may be subjected to a planarization process such as chemical mechanical polishing (CMP) to planarize the surface and remove excess deposits of the conductive filler material used to form the bonding pad 380.

[0074] Although the bonding pad via 375 and the bonding pad 380 are described and shown as being formed in the same process, in some embodiments, the bonding pad via 375 may be completely formed first, and then the bonding pad 380 may be formed in a separate process. In such embodiments, a separate dielectric layer may be formed as an upper layer of the second passivation structure 350, and the bonding pad opening 365 may be formed in the separate dielectric layer and then filled in a separate process to form the bonding pad 380.

[0075] Fig.21A and Fig.21B A portion of a horizontal cross-section of a second capacitor insulating layer 240 is shown in accordance with some embodiments. Fig.21A and Fig.21B The structure shown in Fig. 20A The structure of the line BB in FIG. 2 shows the second capacitor insulating layer 240 and the middle dummy metal plate 235 . Fig.21A and Fig.21B A KOZ 310 or a KOZ 360 is shown in each case. Fig.21A It is shown that KOZ 310 or KOZ 360 may be rectangular. Fig.21B It is shown that the KOZ 310 or KOZ 360 may be circular. The shape of the KOZ 310 or KOZ 360 may be any suitable shape, such as a polygon having three to twelve sides, etc., and the lengths of the sides may be equal or unequal. The KOZ 310 or KOZ 360 ensures that the dummy metal plates 225, 235, and 245 do not interfere with the conductive plugs 340 or the bond pad vias 375. The dummy metal plates 225, 235, and 245 that are very close to (i.e., adjacent to) the KOZ 310 or KOZ 360 may change position and size to maintain the KOZ 310 or KOZ 360. Therefore, in an otherwise regular pattern of dummy metal plates 225, 235, or 245, the dummy metal plates 225, 235, or 245 that are close to the KOZ 310 or KOZ 360 may disrupt the pattern and / or size to maintain a distance from the KOZ 310 or KOZ 360.

[0076] In some embodiments, the pattern and size of the dummy metal plates 225, 235, and 245 in each layer may be the same, wherein each of the dummy metal plates 225, 235, and 245 is stacked on top of each other. In other embodiments, the pattern and / or size of the dummy metal plates 225, 235, and 245 may be different in each layer, and overlap between each layer may be achieved (e.g., such as Fig. 9A and Fig.11A OV1 and / or OV2 in the .

[0077] Fig. 21C and Fig.21D and Fig.21Aand Fig.21B Similarly, but illustrating that the dummy metal plate 235 (or 225 or 245 ) may be patterned to include cutouts that may accommodate the KOZ 310 or KOZ 360 . Fig. 21C It is shown that the cutouts may be such that a single one of the dummy metal plates 225 , 235 , or 245 surrounds the conductive plug 340 or the bond pad via 375 outside the KOZ 310 or KOZ 360 . Fig.21D It is shown that the cutouts may allow a single one of the dummy metal plates 225 , 235 , or 245 to partially surround the conductive plug 340 or the bond pad via 375 outside the KOZ 310 or KOZ 360 on two sides or on three sides.

[0078] Figure 22 to Figure 24 Different configurations of bond pad vias 375 , conductive plugs 340 , and conductive platforms 345 are shown in accordance with some embodiments. Fig. 22 An embodiment is shown in which a bond pad via 375 traverses the second passivation structure 350 and lands on the conductive platform 345. In such an embodiment, the KOZ 360 may be omitted for the bond pad via 375. Fig. 22 It is also shown that in all embodiments where the bonding pad via 375 can land on the conductive platform 345, the bonding pad via 375 can land on the conductive platform 345 at a position that coincides with a recess in the upper surface of the conductive platform 345, where the bottom of the bonding pad via 375 matches the recess.

[0079] Fig.23 An embodiment is shown where the bond pad via 375 can land on both the conductive platform 345 and the top metal line 134A. For the bond pad via 375 landing on the conductive platform 345, the KOZ 360 can be omitted, while for the bond pad via 375 landing on the top metal line 134A, the KOZ 360 can be retained.

[0080] Fig.24 Embodiments are shown in which the bond pad via 375 may contact the bottom electrode 223 , the middle electrode 233 , and / or the top electrode 243 to form a SHDMIM capacitor, such as the SHDMIM capacitor 270 . Fig.24 Also shown is an embodiment where the conductive plug 340 utilizes the KOZ 310 to ensure that the dummy metal plates 225 , 235 , and 245 do not interfere with the conductive plug 340 as it passes through the layers of the dummy metal plates 225 , 235 , and 245 .

[0081] Fig.25The formation of a wafer 400 including a device die 405 is shown. According to some embodiments of the present invention, the device die 405 is a logic die, which may be a CPU die, an MCU die, an IO die, a baseband die, or an AP die. The device die 405 may also be a memory die. The wafer 400 includes a semiconductor substrate 420, which may be a silicon substrate.

[0082] The device die 405 may include an integrated circuit device 422, an ILD 424 located over the integrated circuit device 422, and a contact plug 428 for electrically connecting to the integrated circuit device 422. The device die 405 may also include an interconnect structure 430 for connecting to active devices and passive devices in the device die 405. The interconnect structure 430 includes metal lines 434 and vias 436.

[0083] Through silicon vias (TSVs) 416 (sometimes referred to as semiconductor through vias or vias) are formed to penetrate into semiconductor substrate 420 (and ultimately pass through semiconductor substrate 420 by emerging from the opposite side). TSVs 416 are used to connect devices and metal lines formed on the front side (top side shown) of semiconductor substrate 420 to the back side. TSVs 416 may be formed using processes and materials similar to those used to form bonding pads 380 and / or bonding pad vias 375, as described above and not repeated, including, for example, a time-based etching process such that TSVs 416 may have a bottom disposed between the top and bottom surfaces of semiconductor substrate 420 and may be surrounded by a diffusion barrier layer.

[0084] Device die 405 may include a first passivation structure 500 and a second passivation structure 650 having an integrated SHDMIM device. For simplicity, the integrated SHDMIM device is not shown. Conductive plugs 640 and conductive platforms 645 may be formed and disposed in the first passivation structure 500 and the second passivation structure 650. Bonding pads 680 and bonding pad vias 675 are also formed and disposed in the first passivation structure 500 and the second passivation structure 650.

[0085] The processes and materials used to form the various components of device die 405 may be similar to the processes and materials used to form their corresponding components in device die 105 , and therefore the details are not repeated herein. Wafer 400 is singulated into a plurality of discrete device dies 405 .

[0086] exist Fig.26 , device die 405 is bonded to device die 105 . Fig.26The bonding of device die 405 to device die 105 is shown. In the embodiment shown, each device die 105 is still within wafer 100. In some embodiments, each KGD device die 105 can be cut out of wafer 100 and attached, for example, to a carrier substrate for further processing. Each device die 405 bonded to device die 105 has been tested and determined to be KGD before bonding to device die 105.

[0087] Although one device die 405 is shown as being bonded to device die 105, it should be understood that other device dies may also be bonded to device die 105, such as device die 405. Other device dies may be the same as device die 405 or may be different from device die 405. In addition, different technologies such as 45nm technology, 28nm technology, 20nm technology, etc. may be used to form device die 405 and other device dies. Moreover, device die 405 may be a digital circuit die, while other device dies may be analog circuit dies. The combined device dies 105 and 405 (and other device dies, if any) are used as a system. Separating the functions and circuits of the system into different dies (such as device dies 105 and 405) can optimize the formation of these dies and can reduce manufacturing costs.

[0088] The device die 405 is placed on the wafer 100, for example, by a pick-and-place process. The bonding of the device die 405 to the device die 105 can be achieved by composite bonding. For example, the bonding pad 680 is bonded to the bonding pad 380 by metal-to-metal direct bonding. According to some embodiments of the present invention, the metal-to-metal direct bonding is copper-to-copper direct bonding. The size of the bonding pad 680 can be greater than, equal to, or less than the size of the corresponding bonding pad 380. In addition, the dielectric material of the second passivation structure 650 and the dielectric material of the second passivation structure 350 are bonded together in a dielectric-to-dielectric bonding manner, which dielectric-to-dielectric bonding can be, for example, a fusion bond performed by a generated Si-O-Si bond. The gap 702 is retained around the device die 405.

[0089] To achieve composite bonding, device die 405 is positioned relative to device die 105 to align their respective bonding pads 680 and bonding pads 380, and device dies 105 and 405 are pressed together. Subsequently, annealing is performed to allow the metals in bonding pad 380 and corresponding overlying bonding pad 680 to diffuse into each other. According to some embodiments, the annealing temperature may be higher than about 350°C, and may be in a range between about 350°C and about 550°C. According to some embodiments, the annealing time may be in a range between about 1.5 hours and about 3.0 hours, and may be in a range between about 1.0 hours and about 2.5 hours. Through composite bonding, bonding pad 680 is bonded to corresponding bonding pad 380 through direct metal bonding caused by metal interdiffusion. Similarly, second passivation structure 650 is melt-bonded to corresponding second passivation structure 350. The area where the bond pad 380 / 680 of one device die 105 / 405 contacts the second passivation structure 650 / 350 of the opposing device die 405 / 105 is not bonded.

[0090] In the absence of dummy metal plates 225, 235 and 245, the upper surface of the second passivation structure 350 and / or the second passivation structure 650 may not be flat enough to achieve good bonding. In other words, gaps may appear between the bonding pads 380 / 680, resulting in device failure or weak bonding, which leads to premature device failure. Similarly, gaps may also appear between the second passivation structures 350 / 650, resulting in a weakened die-to-die bond, which may eventually fail due to warping or other factors. These gaps may appear due to the slight differences that exist without dummy metal plates 225, 235 and 245. These differences will propagate to the upper surface, because the flattening process (such as CMP process) used may not be able to effectively eliminate these differences. However, dummy metal plates 225, 235 and 245 provide vertical filling, which results in a more effective flattening process and a flatter upper surface of the device die 105 (and / or device die 405).

[0091] Fig. 27 The formation of gap filler 764, redistribution layer 772, and contact structure including electrical connector 792 formed over bonded device die 105 and device die 405 are shown in accordance with some embodiments. The views of device die 105 and device die 405 have been simplified.

[0092] The gap filler 764 may include an underlying etch stop layer 760 and a dielectric fill layer 762. The etch stop layer 760 is formed of a dielectric material having good adhesion to the sidewalls of the device die 405 and the top surface of the device die 105. According to some embodiments of the present invention, the etch stop layer 760 is formed of a nitride-containing material such as silicon nitride. The etch stop layer 760 may be a conformal layer, for example, the thickness of the horizontal portion and the thickness of the vertical portion are substantially equal to each other, for example, the absolute value of the difference is less than about 20% or less than about 10% of the two thicknesses. The deposition may include a conformal deposition method such as atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0093] The dielectric filling layer 762 is formed of a material different from that of the etch stop layer 760. According to some embodiments of the present invention, the dielectric filling layer 762 is formed of silicon oxide, which may be silicon oxide formed by TEOS, and other dielectric materials such as silicon carbide, silicon oxynitride, silicon oxycarbonitride, PSG, BSG, BPSG, etc. may also be used. The dielectric layer 162 may be formed using CVD, high density plasma chemical vapor deposition (HDPCVD), flowable CVD, spin coating, etc. The dielectric layer 762 completely fills the remaining gap 702 ( Fig.26 ). A dielectric fill layer 762 may cover over the top surface of the device die 405 .

[0094] After forming the dielectric filling layer 762, a planarization process such as a CMP process or a mechanical grinding process may be used to remove excess portions of the gap filler 764, thereby exposing the device die 405. In addition, the TSV 416 (see also FIG. Fig.25 ).

[0095] Next, an opening may be formed in the gap filler 764 to form an optional via through the gap filler 764. According to some embodiments, a photoresist (not shown) is formed and patterned, and the gap filler 764 is etched using the patterned photoresist as an etching mask. An opening is formed and extends downward to an etch stop layer 760 that serves as an etch stop layer. The etching may be performed using any suitable process, such as by dry etching using a mixture of NF3 and NH3 or a mixture of HF and NH3. Next, the etch stop layer 760 is etched so that the opening extends downward to the bonding pad 380 of the device die 105. The etching may be performed using any suitable process, such as by dry etching using a mixture of CF4, O2, and N2; a mixture of NF3 and O2; SF6; or a mixture of SF6 and O2.

[0096] A through hole 770 is formed in the opening and connected to the bonding pad 380. According to some embodiments of the present invention, the formation of the through hole 770 includes performing a plating process such as an electrochemical plating process or an electroless plating process. The through hole 770 may include a metal material such as tungsten, aluminum, copper, etc. A conductive barrier layer (such as titanium, titanium nitride, tantalum, tantalum nitride, etc.) may also be formed under the metal material. A planarization such as CMP is performed to remove excess portions of the plated metal material, and the remaining portion of the metal material forms the through hole 770. The through hole 770 may have substantially straight and vertical sidewalls. Moreover, the through hole 770 may have a tapered profile with a top width slightly greater than a corresponding bottom width.

[0097] In some embodiments, via 770 may be formed through a portion of device die 405 using similar processes and materials as via 770. For example, device die 405 may be etched to form additional openings (e.g., occupied by TSV 416 as shown) before or after forming the openings for via 770. The additional openings in device die 405 and the openings for via 770 may be filled simultaneously to form TSV 416 and via 770. The upper portion of the resulting TSV 416 may be wider than the corresponding lower portion, which is consistent with the embodiment of the present invention. Fig. 27 The opposite of what is shown.

[0098] Redistribution lines (RDL) 772 and dielectric layer 774 are formed by a redistribution structure. According to some embodiments of the present invention, dielectric layer 774 is formed of an oxide such as silicon oxide, a nitride such as silicon nitride, etc. RDL 772 may be formed using a damascene process, which includes etching dielectric layer 774 to form an opening, depositing a conductive barrier layer into the opening, plating a metal material such as copper or a copper alloy, and performing planarization to remove excess portions of the metal material.

[0099] Fig. 27 Also shown is the formation of a passivation layer, a metal pad, and an overlying dielectric layer. A passivation layer 776 is formed over dielectric layer 774, and a via 778 is formed in passivation layer 776 to electrically connect to RDL 772. A metal pad 780 is formed over passivation layer 776 and electrically coupled to RDL 772 and via 778. Metal pad 780 may be an aluminum pad or an aluminum-copper pad, and other metal materials may be used.

[0100] Likewise Fig. 27As shown, a passivation layer 782 is formed over the passivation layer 776. Each of the passivation layers 776 and 782 may be a single layer or a composite layer and may be formed of a non-porous material. According to some embodiments of the present invention, one or both of the passivation layers 776 and 782 is a composite layer including a silicon oxide layer (not shown separately) and a silicon nitride layer (not shown separately) over the silicon oxide layer. The passivation layers 776 and 782 may also be formed of other non-porous dielectric materials, such as undoped silicate glass (USG), silicon oxynitride, and the like.

[0101] Next, passivation layer 782 is patterned so that some portions of passivation layer 782 cover edge portions of metal pad 780 and some portions of metal pad 780 are exposed through openings in passivation layer 782. Polymer layer 784 is then formed and then patterned to expose metal pad 780. Polymer layer 784 may be formed of polyimide, polybenzoxazole (PBO), or the like.

[0102] Next, a post-passivation interconnect (PPI) 786 is formed, which may include forming a metal seed layer and a patterned mask layer (not shown) above the metal seed layer, and plating the PPI 786 in the patterned mask layer. The patterned mask layer and the portion of the metal seed layer overlapping the patterned mask layer are then removed in an etching process. A polymer layer 788 is then formed, which may be formed of PBO, polyimide, etc.

[0103] Next, an under-bump metallization layer (UBM) 790 is formed, and the UBM 790 extends into the polymer layer 788 to connect to the PPI 786. Each UBM 790 may include a barrier layer (not shown) and a seed layer (not shown) above the barrier layer. The barrier layer may be a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or a layer formed by a titanium alloy or a tantalum alloy. The material of the seed layer may include copper or a copper alloy. Other metals such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium, chromium alloys, and combinations thereof may also be included in the UBM 790. The formation process for forming the UBM 790 and the electrical connector 792 includes: depositing a covering UBM layer, forming a mask (which may be a photoresist, not shown) and patterning it, wherein the portion covering the UBM layer is exposed through an opening in the mask. The exposed portion may then be removed by an etching process. The mask may then be removed to expose the UBM 790.

[0104] After forming the UBM 790, an electrical connector 792 is formed. The package may be placed in a plating solution (not shown), and a plating step may be performed to form the electrical connector 792 on the UBM 790. According to some embodiments of the present invention, the electrical connector 792 may include a non-solder portion (not shown) that is not melted in a subsequent reflow process. The non-solder portion may be formed of copper, and is therefore referred to as a copper bump hereinafter, although the non-solder portion may be formed of other non-solder materials. Each electrical connector 792 may also include a protective layer selected from a nickel layer, a nickel alloy, a palladium layer, a gold layer, a silver layer, or a multilayer thereof. The protective layer is formed over the copper bump. The protective layer of the electrical connector 792 may include a solder, which may be formed of a Sn-Ag alloy, a Sn-Cu alloy, a Sn-Ag-Cu alloy, etc., and may be lead-free or lead-containing.

[0105] Fig. 27 A singulation process is also shown, for example using die sawing 710 , although another suitable process may be used. The resulting structure is a packaged device 700 .

[0106] Embodiments advantageously incorporate pseudo metal plates to fill the integrated SHDMIM capacitor device layer so that the device layer has a more consistent vertical footprint (i.e., thickness). The pseudo metal plate provides a fill that propagates upward to the bonding layer for composite bonding. Therefore, the bonding layer is flatter than the bonding layer without the pseudo metal plate. Therefore, the gap in the bonding interface can be reduced or eliminated. Embodiments also provide avoidance zones around conductive plugs and vias that traverse the integrated device layer but are not connected to any integrated SHDMIM capacitor. The avoidance zone ensures that the pseudo metal plate is electrically floating and does not inadvertently change the device layer characteristics of the integrated SHDMIM capacitor.

[0107] One embodiment is a method including depositing a first insulating layer over a semiconductor substrate. The method also includes depositing a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. The method also includes depositing a second insulating layer over the series of conductive layers and the dielectric layer. The method also includes forming a first set of contact plugs through the series of conductive layers, each of the first set of contact plugs contacting one or more conductive layers in a first portion of the series of conductive layers. The method also includes forming a second set of contact plugs through the series of dielectric layers, each of the second set of contact plugs avoiding contacting a second portion of the series of conductive layers, the second portion of the series of conductive layers being electrically floating.

[0108] In an embodiment, the density of the pseudo metal plate is between 70% and 99.5%. In an embodiment, forming a second group of contact plugs may further include: etching a contact opening through the second insulating layer to expose a first dielectric layer in a series of dielectric layers; extending and continuously etching the contact opening through the series of dielectric layers; extending the contact opening through the first insulating layer by etching to expose interconnected contact elements; and depositing a conductive filling material over the contact opening and filling the contact opening. In an embodiment, the method may include: depositing a passivation structure over the first group of contact plugs and over the second group of contact plugs; and forming a first group of bonding pad vias through the passivation structure. In an embodiment, the first group of bonding pad vias extend through the passivation structure and are electrically coupled to the contact plugs. In an embodiment, forming a first group of bonding pad vias may include: forming a contact opening through the passivation structure to expose a conductive platform; and depositing a conductive filling material in the contact opening, the conductive filling material being physically coupled to the conductive platform. In an embodiment, forming a first group of bonding pad vias may also include: forming a contact opening in the passivation structure to expose a second insulating layer; extending the opening through the second insulating layer; extending the opening through a series of dielectric layers; extending the opening through the first insulating layer, the contact opening exposing interconnected conductive elements; and depositing a conductive fill material over the contact opening and filling the contact opening, the conductive fill material being electrically coupled to the interconnected conductive elements.

[0109] One embodiment is a package including a first die, wherein the first die may include an integrated device structure disposed above an interconnect structure. The integrated device structure may include: a first capacitor electrode formed on a first layer of the integrated device structure; a second capacitor electrode formed on a second layer of the integrated device structure; a first capacitor insulator layer interposed between the first capacitor electrode and the second capacitor electrode; and a first dummy metal plate formed on the first layer of the integrated device structure and a second dummy metal plate formed on the second layer of the integrated device structure, wherein the first dummy metal plate and the second dummy metal plate are electrically floating from the first capacitor electrode and the second capacitor electrode. The package also includes a second die, a connector of the second die contacting a connector of the first die.

[0110] In an embodiment, the first pseudo metal plate is arranged in a first pattern, the second pseudo metal plate is arranged in a second pattern, and the first pattern is different from the second pattern. In an embodiment, the package may include: a first connector electrically connected to the first metal plate of the first capacitor electrode; and a second connector passing through the second metal plate in the first pseudo metal plate and electrically isolated from the second metal plate. In an embodiment, the avoidance zone does not have any of the first capacitor electrode, the second capacitor electrode, the first pseudo metal plate, and the second pseudo metal plate. In an embodiment, the package may include: a passivation structure formed above the integrated device structure; and a bonding pad disposed on the upper surface of the passivation structure. In an embodiment, the second connector physically couples the bonding pad to the interconnect structure. In an embodiment, the package may include a third connector, which physically couples the bonding pad to the platform of the second connector, and the platform of the second connector is disposed above the integrated device structure. In an embodiment, the second metal plate is disposed adjacent to at least 2 sides of the second connector.

[0111] Another embodiment is a device, including an embedded device. The device also includes an interconnect structure disposed above the embedded device. The device also includes a first passivation structure disposed above the interconnect structure. The first passivation structure may include an integrated device layer; the integrated device layer may include a first capacitor and a first pseudo-metal plate. The device also includes a second passivation structure disposed above the first passivation structure, the second passivation structure having a bonding pad disposed on an upper surface thereof. The device also includes a first connector coupled to the interconnect structure and coupled to the first capacitor. The device also includes a second connector coupled to the interconnect structure, the second connector passing through the integrated device layer and away from the first capacitor and the first pseudo-metal plate.

[0112] In an embodiment, the first dummy metal plate is electrically floated from the first capacitor. In an embodiment, the second connector is physically coupled to the first of the bonding pads and coupled to the interconnect structure. In an embodiment, the device may include a third connector that is physically coupled to the first of the bonding pads and the second connector. In an embodiment, the second connector is surrounded on three sides by the first dummy metal plate.

[0113] In some embodiments, a method includes: depositing a first insulating layer over a semiconductor substrate; depositing a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates; depositing a second insulating layer over the series of conductive layers and the dielectric layer; forming a first set of contact plugs through the series of conductive layers, each of the first set of contact plugs contacting one or more conductive layers in a first portion of the series of conductive layers; forming a second set of contact plugs through the series of dielectric layers, each of the second set of contact plugs avoiding contacting a second portion of the series of conductive layers, the second portion of the series of conductive layers being electrically floating. In some embodiments, the density of the dummy metal plates is between 70% and 99.5%. In some embodiments, forming the second set of contact plugs further includes: etching contact openings through the second insulating layer to expose a first dielectric layer in the series of dielectric layers; extending the contact openings continuously etched through the series of dielectric layers; extending the contact openings through the first insulating layer by etching to expose interconnected contact elements; and depositing a conductive fill material over the contact openings and filling the contact openings. In some embodiments, the present invention further comprises: depositing a passivation structure over the first group of contact plugs and over the second group of contact plugs; and forming a first group of bonding pad vias through the passivation structure. In some embodiments, the first group of bonding pad vias extend through the passivation structure and are electrically coupled to the contact plugs. In some embodiments, the present invention further comprises: forming a conductive platform extending horizontally along the upper surface of the second insulating layer, the conductive platform being coupled to one or more of the first group of contact plugs or one or more of the second group of contact plugs, wherein forming the first group of bonding pad vias comprises: forming a contact opening through the passivation structure to expose the conductive platform; and depositing a conductive filling material in the contact opening, the conductive filling material being physically coupled to the conductive platform. In some embodiments, forming the first group of bonding pad vias further comprises: forming a contact opening in the passivation structure to expose the second insulating layer; extending the opening through the second insulating layer; extending the opening through the series of dielectric layers; extending the opening through the first insulating layer, the contact opening exposing the conductive element of the interconnection; and depositing a conductive filling material over the contact opening and filling the contact opening, the conductive filling material being electrically coupled to the conductive element of the interconnection.

[0114] In some embodiments, a package includes: a first die, the first die including an integrated device structure disposed above an interconnect structure, the integrated device structure including: a first capacitor electrode, the first capacitor electrode formed in a first layer of the integrated device structure; a second capacitor electrode, the second capacitor electrode formed in a second layer of the integrated device structure; a first capacitor insulator layer, interposed between the first capacitor electrode and the second capacitor electrode; and a first dummy metal plate and a second dummy metal plate, the first dummy metal plate formed in the first layer of the integrated device structure, the second dummy metal plate formed in the second layer of the integrated device structure, wherein the first dummy metal plate and the second dummy metal plate are electrically floating from the first capacitor electrode and the second capacitor electrode; and a second die, a connector of the second die contacting a connector of the first die. In some embodiments, the first dummy metal plate is arranged in a first pattern, wherein the second dummy metal plate is arranged in a second pattern, and the first pattern is different from the second pattern. In some embodiments, it also includes: a first connector electrically connected to the first metal plate of the first capacitor electrode; and a second connector passing through the second metal plate in the first dummy metal plate and electrically isolated from the second metal plate. In some embodiments, it also includes an avoidance zone set around the second connector, wherein the avoidance zone does not have any of the first capacitor electrode, the second capacitor electrode, the first pseudo metal plate, and the second pseudo metal plate. In some embodiments, it also includes: a passivation structure formed above the integrated device structure; and a bonding pad disposed on the upper surface of the passivation structure. In some embodiments, the second connector physically couples the bonding pad to the interconnect structure. In some embodiments, it also includes a third connector, the third connector physically couples the bonding pad to the platform of the second connector, and the platform of the second connector is disposed above the integrated device structure. In some embodiments, the second metal plate is disposed adjacent to at least two sides of the second connector.

[0115] In some embodiments, a device includes: an embedded device; an interconnect structure disposed above the embedded device; a first passivation structure disposed above the interconnect structure, the first passivation structure including an integrated device layer, the integrated device layer including a first capacitor and a first pseudo metal plate; a second passivation structure disposed above the first passivation structure, the second passivation structure having a bonding pad disposed on its upper surface; a first connector coupled to the interconnect structure and coupled to the first capacitor; and a second connector coupled to the interconnect structure, the second connector passing through the integrated device layer and away from the first capacitor and the first pseudo metal plate. In some embodiments, the first pseudo metal plate is electrically floating from the first capacitor. In some embodiments, the second connector is physically coupled to a first bonding pad in the bonding pads and coupled to the interconnect structure. In some embodiments, a third connector is also included, the third connector being physically coupled to the first bonding pad in the bonding pads and the second connector. In some embodiments, the second connector is surrounded by the first pseudo metal plate on three sides.

[0116] The features of several embodiments are discussed above so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and without departing from the spirit and scope of the present invention, they can make various changes, substitutions and changes herein.

Claims

1. A method for forming a semiconductor device, comprising: depositing a first insulating layer over the semiconductor substrate; depositing a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates; depositing a second insulating layer over the series of conductive and dielectric layers; forming a first set of contact plugs through the series of conductive layers, each of the first set of contact plugs contacting one or more conductive layers in a first portion of the series of conductive layers; A second set of contact plugs is formed through the series of dielectric layers, each of the second set of contact plugs avoiding contact with a second portion of the series of conductive layers, the second portion of the series of conductive layers being electrically floating.

2. The method according to claim 1, wherein: The density of the pseudo metal plate is between 70% and 99.5%.

3. The method according to claim 1, wherein: Forming the second group of contact plugs further includes: etching a contact opening through the second insulating layer to expose a first dielectric layer in the series of dielectric layers; extending said contact openings continuously etched through said series of dielectric layers; extending the contact openings through the first insulating layer by etching to expose interconnected contact elements; and A conductive filling material is deposited over the contact opening and fills the contact opening.

4. The method according to claim 1, further comprising: depositing a passivation structure over the first set of contact plugs and over the second set of contact plugs; as well as A first set of bond pad vias are formed through the passivation structure.

5. The method according to claim 4, wherein: The first set of bond pad vias extend through the passivation structure and are electrically coupled to the contact plugs.

6. The method according to claim 5, further comprising: forming a conductive platform extending horizontally along an upper surface of the second insulating layer, the conductive platform being coupled to one or more of the first group of contact plugs or one or more of the second group of contact plugs, wherein forming the first group of bonding pad vias comprises: forming a contact opening through the passivation structure to expose the conductive platform; and A conductive fill material is deposited in the contact opening, the conductive fill material being physically coupled to the conductive platform.

7. The method according to claim 4, wherein: Forming the first set of bond pad vias further comprises: forming a contact opening in the passivation structure to expose the second insulating layer; extending the opening through the second insulating layer; extending the opening through the series of dielectric layers; extending the opening through the first insulating layer, the contact opening exposing interconnected conductive elements; and A conductive fill material is deposited over and fills the contact opening, the conductive fill material being electrically coupled to the conductive element of the interconnect.

8. A package comprising: A first die, the first die comprising an integrated device structure disposed above the interconnect structure, the integrated device structure comprising: a first capacitor electrode formed in a first layer of the integrated device structure; a second capacitor electrode formed in a second layer of the integrated device structure; a first capacitor insulator layer interposed between the first capacitor electrode and the second capacitor electrode; and a first dummy metal plate and a second dummy metal plate, the first dummy metal plate being formed at the first layer of the integrated device structure and the second dummy metal plate being formed at the second layer of the integrated device structure, wherein the first dummy metal plate and the second dummy metal plate are electrically floated from the first capacitor electrode and the second capacitor electrode; and A second die having a connector contacting a connector of the first die.

9. The package according to claim 8, wherein: The first dummy metal plate is arranged in a first pattern, wherein the second dummy metal plate is arranged in a second pattern, and the first pattern is different from the second pattern.

10. The package according to claim 8, further comprising: a first connector electrically connected to a first metal plate of the first capacitor electrode; as well as The second connector passes through a second metal plate in the first dummy metal plate and is electrically isolated from the second metal plate.

11. The package of claim 10, further comprising a keep-out zone disposed around the second connector, wherein: The keep-away zone is free from any of the first capacitor electrode, the second capacitor electrode, the first dummy metal plate, and the second dummy metal plate.

12. The package according to claim 10, further comprising: a passivation structure formed above the integrated device structure; as well as The bonding pad is arranged on the upper surface of the passivation structure.

13. The package according to claim 12, wherein: The second connector physically couples the bond pad to the interconnect structure. 14 . The package of claim 12 , further comprising a third connector that physically couples a bond pad to a platform of the second connector, the platform of the second connector being disposed above the integrated device structure.

15. The package according to claim 10, wherein: The second metal plate is disposed adjacent to at least two side surfaces of the second connector.

16. A semiconductor device comprising: Embedded devices; an interconnect structure disposed above the embedded device; a first passivation structure disposed above the interconnect structure, the first passivation structure comprising a first integrated device layer and a second integrated device layer, the first integrated device layer comprising a first capacitor plate and a first pseudo metal plate, the bottommost surface of the first capacitor plate being flush with the bottommost surface of the first pseudo metal plate, and the topmost surface of the first capacitor plate being flush with the topmost surface of the first pseudo metal plate, the second integrated device layer comprising a second capacitor plate and a second pseudo metal plate, the bottommost surface of the second capacitor plate being located above the topmost surface of the first capacitor plate, the bottommost surface of the second capacitor plate being flush with the bottommost surface of the second pseudo metal plate, and the topmost surface of the second capacitor plate being flush with the topmost surface of the second pseudo metal plate; a second passivation structure disposed above the first passivation structure, the second passivation structure having a bonding pad disposed on an upper surface thereof; a first connector coupled to the interconnect structure and to the first capacitor plate; as well as A second connector is coupled to the interconnect structure, the second connector passes through the first integrated device layer and the second integrated device layer and is away from the first capacitor plate and the first dummy metal plate.

17. The device according to claim 16, wherein The first dummy metal plate is electrically floating from the first capacitor plate.

18. The device according to claim 16, wherein The second connector is physically coupled to a first one of the bond pads and to the interconnect structure. 19 . The device of claim 16 , further comprising a third connector physically coupled to a first one of the bonding pads and the second connector.

20. The device according to claim 16, wherein The second connector is surrounded on three sides by the first dummy metal plate.

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