Memory device and method of operating the same

Abstract

A memory device includes a field effect transistor and a variable capacitance capacitor. The gate structure includes a gate dielectric and an intermediate electrode. The variable capacitance capacitor includes: a lower capacitor plate including the intermediate electrode; an upper capacitor plate including a control gate electrode; and a variable capacitance node dielectric, and includes an electric field programmable metal oxide material. The electric field programmable metal oxide material provides a variable effective dielectric constant, and data bits can be stored in the memory device as a dielectric state of the variable capacitance node dielectric. The variable capacitance node dielectric provides reversible electric field dependent resistivity modulation or reversible electric field dependent movement of metal atoms therein. Embodiments of the present invention also relate to methods of operating a memory device.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory devices and methods of operating the same. Background Art

[0002] The threshold voltage of a field effect transistor is affected by the capacitance of the gate electrode. If the gate voltage is higher than the threshold voltage, the field effect transistor is turned on. If the gate voltage is lower than the threshold voltage, the field effect transistor is turned off. Conventional charge trap memory devices typically include large programming / erase power (greater than 5 volts) to achieve metal oxide semiconductor field effect transistor (MOSFET) threshold voltage modulation. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a memory device including a field effect transistor and a variable capacitance capacitor is provided, wherein the field effect transistor includes: a source region, a drain region and a channel region, within a semiconductor material layer; and a gate structure, covering the channel region and including a gate dielectric and an intermediate electrode. Wherein, the variable capacitance capacitor includes: a lower capacitor plate, including an intermediate electrode; an upper capacitor plate, vertically spaced apart from the lower capacitor plate, wherein the upper capacitor plate includes a control gate electrode; and a variable capacitance node dielectric, located between the lower capacitor plate and the upper capacitor plate, and including an electric field programmable dielectric material that provides a variable effective dielectric constant, and data bits are stored in the memory device as dielectric states of the variable capacitance node dielectric.

[0004] According to one aspect of an embodiment of the present invention, a memory device including a transistor and a variable capacitance capacitor is provided, wherein the transistor includes: a source region, a drain region and a channel region, within a semiconductor material layer; and a gate structure, covering the channel region and including a gate dielectric and an intermediate electrode. Wherein, the variable capacitance capacitor includes: a lower capacitor plate, including an intermediate electrode; an upper capacitor plate, vertically spaced apart from the lower capacitor plate, wherein the upper capacitor plate includes a control gate electrode; and a variable capacitance node dielectric, located between the lower capacitor plate and the upper capacitor plate and including a metal oxide material, the metal oxide material providing a reversible electric field dependent resistivity modulation.

[0005] According to another aspect of an embodiment of the present invention, a method for operating a memory device is provided, comprising: providing a memory device comprising a field effect transistor and a variable capacitance capacitor, wherein the field effect transistor comprises a gate structure having a gate dielectric and an intermediate electrode, and the variable capacitance capacitor comprises a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate, wherein a threshold voltage of the field effect transistor when the intermediate electrode is electrically floating depends on a dielectric state of the variable capacitance node dielectric; programming the dielectric state of the variable capacitance node dielectric to a state selected from a first dielectric state and a second dielectric state, the first dielectric state providing a first capacitance for the variable capacitance capacitor, and the second dielectric state providing a second capacitance for the variable capacitance capacitor; and sensing the dielectric state of the variable capacitance node dielectric by applying a sensing gate voltage between a first threshold voltage and a second threshold voltage to the control gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a top view of a first exemplary structure after forming a shallow trench isolation structure, a gate dielectric material layer, an intermediate electrode material layer, a variable capacitance node dielectric material layer, and a control gate electrode material layer according to an embodiment of the present invention.

[0008] Figure 1B It is along Figure 1A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'.

[0009] Figure 1C It is along Figure 1A A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0010] Figure 2A is a top view of the first exemplary structure after forming a control gate electrode and a variable capacitance node dielectric in accordance with an embodiment of the present invention.

[0011] Figure 2B It is along Figure 2A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'.

[0012] Figure 2C It is along Figure 2A A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0013] Figure 3A is a top view of the first exemplary structure after forming an intermediate electrode and a gate dielectric according to an embodiment of the present invention.

[0014] Figure 3B It is along Figure 3A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'.

[0015] Figure 3C It is along Figure 3A A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0016] Figure 4A is a top view of the first exemplary structure after forming source / drain extension regions and dielectric gate spacers in accordance with an embodiment of the present invention.

[0017] Figure 4B It is along Figure 4A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'.

[0018] Figure 4C It is along Figure 4A A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0019] Figure 5A is a top view of the first exemplary structure after forming source / drain regions according to an embodiment of the present invention.

[0020] Figure 5B It is along Figure 5A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'.

[0021] Figure 5C It is along Figure 5A A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0022] Fig. 6A is a top view of the first exemplary structure after forming a contact-level dielectric layer, a contact via cavity, and a metal-semiconductor alloy region in accordance with an embodiment of the present invention.

[0023] Figure 6B It is along Fig. 6A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'.

[0024] Figure 6C It is along Fig. 6A A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0025] Fig. 7Ais a top view of the first exemplary structure after forming a contact via structure according to an embodiment of the present invention.

[0026] Figure 7B It is along Fig. 7A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'.

[0027] Figure 7C It is along Fig. 7A A vertical cross-sectional view of the first exemplary structure along a vertical plane CC'.

[0028] Fig. 8A is a top view of the second exemplary structure after forming shallow trench isolation structures, sacrificial dielectric layers, dummy gate structures, and source and drain extension regions according to an embodiment of the present invention.

[0029] Figure 8B It is along Fig. 8A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane BB'.

[0030] Figure 8C It is along Fig. 8A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0031] Fig.9A is a top view of the second exemplary structure after forming dummy spacers, deep source regions, and deep drain regions in accordance with an embodiment of the present invention.

[0032] Fig. 9B It is along Fig.9A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane BB'.

[0033] Fig. 9C It is along Fig.9A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0034] Fig. 10A is a top view of the second exemplary structure after removal of the dummy structure according to an embodiment of the present invention.

[0035] Fig. 10B It is along Fig. 10A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane BB'.

[0036] Fig. 10C It is along Fig. 10A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0037] Fig.11A is a top view of the second exemplary structure after forming a gate dielectric and an intermediate electrode according to an embodiment of the present invention.

[0038] Fig. 11B It is along Fig.11A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane BB'.

[0039] Fig. 11C It is along Fig.11A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0040] Fig. 12A is a top view of a second exemplary structure after forming a variable capacitance node dielectric and a control gate electrode in accordance with an embodiment of the present invention.

[0041] Fig. 12B It is along Fig. 12A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane BB'.

[0042] Fig. 12C It is along Fig. 12A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0043] Fig.13A is a top view of the second exemplary structure after forming a contact-level dielectric layer, a metal-semiconductor alloy region, and a contact via structure in accordance with an embodiment of the present invention.

[0044] Fig. 13B It is along Fig.13A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane BB'.

[0045] Fig. 13C It is along Fig.13A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0046] Fig.14A is a top view of the third exemplary structure after forming semiconductor fins in accordance with an embodiment of the present invention.

[0047] Fig. 14B It is along Fig.14A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane BB'.

[0048] Fig. 14C It is along Fig.14A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0049] Fig.15A is a top view of the third exemplary structure after forming a gate dielectric, an intermediate gate electrode, a source extension region, and a drain extension region in accordance with an embodiment of the present invention.

[0050] Fig. 15B It is along Fig.15A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane BB'.

[0051] Fig. 15C It is along Fig.15A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0052] Fig.16A is a top view of the third exemplary structure after forming a variable capacitance node dielectric and a control gate electrode according to an embodiment of the present invention.

[0053] Fig. 16B It is along Fig.16A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane BB'.

[0054] Fig. 16C It is along Fig.16A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0055] Fig.17A is a top view of the third exemplary structure after forming dielectric gate spacers and deep source / drain regions in accordance with an embodiment of the present invention.

[0056] Fig. 17B It is along Fig.17A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane BB'.

[0057] Fig. 17C It is along Fig.17A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0058] Fig.18A is a top view of the third exemplary structure after forming a contact-level dielectric layer, a metal-semiconductor alloy region, and a contact via structure in accordance with an embodiment of the present invention.

[0059] Fig.18B It is along Fig.18A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane BB'.

[0060] Fig.18C It is along Fig.18A A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0061] Fig.19 is a circuit diagram of a combination of a memory device and a control circuit according to an embodiment of the present invention.

[0062] Fig. 20 is during a programming operation according to an embodiment of the present invention. Fig.19A circuit diagram of the active portion of a memory device in combination with a control circuit.

[0063] Fig.21 is during an erase operation according to an embodiment of the present invention Fig.19 A circuit diagram of the active portion of a memory device in combination with a control circuit.

[0064] Fig. 22 is during a sensing operation according to an embodiment of the present invention Fig.19 A circuit diagram of the active portion of a memory device in combination with a control circuit.

[0065] Fig.23 is a flow chart illustrating steps for operating the memory device of the present invention according to an embodiment of the present invention.

[0066] Fig.24 is a flow chart showing steps for fabricating the memory device of the present invention according to an embodiment of the present invention. DETAILED DESCRIPTION

[0067] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0068] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise expressly stated, each element having the same reference numeral is assumed to have the same material composition and have a thickness within the same thickness range.

[0069] The present invention relates generally to semiconductor devices, and specifically to threshold voltage modulation memory devices using variable capacitors and methods of forming the same, and aspects of the devices and methods are described in detail herein. Conventional charge capture memories use large program / erase powers (greater than 5 volts) to achieve MOSFET threshold voltage modulation. By stacking a resistive switching oxide layer and covering the gate on the MOSFET, the variable capacitor can modulate the threshold voltage through a resistive switch. By inserting RRAM / PCRAM / MRAM as a variable capacitor on the MOSFET, the threshold voltage can be modulated through a resistive switch. In such embodiments, the power consumption of the program / erase operation can be reduced to less than 5 volts compared to other charge capture memory devices that may require up to 10 volts.

[0070] Figure 1A is a top view of a first exemplary structure after forming a shallow trench isolation structure, a gate dielectric material layer, an intermediate electrode material layer, a variable capacitance node dielectric material layer, and a control gate electrode material layer according to an embodiment of the present invention. Figure 1B It is along Figure 1A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'. Figure 1C It is along Figure 1A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. Figures 1A to 1C , shows a first exemplary structure according to an embodiment of the present invention, which includes a substrate 8 having a semiconductor material layer 10. The substrate 8 may be a bulk semiconductor substrate, wherein the semiconductor material layer 10 may extend from the front surface to the back surface, or may be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer (not shown) below the semiconductor material layer 10 and a handle substrate (not shown) below the buried insulator layer. For example, the substrate 8 may be a commercially available single crystal semiconductor substrate or a commercially available semiconductor-on-insulator substrate.

[0071] The semiconductor material layer 10 may include a single crystal semiconductor material or a polycrystalline semiconductor material. In one embodiment, the entire semiconductor material layer 10 may include a single crystal semiconductor material such as single crystal silicon. The semiconductor material of the semiconductor material layer 10 may have a doping of a first conductivity type (which may be a p-type or an n-type). The atomic concentration of the dopant of the first conductivity type in the semiconductor material layer 10 may be between 1.0×10 14 / cm 3 Up to 3.0x 10 17 / cm 3 In one embodiment, the semiconductor material layer 10 may consist essentially of silicon and a dopant of the first conductivity type.

[0072] A shallow trench isolation structure 12 may be formed in an upper portion of the semiconductor material layer 10. For example, by applying a photoresist layer above the top surface of the semiconductor material layer 10 and patterning it, and by using an anisotropic etching process to transfer the pattern in the photoresist layer to the upper portion of the semiconductor material layer 10, a shallow trench having a depth ranging from 50 nm to 500 nm penetrating the top surface of the semiconductor material layer 10 may be formed. The photoresist layer may then be removed, for example, by ashing. A dielectric material may be deposited in the shallow trench, and a planarization process such as a chemical mechanical polishing (CMP) process may be used to remove excess portions of the dielectric from above a horizontal plane including the top surface of the semiconductor material layer 10. The remaining portion of the dielectric material filling the shallow trench comprises a shallow trench isolation structure 12. The shallow trench isolation structure 12 may laterally surround the device area, at Figures 1A to 1C 1 . For example, the device region may have a periphery P that is laterally surrounded by the shallow trench isolation structure 12. In one embodiment, each device region may be laterally surrounded by the shallow trench isolation structure 12. Although a single device region is used to describe the embodiments of the present invention, it is understood that a plurality of device regions laterally surrounded by corresponding shallow trench isolation structures 12 may be formed in the first exemplary structure.

[0073] The gate dielectric material layer 50L may be formed over the top surface of the semiconductor material layer 10. The gate dielectric material layer 50L may include a semiconductor oxide material formed by oxidizing a surface portion of the semiconductor material layer 10. For example, the semiconductor material layer 10 may include silicon, and a thermal oxidation process or a plasma oxidation process may be performed to convert the surface portion of the semiconductor material layer 10 into a silicon oxide layer. Alternatively or additionally, a gate dielectric material may be deposited over the top surface of the substrate 8. The gate dielectric material may include silicon oxide and / or a dielectric metal oxide material, such as aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, hafnium zirconium oxide, hafnium tantalum oxide, and other suitable gate dielectric materials may be within the expected disclosure range. The gate dielectric material may be deposited by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. The thickness of the gate dielectric material layer 50L may be in the range of 1 nm to 10 nm, such as in the range of 2 nm to 6 nm, but smaller or larger thicknesses may also be used.

[0074] The intermediate electrode material layer 52L may be deposited above the gate dielectric material layer 50L. The intermediate electrode material layer 52L includes a conductive material that can be subsequently used to form a gate electrode. Specifically, the intermediate electrode material layer 52L includes a material that can provide a suitable threshold voltage to a subsequently formed field effect transistor. In an illustrative example, the intermediate electrode material layer 52L may include at least one conductive material, such as doped polysilicon, metal silicide, platinum, ruthenium, iridium, aluminum, molybdenum, palladium, tantalum, zirconium, titanium, rhodium, rhenium, alloys thereof, or a combination thereof. Other suitable intermediate electrode materials may be within the expected disclosure range. The intermediate electrode material layer 52L may be deposited by a conformal deposition process such as a chemical vapor deposition process and / or by a non-conformal deposition process such as a physical vapor deposition process. The thickness of the intermediate electrode material layer 52L may be in the range of 5nm to 100nm, such as in the range of 10nm to 40nm, but a smaller or larger thickness may also be used.

[0075] The variable capacitance node dielectric material layer 54L may then be deposited over the intermediate electrode material layer 52L. The variable capacitance node dielectric material layer 54L includes a dielectric material that can provide a variable effective dielectric constant based on the hysteresis effect of an external vertical electric field applied thereto. The variable capacitance node dielectric material layer 54L is then used as a node oxide for a capacitor structure to be formed subsequently. The effective dielectric constant of the variable capacitance node dielectric material layer 54L may vary by at least 5%, and preferably by at least 10%, and may vary by a percentage ranging from 10% to 100% relative to a minimum value, but a larger percentage variation may also be used.

[0076] In one embodiment, the variable capacitance node dielectric material layer 54L may include or consist essentially of a metal oxide material that provides reversible electric field dependent resistivity modulation. The reversible electric field dependent resistivity modulation within the material of the variable capacitance node dielectric material layer 54L may provide two dielectric states that may be provided by using the hysteresis effect of a vertical electric field to be subsequently applied across it. The two dielectric states may include a first dielectric state having a first resistivity and having a first effective dielectric constant and a second dielectric state having a second resistivity and having a second effective dielectric constant. The range of the first resistivity and the second resistivity may be less than 1.0 x 10 -2 S / m, and can usually be between 1.0x10 -15 S / m to 1.0x 10 - 3 Generally, the first dielectric state and the second dielectric state may provide different resistivities for the metal oxide material of the variable capacitance node dielectric material layer 54L.

[0077] In one embodiment, the variable capacitor node dielectric material layer 54L may include an oxygen vacancy modulated metal oxide material or a filament-forming metal oxide. The oxygen vacancy modulated metal oxide material includes oxygen vacancies that drift along the direction of an externally applied electric field. The filament-forming metal oxide material produces a conductive filament that increases the conductivity of the filament-forming metal oxide material when an electric field having a field strength exceeding a critical field strength is applied. Resistivity modulation in a thin metal oxide material may result in a change in the effective resistivity of the metal oxide material and a change in the effective dielectric constant of the metal oxide material. Exemplary metal oxide materials that exhibit resistivity modulation include, but are not limited to, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, hafnium aluminum oxide, hafnium zirconium oxide, and hafnium tantalum oxide. The metal oxide material that provides reversible electric field-dependent resistivity modulation may be deposited by chemical vapor deposition or physical vapor deposition.

[0078] In another embodiment, the variable capacitor node dielectric material layer 54L includes a metal oxide material that can provide reversible electric field dependent movement of metal atoms therein. Typically, dielectric metal oxides and dielectric semiconductor compounds that can be used in conductive bridge structures belong to this category. For example, the variable capacitor node dielectric material layer 54L may include metal oxide materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, hafnium aluminum oxide, hafnium zirconium oxide, and hafnium tantalum oxide. Alternatively, the variable capacitor node dielectric material layer 54L may include dielectric semiconductor compound materials such as silicon oxide, silicon oxynitride, or silicon nitride. Typically, the reversible electric field dependent movement of metal atoms through the variable capacitor node dielectric material layer 54L enables a reversible conductive bridge to be formed in the variable capacitor node dielectric material layer 54L. Other suitable variable capacitor node dielectric materials may be within the expected disclosure range.

[0079] Typically, the variable capacitance node dielectric material layer 54L can be deposited by chemical vapor deposition, atomic layer deposition and / or physical vapor deposition. The thickness of the variable capacitance node dielectric material layer 54L can be in the range of 2nm to 20nm, such as in the range of 4nm to 10nm, but smaller or larger thicknesses can also be used. The variable capacitance node dielectric material layer 54L can be thick enough to avoid dielectric breakdown during operation of the field effect transistor, and can be thin enough to apply a strong enough electric field thereon to achieve switching from a first dielectric state to a second dielectric state, and vice versa. Typically, the variable capacitance node dielectric material layer 54L has a variable effective dielectric constant that depends on the hysteresis effect of the electric field across it.

[0080] The control gate electrode material layer 58L may be deposited over the variable capacitance node dielectric material layer 54L. The control gate electrode material layer 58L includes a conductive material that facilitates the creation of two dielectric states in combination with the variable capacitance node dielectric material layer 54L and the intermediate electrode material layer 52L. In one embodiment, the control gate electrode material layer 58L includes a metallic material that is different from the conductive material of the intermediate electrode material layer 52L, thereby providing an asymmetry in material composition between the control gate electrode material layer 58L and the intermediate electrode material layer 52L relative to the variable capacitance node dielectric material layer 54L.

[0081] In one embodiment, the variable capacitance node dielectric material layer 54L includes an oxygen vacancy modulated metal oxide material or a filament-forming metal oxide, and the control gate electrode material layer 58L includes a metal material that is not affected by bulk diffusion or surface diffusion of the material under device operating conditions. In one embodiment, the control gate electrode material layer 58L includes a transition metal or a conductive metal nitride material having a melting point greater than 1,000 degrees Celsius. For example, the control gate electrode material layer 58L may include a metal such as hafnium, zirconium, tungsten, tantalum, titanium, molybdenum, niobium, rhenium, iridium, or a combination thereof. In another embodiment, the control gate electrode material layer 58L may include a conductive metal nitride material such as TiN, TaN, or WN. Other suitable control gate electrode materials may be within the intended disclosure.

[0082] In another embodiment, the variable capacitance node dielectric material layer 54L includes a metal oxide material that can provide reversible electric field dependent movement of metal atoms therein, and the control gate electrode material layer 58L includes a metal material that facilitates diffusion of the metal within the variable capacitance node dielectric material layer 54L. In one embodiment, the control gate electrode material layer 58L includes and / or consists essentially of a conductive bridge metal material selected from copper, copper-containing compounds or intermetallic alloys, silver, silver-containing compounds or intermetallic alloys, tellurium, tellurium-containing compounds or intermetallic alloys, aluminum, and aluminum-containing compounds or intermetallic alloys.

[0083] The control gate electrode material layer 58L may be deposited by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The thickness of the control gate electrode material layer 58L may be in the range of 5 nm to 100 nm, such as in the range of 10 nm to 40 nm, although lesser or greater thicknesses may also be used.

[0084] Figure 2A is a top view of the first exemplary structure after forming a control gate electrode and a variable capacitance node dielectric in accordance with an embodiment of the present invention. Figure 2B It is along Figure 2A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'. Figure 2C It is along Figure 2A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. FIG. 2A to FIG. 2C , a first photoresist layer may be applied over the control gate electrode material layer 58L, and the first photoresist layer may be photolithographically patterned to form a first photoresist material portion 59. In one embodiment, the first photoresist material portion 59 covers the region of the shallow trench isolation structure 12 and does not cover the region of the device region. In one embodiment, the first photoresist material portion 59 is adjacent to the region of the channel region, which will be subsequently formed in the device region.

[0085] A first anisotropic etching process may be performed to remove unmasked portions of the control gate electrode material layer 58L and the variable capacitance node dielectric material layer 54L. During the first anisotropic etching process, the first photoresist material portion 59 is used as an etching mask. The first anisotropic etching process may include a series of anisotropic etching steps that etch the materials of the control gate electrode material layer 58L and the variable capacitance node dielectric material layer 54L. The patterned portion of the control gate electrode material layer 58L includes the control gate electrode 58. The patterned portion of the variable capacitance node dielectric material layer 54L includes the variable capacitance node dielectric 54. The first photoresist material portion 59 may then be removed, for example, by ashing.

[0086] Figure 3A is a top view of the first exemplary structure after forming an intermediate electrode and a gate dielectric according to an embodiment of the present invention. Figure 3B It is along Figure 3A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'. Figure 3C It is along Figure 3A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. FIG. 3A to FIG. 3C , a second photoresist layer may be applied over the control gate electrode 58 and the intermediate electrode material layer 52L, and the second photoresist layer may be photolithographically patterned to form a second photoresist material portion 69. The second photoresist material portion 69 may cover the entire area of ​​the control gate electrode 58 and include a strip-shaped portion covering an additional area extending across the middle portion of the device region adjacent to the control gate electrode 58. In one embodiment, the area of ​​the strip-shaped portion of the second photoresist material portion 69 corresponds to the area of ​​a channel region to be formed subsequently.

[0087] A second anisotropic etching process may be performed to remove the unmasked portions of the intermediate electrode material layer 52L and the gate dielectric material layer 50L. During the second anisotropic etching process, the second photoresist material portion 69 is used as an etching mask. The second anisotropic etching process may include a series of anisotropic etching steps that etch the materials of the intermediate electrode material layer 52L and the gate dielectric material layer 50L. The patterned portion of the intermediate electrode material layer 52L includes the intermediate electrode 52. The patterned portion of the gate dielectric material layer 50L includes the gate dielectric 50.

[0088] Figure 4A is a top view of the first exemplary structure after forming source / drain extension regions and dielectric gate spacers in accordance with an embodiment of the present invention. Figure 4B It is along Figure 4A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'. Figure 4C It is along Figure 4A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. FIG. 4A to FIG. 4C , electrical dopants may be implanted into the unmasked portion of semiconductor material layer 10 to form source extension region 32E / drain extension region 38E. For example, if semiconductor material layer 10 includes a dopant of a first conductivity type, a dopant of a second conductivity type may be implanted into the surface portion of semiconductor material layer 10 to form source extension region 32E / drain extension region 38E. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Source extension region 32E / drain extension region 38E may include source extension region 32E and drain extension region 38E. The atomic concentration of the dopant of the second conductivity type in source extension region 32E / drain extension region 38E may be between 1.0 x 10 16 / cm 3 Up to 5.0x 10 19 / cm 3 , but lesser or greater atomic concentrations may be used. The depth of the source extension region 32E / drain extension region 38E may be in the range of 5nm to 50nm, but lesser or greater depths may be used. The portion of the semiconductor material layer 10 located between the source extension region 32E and the drain extension region 38E includes a channel region 35. The channel region 35 is below the gate dielectric 50. In one embodiment, the control gate electrode 58 is located within the region of a portion of the shallow trench isolation structure 12 and does not extend over the channel region 35. The second photoresist material portion 69 may then be removed, for example, by ashing.

[0089] The combination of the control gate electrode 58, the variable capacitance node dielectric 54 and the intermediate electrode 52 constitutes a variable capacitance capacitor or a varactor diode. The control gate electrode 58 serves as an upper capacitor plate, the variable capacitance node dielectric 54 serves as a node dielectric that can provide a variable dielectric constant, and the intermediate electrode 52 serves as a lower capacitor plate. Therefore, the intermediate electrode 52 spans over a portion of the channel region 35 and the shallow trench isolation structure 12. The upper capacitor plate includes the control gate electrode 58 vertically spaced from the lower capacitor plate, which includes the intermediate electrode 52. The variable capacitance node dielectric 54 is located between the lower capacitor plate and the upper capacitor plate and includes an electric field programmable metal oxide material that provides a variable effective dielectric constant. The electric field programmable metal oxide material may have two dielectric states that provide two different effective dielectric constants. Data bits may be stored in the memory device as dielectric states of the variable capacitance node dielectric.

[0090] At least one dielectric material such as silicon oxide and / or silicon nitride may be conformally deposited over the control gate electrode 58 and the intermediate electrode 52 and may be anisotropically etched to form a dielectric gate spacer 56. Specifically, the at least one dielectric material may be deposited by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. The horizontal portion of the at least one dielectric material may be removed by performing an anisotropic etching process. The remaining vertical portion of the at least one dielectric material constitutes the dielectric gate spacer 56. The lateral thickness of the dielectric gate spacer 56 may be in the range of 5 nm to 100 nm, such as in the range of 10 nm to 50 nm, but smaller or larger lateral thicknesses may also be used. The lower portion of the dielectric gate spacer 56 laterally surrounds the stack of the gate dielectric 50 and the intermediate electrode 52, and the upper portion of the dielectric gate spacer 56 laterally surrounds the stack of the control gate electrode 58 and the variable capacitance node dielectric 54. In one embodiment, the dielectric gate spacer 56 may include a first opening in which the stack of the control gate electrode 58 and the variable capacitance node dielectric 54 is located, and a second opening surrounding an area of ​​the channel region 35 .

[0091] Figure 5A is a top view of the first exemplary structure after forming source / drain regions according to an embodiment of the present invention. Figure 5B It is along Figure 5A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'. Figure 5C It is along Figure 5A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. FIG. 5A to FIG. 5C, an electrical dopant of the second conductivity type may be implanted into the semiconductor material layer 10 and the unmasked portion of the source extension region 32E / drain extension region 38E to form a deep source region 32D / drain region 38D. The deep source region 32D / drain region 38D may include a deep source region 32D and a deep drain region 38D. The atomic concentration of the dopant of the second conductivity type in the deep source region 32D / drain region 38D may be between 5.0 x 10 19 / cm 3 Up to 2.0x10 21 / cm 3 The depth of deep source region 32D / drain region 38D may be in the range of 20 nm to 200 nm, such as in the range of 40 nm to 100 nm, although lesser or greater atomic concentrations may be used. The combination of source extension region 32E and deep source region 32D constitutes source region 32, and the combination of drain extension region 38E and deep drain region 38D constitutes drain region 38.

[0092] The shallow trench isolation structure 12 laterally surrounds the device region including the source region 32, the drain region 38, and the channel region 35. In one embodiment, the entire upper capacitor plate including the control gate electrode 58 is located within the region of the shallow trench isolation structure 12 and outside the device region, that is, outside the region of the source region 32, the drain region 38, and the channel region 35. The lower capacitor plate including the intermediate electrode 52 also includes a first portion above the channel region 35 and a second portion below the upper capacitor plate. The entire area of ​​the upper capacitor plate may be located within the region of the lower capacitor plate.

[0093] A combination of a field effect transistor and a variable capacitance capacitor is provided. The variable capacitance capacitors 52, 54, 58 serve as a composite gate structure of the field effect transistor. The threshold voltage V t Given by: V t =V FB +2φ F +(4εqN a φ F ) 1 / 2 / C total , where V FB is the flat band voltage of the semiconductor material of the channel region 35, φ F is the Fermi potential of the semiconductor material of the channel region 35, ε is the dielectric constant of the semiconductor material of the channel region 35, q is the charge per charge carrier in the semiconductor material of the channel region 35, N a is the density of donor atoms or acceptor atoms in the semiconductor material of the channel region 35 and, C totalis the total capacitance between the channel region 35 and the electrode to which the gate voltage is applied. According to an embodiment of the present invention, a gate voltage is applied to the control gate electrode. In this embodiment, the total capacitance C between the channel region 35 and the control gate electrode 58 is total is the series capacitance of the two capacitor structures including the channel region 35, the gate dielectric 50, the intermediate electrode 52, the variable capacitance node dielectric 54, and the control gate electrode. Therefore, the change in the effective dielectric constant of the variable capacitance node dielectric 54 results in a total capacitance C between the channel region 35 and the control gate electrode 58. total changes, and thus causes the threshold voltage V t changes.

[0094] Fig. 6A is a top view of the first exemplary structure after forming a contact-level dielectric layer, a contact via cavity, and a metal-semiconductor alloy region in accordance with an embodiment of the present invention. Figure 6B It is along Fig. 6A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'. Figure 6C It is along Fig. 6A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. FIG. 6A to FIG. 6C , a dielectric material may be deposited over the field effect transistor incorporating the variable capacitance capacitors 52, 54, 58 and the shallow trench isolation structure 12. The dielectric material may include a planarizable dielectric material such as undoped silicate glass or doped silicate glass, or a self-planarizing dielectric material such as a flowable oxide (FOX). The dielectric material may be deposited by a chemical vapor deposition process (such as a plasma enhanced chemical vapor deposition process) or by spin coating. The top surface of the dielectric material may be planarized during or after the deposition process. A dielectric material layer having a flat (i.e., horizontal) top surface is formed, and a contact via structure is subsequently formed through the dielectric material layer. As such, the dielectric material layer is referred to herein as a contact-level dielectric layer 70. The top surface of the contact-level dielectric layer 70 may be flat and may be located above the top surface of the control gate electrode 58. The vertical distance between the top surface of the contact-level dielectric layer 70 and the top surface of the control gate electrode 58 may be in the range of 30nm to 400nm, but smaller or larger thicknesses may also be used.

[0095] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 70, and the photoresist layer may be photolithographically patterned to form discrete openings therethrough. The openings in the photoresist layer may be formed over the source region 32, the drain region 38, the control gate electrode 58, and a portion of the intermediate electrode 52 that is not located below the control gate electrode 58. An anisotropic etching process may be performed to form a contact via cavity 71 through the contact-level dielectric layer 70. The contact via cavity 71 includes: a source contact via cavity extending from the top surface of the contact-level dielectric layer 70 to the top surface of the source region 32, a drain contact via cavity extending from the top surface of the contact-level dielectric layer 70 to the top surface of the drain region 38, and an intermediate gate contact via cavity extending from the top surface of the contact-level dielectric layer 70 to the top surface of the intermediate electrode 52, and a control gate contact via cavity extending from the top surface of the contact-level dielectric layer 70 to the top surface of the control gate electrode 58.

[0096] Alternatively, a metal that can form a metal-semiconductor alloy can be deposited into the contact via the contact through-hole cavity 71 by a conformal or non-conformal deposition process. If the semiconductor material layer 10 includes and / or is substantially composed of doped silicon, the metal can be a material that can form a metal silicide. For example, the metal can include nickel, titanium, tungsten, molybdenum, platinum, or another metal that forms a metal silicide. Other suitable metal materials are within the expected disclosed range. An annealing process can be performed at an elevated temperature to induce the formation of a metal silicide material. The elevated temperature can be in the range of 500 degrees Celsius to 750 degrees Celsius. Unreacted metal portions can be removed by a wet etching process that selectively etches the metal into a metal silicide material. The remaining portion of the metal silicide material can include a source side metal-semiconductor alloy region 62 in contact with the source region 32 and a drain side metal-semiconductor alloy region 68 in contact with the drain region 38. In an embodiment where the intermediate electrode 52 includes a semiconductor material, a gate side metal-semiconductor alloy region can be formed.

[0097] Fig. 7A is a top view of the first exemplary structure after forming a contact via structure according to an embodiment of the present invention. Figure 7B It is along Fig. 7A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane BB'. Figure 7C It is along Fig. 7A A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'. 7A to 7C, a metal liner 72A including a diffusion barrier material may be placed at a peripheral portion of the remaining volume of the contact via cavity 71. The metal liner 72A includes a conductive metal nitride material (such as TiN, TaN or WN) and / or a metal carbide material (such as TiC, TaC or WC). Other suitable metal liners and metal carbide materials are within the expected disclosed range. The thickness of the metal liner 72A may be in the range of 3nm to 15nm, but lesser or greater thicknesses may also be used.

[0098] A metal fill material 72B (such as Cu, W, Mo, Co, Ru and / or another elemental metal or intermetallic alloy) may be deposited in the remaining volume of the contact via cavity 71. Other suitable metal fill materials are within the contemplated disclosure. Portions of the metal fill material 72B and metal liner 72A located above a horizontal plane including the top surface of the contact-level dielectric layer 70 may be removed by a planarization process. The remaining portion of each combination of the metal fill material 72B and the metal liner 72A that fills a corresponding one of the contact via cavities 71 constitutes a contact via structure 82, 88, 85, 86. The contact via structures 82, 88, 85, 86 include a source contact via structure 82 in contact with the source-side metal-semiconductor alloy region 62, a drain contact via structure 88 in contact with the drain-side metal-semiconductor alloy region 68, an intermediate gate contact via structure 85 in contact with the intermediate electrode 52 (or the gate-side metal-semiconductor alloy region, if present), and a control gate contact via structure 86 in contact with the control gate electrode 58. Each of the contact via structures 82, 88, 85, 86 includes a corresponding portion of a corresponding metal liner 72A and a metal filling material 72B, and may have a top surface including a top surface of the contact-level dielectric layer 70 in a horizontal plane.

[0099] The combination of the field effect transistor and variable capacitance capacitors 52 , 54 , 58 acts as a memory device that can store a bit as the dielectric state of the variable capacitance node dielectric 54 .

[0100] refer to FIG. 8A to FIG. 8C , showing a second exemplary structure according to an embodiment of the present invention, the structure includes a shallow trench isolation structure formed in a semiconductor material layer 10 of a substrate 8. The semiconductor material layer 10 and the shallow trench isolation structure 12 may be formed in the same manner as in the above Figures 1A to 7C The same as in the first exemplary structure shown.

[0101] A sacrificial dielectric layer such as a silicon oxide layer and a sacrificial gate material layer may be formed over the top surface of the substrate 8. The sacrificial dielectric layer and the sacrificial gate material layer may be patterned into a gate pattern to form a stack of a sacrificial gate dielectric 450 and a dummy gate structure 452. The sacrificial gate dielectric 450 may include a sacrificial dielectric material such as silicon oxide with a thickness ranging from 1 nm to 30 nm, but thicker or thinner layers may be used. The dummy gate structure 452 includes any sacrificial material that can selectively remove the material of the semiconductor material layer 10 and the shallow trench isolation structure 12. For example, the dummy gate structure 452 may include a silicon germanium alloy, amorphous carbon, diamond-like carbon, borosilicate glass, a silicon-based polymer, etc.

[0102] Semiconductor material layer 10 may have a first conductivity type of doping. Dummy gate structure 452 may be used as an implantation mask to implant a second conductivity type of dopant to form source extension region 32E and drain extension region 38E, which may have the same depth and the same dopant concentration range as in the first exemplary structure.

[0103] refer to 9A to 9C , a dummy spacer 456 may be formed around the dummy gate structure 452 by conformal deposition of a sacrificial material layer and anisotropic etching of the sacrificial material layer. The dummy spacer 456 may include any material that may be used for the dummy gate structure 452. The material of the dummy spacer 456 may be the same as or may be different from the material of the dummy gate structure 452. The thickness of the dummy spacer 456 may be within the same range as the dielectric gate spacer 56 of the first exemplary structure.

[0104] Additional dopants of the second conductivity type may be implanted into the unmasked portions of the semiconductor material layer 10 and the source extension region 32E / drain extension region 38E to form deep source region 32D and deep drain region 38E. The combination of dummy spacer 456 and dummy gate structure 452 may be used as an implantation mask. The deep source region 32D and the deep drain region 38D may have the same dopant concentration range and the same depth range as in the first exemplary structure. Each combination of source extension region 32E and deep source region 32D constitutes source region 32, and each combination of drain extension region 38E and deep drain region 38D constitutes drain region 38.

[0105] refer to FIG. 10A to FIG. 10C By performing an etching process (such as at least one wet etching process) and / or an ashing process, the dummy spacers 456, the dummy gate structures 452, and the sacrificial gate dielectric 450 may be selectively removed from the materials of the semiconductor material layer 10 and the shallow trench isolation structure 12. An appropriate cleaning process may then be performed.

[0106] refer to FIG. 11A to FIG. 11C, a gate dielectric material layer and an intermediate electrode material layer may be deposited. The gate dielectric material layer and the intermediate electrode material layer may be patterned into a gate electrode pattern to form a gate dielectric 50 and an intermediate electrode 52. A patterned photoresist layer may be formed over the intermediate electrode material layer. An anisotropic etching process may be used to transfer the pattern in the photoresist layer through the intermediate electrode material layer and the gate dielectric material layer. The pattern of the patterned photoresist layer may be the same as that described in the reference numerals above. Figures 1A to 7C The pattern of the intermediate electrode 52 in the first exemplary structure shown is the same. The gate dielectric 50 may include the same material and may have the same thickness range as the first exemplary structure. The intermediate electrode 52 may include the same material and may have the same thickness range as the first exemplary structure.

[0107] refer to FIG. 12A to FIG. 12C , a variable capacitor node dielectric material layer and a control gate electrode material layer may be deposited. The variable capacitor node dielectric material layer and the control gate electrode material layer may be patterned into a variable capacitor node dielectric 54 and a control gate electrode 58. A patterned photoresist layer may be formed over the control gate electrode material layer. An anisotropic etching process may be used to transfer the pattern in the photoresist layer through the control gate electrode material layer and the variable capacitor node dielectric material layer. The pattern of the patterned photoresist layer may be the same as the pattern of the control gate electrode 58 in the first exemplary structure (e.g., see FIG. 2A to FIG. 2C ). The variable capacitance node dielectric 54 may include the same material and may have the same thickness range as in the first exemplary structure. The control gate electrode 58 may include the same material and may have the same thickness range as in the first exemplary structure.

[0108] refer to FIG. 13A to FIG. 13C , a dielectric gate spacer 56 may be optionally formed by conformally depositing and anisotropically etching a dielectric gate spacer material layer. The dielectric gate spacer 56 may include the same material as in the first exemplary structure and may have the same lateral thickness as in the first exemplary structure. Subsequently, a 6A to 7C The processing steps are as follows to form the contact-level dielectric layer 70, the metal-semiconductor alloy regions 62, 68 and the contact via structures 82, 85, 88, 86.

[0109] In general, various other types of field effect transistors may be used to provide the semiconductor device of the present invention, which may be a fin field effect transistor, a gate of a gate-all-around field effect transistor, a nanowire field effect transistor, a vertical field effect transistor, or any other type of field effect transistor. In each embodiment, a gate dielectric 50 and an intermediate gate electrode 52 may be formed on the entire channel surface covering the channel region 35, and a stack of a variable capacitance node dielectric 54 and a control gate electrode 58 may be formed on a portion of the intermediate gate electrode 52. Another portion of the intermediate gate electrode 52 may be contacted by an intermediate gate contact via structure 85.

[0110] FIG. 14A to FIG. 18C A third exemplary structure is shown in which a fin field effect transistor may be formed instead of a planar field effect transistor.

[0111] refer to FIG. 14A to FIG. 14C , a semiconductor fin 720 may be disposed above a substrate 8 including an insulating substrate layer 710. In one embodiment, the semiconductor fin 720 may be a patterned portion of a top semiconductor layer of a semiconductor on insulator (SOI) substrate. The insulating substrate layer 720 may be a buried oxide layer of the SOI substrate. Alternatively, the semiconductor fin 720 may be a portion of a semiconductor material layer bonded to the insulating substrate layer 710 and subsequently patterned. For example, a single crystal silicon substrate having a hydrogen implantation layer therein may be bonded to the insulating substrate layer 710 and may then be cut to remove a bulk portion of the single crystal silicon substrate. The remaining thin surface portion of the single crystal silicon substrate may be patterned to form the semiconductor fin 720. Although the present invention is described using an embodiment in which the semiconductor fin 720 is disposed on the insulating substrate layer 710, embodiments in which the semiconductor fin 720 may be formed above the top surface of the semiconductor material layer are explicitly contemplated herein, and the underlying portion of the semiconductor material layer is suitable for electrical isolation by a shallow trench isolation structure with a combination of multiple doped wells having a reverse bias therein. The semiconductor fin 720 may be single crystal or polycrystalline. The height of semiconductor fin 720 may be in the range of 50 nm to 500 nm, although smaller or larger heights may also be used. Semiconductor fin 720 may have a doping of the first conductivity type. The atomic concentration of the dopant in semiconductor fin 720 may be in the range of 1.0 x 10 14 / cm 3 Up to 3.0x 10 17 / cm 3 The width of the semiconductor fin 720 may be in the range of 10 nm to 80 nm, but a smaller or larger atomic concentration may also be used.

[0112] refer to FIG. 15A to FIG. 15C , you can execute the above Figures 1A to 1CThe process steps are to sequentially deposit the gate dielectric material layer 50L, the intermediate electrode material layer 52L, the variable capacitance node dielectric material layer, and the control gate electrode material layer. The material composition and thickness of each layer may be the same as in the first exemplary structure.

[0113] A photoresist layer (not shown) may be applied over the control gate electrode material layer. The photoresist layer may be photolithographically patterned to form a gate pattern that covers a portion of the control gate electrode material layer that is laterally offset from the middle portion of the semiconductor fin 720. An anisotropic etching process may be performed to etch the unmasked portions of the control gate electrode material layer and the variable capacitance node dielectric material layer. The patterned portion of the control gate electrode material layer includes the control gate electrode 58. The patterned portion of the variable capacitance node dielectric material layer includes the variable capacitance node dielectric 54. The control gate electrode 58 and the variable capacitance node dielectric 54 may have vertically coincident sidewalls, i.e., sidewalls that are located in a common vertical plane. The photoresist layer may then be removed, for example, by ashing.

[0114] refer to FIG. 16A to FIG. 16C , you can execute the above FIG. 3A to FIG. 3C The process steps of the semiconductor fin 720 are performed to pattern the gate dielectric material layer 50L and the intermediate electrode material layer 52L. The patterned photoresist layer can be used as an etching mask layer during the anisotropic etching process, which patterns the gate dielectric material layer 50L and the intermediate electrode material layer 52L into the gate dielectric 50 and the intermediate electrode 52. The gate dielectric 50 and the intermediate electrode 52 span the middle portion of the semiconductor fin 720 and are located below the stack of the control gate electrode 58 and the variable capacitance node dielectric 54. The dimension of the intermediate electrode 52 along the length direction of the semiconductor fin 720 is the gate length of the fin field effect transistor.

[0115] The intermediate electrode 52 may be used as an implantation mask structure to perform an ion implantation process to implant a second conductivity type dopant into the unmasked portion of the semiconductor fin 720. The second conductivity type is opposite to the first conductivity type. The source extension region 32E and the drain extension region 38E may be formed in the implanted portion of the semiconductor fin 720. The unimplanted portion of the semiconductor fin 720 located below the intermediate electrode 52 constitutes the channel region 35. The atomic concentration of the second conductivity type dopant in the source extension region 32E and the drain extension region 38E may be the same as in the first exemplary structure.

[0116] refer to FIG. 17A to FIG. 17C , you can execute the above FIG. 5A to FIG. 5CThe process steps are as follows to form dielectric gate spacers 56, deep source regions 32D, and deep drain regions 38D. As in the first exemplary structure, dielectric gate spacers 56 may include the same material and may have the same thickness range. Using the combination of intermediate electrode 52 and dielectric gate spacers 56 as an implantation mask, deep source regions 32D and deep drain regions 38D may be performed by implanting dopants of the second conductivity type. The deep source regions 32D and deep drain regions 38D may have the same atomic concentration range of dopants of the second conductivity type as the first exemplary structure. Each combination of source extension region 32E and deep source region 32D constitutes source region 32, and each combination of drain extension region 38E and deep drain region 38D constitutes drain region 38.

[0117] refer to 18A to 18C , executable 6A to 7C The processing steps are as follows to form the contact-level dielectric layer 70, the metal-semiconductor alloy regions 62, 68 and the contact via structures 82, 85, 88, 86.

[0118] Fig.19 A circuit schematic diagram of a combination of a memory device 100 (including a combination of a field effect transistor and a variable capacitance capacitor 52, 54, 58) and a control circuit according to an embodiment of the present invention is shown. The memory device 100 includes a field effect transistor and a variable capacitance capacitor 52, 54, 58. The field effect transistor includes a gate structure 50, 52 having a gate dielectric 50 and an intermediate electrode 52, and the variable capacitance capacitor 52, 54, 58 includes a lower capacitor including the intermediate electrode 52, an upper capacitor plate including a control gate electrode 58, and a variable capacitance node dielectric 54 located between the lower capacitor plate and the upper capacitor plate. The threshold voltage of the field effect transistor when the intermediate electrode 52 is electrically floating depends on the dielectric state of the variable capacitance node dielectric 54. The threshold voltage of the field effect transistor when the intermediate electrode 52 is electrically floating is the minimum voltage that needs to be applied to the control gate electrode 58 when the intermediate electrode 52 is electrically floating to turn on the field effect transistor.

[0119] The dielectric state of the variable capacitance node dielectric 54 may be programmed to a state selected from a first dielectric state (e.g., a programmed state) that provides a first capacitance to the variable capacitance capacitors 52, 54, 58 and a second dielectric state (e.g., an erased state) that provides a second capacitance to the variable capacitance capacitors 52, 54, 58. For example, the dielectric state of the variable capacitance node dielectric 54 may be programmed to the first dielectric state by applying a first voltage having a first polarity to the control gate electrode 58 relative to the middle electrode 52, or may be programmed to the second dielectric state by applying a second voltage having a second polarity to the control gate electrode 58 relative to the middle electrode 52. The second polarity may be opposite to the first polarity.

[0120] The first voltage or the second voltage may be applied by the programming circuit 120, 110 or by the erasing circuit 130, 110. The programming circuit 120, 110 is configured to apply a programming voltage having a first polarity to the control gate electrode 58 relative to the middle electrode 52. The erasing circuit 130, 110 may be configured to apply an erasing voltage having a second polarity to the control gate electrode 58 relative to the middle electrode 52. The second polarity is opposite to the first polarity. For example, if the first polarity is positive, the second polarity is negative, and vice versa.

[0121] In an illustrative example, the programming circuit 120, 110 may include a programming voltage connection switch 120 that may include a field effect transistor. One of the source / drain regions of the field effect transistor of the programming voltage connection switch 120 may be electrically connected to the control gate electrode 58, and the other of the source / drain regions of the field effect transistor of the programming voltage connection switch 120 may be electrically connected to a voltage source that provides a programming voltage +Vp (which may be a first voltage). The programming circuit 120, 110 may include a grounding switch 110 that is connected to the middle electrode 52 and is configured to provide a state selected from a first state (floating state) and a second state (i.e., grounding state) to the middle electrode 52, in which the middle electrode 52 is electrically floating and in which the middle electrode is electrically grounded. In one embodiment, the programming voltage +Vp may have a magnitude in the range of 2V to 10V (such as 3V to 10V), but smaller or larger magnitudes may also be used.

[0122] The erase circuit 130, 110 may include an erase voltage connection switch 130 of a field effect transistor. One of the source / drain regions of the field effect transistor of the erase voltage connection switch 130 may be electrically connected to the control gate electrode 58, and the other of the source / drain regions of the field effect transistor of the erase voltage connection switch 130 may be electrically connected to a voltage source that provides an erase voltage -Ve (which may be a second voltage). The erase circuit 130, 110 may include a ground switch 110. In one embodiment, the erase voltage -Ve may have a magnitude in the range of 2V to 10V (such as 3V to 10V), but smaller or larger magnitudes may also be used.

[0123] Typically, the variable capacitance node dielectric 54 of the variable capacitance capacitors 52, 54, 58 may have a variable effective dielectric constant that depends on the hysteresis effect of the electric field across the upper capacitor plate (including the control gate electrode 58) and the lower capacitor plate (including the middle electrode 52). The variable capacitance node dielectric 54 may be programmed to a first state or a second state by applying an electric field across the upper capacitor plate and the lower capacitor plate. To perform a programming operation, the programming voltage connection switch 120 and the grounding switch 110 are turned on. During a programming operation, a programming voltage having a first polarity is applied to the control gate electrode 58 relative to the middle electrode 52. To perform an erase operation, the erase voltage connection switch 130 and the grounding switch 110 are turned on. During an erase operation, an erase voltage having a second polarity may be applied to the control gate electrode 58 relative to the middle electrode 52.

[0124] In one embodiment, the variable capacitor node dielectric 54 includes or consists essentially of a metal oxide material that provides reversible electric field dependent resistivity modulation, and the first dielectric state and the second dielectric state provide different resistivities for the metal oxide material of the variable capacitor node dielectric 54. The ratio of the resistivity of the first electrical state to the resistivity of the second electrical state may be between 1.0x10 -10 to 1 / 3 or between 3 and 1.0x 10 10 In one embodiment, the variable capacitance node dielectric 54 includes and / or consists essentially of a resistivity modulated metal oxide material, and the control gate electrode 58 includes and / or consists essentially of a transition metal or conductive metal nitride material having a melting point greater than 1,000 degrees Celsius. In one embodiment, the oxygen vacancy distribution 54 within the variable capacitance node dielectric 54 can be changed during programming of the dielectric state of the variable capacitance node dielectric.

[0125] In one embodiment, the variable capacitance node dielectric 54 includes and / or consists essentially of a metal oxide material that provides reversible electric field dependent movement of metal atoms therein. In this embodiment, the control gate electrode 58 may include and / or may consist essentially of a conductive bridge metal material selected from copper, copper-containing compounds or intermetallic alloys, tellurium, tellurium-containing compounds or intermetallic alloys, aluminum and aluminum-containing compounds or intermetallic alloys. Other suitable metal materials are within the expected disclosure. During programming of the dielectric state of the variable capacitance node dielectric 54, the resistivity within the variable capacitance node dielectric 58 may be changed.

[0126] The memory device may include sensing circuits 150, 110, 160, 180, 190. The sensing circuits 150, 110, 160, 180, 190 may be configured to apply a voltage bias across the drain region 38 and the source region 32, and to apply a sensing gate voltage Vs to the control gate electrode 58 during a sensing step. When the variable capacitance node dielectric 58 is in a first dielectric state, the field effect transistor may have a first threshold voltage, and when the variable capacitance node dielectric 58 is in a second dielectric state, the field effect transistor may have a second threshold voltage. The sensing gate voltage Vs may be between the first threshold voltage and the second threshold voltage.

[0127] In one embodiment, the sensing circuits 150, 110, 160, 180, 190 may include: a sensing gate voltage switch 150 configured to apply a sensing gate voltage Vs to the control gate electrode 58 during a sensing operation; a source grounding switch 160 configured to ground the source region 32 during a sensing operation; a drain bias switch 180 configured to apply a drain bias voltage Vd to the drain region 38 during a sensing operation; and a current sensing circuit 190 configured to measure a current flowing between the source region 32 and the drain region 38 during a sensing operation. The sensing circuits 150, 110, 160, 180, 190 include a grounding switch 110 configured to provide a first state (i.e., an electrically floating state) to the middle electrode 52 during a sensing operation, and to provide a second state (i.e., an electrically grounded state) to the middle electrode 52 during a programming operation or during an erase operation.

[0128] refer to Fig. 20 , showing the Fig.19 The programming voltage +Vp is applied to the control gate electrode 58, and the middle electrode 52 can be electrically grounded to program the middle electrode 52 to the first dielectric state. Since the middle electrode is electrically grounded, the field effect transistor is turned off.

[0129] refer to Fig.21 , showing the Fig.19 The erase voltage -Ve is applied to the control gate electrode 58, and the middle electrode 52 can be electrically grounded to program the middle electrode 52 to the first dielectric state. Since the middle electrode is electrically grounded, the field effect transistor is turned off.

[0130] refer to Fig. 22 , showing the Fig.19. The sensing gate voltage Vs is applied to the control gate electrode 58, and the intermediate electrode 52 may be electrically floating. The drain bias switch 180 is turned on and applies a drain bias voltage Vd to the drain region 38, and the source grounding switch 160 is turned on and electrically grounds the source region 32. The current sensing circuit 190 measures the current flowing between the source region 32 and the drain region 38 during the sensing operation. In one embodiment, the magnitude of the first threshold voltage, the second threshold voltage, and the sensing gate voltage may be no greater than 5V and / or may be in the range of 2V to 5V.

[0131] In an embodiment where the first threshold voltage is lower than the second threshold voltage, the sensing gate voltage Vs is higher than the first threshold voltage and lower than the second threshold voltage. In this embodiment, if the current sensing circuit 190 detects the flow of current during the sensing operation, the variable capacitance node dielectric 54 is in the first dielectric state, and if the current sensing circuit 190 does not detect the flow of current during the sensing operation, the variable capacitance node dielectric 54 is in the second dielectric state.

[0132] Conversely, in an embodiment where the first threshold voltage is higher than the second threshold voltage, the sensing gate voltage Vs is lower than the first threshold voltage and higher than the second threshold voltage. In this embodiment, if the current sensing circuit 190 detects the flow of current during the sensing operation, the variable capacitance node dielectric 54 is in the second dielectric state, and if the current sensing circuit 190 does not detect the flow of current during the sensing operation, the variable capacitance node dielectric 54 is in the first dielectric state.

[0133] refer to Fig.23 , the flowchart shows the operation steps for operating the memory device of the present invention according to an embodiment of the present invention. Referring to step 2310 and Figures 1A to 18C , a memory device including a field effect transistor and a variable capacitance capacitor 52, 54, 58 is provided. The field effect transistor includes a gate structure 50, 52 having a gate dielectric 50 and an intermediate electrode 52, and the variable capacitance capacitor 52, 54, 58 includes a lower capacitor plate including the intermediate electrode 52, an upper capacitor plate including a control gate electrode 58, and a variable capacitance node dielectric 54 located between the lower capacitor plate and the upper capacitor plate. When the intermediate electrode 52 is electrically floating, the threshold voltage of the field effect transistor (for the control gate electrode 58) depends on the dielectric state of the variable capacitance node dielectric 54.

[0134] Refer to step 2320 and Fig.19 , Fig. 20 and Fig.21, the dielectric state of the variable capacitance node dielectric 54 can be programmed to a state selected from a first dielectric state and a second dielectric state, wherein the first dielectric state provides a first capacitance for the variable capacitance capacitor 52, 54, 58 and the second dielectric state provides a second capacitance for the variable capacitance capacitor 52, 54, 58. Referring to step 2330 and Fig.19 and Fig. 22 , the dielectric state of the variable capacitance node dielectric 54 may be sensed by applying a sensing gate voltage Vs between a first threshold voltage and a second threshold voltage to the control gate electrode 58 .

[0135] refer to Fig.24 , a flowchart showing the processing steps for manufacturing the memory device of the present invention according to an embodiment of the present invention. Referring to step 2410 and Figures 1A to 1C , FIG. 11A to FIG. 12C and FIG. 15A to FIG. 15C , a gate dielectric material layer 50L, an intermediate electrode material layer 52L, a variable capacitor node dielectric material layer 54L and a control gate electrode material layer 58L may be deposited over the device region and the shallow trench isolation structure 12. Referring to step 2420 and FIG. 2A to FIG. 2C , FIG. 12A to FIG. 12C and FIG. 15A to FIG. 15C , the variable capacitor node dielectric 54 and the control gate electrode 58 can be formed by patterning the variable capacitor node dielectric material layer 54L and the control gate electrode material layer 58L, respectively. Referring to step 2430 and FIG. 3A to FIG. 3C , FIG. 11A to FIG. 11C and FIG. 16A to FIG. 16C , the gate dielectric 50 and the intermediate electrode 52 can be formed by patterning the gate dielectric material layer 50L and the intermediate electrode material layer 52L. Referring to steps 2440 and 4A to 7C , 8A to 9C , FIG. 13A to FIG. 13C and FIG. 16A to FIG. 18C Source / drain regions 32, 38 and metal interconnect structures such as contact via structures 82, 88, 85, 86 may be formed to provide electrical connections to various nodes of the field effect transistors and variable capacitance capacitors 52, 54, 58.

[0136] With reference to all the drawings and in accordance with various embodiments of the present invention, there is provided a memory device including a field effect transistor and a variable capacitance capacitor 52, 54, 58. The field effect transistor includes: a source region 32, a drain region 38, and a channel region 35 located within a semiconductor material layer 10; and a gate structure 50, 52 covering the channel region 35 and including a gate dielectric 50 and an intermediate electrode 52. The variable capacitance capacitor 52, 54, 58 includes: a lower capacitor plate including the intermediate electrode 52; an upper capacitor plate vertically spaced apart from the lower capacitor plate and including a control gate electrode 58; and a variable capacitance node dielectric 54, the variable capacitance node dielectric being located between the lower capacitor plate and the upper capacitor plate and including an electric field programmable metal oxide material providing a variable effective dielectric constant. Data bits are stored in the memory device as dielectric states of the variable capacitance node dielectric 54. The area of ​​the upper capacitor plate may be less than the area of ​​the lower capacitor plate and may be completely within the area of ​​the lower capacitor plate.

[0137] According to another embodiment of the present invention, there is provided a memory device including a field effect transistor and a variable capacitance capacitor 52, 54, 58. The field effect transistor includes: a source region 32, a drain region 38, and a channel region 35 located in a semiconductor material layer 10; and a gate structure 50, 52 covering the channel region 35 and including a gate dielectric 50 and an intermediate electrode 52. The variable capacitance capacitor 52, 54, 58 includes: a lower capacitor plate including the intermediate electrode 52; an upper capacitor plate vertically spaced apart from the lower capacitor plate and including a control gate electrode 58; and a variable capacitance node dielectric 54, which is located between the lower capacitor plate and the upper capacitor plate and includes a metal oxide material that provides a reversible electric field dependent resistivity modulation.

[0138] Various embodiments of the present invention may be used to provide a memory device in which the dielectric state of a variable capacitance node dielectric 54 located between a lower capacitor plate and an upper capacitor plate is used to store a data bit. The lower capacitor plate includes an intermediate electrode that directly contacts the gate dielectric 50 and is electrically floating during sensing. The upper capacitor plate includes a control gate electrode to which a gate control voltage is applied during programming, erasing, and sensing. Various embodiments of the present invention may be used to provide a compact non-volatile memory device. The gate dielectric 50 may be non-tunneling, and therefore, the durability and reliability of the memory device are not affected by any tunneling damage or tunneling degradation.

[0139] In some embodiments, a memory device includes a field effect transistor and a variable capacitance capacitor, wherein the field effect transistor includes: a source region, a drain region, and a channel region within a semiconductor material layer; and a gate structure covering the channel region and including a gate dielectric and an intermediate electrode, and wherein the variable capacitance capacitor includes: a lower capacitor plate including the intermediate electrode; an upper capacitor plate vertically spaced apart from the lower capacitor plate, wherein the upper capacitor plate includes a control gate electrode; and a variable capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate and including an electric field programmable dielectric material providing a variable effective dielectric constant, and data bits are stored in the memory device as dielectric states of the variable capacitance node dielectric.

[0140] In the above memory device, it also includes a sensing circuit configured to perform the following operations: apply a voltage bias across the drain region and the source region during a sensing step; and apply a sensing gate voltage to the control gate electrode during the sensing step.

[0141] In the above-mentioned memory device, the field effect transistor has two stable configurations, including: a first configuration, wherein the variable capacitance node dielectric has a first effective dielectric constant and the field effect transistor has a first threshold voltage; and a second configuration, wherein the variable capacitance node dielectric has a second effective dielectric constant and the field effect transistor has a second threshold voltage, wherein the sensing gate voltage is greater than the first threshold voltage and less than the second threshold voltage.

[0142] In the above memory device, it also includes: an intermediate electrode contact through-hole structure, which is in contact with the top surface of the intermediate electrode; and a control electrode contact through-hole structure, which is in contact with the top surface of the control gate electrode.

[0143] The above-mentioned memory device also includes: a programming circuit configured to apply a programming voltage having a first polarity to the control gate electrode relative to the intermediate electrode; and an erasing circuit configured to apply an erasing voltage having a second polarity to the control gate electrode relative to the intermediate electrode, and the second polarity is opposite to the first polarity.

[0144] In the above memory device, it also includes a grounding switch, which is connected to the middle electrode and is configured to provide the middle electrode with a state selected from the following: a first state, in which the middle electrode is electrically floating; and a second state, in which the middle electrode is electrically grounded.

[0145] In the above memory device, the grounding switch is configured to: provide the first state to the middle electrode during a sensing operation; and provide the second state to the middle electrode during a programming operation.

[0146] In the above-mentioned memory device, it also includes a shallow trench isolation structure, which laterally surrounds the source region, the drain region and the channel region, wherein the intermediate electrode straddles the channel region and a portion of the shallow trench isolation structure, and the control gate electrode is located within the region of the portion of the shallow trench isolation structure and does not extend above the channel region.

[0147] In some embodiments, a memory device includes a transistor and a variable capacitance capacitor, wherein the transistor includes: a source region, a drain region, and a channel region within a semiconductor material layer; and a gate structure covering the channel region and including a gate dielectric and an intermediate electrode, and wherein the variable capacitance capacitor includes: a lower capacitor plate including the intermediate electrode; an upper capacitor plate vertically spaced apart from the lower capacitor plate, wherein the upper capacitor plate includes a control gate electrode; and a variable capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate and including a metal oxide material, wherein the metal oxide material provides reversible electric field dependent resistivity modulation.

[0148] In the above-mentioned memory device, it also includes a shallow trench isolation structure, which laterally surrounds the source region, the drain region and the channel region, wherein: the entire upper capacitor plate is located within the area of ​​the shallow trench isolation structure and outside the areas of the source region, the drain region and the channel region; the lower capacitor plate includes a first portion located above the channel region and a second portion located below the upper capacitor plate.

[0149] In the above memory device, the metal oxide material of the variable capacitance node dielectric has two dielectric states determined by a hysteresis effect of a vertical electric field across the lower capacitor plate and the upper capacitor plate.

[0150] In the above-mentioned memory device, the two dielectric states of the variable capacitance node dielectric include: a first dielectric state having a first effective dielectric constant and a first resistivity; and a second dielectric state having a second effective dielectric constant different from the first effective dielectric constant and a second resistivity different from the first resistivity.

[0151] In the above memory device, the variable capacitance node dielectric includes an oxygen vacancy modulated metal oxide material or a filament-forming metal oxide; and the control gate electrode includes a transition metal or a conductive metal nitride material having a melting point above 1,000 degrees Celsius.

[0152] In the above-mentioned memory device, the variable capacitor node dielectric includes a metal oxide material, which provides reversible electric field-dependent movement of metal atoms therein; and the control gate electrode includes a conductive bridge metal material selected from copper, copper-containing compounds or intermetallic alloys, tellurium, tellurium-containing compounds or intermetallic alloys, aluminum and aluminum-containing compounds or intermetallic alloys.

[0153] In some embodiments, a method of operating a memory device includes: providing a memory device including a field effect transistor and a variable capacitance capacitor, wherein the field effect transistor includes a gate structure having a gate dielectric and an intermediate electrode, and the variable capacitance capacitor includes a lower capacitor plate including the intermediate electrode, an upper capacitor plate including a control gate electrode, and a variable capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate, wherein a threshold voltage of the field effect transistor when the intermediate electrode is electrically floating depends on a dielectric state of the variable capacitance node dielectric; programming the dielectric state of the variable capacitance node dielectric to a state selected from a first dielectric state and a second dielectric state, the first dielectric state providing a first capacitance for the variable capacitance capacitor, and the second dielectric state providing a second capacitance for the variable capacitance capacitor; and sensing the dielectric state of the variable capacitance node dielectric by applying a sensing gate voltage between the first threshold voltage and the second threshold voltage to the control gate electrode.

[0154] In the above method, the variable capacitance node dielectric has a variable effective dielectric constant, the variable effective dielectric constant depends on the hysteresis effect of the electric field across the upper capacitor plate and the lower capacitor plate, and the method includes programming the variable capacitance node dielectric to the first state or the second state by applying an electric field across the upper capacitor plate and the lower capacitor plate.

[0155] In the above method, programming the dielectric state of the variable capacitor node dielectric includes: applying a programming voltage with a first polarity to the control gate electrode relative to the intermediate electrode; or applying an erasing voltage with a second polarity to the control gate electrode relative to the intermediate electrode, and the second polarity is opposite to the first polarity.

[0156] In the above method, the variable capacitor node dielectric includes a metal oxide material, which provides at least one of reversible electric field dependent resistivity modulation and reversible electric field dependent movement of metal atoms therein; and the first dielectric state and the second dielectric state provide different resistivities for the metal oxide material of the variable capacitor node dielectric.

[0157] In the above method, the variable capacitor node dielectric includes an oxygen vacancy modulated metal oxide material or a filament-forming metal oxide; the control gate electrode includes a transition metal or a conductive metal nitride material with a melting point greater than 1,000 degrees Celsius; and the method also includes changing the oxygen vacancy distribution within the variable capacitor node dielectric during programming of the dielectric state of the variable capacitor node dielectric.

[0158] In the above method, the variable capacitor node dielectric includes a metal oxide material, which provides reversible electric field-dependent movement of metal atoms therein; the control gate electrode includes a conductive bridge metal material selected from copper, copper-containing compounds or intermetallic alloys, tellurium, tellurium-containing compounds or intermetallic alloys, aluminum and aluminum-containing compounds or intermetallic alloys; and the method also includes changing the resistivity within the variable capacitor node dielectric during programming of the dielectric state of the variable capacitor node dielectric.

[0159] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A memory device comprising a field effect transistor and a variable capacitance capacitor, wherein: The field effect transistor comprises: a source region, a drain region, and a channel region within the semiconductor material layer; and a gate structure covering the channel region and comprising a gate dielectric and an intermediate electrode, and Wherein, the variable capacitance capacitor comprises: a lower capacitor plate including said intermediate electrode; an upper capacitor plate vertically spaced apart from the lower capacitor plate, wherein the upper capacitor plate includes a control gate electrode; and a variable capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate and comprising an electric field programmable dielectric material providing a variable effective dielectric constant, and a data bit is stored in the memory device as a dielectric state of the variable capacitance node dielectric; The memory device also includes a sensing circuit configured to: applying a voltage bias across the drain region and the source region during a sensing step; and During the sensing step a sensing gate voltage will be applied to the control gate electrode.

2. The memory device according to claim 1, wherein: The field effect transistor is a fin field effect transistor.

3. The memory device according to claim 1, wherein: The field effect transistor has two stable configurations, including: a first configuration, wherein the variable capacitance node dielectric has a first effective dielectric constant and the field effect transistor has a first threshold voltage; and A second configuration wherein the variable capacitance node dielectric has a second effective dielectric constant and the field effect transistor has a second threshold voltage, wherein the sense gate voltage is greater than the first threshold voltage and less than the second threshold voltage.

4. The memory device according to claim 1, further comprising: The middle electrode contacts the through-hole structure, contacting the top surface of the middle electrode; as well as The control electrode contacts the through-hole structure and contacts the top surface of the control gate electrode.

5. The memory device according to claim 4, further comprising: a programming circuit configured to apply a programming voltage having a first polarity to the control gate electrode relative to the intermediate electrode; as well as The erase circuit is configured to apply an erase voltage having a second polarity opposite to the first polarity to the control gate electrode relative to the intermediate electrode.

6. The memory device of claim 5, further comprising a ground switch connected to the middle electrode and configured to provide a state selected from the following to the middle electrode: The first state, where The intermediate electrode is electrically floating; and A second state, wherein the intermediate electrode is electrically grounded.

7. The memory device according to claim 6, wherein: The grounding switch is configured as: providing the first state to the intermediate electrode during a sensing operation; as well as The second state is provided to the intermediate electrode during a programming operation.

8. The memory device according to claim 1, further comprising a shallow trench isolation structure, wherein the shallow trench isolation structure laterally surrounds the source region, the drain region and the channel region, wherein: The intermediate electrode straddles the channel region and a portion of the shallow trench isolation structure, and the control gate electrode is located within the region of the portion of the shallow trench isolation structure and does not extend over the channel region.

9. A memory device comprising a transistor and a variable capacitance capacitor, wherein: The transistor comprises: A source region, a drain region and a channel region are within the semiconductor material layer; a gate structure covering the channel region and comprising a gate dielectric and an intermediate electrode, and Wherein, the variable capacitance capacitor comprises: a lower capacitor plate including said intermediate electrode; an upper capacitor plate vertically spaced apart from the lower capacitor plate, wherein the upper capacitor plate includes a control gate electrode; and a variable capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate and comprising a metal oxide material that provides reversible electric field dependent resistivity modulation; and A shallow trench isolation structure laterally surrounds the source region, the drain region and the channel region, wherein the entire upper capacitor plate is located within the region of the shallow trench isolation structure and outside the regions of the source region, the drain region and the channel region, and the lower capacitor plate includes a first portion located above the channel region and a second portion located below the upper capacitor plate.

10. The memory device according to claim 9, further comprising: The middle electrode contacts the through-hole structure, and contacts the top surface of the middle electrode.

11. The memory device according to claim 9, wherein: The metal oxide material of the variable capacitance node dielectric has two dielectric states determined by a hysteresis effect of a vertical electric field across the lower and upper capacitor plates.

12. The memory device according to claim 11, wherein: The two dielectric states of the variable capacitance node dielectric include: a first dielectric state having a first effective dielectric constant and a first resistivity; and A second dielectric state has a second effective dielectric constant different from the first effective dielectric constant and a second resistivity different from the first resistivity.

13. The memory device according to claim 9, wherein: The variable capacitance node dielectric comprises an oxygen vacancy modulated metal oxide material or a filament-formed metal oxide; and The control gate electrode includes a transition metal or a conductive metal nitride material having a melting point above 1,000 degrees Celsius.

14. The memory device according to claim 9, wherein: The variable capacitance node dielectric comprises a metal oxide material that provides reversible electric field dependent movement of metal atoms therein; and The control gate electrode includes a conductive bridge metal material selected from copper, copper-containing compounds or intermetallic alloys, tellurium, tellurium-containing compounds or intermetallic alloys, aluminum, and aluminum-containing compounds or intermetallic alloys.

15. A method of operating a memory device, comprising: A memory device is provided comprising a field effect transistor and a variable capacitance capacitor, wherein the field effect transistor comprises a gate structure having a gate dielectric and an intermediate electrode, and the variable capacitance capacitor comprises a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate, wherein a threshold voltage of the field effect transistor when the intermediate electrode is electrically floating depends on a dielectric state of the variable capacitance node dielectric; programming the dielectric state of the variable capacitance node dielectric to a state selected from a first dielectric state providing a first capacitance for the variable capacitance capacitor and a second dielectric state providing a second capacitance for the variable capacitance capacitor; and The dielectric state of the variable capacitance node dielectric is sensed by applying a sense gate voltage between a first threshold voltage and a second threshold voltage to the control gate electrode.

16. The method according to claim 15, wherein: The variable capacitance node dielectric has a variable effective dielectric constant that depends on a hysteresis effect of an electric field across the upper capacitor plate and the lower capacitor plate, and the method includes programming the variable capacitance node dielectric to the first dielectric state or the second dielectric state by applying an electric field across the upper capacitor plate and the lower capacitor plate.

17. The method according to claim 15, wherein: Programming the dielectric state of the variable capacitance node dielectric includes: applying a programming voltage having a first polarity to the control gate electrode relative to the intermediate electrode; or An erase voltage having a second polarity opposite to the first polarity is applied to the control gate electrode with respect to the intermediate electrode.

18. The method of claim 15, wherein: The variable capacitance node dielectric comprises a metal oxide material that provides at least one of reversible electric field dependent resistivity modulation and reversible electric field dependent movement of metal atoms therein; and The first dielectric state and the second dielectric state provide different resistivities for the metal oxide material of the variable capacitance node dielectric.

19. The method of claim 15, wherein: The variable capacitance node dielectric includes an oxygen vacancy modulated metal oxide material or a filament-forming metal oxide; The control gate electrode comprises a transition metal or a conductive metal nitride material having a melting point greater than 1,000 degrees Celsius; and The method also includes changing a distribution of oxygen vacancies within the variable capacitance node dielectric during programming the dielectric state of the variable capacitance node dielectric.

20. The method of claim 15, wherein: The variable capacitance node dielectric includes a metal oxide material that provides reversible electric field dependent movement of metal atoms therein; The control gate electrode comprises a conductive bridge metal material selected from copper, copper-containing compounds or intermetallic alloys, tellurium, tellurium-containing compounds or intermetallic alloys, aluminum and aluminum-containing compounds or intermetallic alloys; and The method also includes changing a resistivity within the variable capacitance node dielectric during programming the dielectric state of the variable capacitance node dielectric.

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