Optoelectronic devices and methods

Abstract

An optoelectronic device. The device comprises: a multilayer optically active stack comprising one or more layers comprising III‑V semiconductor materials; an input waveguide arranged to guide light into the stack; and an output waveguide arranged to guide light out of the stack. The multilayer optically active stack is butt- or edge-coupled to the input waveguide and the output waveguide.

Description

[0001] The present invention relates to optoelectronic devices and methods of forming optoelectronic devices.

[0002] The integration of silicon-based waveguide technology with III-V semiconductors offers the benefits of both material systems: the high-speed properties of III-V semiconductors and the manufacturability and stability of silicon-based waveguide technology.

[0003] However, integrating III-V semiconductors with silicon waveguides has proven to be technically challenging. Often, poor integration results in significant optical losses.

[0004] There exists, then, a need for optoelectronic devices and methods of fabricating the same that combine silicon-based waveguide technology and III-V semiconductors without incurring unacceptable optical losses.

[0005] Therefore, in a first aspect, an embodiment of the present invention provides an optoelectronic device, comprising:

[0006] a multilayer optically active stack comprising one or more layers comprising III-V semiconductor materials;

[0007] an input waveguide arranged to guide light into the stack; and

[0008] an output waveguide arranged to guide light out of the stack;

[0009] The multi-layer optically active stack is butt- or edge-coupled to the input waveguide and the output waveguide.

[0010] Advantageously, such optoelectronic devices exhibit low optical losses.

[0011] The optoelectronic component may have any one or any combination (provided they are compatible) of the following optional features.

[0012] An optoelectronic device may include a silicon substrate underlying a multilayer optically active stack.

[0013] The input and output waveguides can be formed from silicon nitride. This can further reduce the optical losses of the device.

[0014] The device may further include a first antireflective coating located between the input waveguide and the multilayer optically active stack, and the input waveguide may be directly adjacent to the first antireflective coating, and the first antireflective coating may be directly adjacent to the multilayer optically active stack.

[0015] The device may further include a second anti-reflective coating located between the output waveguide and the multilayer optically active stack, and the output waveguide may be directly adjacent to the second anti-reflective coating, and the second anti-reflective coating may be directly adjacent to the multilayer optically active stack. The first and / or second anti-reflective coating may be formed of a composition of silicon nitride having a refractive index greater than the refractive index of the silicon nitride core layer of the input waveguide or the output waveguide. The refractive index of the first and / or second anti-reflective coating may be at least 2.6 and not greater than 2.85. The first and / or second anti-reflective coating may have a respective length of at least 90 nm and not greater than 200 nm as measured parallel to the guiding direction of the input waveguide.

[0016] A multilayer optically active stack may be directly adjacent to the input waveguide and the output waveguide.

[0017] The refractive index of the core layers of the input waveguide and the output waveguide may be at least 1.9 and no greater than 2.35.

[0018] The multilayer optically active stack may include a buffer region and an optically active region. The buffer region mitigates the lattice constant mismatch between silicon and InP (or InGaAs), and the multilayer optically active stack is grown on the buffer region. The buffer region may include a crystalline rare oxide layer.

[0019] The device may further include an oxide cladding layer, which may be located directly between the input waveguide and the buffer layer or buried oxide layer.

[0020] The device may be an electroabsorption modulator (EAM). The EAM may utilize the quantum confined Stark effect (QCSE) or the Franz-Keldysh effect.

[0021] In a second aspect, an embodiment of the present invention provides a method for forming an optoelectronic device, comprising the following steps:

[0022] (a) blank growing a multi-layer optically active region on a substrate, wherein the multi-layer optically active region includes one or more layers formed of III-V semiconductor-based materials;

[0023] (b) patterning and etching the multi-layer optically active region to provide a multi-layer optically active stack; and

[0024] (c) depositing input and output waveguides adjacent to the stack, the stack being arranged so as to butt or edge couple the input and output waveguides to the multilayer optically active stack.

[0025] Advantageously, such an approach results in optoelectronic devices exhibiting lower optical losses.

[0026] The optoelectronic component may have any one or any combination (provided they are compatible) of the following optional features.

[0027] The input waveguide and the output waveguide may be formed from silicon nitride.

[0028] The method may further include, between steps (b) and (c), a step of depositing an anti-reflective coating around at least a portion of the stack. After depositing the anti-reflective coating, the method may include a step of etching the anti-reflective coating. The anti-reflective coating may be formed of a composition of silicon nitride having a refractive index greater than the refractive index of the silicon nitride core layer of the input waveguide or the output waveguide. The method may further include, after etching the anti-reflective coating, a step of depositing a bulk insulator onto the device. The method may further include, after depositing the bulk insulator, a step of etching the bulk insulator such that an upper surface of the bulk insulator is above an uppermost surface of a buffer layer of the optically active stack.

[0029] The step of blanket growing the multilayer optically active region may comprise an initial step of growing a buffer region and a subsequent step of growing the optically active region.The buffer region may comprise a crystalline rare earth oxide layer.

[0030] The method may further comprise the step of depositing a multilayer hard mask on top of the upper surface of the optically active stack between steps (a) and (b).The multilayer mask may comprise a silicon nitride layer and two insulator layers.

[0031] Patterning the optically active stack may include the step of depositing a photoresist over a portion of the upper surface of the optically active stack, which may be removed after the step of etching the optically active stack.

[0032] The substrate may be formed of silicon. The substrate may be a silicon-on-insulator layer of a silicon-on-insulator wafer.

[0033] The device may be an electroabsorption modulator (EAM). The EAM may utilize the quantum confined Stark effect (QCSE) or the Franz-Keldysh effect.

[0034] Other aspects of the present invention provide: a computer program comprising code, which when executed on a computer causes the computer to execute the method of the second aspect; a computer-readable medium storing a computer program comprising code, which when executed on a computer causes the computer to execute the method of the second aspect; and a computer system programmed to execute the method of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0036] Figure 1 A schematic top view of an optoelectronic device according to an embodiment of the present invention is shown;

[0037] Figure 2A yes Figure 1 A cross-sectional view of the device along line A-A';

[0038] Figure 2B yes Figure 1 A cross-sectional view of the device along line BB';

[0039] Figure 2C yes Figure 1 A cross-sectional view of the device along line C-C';

[0040] Figure 2D yes Figure 1 A cross-sectional view of the device along line D-D';

[0041] Figure 3A yes Figure 1 A cross-sectional view of a variation of the device along line AA';

[0042] Figure 3B yes Figure 1 A cross-sectional view of a variation of the device along line BB';

[0043] Figure 3C yes Figure 1 A cross-sectional view of a variation of the device along line CC';

[0044] Figure 3D yes Figure 1 A cross-sectional view of a variation of the device along line D-D';

[0045] Figure 4A yes Figure 1 A cross-sectional view of a variation of the device along line AA';

[0046] Figure 4B yes Figure 1 A cross-sectional view of a variation of the device along line BB';

[0047] Figure 4C yes Figure 1 A cross-sectional view of a variation of the device along line CC';

[0048] Figure 4D yes Figure 1 A cross-sectional view of a variation of the device along line D-D';

[0049] Figure 5A is a schematic cross section of a buffer region located above a silicon-on-insulator wafer;

[0050] Figure 5B It is located on the silicon substrate Figure 5A A schematic cross section of a buffer region;

[0051] Fig. 6A yes Figure 5A A schematic cross section of a buffer region and an SOI wafer and a multilayer optically active stack including a multi-quantum well layer;

[0052] Figure 6B yes Figure 5B A schematic cross section of a buffer region and a substrate and a multilayer optically active stack including a multiple quantum well layer;

[0053] Fig. 7A yes Figure 5A Schematic cross section of a buffer region and an SOI wafer and a multilayer optically active stack including bulk III-V layers;

[0054] Figure 7B yes Figure 5B Schematic cross section of a buffer region and substrate and a multilayer optically active stack including bulk III-V layers;

[0055] Fig. 8A is a schematic cross section of a modified buffer region including a crystalline rare earth oxide layer above an SOI wafer;

[0056] Figure 8B It is on the silicon substrate Fig. 8A A schematic cross section of a modified buffer region of ;

[0057] Fig.9A yes Fig. 8A A schematic cross section of a buffer region and an SOI wafer and a multilayer optically active stack including a multi-quantum well layer;

[0058] Fig. 9B yes Figure 8B A schematic cross section of a buffer region and a substrate and a multilayer optically active stack including a multiple quantum well layer;

[0059] Fig. 10A yes Fig. 8A Schematic cross section of a buffer region and an SOI wafer and a multilayer optically active stack including bulk III-V layers;

[0060] Fig. 10B yes Figure 8B A schematic cross section of a buffer region and a substrate and a multilayer optically active stack including bulk III-V layers; and

[0061] Figure 11(i)-1 1(xx')(B) shows various manufacturing steps of the method of an embodiment of the present invention. DETAILED DESCRIPTION

[0062] Aspects and embodiments of the present invention will now be discussed with reference to the accompanying drawings. Other aspects and embodiments will be apparent to those skilled in the art.

[0063] Figure 1 A schematic top view of an optoelectronic device 100 according to an embodiment of the present invention is shown. The device includes an input waveguide 101, which in this example is formed of silicon nitride (SiN). The input waveguide is coupled to an anti-reflective coating 102, which in this example is also formed of SiN but has a different composition. The anti-reflective coating is then coupled to a multilayer optically active stack 103, which includes one or more layers formed of III-V semiconductors. The multilayer optically active stack can be used to modulate optical signaling passing therethrough in a manner discussed in more detail below. The multilayer optically active stack is coupled to another anti-reflective coating 102 at an opposite end, which is coupled to an output waveguide 104. The output waveguide and anti-reflective coating are also formed of SiN.

[0064] The device 100 comprises a first electrode 105a and a second electrode 105b which may be connected to an electronic driver and used to impart a modulated signal onto an optical signal present in a multi-layer optically active stack. In this example, the electrodes are made of aluminum.

[0065] Figure 2A yes Figure 1 1-4 is a cross-sectional view of the device 100 along line A-A'. As can be seen in more detail, the anti-reflective coating extends on opposite lateral sides of the multilayer optically active stack. Also of note is the buffer layer 108, which is adjacent to the silicon substrate 109 and is located between the silicon substrate and the multilayer optically active stack 103. The buffer layer is used to mitigate the lattice constant mismatch between the silicon substrate and the bottom layer of the multilayer optically active stack to provide better crystal quality to the multilayer optically active stack and to reduce crystal defects. Also shown in this view are the upper cladding 106 and the lower cladding 107, which cover both the input waveguide 101 and the output waveguide 104. The cladding is composed of silicon dioxide (SiO2) in this example.

[0066] In use, light enters the device 100 into the input waveguide 101. It is then guided through the input waveguide along the "x" direction and then coupled into the multilayer optically active stack 103 via the anti-reflective coating 102. A modulating signal may then be applied, for example, to modify the phase or amplitude of the signal, before the signal is then coupled out of the multilayer optically active stack 103 via another anti-reflective coating 102 and into the output waveguide 104.

[0067] Figure 2B yes Figure 11 is a cross-sectional view of the device along line BB'. This view shows the input waveguide 101 in more detail (note that the structure of the input waveguide substantially matches the structure of the output waveguide 104). The input waveguide is formed of a slab region, and a ridge or rib region extending away from the slab region in the "y" direction. In this example, the input waveguide is formed of silicon nitride, which has a refractive index of about 2.2. In addition, in this example, the slab has a height of about 0.4 μm (as measured from the uppermost surface of the lower cladding 107 to the uppermost surface of the slab). The ridge or rib has a height of about 0.6 μm, so that the height of the waveguide including the ridge and the slab is about 1 μm.

[0068] Figure 2C yes Figure 1 1 is a cross-sectional view of the device along line CC'. This view shows in more detail the anti-reflection coating 102 located between the input waveguide and the multilayer optically active stack (note that the structure of this coating is essentially the same as the other anti-reflection coatings between the stack and the output waveguide). The anti-reflection coating 103 essentially matches the input waveguide 101 in geometry, except that it does not extend as far in the "x" direction. The anti-reflection coating in this example is formed of silicon nitride, which has a refractive index of about 2.8.

[0069] Figure 2D yes Figure 1 1 . A cross-sectional view of a device of FIG. 1 along line D-D' is shown in FIG. 1 . This view shows the multilayer optically active stack 103 in more detail. As can be seen, the first electrode 105a extends through a via in the upper cladding layer 106 so as to electrically contact one layer of the multilayer optically active stack. Similarly, the second electrode 105b extends on the sidewall of the stack and through a second via in the upper cladding layer 106 so as to electrically contact a different layer of the multilayer optically active stack.

[0070] Figure 3A yes Figure 1 A cross-sectional view of a variation of the device 300 taken along line AA'. Figure 3B is a cross-sectional view of the modified device 300 along line BB′. Figure 3C 3 is a cross-sectional view of the modified device 300 along line CC′. Figure 3D is a cross-sectional view of the modified device 300 along line DD′.

[0071] exist Figures 3A-3D Where the variant device 300 shown in FIG. 1 shares features with the previously shown device 100, like features are indicated by like reference numerals. Primarily, the device 300 differs in that the buffer layer 108 is located atop a silicon-on-insulator (or device) layer 301. The SOI layer is above a buried oxide layer 302, which is atop a silicon substrate 109.

[0072] Figure 4A yes Figure 1 A cross-sectional view of a variation of the device 400 along line AA'. Figure 4B is a cross-sectional view of the modified device 400 along line BB′. Figure 4C is a cross-sectional view of the modified device 400 along line CC′. Figure 4D 4 is a cross-sectional view of a variant of the variant device 400 along line DD′.

[0073] exist Figures 4A-4D Where the variant device 400 shown in FIG. 4 shares features with the previously shown device 100, like features are indicated by like reference numerals. The device 400 differs in that the silicon device layer 301 has been selectively etched so as to be confined to the region between only the anti-reflective coatings 102. Thus, the buried oxide layer 302 is directly adjacent to the lower cladding layer 107.

[0074] Figure 5A is a schematic cross section of a buffer region located above a silicon-on-insulator wafer. As previously described, the SOI wafer includes a silicon substrate 109, a buried oxide layer 302, and a silicon device layer 301. In this example, the buffer region includes the following layers from the top layer downward: an indium gallium arsenide (InGaAs) or indium phosphide (InP) layer 501; a graded indium arsenide aluminum (InA) layer 502; x Al 1- x As) layer 502, whose lattice constant changes linearly (or stepwise) from the lattice constant of GaAs to the lattice constant of InP, where x changes from about 0.03 to about 0.60 and then back to about 0.52, at which InP x Al 1-x Gallium arsenide (GaAs) layer 503; and germanium (Ge) layer 504. The combination of layers 501-504 may be referred to as a buffer region or buffer layer because together they act as a buffer layer for subsequently grown materials. Figure 5B is located above the silicon substrate 109 Figure 5A Schematic cross section of the buffer area.

[0075] Fig. 6A yes Figure 5A Schematic cross section of buffer regions 501-504 and SOI wafer and a multilayer optically active stack including a multi-quantum well layer. The multilayer optically active stack includes the following layers from the top layer downwards: p-doped InGaAs layer 601; p-doped InP layer 602; multi-quantum well layer based on III-V semiconductor 603; and n-doped InP layer 604. Figure 6B yes Figure 5B The buffer region and substrate and including Fig. 6A Schematic cross section of a multilayer optically active stack of the discussed multiple quantum well layers.

[0076] Fig. 6A and 6B The multilayer optically active stack in can have the following components:

[0077]

[0078] Layers 2-5 form a buffer region or layer 108, and layer 4 is a graded buffer layer. R is the number of times the layer is repeated.

[0079] Fig. 6A and 6B The multilayer optically active stack in can have the following components:

[0080]

[0081] In this example, layers 2 and 3 form a buffer region or buffer layer. R is the number of times the layer is repeated.

[0082] Fig. 7A yes Figure 5A Schematic cross section of a buffer region and SOI wafer and a variant multilayer optically active stack including bulk III-V layers. In contrast to the quantum confined Stark effect example, bulk III-V layers can exploit the Franz-Keldysh effect to fabricate polarization-independent electro-absorption modulators (EAMs). The multilayer optically active stack comprises the following layers from the topmost layer downwards: p-doped InGaAs layer 701; p-doped InP layer 702; bulk layer based on III-V semiconductor 703; and n-doped InP layer. Figure 7B yes Figure 5B Schematic cross section of a buffer region and substrate and a variant multilayer optically active stack. Fig. 7A and 7B A variant in which the multilayer optically active stack can have the following composition:

[0083]

[0084] Layers 1-5 form the buffer region or buffer layer discussed above. Layer 4 formed of InAlAs is a graded buffer layer.

[0085] Fig. 8A 80 is a schematic cross section of a modified buffer region including a crystalline rare earth oxide layer above a SOI wafer. The modified buffer region includes two layers: an indium phosphide layer 801 and a crystalline rare earth oxide (CREO) layer 802. The CREO layer is below the InP layer and adjacent to the silicon device layer 301 in this example. Figure 8B is on the silicon substrate 109 Fig. 8ASchematic cross section of a modified buffer area.

[0086] Fig.9A yes Fig. 8A Schematic cross section of a buffer region and an SOI wafer and a multilayer optically active stack comprising layers 601 to 604. Fig. 9B yes Figure 8B Schematic cross section of a buffer region and a substrate and a multilayer optically active stack including layers 601 to 604.

[0087] Fig.9A and 9B The multilayer optically active stack in can have the following components:

[0088]

[0089] Layers 2 and 3 form the aforementioned buffer region or buffer layer.

[0090] Fig. 10A yes Fig. 8A Schematic cross section of a buffer region and an SOI wafer and a variant multilayer optically active stack including layers 701 - 704 . Fig. 10B yes Figure 8B Schematic cross section of a buffer region and substrate and a variant multilayer optically active stack including layers 701 - 704 .

[0091] Fig.9A and 9B A variant in which the multilayer optically active stack can have the following composition:

[0092]

[0093] Figure 11(i)-1 1(xx')(B) shows various manufacturing steps of the method of an embodiment of the present invention. Figure 11(i)-1 The multilayer optically active stack, buffer region, and platform (i.e., substrate) shown in FIG. Figure 6B The optically active layers shown in the drawings are substantially matched to those shown in the drawings, but any of the multilayer optically active stacks, buffer regions or layers, or platforms shown herein may be substituted. That is, the manufacturing steps shown are applicable to any of the buffer types, multilayer optically active stacks, and platforms disclosed herein.

[0094] In the first step, as shown in FIG11(i), a silicon substrate 109 is provided. If, for example, Figure 5A11( ii ) , a buffer region or buffer layer 108 is epitaxially grown from the exposed upper surface of the silicon substrate. Subsequently, in the step shown in FIG. 11( iii ), a multilayer optically active region 852 is epitaxially grown from the exposed upper surface of the buffer region 108. Next, a silicon dioxide layer 901, silicon nitride 902, and an additional silicon dioxide 901 layer are deposited in this order on top of the exposed upper surface of the multilayer optically active region 852. The result is shown in FIG. 11( iv ).

[0095] Next, in the step shown in Figure 11(v)(A), a photoresist 903 is deposited and patterned so as to define a multilayer optically active stack 103. Figure 11(v)(B) shows the same step from a top-down perspective in the first example, and Figure 11(v')(B) shows a variation of the step in the second example. In both examples, the lateral sides of the photoresist are angled α relative to the "z" direction. In this example, the angle α has a value of approximately 8°. In the first example, the patterned photoresist 903 has a parallelogram geometry. In the second example, a gap is formed in a portion of the photoresist so that the photoresist has an inverted "U" shape.

[0096] After providing the photoresist, etching is performed down to the GaAs layer of the buffer region or the graded InAlAs layer of the buffer region, depending on the buffer region thickness and the subsequent lower cladding 107 thickness. Typically, the input and output waveguides should not experience optical losses caused by the lower cladding thickness. The result of this etching is shown in cross section in FIG. 11(vi)(A), whereby the multilayer optically active stack 103 has now been defined. FIG. 11(vi)(B) shows the first optically active stack 103 from a top view. one Example 1 and Figure (vi')(B) shows the same steps in a second example from a top view. In both examples, the upper silicon dioxide layer 901 has been omitted for clarity.

[0097] Next, in the step shown in FIG11(vii), a silicon-rich silicon nitride anti-reflective coating 102 is deposited on all exposed surfaces of the device. As shown in the figure, the anti-reflective coating is present not only on the sidewalls of the multilayer optically active stack 103, but also on the upper surface of the upper silicon dioxide layer 901 and also on the upper surface of the exposed buffer region. An anisotropic etching process is then used to remove all of the anti-reflective coating except for those portions 102 on the sidewalls of the multilayer optically active stack 103. The result of this anisotropic etching process is shown in FIG11(viii).

[0098] Subsequently, in the step shown in FIG. 11( ix), additional silicon dioxide 901 is deposited over the device. The deposition provides a silicon dioxide 901 region that extends entirely around the antireflective coating 102 and the multilayer optically active stack 103. In the second example mentioned in FIG. 11( vi')(B), this step also provides a spacer 906, which is discussed in more detail below. Next, in the step shown in FIG. 11( x), a chemical mechanical planarization (CMP) process is performed so that the uppermost surface of the silicon dioxide 910 region is aligned with the uppermost surface of the upper silicon nitride layer 902. Note that this includes the removal of the upper silicon dioxide layer shown previously.

[0099] After this CMP process, a further etch is performed so that the silicon dioxide regions provide the lower cladding 107. The height of the etch depends on the subsequently formed input / output waveguides and mode centres of the multilayer optically active stack 103. The result of the further etch is shown in Figure 11 (xi).

[0100] After a further etching step, in the step shown in FIG. 11 (xii), silicon nitride 902 is deposited in the same manner as silicon dioxide. That is, the deposition provides a silicon nitride region 902 that extends entirely around the anti-reflective coating 102 and the exposed area of ​​the multilayer optically active stack 103. Next, in the step shown in FIG. 11 (xiii), a CMP process is used to align the uppermost surface of the silicon nitride region 902 with the uppermost surface of the lower silicon dioxide layer 901. It is noted that this includes the removal of the previously mentioned silicon nitride layer 902. After the CMP process, a further etch is performed so as to define the height of the input and / or output waveguide. The height of the etch is selected so as to maximize the coupling efficiency between the input and / or output waveguide and the multilayer optically active stack. The result of the etching is shown in FIG. 11 (xiv).

[0101] After the silicon nitride 902 regions have been etched, further silicon dioxide 901 is deposited over the device and then planarised. This is shown in Figure 11 (xv).

[0102] Next, the multilayer optically active stack is partially etched down to the doped layer on either side of the core region to form an optically active stacked waveguide, and the input and output waveguides are also partially etched to form ridges or ribs with self-alignment. Figure 11 (xvi) shows the photoresist 903 used for this etching step, and Figures 11 (xvii) (A) and (B) are cross-sections along lines A-A' and B-B', respectively. It should be noted that, as shown in Figure 11 (xvii) (B), the etching is performed so that the upper surface of the doped layer 905 of the multilayer optically active stack is exposed. In this example, it is an n-doped indium phosphide layer. Figures 11 (xvii) (D) and (E) show the input waveguide and the anti-reflection layer cross-section along the lines C-C' and D-D' in Figure 11 (xvii) (C) in the input side of the optically active stacked waveguide, and the same cross-sections are also in the output side of the optically active stacked waveguide.

[0103] Alternatively, in a second example discussed with reference to FIG. 11(vi')(B), the multilayer optical stack is partially etched down to the doped layer 905 on one side of the core region. This is shown in FIGS. 11(xvii') and 11(xvii')(A)-(B), which are cross-sections along lines A-A' and B-B'. As shown in FIG. 11(xvii')(B), etching is performed so that the upper surface of the doped layer 905 on one side of the multilayer optically active stack is exposed. On the other hand, the previously provided isolation pad 906 serves as an etching stop. A small area of ​​the doped layer 905 can be exposed on the same side as the isolation pad 906.

[0104] Figure 11(xviii) and 11(xviii)(A) -(B) shows a step which is performed only for the first example and skipped in the second example. In this step, additional silicon dioxide is provided which defines the upper cladding layer 106. Etching is then performed through this silicon dioxide and also through the doped layer 905, and partially into the subsequently exposed layer 907 of the buffer region. The result of this etching is most clearly shown in Figure 11(xviii)(B), which is a cross section along the line BB' shown in Figure 11(xviii).

[0105] In either example, the steps of depositing additional silicon dioxide and etching one or more vias 908 are performed. Figure 11(xix) and 11(xix)(A) -(B) is shown. Figure 11(xix)(A) and 11(xix)(B)As most clearly shown in FIG. 11( a ) and FIG. 11( b ) (which are cross-sections along lines A-A' and BB' of FIG. 11( xix ) respectively), one through hole 908 is formed above the uppermost layer of the multilayer optically active stack 103, and another through hole 908s is formed above the doped layer 905. FIG. 11( xix )(B) is a cross-section of the first example, and FIG. 11( xix ')(B) is a cross-section of the second example.

[0106] After providing the through hole 908, a metallization process is performed to provide the first electrode 105a and the second electrode 105b discussed previously. Figure 11 (xx) shows the result of this metallization process from a top view. Figure 11 (xx) (A) is a cross-section along the line A-A' of Figure 11 (xx). Figure 11 (xx) (B) is a cross-section along the line BB' of Figure 11 (xx) for the first example, and Figure 11 (xx') (B) is a cross-section along the line BB' of Figure 11 (xx) for the second example.

[0107] Although the present invention has been described in conjunction with the above exemplary embodiments, many equivalent modifications and variations will be apparent to those skilled in the art when this disclosure is given. Therefore, the exemplary embodiments of the present invention set forth above are considered to be illustrative rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the present invention.

[0108] Features

[0109] 100, 300, 400 Optoelectronic Devices

[0110] 101 Input waveguide

[0111] 102 Anti-reflective coating

[0112] 103 Multilayer Optically Active Stacks

[0113] 104 Output waveguide

[0114] 105a, b electrodes

[0115] 106 Upper cladding

[0116] 107 Lower cladding

[0117] 108 Buffer layer

[0118] 109 Substrate

[0119] 301 SOI layer

[0120] 302 buried oxide layer

[0121] 501-504 Buffer layer

[0122] 601-604 III-V semiconductor stacking layer

[0123] 701-704 III-V semiconductor stacking layer

[0124] 801-802 Buffer layer

[0125] 852 Multilayer optically active region

[0126] 901 SiO2

[0127] 902 SiN

[0128] 903 Photoresist

[0129] 905 Doped Layers of Multilayer Optically Active Stacks

[0130] 906 Isolation Pad

[0131] 907 Exposed layer in buffer area

[0132] 908 Through hole

Claims

1. An optoelectronic device, comprising: a multilayer optically active stack comprising a crystalline rare earth oxide layer and an optically active region, wherein the optically active region comprises one or more layers comprising a III-V semiconductor material, and the crystalline rare earth oxide layer is used to mitigate a lattice constant mismatch between a silicon substrate and a bottom layer of the multilayer optically active stack; an input waveguide arranged to guide light into the stack; an output waveguide arranged to guide light out of the stack; as well as an oxide cladding layer directly between the crystalline rare earth oxide layer and the input waveguide, the upper surface of the oxide cladding layer being above the uppermost surface of the crystalline rare earth oxide layer; a first antireflective coating located between the input waveguide and the multilayer optically active stack, and wherein the input waveguide is directly adjacent to the first antireflective coating and the first antireflective coating is directly adjacent to the multilayer optically active stack, the first antireflective coating being formed of a composition of silicon nitride having a refractive index greater than a refractive index of a silicon nitride core layer of the input waveguide; Wherein the multilayer optically active stack is butt- or edge-coupled to the input waveguide and the output waveguide.

2. The optoelectronic device of claim 1, wherein the input waveguide and the output waveguide are formed of silicon nitride.

3. The optoelectronic device of claim 1 , further comprising a second antireflective coating located between the output waveguide and the multilayer optically active stack, and wherein the output waveguide is directly adjacent to the second antireflective coating and the second antireflective coating is directly adjacent to the multilayer optically active stack.

4. The optoelectronic device of claim 3, wherein the second antireflection coating is formed of a composition of silicon nitride having a refractive index greater than a refractive index of a silicon nitride core layer of the output waveguide. 5 . The optoelectronic device according to claim 3 , wherein the refractive index of the first and / or the second antireflection coating is at least 2.6 and not greater than 2.

85.

6. The optoelectronic device of claim 3, wherein the first and / or the second antireflection coating has a respective length, as measured parallel to the guiding direction of the input waveguide, of at least 90 nm and not more than 200 nm.

7. An optoelectronic device according to claim 1 or claim 2, wherein the multilayer optically active stack is directly adjacent to the output waveguide.

8. The optoelectronic device of claim 1, wherein the refractive index of the core layers of the input waveguide and the output waveguide is at least 1.9 and not more than 2.

35.

9. The optoelectronic device of claim 1, wherein the multilayer optically active stack comprises graded layers of III-V semiconductor material.

10. The optoelectronic device of claim 1, wherein the multi-layer optically active stack comprises a multiple quantum well layer formed of a III-V semiconductor material.

11. The optoelectronic device of claim 1 , further comprising an oxide cladding layer directly between the input waveguide and a buffer layer or a buried oxide layer.

12. A method for forming an optoelectronic device, comprising the steps of: (a) blanket growing a multilayer optically active region on a substrate, wherein the multilayer optically active region comprises one or more layers formed of III-V semiconductor materials, wherein the step of blanket growing the multilayer optically active region comprises an initial step of growing a crystalline rare earth oxide layer, and a subsequent step of growing the optically active region, and the crystalline rare earth oxide layer is used to mitigate the lattice constant mismatch between the substrate and the bottom layer of the multilayer optically active region; (b) patterning and etching the multilayer optically active region to provide a multilayer optically active stack; as well as (c) depositing an input waveguide and an output waveguide adjacent to the stack, the stack being arranged so as to butt or edge couple the input waveguide and the output waveguide to the multilayer optically active stack; The method further comprises, between steps (b) and (c), the step of depositing an antireflective coating around at least a portion of the stack and the step of etching the antireflective coating, wherein the antireflective coating is formed of a composition of silicon nitride having a refractive index greater than a refractive index of a silicon nitride core layer of the input waveguide or the output waveguide; The method further comprises the steps of depositing an oxide cladding material onto the crystalline rare earth oxide layer and etching the oxide cladding material after etching the antireflective coating so that an upper surface of the oxide cladding material is above an uppermost surface of the crystalline rare earth oxide layer; and Wherein depositing the input waveguide comprises depositing silicon nitride directly on the oxide cladding material, and the deposited silicon nitride is etched to form the input waveguide.

13. The method of claim 12, wherein the input waveguide and the output waveguide are formed of silicon nitride.

14. The method of claim 12, further comprising the step of depositing a multi-layer hard mask on top of the upper surface of the optically active stack between steps (a) and (b).

15. The method of claim 14, wherein the multi-layer hard mask comprises a silicon nitride layer and two insulator layers.

16. The method of claim 12, wherein patterning the optically active stack comprises the step of depositing a photoresist over a portion of an upper surface of the optically active stack, which is removed after the step of etching the optically active stack.

17. The method of claim 12, wherein the substrate is formed of silicon.

18. The method of claim 12, wherein the substrate is a silicon-on-insulator layer of a silicon-on-insulator wafer.

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