Power management circuit, method for generating pixel power supply voltage, and display device

Abstract

The present application discloses a power management circuit, a method for generating a pixel power supply voltage, and a display device. The power management circuit includes: a boost converter that generates a boosted voltage at a boost node by boosting an input voltage using a reference boost voltage; a voltage regulator coupled to the boost node and an output node; a bypass transistor coupled between the boost node and the output node; and a regulator control block that compares the input voltage with a reference input voltage. When the input voltage is higher than or equal to the reference input voltage, the regulator control block increases the reference boost voltage to increase the boosted voltage, enables the voltage regulator to generate a regulated voltage by regulating the increased boosted voltage, turns off the bypass transistor so that the regulated voltage is output as the pixel power supply voltage at the output node, and maintains the voltage regulator in an enabled state for a minimum enable time.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device, and more particularly, to a power management circuit for supplying a pixel power supply voltage to pixels of a display panel, a method of generating the pixel power supply voltage, and a display device including the power management circuit. Background Art

[0002] The display device may include a power management circuit that generates a power supply voltage suitable for driving the display panel based on an input voltage such as a battery voltage or a system voltage. For example, the power management circuit may generate a pixel power supply voltage supplied to pixels of the display panel by performing a voltage boost operation on the input voltage. Summary of the Invention

[0003] In a display device in which a power management circuit generates a pixel power supply voltage supplied to pixels of a display panel by performing a boost operation on an input voltage, if the input voltage fluctuates due to noise, etc., the pixel power supply voltage generated by the power management circuit may fluctuate. Specifically, if the input voltage has a voltage level higher than a desired voltage level of the pixel power supply voltage, the boost operation may not be performed normally, and a pixel power supply voltage having a desired voltage level may not be generated.

[0004] Embodiments provide a power management circuit capable of generating a pixel supply voltage having a desired voltage level for a wide range of input voltages.

[0005] Embodiments provide methods of generating pixel supply voltages having desired voltage levels for a wide range of input voltages.

[0006] Embodiments provide a display device including a power management circuit capable of generating a pixel supply voltage having a desired voltage level for a wide range of input voltages.

[0007] According to an embodiment, a power management circuit for supplying a pixel power supply voltage to pixels of a display panel includes: a boost converter that generates a boosted voltage at a boost node by boosting an input voltage using a reference boost voltage; a voltage regulator coupled to the boost node and an output node; a bypass transistor coupled between the boost node and the output node; and a regulator control block that receives an input voltage, outputs a reference boost voltage, and controls the voltage regulator and the bypass transistor, wherein the regulator control block compares the input voltage with a reference input voltage. In such an embodiment, when the input voltage is greater than or equal to the reference input voltage, the regulator control block increases the reference boost voltage to increase the boosted voltage, enables the voltage regulator to generate a regulated voltage by regulating the increased boosted voltage, turns off the bypass transistor so that the regulated voltage is output as the pixel power supply voltage at the output node, and maintains the voltage regulator in an enabled state for a minimum activation time.

[0008] In an embodiment, when the input voltage is lower than the reference input voltage, the regulator control block may disable the voltage regulator and may turn on the bypass transistor so that the boosted voltage is output as the pixel power supply voltage at the output node.

[0009] In an embodiment, the regulator control block may generate a regulator enable signal having a first voltage level when the input voltage is lower than a reference input voltage, and may generate a regulator enable signal having a second voltage level when the input voltage is higher than or equal to the reference input voltage.

[0010] In an embodiment, the voltage regulator may be disabled in response to a regulator enable signal having a first voltage level, and the voltage regulator may be enabled in response to a regulator enable signal having a second voltage level.

[0011] In an embodiment, the bypass transistor may be turned on in response to a regulator enable signal having a first voltage level to connect the boost node to the output node, and the bypass transistor may be turned off in response to a regulator enable signal having a second voltage level to disconnect the boost node from the output node.

[0012] In one embodiment, the regulator control block may include: an input voltage sensing block that senses an input voltage and compares the input voltage with a reference input voltage; and a timing control block that counts a time period starting from a point in time when the voltage regulator is enabled. In such an embodiment, when the input voltage is higher than or equal to the reference input voltage, the regulator control block may generate a regulator enable signal having a second voltage level, may maintain the regulator enable signal at the second voltage level until the counted time period reaches a minimum enable time, and may change the regulator enable signal from the second voltage level to the first voltage level when the input voltage becomes lower than the reference input voltage after the counted time period reaches the minimum enable time.

[0013] In an embodiment, before the counted time period becomes the shortest enable time, when the input voltage becomes higher than or equal to the reference input voltage again, the timing control block may reset the counted time period and may count the time period again.

[0014] In an embodiment, the shortest enable time may correspond to one frame period of the display panel.

[0015] In an embodiment, the minimum enable time may be approximately 16 ms.

[0016] In an embodiment, the voltage regulator may be a low dropout regulator.

[0017] In an embodiment, the voltage regulator may include: a switch coupled between a boost node and an output node; a voltage divider coupled to the output node and generating a regulator feedback voltage by dividing the regulated voltage; and an amplifier controlling the switch by comparing the regulator feedback voltage with a reference regulator voltage.

[0018] In an embodiment, a boost converter may include: an inductor receiving an input voltage; a capacitor coupled to a boost node; a p-type transistor coupled between the inductor and the boost node; an n-type transistor coupled between the inductor and a ground voltage; a boost voltage divider coupled to the boost node and generating a boost feedback voltage by dividing the boosted voltage; an error amplifier amplifying a difference between the boost feedback voltage and a reference boost voltage; a comparator comparing an output signal of the error amplifier with a ramp voltage; and a switch control block generating a first switching signal and a second switching signal for controlling the p-type transistor and the n-type transistor, respectively, based on an output signal of the comparator.

[0019] In an embodiment, the power management circuit may further comprise an inverting buck-boost converter to convert the input voltage into a negative pixel supply voltage for the pixel; and an additional boost converter to convert the input voltage into an analog supply voltage.

[0020] According to an embodiment, a method for generating a pixel power supply voltage to be supplied to pixels of a display panel includes: comparing an input voltage with a reference input voltage; generating a boosted voltage by boosting the input voltage using a reference boost voltage when the input voltage is lower than the reference input voltage; outputting the boosted voltage as a pixel power supply voltage when the input voltage is lower than the reference input voltage; increasing the reference boost voltage when the input voltage is higher than or equal to the reference input voltage; generating an increased boosted voltage by boosting the input voltage using the increased reference boost voltage when the input voltage is higher than or equal to the reference input voltage; generating a regulated voltage at a voltage regulator by regulating the increased boosted voltage when the input voltage is higher than or equal to the reference input voltage; outputting the regulated voltage as the pixel power supply voltage when the input voltage is higher than or equal to the reference input voltage; and maintaining an enabled state of the voltage regulator for a minimum enabled time when the input voltage is higher than or equal to the reference input voltage.

[0021] In an embodiment, outputting the boosted voltage as the pixel power supply voltage may include: disabling a voltage regulator; and turning on a bypass transistor coupled between the boosting node and the output node.

[0022] In an embodiment, outputting the regulated voltage as the pixel power supply voltage may include: enabling a voltage regulator; and turning off a bypass transistor coupled between the boost node and the output node.

[0023] In an embodiment, maintaining the enabled state of the voltage regulator for the shortest enabled time may include: counting a time period starting from a time point when the voltage regulator is enabled; and maintaining the enabled state of the voltage regulator until the counted time period becomes the shortest enabled time.

[0024] In an embodiment, the method may further include disabling the voltage regulator when the input voltage becomes lower than the reference input voltage after the counted time period becomes the shortest enable time.

[0025] In an embodiment, the method may further include resetting the counted time period when the input voltage becomes higher than or equal to the reference input voltage again before the counted time period becomes the shortest enable time.

[0026] According to an embodiment, a display device includes: a display panel including pixels; a data driver that provides data signals to the pixels; a scan driver that provides scan signals to the pixels; a controller that controls the data driver and the scan driver; and a power management circuit that supplies a pixel power supply voltage to the pixels. In such an embodiment, the power management circuit includes: a boost converter that generates a boosted voltage at a boost node by boosting an input voltage using a reference boost voltage; a voltage regulator coupled to the boost node and an output node; a bypass transistor coupled between the boost node and the output node; and a regulator control block that receives an input voltage, outputs a reference boost voltage, and controls the voltage regulator and the bypass transistor. The regulator control block compares the input voltage with a reference input voltage. In such an embodiment, when the input voltage is greater than or equal to the reference input voltage, the regulator control block increases the reference boost voltage to increase the boosted voltage, enables the voltage regulator to generate a regulated voltage by regulating the increased boosted voltage, turns off the bypass transistor so that the regulated voltage is output as the pixel power supply voltage at the output node, and maintains the voltage regulator in an enabled state for a minimum enable time.

[0027] As described above, in embodiments of the power management circuit, method for generating a pixel supply voltage, and display device according to the present invention, when the input voltage is higher than or equal to the reference input voltage, the boosted voltage can be increased, the voltage regulator can be enabled to generate a regulated voltage by regulating the increased boosted voltage, the regulated voltage can be output as the pixel supply voltage, and the enabled state of the voltage regulator can be maintained for the shortest possible time. Thus, a pixel supply voltage having a desired voltage level can be generated for a wide range of input voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating a power management circuit according to an embodiment.

[0030] Figure 2 is a schematic circuit diagram illustrating a power management circuit according to an embodiment.

[0031] Figure 3 is a flowchart illustrating a method of generating a pixel power supply voltage according to an embodiment.

[0032] Figure 4 is a signal timing diagram illustrating the operation of an embodiment of a power management circuit as the input voltage fluctuates during a battery charging period.

[0033] Figure 5is a signal timing diagram illustrating the operation of an embodiment of a power management circuit when the input voltage fluctuates due to touch noise.

[0034] Figure 6A is a diagram illustrating input voltage and pixel power supply voltage in a conventional power management circuit, and Figure 6B is a diagram illustrating input voltages and pixel power supply voltages in a power management circuit according to an embodiment.

[0035] Figure 7 is a block diagram illustrating a power management circuit according to an alternative embodiment.

[0036] Figure 8 is a block diagram illustrating a display device including a power management circuit according to an embodiment.

[0037] Figure 9 is a block diagram illustrating an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0038] The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0039] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0040] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, the "first element," "first component," "first region," "first layer," or "first portion" discussed below may be referred to as a second element, second component, second region, second layer, or second portion without departing from the teachings herein.

[0041] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to be limiting. As used herein, "one", "the (or described)" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" is not interpreted as limiting "one". "Or" refers to "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It will be further understood that when used in this specification, the terms "include" and / or "comprising" and their variations specify the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0042] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientations depicted in the figures. For example, if the device in a figure is flipped, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, depending on the particular orientation of the figure, the term "lower" may encompass both "lower" and "upper" orientations. Similarly, if the device in a figure is flipped, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Thus, the term "below" or "below" may encompass both upper and lower orientations.

[0043] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 is a block diagram illustrating a power management circuit according to an embodiment.

[0047] See also Figure 1 Embodiments of the power management circuit 100 can generate a pixel power supply voltage ELVDD based on an input voltage VIN and can supply the pixel power supply voltage ELVDD to pixels of a display panel. In embodiments, the input voltage VIN can be, but is not limited to, a battery voltage or a system voltage. In embodiments, the pixel power supply voltage ELVDD can be, but is not limited to, a high power supply voltage supplied to the pixels.

[0048] In one embodiment, for example, the input voltage VIN may have a normal input voltage within a range of, but not limited to, approximately 3.4 volts (V) to approximately 4.4 V, and the pixel supply voltage ELVDD may be, but not limited to, approximately 4.6 V. Therefore, in such an embodiment, the power management circuit 100 may generate a pixel supply voltage ELVDD of approximately 4.6 V by performing a boost operation on the input voltage VIN of approximately 4.4 V. In such an embodiment, the input voltage VIN may fluctuate during a period when the battery is being charged or due to touch noise generated when the touch screen is touched, and the input voltage VIN may have a voltage level that is close to or higher than the desired voltage level of the pixel supply voltage ELVDD (e.g., approximately 4.6 V). When the input voltage VIN has a voltage level that is higher than or equal to the desired voltage level of the pixel supply voltage ELVDD, a conventional power management circuit may not perform a boost operation properly, and the pixel supply voltage ELVDD of the desired voltage level (e.g., approximately 4.6 V) may not be generated in the conventional power management circuit.

[0049] In an embodiment of the present invention, the power management circuit 100 can operate in a regulator bypass mode when the input voltage VIN is lower than a reference input voltage, and can operate in a regulator enable mode when the input voltage VIN is higher than or equal to the reference input voltage. Therefore, the power management circuit 100 can generate a pixel supply voltage ELVDD having a desired voltage level for a wide range of input voltages VIN, including input voltages VIN having a voltage level higher than a desired voltage level. In an embodiment, the power management circuit 100 can include a boost converter 110, a voltage regulator 130, a bypass transistor 150, and a regulator control block 170 to generate a pixel supply voltage ELVDD having a desired voltage level for a wide range of input voltages VIN.

[0050] The boost converter 110 can generate a boosted voltage VBST at a boost node NBST by boosting the input voltage VIN using a reference boost voltage VREF_BST. In an embodiment, when the input voltage VIN is approximately 4.4V, which is lower than the reference input voltage, the power management circuit 100 can operate in a regulator bypass mode. In the regulator bypass mode, the boost converter 110 can generate a boosted voltage VBST having a desired voltage level, for example, approximately 4.6V, by boosting the input voltage VIN of approximately 4.4V using a reference boost voltage VREF_BST of approximately 1.2V. In such an embodiment, when the input voltage VIN is approximately 4.6V, which is higher than or equal to the reference input voltage, the power management circuit 100 can operate in a regulator enable mode. In the regulator enabled mode, the boost converter 110 may receive an increased reference boost voltage VREF_BST of approximately 1.25 V, which is increased from the reference boost voltage VREF_BST of approximately 1.2 V in the regulator bypass mode, and may generate a boosted voltage VBST of approximately 4.8 V, which is increased from a desired voltage level of approximately 4.6 V, by performing a boost operation on an input voltage VIN of approximately 4.6 V using the increased reference boost voltage VREF_BST of approximately 1.25 V. However, the increased boosted voltage VBST generated by the boost converter 110 in the regulator enabled mode is not limited to approximately 4.8 V. In one embodiment, for example, the increased boosted voltage VBST in the regulator enabled mode may be higher than the input voltage VIN by an operating voltage margin of the boost converter 110 in the regulator enabled mode. Therefore, even when the input voltage VIN has a voltage level higher than the normal input voltage range, for example, during a period when the battery is being charged or due to touch noise, the boost converter 110 can generate an increased boosted voltage VBST that is higher than the input voltage VIN by an operating voltage margin, and thus can perform a boost operation normally.

[0051] The voltage regulator 130 may be coupled to the boost node NBST and the output node NO. In an embodiment, the voltage regulator 130 may be, but is not limited to, a low dropout ("LDO") regulator. The voltage regulator 130 may be disabled in a regulator bypass mode and may be enabled in a regulator enable mode. In an embodiment, in the regulator bypass mode, the voltage regulator 130 may receive a regulator enable signal LDO_EN having a first voltage level (e.g., a low level) and may be disabled in response to the regulator enable signal LDO_EN having the first voltage level. In addition, in the regulator enable mode, the voltage regulator 130 may receive a regulator enable signal LDO_EN having a second voltage level (e.g., a high level) and may be enabled in response to the regulator enable signal LDO_EN having the second voltage level. Therefore, in the regulator bypass mode, the voltage regulator 130 may be disabled in response to the regulator enable signal LDO_EN having the first voltage level, thereby reducing power consumption of the voltage regulator 130 and the power management circuit 100. In such an embodiment, in the regulator enable mode, the voltage regulator 130 may be enabled in response to the regulator enable signal LDO_EN having the second voltage level, and may receive the increased boosted voltage VBST of approximately 4.8 V from the boost converter 110. The voltage regulator 130 in the enabled state may generate a regulated voltage VLDO having a desired voltage level of the pixel power supply voltage ELVDD, for example, a regulated voltage VLDO of approximately 4.6 V, by regulating the increased boosted voltage VBST of approximately 4.8 V.

[0052] The bypass transistor 150 may be coupled between the boost node NBST and the output node NO. Figure 1 As shown in FIG, the bypass transistor 150 may be connected in parallel with the voltage regulator 130 between the boost node NBST and the output node NO. Figure 1As shown in FIG, the bypass transistor 150 may be implemented with, but not limited to, a p-type transistor. In one embodiment, for example, the bypass transistor 150 may include a gate for receiving the regulator enable signal LDO_EN, a source coupled to the boost node NBST, and a drain coupled to the output node NO. The bypass transistor 150 may connect the boost node NBST to the output node NO in the regulator bypass mode, and may disconnect the boost node NBST from the output node NO in the regulator enable mode. In an embodiment, in the regulator bypass mode, the bypass transistor 150 may receive the regulator enable signal LDO_EN having a first voltage level (e.g., a low level), and may be turned on in response to the regulator enable signal LDO_EN having the first voltage level to connect the boost node NBST to the output node NO. In such an embodiment, in the regulator enable mode, the bypass transistor 150 can receive the regulator enable signal LDO_EN having a second voltage level (e.g., a high level) and can be turned off in response to the regulator enable signal LDO_EN having the second voltage level to disconnect the boost node NBST from the output node NO. Thus, in the regulator bypass mode, the boost node NBST can be connected to the output node NO, and thus the boosted voltage VBST having a desired voltage level (e.g., the boosted voltage VBST of approximately 4.6V) can be output as the pixel power supply voltage ELVDD at the output node NO. In such an embodiment, in the regulator enable mode, the boost node NBST can be disconnected from the output node NO, and thus the regulated voltage VLDO having a desired voltage level (e.g., the regulated voltage VLDO of approximately 4.6V) can be output as the pixel power supply voltage ELVDD at the output node NO.

[0053] Regulator control block 170 can sense input voltage VIN and, based on the voltage level of input voltage VIN, can control power management circuit 100 to selectively operate in regulator bypass mode or regulator enable mode. In an embodiment, regulator control block 170 can compare input voltage VIN with a reference input voltage and control power management circuit 100 to operate in regulator bypass mode when input voltage VIN is lower than the reference input voltage, and can control power management circuit 100 to operate in regulator enable mode when input voltage VIN is higher than or equal to the reference input voltage. In an embodiment, the reference input voltage can be determined by subtracting the operating voltage margin of boost converter 110 from the desired voltage level of pixel power supply voltage ELVDD, thereby allowing the boost operation of boost converter 110 to proceed normally. In an embodiment, for example, when the desired voltage level of pixel power supply voltage ELVDD is approximately 4.6V, the reference input voltage can be determined to be, but not limited to, approximately 4.5V.

[0054] In an embodiment, when the input voltage VIN is lower than the reference input voltage, the regulator control block 170 may provide a reference boost voltage VREF_BST having a normal voltage level (e.g., a reference boost voltage VREF_BST of approximately 1.2V) to the boost converter 110, and may provide a regulator enable signal LDO_EN having a first voltage level (e.g., a low level) to the voltage regulator 130 and the bypass transistor 150 to control the power management circuit 100 to operate in the regulator bypass mode. The boost converter 110 may boost the input voltage VIN using the reference boost voltage VREF_BST of approximately 1.2V, and generate a boosted voltage VBST having a desired voltage level, e.g., a boosted voltage VBST of approximately 4.6V, at the boost node NBST. In such an embodiment, the voltage regulator 130 may be disabled in response to the regulator enable signal LDO_EN having a first voltage level, and the bypass transistor 150 may connect the boost node NBST to the output node NO in response to the regulator enable signal LDO_EN having a first voltage level. Thus, in the regulator bypass mode, the boosted voltage VBST having a desired voltage level may be output as the pixel power supply voltage ELVDD at the output node NO.

[0055] In such an embodiment, when the input voltage VIN is higher than or equal to the reference input voltage, the regulator control block 170 may provide a reference boost voltage VREF_BST of, for example, approximately 1.25V, which is increased from a normal voltage level of approximately 1.2V, to the boost converter 110, and may provide a regulator enable signal LDO_EN having a second voltage level (e.g., a high level) to the voltage regulator 130 and the bypass transistor 150 to control the power management circuit 100 to operate in the regulator enable mode. The boost converter 110 may boost the input voltage VIN using the increased reference boost voltage VREF_BST, thereby generating a boosted voltage VBST of, for example, approximately 4.8V, which is increased from a desired voltage level of approximately 4.6V, at the boost node NBST. In such an embodiment, the voltage regulator 130 can be enabled in response to the regulator enable signal LDO_EN having the second voltage level and can generate a regulated voltage VLDO having a desired voltage level of the pixel power supply voltage ELVDD, for example, a regulated voltage VLDO of approximately 4.6 V, by regulating the increased boosted voltage VBST of approximately 4.8 V. The bypass transistor 150 can disconnect the boost node NBST from the output node NO in response to the regulator enable signal LDO_EN having the second voltage level. Thus, the regulated voltage VLDO having the desired voltage level can be output as the pixel power supply voltage ELVDD at the output node NO in the regulator enable mode.

[0056] In an embodiment, once the power management circuit 100 enters the regulator enable mode, the regulator control block 170 may maintain the regulator enable mode for at least a minimum enable time. That is, the regulator control block 170 may maintain the enabled state of the voltage regulator 130 for at least the minimum enable time. In an embodiment, the minimum enable time may correspond to one frame period of the display panel. In one embodiment, for example, the minimum enable time may be, but is not limited to, approximately 16 microseconds (ms). If the input voltage VIN fluctuates and the operating mode of the power management circuit 100 switches between the regulator bypass mode and the regulator enable mode within an excessively short time interval, the pixel supply voltage ELVDD output from the power management circuit 100 may have ripples due to such mode transitions. However, in an embodiment of the power management circuit 100, the regulator control block 170 may maintain the regulator enable mode or the enabled state of the voltage regulator 130 for at least the minimum enable time (e.g., one frame period), thereby effectively preventing ripples in the pixel supply voltage ELVDD caused by the mode transitions. In such an embodiment, if the regulator enable mode is maintained for too long, the power consumption of the power management circuit 100 may excessively increase. However, in an embodiment of the power management circuit 100, the regulator control block 170 may maintain the regulator enable mode or the enabled state of the voltage regulator 130 for a minimum enable time corresponding to one frame period, thereby effectively preventing an excessive increase in the power consumption of the power management circuit 100.

[0057] As described above, in an embodiment of the power management circuit 100, when the input voltage VIN is higher than or equal to the reference input voltage, the boosted voltage VBST can be increased, the voltage regulator 130 can be enabled to generate the regulated voltage VLDO by regulating the increased boosted voltage VBST, the regulated voltage VLDO can be output as the pixel power supply voltage ELVDD, and the enabled state of the voltage regulator 130 can be maintained for a minimum enabled time. Thus, a pixel power supply voltage ELVDD having a desired voltage level can be generated for a wide range of input voltages VIN.

[0058] Figure 2 is a schematic circuit diagram illustrating a power management circuit according to an embodiment.

[0059] See also Figure 2, an embodiment of a power management circuit 100 for providing a pixel supply voltage ELVDD to pixels of a display panel may include a boost converter 110, a voltage regulator 130, a bypass transistor 150, and a regulator control block 170. In an embodiment, the power management circuit 100 may further include an input capacitor CIN connected to an input node and an output capacitor COUT connected to an output node NO. In an embodiment, the power management circuit 100 may be implemented using a power management integrated circuit ("PMIC").

[0060] The boost converter 110 may include: an inductor L1 that receives an input voltage VIN; a capacitor C1 coupled to a boost node NBST; a p-type transistor 122 coupled between the inductor L1 and the boost node NBST; an n-type transistor 124 coupled between the inductor L1 and a ground voltage; a boost voltage divider 112 coupled to the boost node NBST and configured to generate a boost feedback voltage VF_BST by dividing the boosted voltage VBST; an error amplifier 114 configured to amplify a difference between the boost feedback voltage VF_BST and a reference boost voltage VREF_BST; a comparator 116 configured to compare an output signal of the error amplifier 114 with a ramp voltage VRAMP; and a switch control block 120 configured to generate a first switching signal SWSP and a second switching signal SWSN for controlling the p-type transistor 122 and the n-type transistor 124, respectively, based on the output signal of the comparator 116. The boost converter 110 having such a configuration can control the p-type transistor 122 and the n-type transistor 124 to increase the boosted voltage VBST when the boost feedback voltage VF_BST is lower than the reference boost voltage VREF_BST, and can control the p-type transistor 122 and the n-type transistor 124 to decrease the boosted voltage VBST when the boost feedback voltage VF_BST is higher than the reference boost voltage VREF_BST, and thus can generate the boosted voltage VBST having a voltage level corresponding to the reference boost voltage VREF_BST. In such an embodiment, when the boost converter 110 receives the increased reference boost voltage VREF_BST from the regulator control block 170, the boost converter 110 can generate the increased boosted voltage VBST by using the increased reference boost voltage VREF_BST. Although Figure 2 The configuration of the embodiment of the boost converter 110 is illustrated, but the configuration of the embodiment of the boost converter 110 is not limited to Figure 2 In addition, in the embodiment, as shown in Figure 2 As illustrated in FIG. 1 , a portion of the passive elements of the power management circuit 100 such as the input capacitor CIN, the output capacitor COUT, the inductor L1, and the capacitor C1 may be disposed outside the power management integrated circuit, but the locations of the passive elements are not limited thereto.

[0061] The voltage regulator 130 may include a switch 132 coupled between a boost node NBST and an output node NO; a voltage divider 134 coupled to the output node NO and configured to generate a regulator feedback voltage VF_LDO by dividing the regulated voltage VLDO; and an amplifier 136 configured to control the switch 132 by comparing the regulator feedback voltage VF_LDO with a reference regulator voltage VREF_LDO. In an embodiment, the switch 132 of the voltage regulator 130 may include a gate for receiving an output signal of the amplifier 136, a source coupled to the boost node NBST, and a drain coupled to the output node NO. The voltage regulator 130 having such a configuration can increase the regulated voltage VLDO by turning on the switch 132 when the regulator feedback voltage VF_LDO is lower than the reference regulator voltage VREF_LDO, and can decrease the regulated voltage VLDO by turning off the switch 132 when the regulator feedback voltage VF_LDO is higher than the reference regulator voltage VREF_LDO, and thus can generate the regulated voltage VLDO having a desired voltage level. Figure 2 FIG. 1 shows a configuration of an embodiment of the voltage regulator 130. The configuration of the voltage regulator 130 according to the embodiment is not limited to Figure 2 The configuration shown in .

[0062] Bypass transistor 150 may be implemented with, but is not limited to, a p-type transistor. In an embodiment, bypass transistor 150 may include a gate for receiving regulator enable signal LDO_EN, a source coupled to boost node NBST, and a drain coupled to output node NO.

[0063] Regulator control block 170 may include an input voltage sensing block 180 configured to sense input voltage VIN and compare input voltage VIN with reference input voltage VREF_IN; and a timing control block 190 configured to count a period of time starting from the time voltage regulator 130 is enabled. Each of regulator control block 170, input voltage sensing block 180, and timing control block 190 may be a circuit block. When input voltage sensing block 180 determines that input voltage VIN is greater than or equal to reference input voltage VREF_IN, regulator control block 170 may generate a regulator enable signal LDO_EN having a second voltage level (e.g., a high level). Boost converter 110 may generate an increased boosted voltage VBST using the increased reference boost voltage VREF_BST. In such an embodiment, the voltage regulator 130 can be enabled in response to the regulator enable signal LDO_EN having a second voltage level and can generate a regulated voltage VLDO having a desired voltage level of the pixel power supply voltage ELVDD by regulating the increased boosted voltage VBST. The bypass transistor 150 can disconnect the boost node NBST from the output node NO in response to the regulator enable signal LDO_EN having a second voltage level. Thus, the regulated voltage VLDO having a desired voltage level can be output as the pixel power supply voltage ELVDD at the output node NO.

[0064] In an embodiment, the timing control block 190 may count a time period starting from the time point when the voltage regulator 130 is enabled, and the regulator control block 170 may maintain the regulator enable signal LDO_EN at the second voltage level until the time period counted by the timing control block 190 becomes the shortest enable time. Thus, the enabled state of the voltage regulator 130 can be maintained for at least the shortest enable time (e.g., one frame period), and thus, ripples in the pixel power supply voltage ELVDD caused by mode conversion can be effectively prevented. In such an embodiment, after the time period counted by the timing control block 190 becomes the shortest enable time, when the input voltage VIN becomes lower than the reference input voltage VREF_IN, the regulator control block 170 may change the regulator enable signal LDO_EN from the second voltage level to the first voltage level.

[0065] In an embodiment, before the time period counted by the timing control block 190 becomes the shortest enable time, when the input voltage VIN becomes higher than or equal to the reference input voltage VREF_IN again after becoming lower than the reference input voltage VREF_IN, the timing control block 190 may reset the counted time period and may again count the time period starting from the point in time when the input voltage VIN becomes higher than or equal to the reference input voltage VREF_IN again. Thus, mode switching with an excessively short time interval caused by fluctuations in the input voltage VIN can be effectively prevented.

[0066] Figure 3 is a flowchart illustrating a method of generating a pixel power supply voltage according to an embodiment, Figure 4 is a timing diagram illustrating the operation of an embodiment of a power management circuit when the input voltage fluctuates during a battery charging period, Figure 5 is a signal timing diagram illustrating the operation of an embodiment of a power management circuit when the input voltage fluctuates due to touch noise, Figure 6A is a diagram illustrating input voltage and pixel power supply voltage in a conventional power management circuit, and Figure 6B is a diagram illustrating input voltages and pixel power supply voltages in a power management circuit according to an embodiment.

[0067] See also Figures 1 to 3 In an embodiment of a method for generating a pixel power supply voltage ELVDD supplied to a pixel of a display panel, the regulator control block 170 may compare the input voltage VIN with a reference input voltage VREF_IN (S210). In an embodiment, the reference input voltage VREF_IN may be determined by subtracting an operating voltage margin for a boost operation of the boost converter 110 from a desired voltage level of the pixel power supply voltage ELVDD. In an embodiment, for example, when the desired voltage level of the pixel power supply voltage ELVDD is approximately 4.6V, the reference input voltage VREF_IN may be determined to be, but not limited to, approximately 4.5V.

[0068] In such an embodiment, when the input voltage VIN is lower than the reference input voltage VREF_IN (S210: No), the boost converter 110 can generate a boosted voltage VBST by boosting the input voltage VIN using the reference boost voltage VREF_BST (S220). In one embodiment, for example, the boost converter 110 can generate a boosted voltage VBST of approximately 4.6V by boosting the input voltage VIN of approximately 4.4V using the reference boost voltage VREF_BST of approximately 1.2V.

[0069] The power management circuit 100 may output a boosted voltage VBST of approximately 4.6V as the pixel power supply voltage ELVDD (S230 and S240). In an embodiment, the regulator control block 170 may generate a regulator enable signal LDO_EN having a first voltage level (e.g., a low level), and the voltage regulator 130 may be disabled in response to the regulator enable signal LDO_EN having the first voltage level (S230). In such an embodiment, the bypass transistor 150 may be turned on in response to the regulator enable signal LDO_EN having the first voltage level to connect the boost node NBST to the output node NO, and the boosted voltage VBST may be output as the pixel power supply voltage ELVDD at the output node NO (S240).

[0070] In such an embodiment, when the input voltage VIN is higher than or equal to the reference input voltage VREF_IN (S210: YES), the regulator control block 170 may increase the reference boost voltage VREF_BST (S250), and the boost converter 110 may generate an increased boosted voltage VBST by using the increased reference boost voltage VREF_BST to boost the input voltage VIN (S260). In one embodiment, for example, the boost converter 110 may generate a boosted voltage VBST that increases from approximately 4.6V to approximately 4.8V by using the reference boost voltage VREF_BST increased from approximately 1.2V to approximately 1.25V to boost the input voltage VIN.

[0071] In an embodiment, the regulator control block 170 may generate a regulator enable signal LDO_EN having a second voltage level (e.g., a high level), and the voltage regulator 130 may be enabled in response to the regulator enable signal LDO_EN having the second voltage level (S270). The voltage regulator 130 in the enabled state may generate a regulated voltage VLDO of approximately 4.6V by regulating the increased boosted voltage VBST of approximately 4.8V. In such an embodiment, the bypass transistor 150 may be turned off in response to the regulator enable signal LDO_EN having the second voltage level to disconnect the boost node NBST from the output node NO, and the regulated voltage VLDO may be output as the pixel power supply voltage ELVDD at the output node NO (S280).

[0072] The second voltage level of the regulator enable signal LDO_EN or the enabled state of the voltage regulator 130 may be maintained for the minimum enabled time (S290). In an embodiment, the timing control block 190 may count a time period starting from the time point when the voltage regulator 130 is enabled, and the enabled state of the voltage regulator 130 may be maintained until the time period counted by the timing control block 190 becomes the minimum enabled time (S290: No). In such an embodiment, after the time period counted by the timing control block 190 becomes the minimum enabled time (S290: Yes), when the input voltage VIN becomes lower than the reference input voltage VREF_IN (S210: No), the voltage regulator 130 may be disabled (S230). In an embodiment, before the time period counted by the timing control block 190 becomes the shortest enable time, when the input voltage VIN becomes higher than or equal to the reference input voltage VREF_IN again after becoming lower than the reference input voltage VREF_IN, the time period counted by the timing control block 190 may be reset, and the timing control block 190 may again count the time period starting from the point in time when the input voltage VIN becomes higher than or equal to the reference input voltage VREF_IN again.

[0073] In one embodiment, for example, Figure 4As shown in FIG, during a battery charging period in which a battery of an electronic device including power management circuit 100 is charged by an adapter or the like, input voltage VIN may be increased from approximately 4.4V to approximately 4.6V. When input voltage VIN becomes higher than or equal to reference input voltage VREF_IN of approximately 4.5V, regulator control block 170 may change the operating mode of power management circuit 100 from regulator bypass mode to regulator enable mode. In one embodiment, for example, regulator control block 170 may increase reference boost voltage VREF_BST from approximately 1.2V to approximately 1.25V, and boost converter 110 may generate a boosted voltage VBST that increases from approximately 4.6V to approximately 4.8V using the increased reference boost voltage VREF_BST. In such an embodiment, regulator control block 170 may change regulator enable signal LDO_EN from a first voltage level VL1 to a second voltage level VL2. The voltage regulator 130 can be enabled in response to a regulator enable signal LDO_EN having a second voltage level VL2 and can generate a regulated voltage VLDO of approximately 4.6V by regulating the boosted voltage VBST of approximately 4.8V. In such an embodiment, the bypass transistor 150 can be turned off in response to the regulator enable signal LDO_EN having the second voltage level VL2, and the regulated voltage VLDO of approximately 4.6V can be output as the pixel power supply voltage ELVDD at the output node NO. The second voltage level VL2 of the regulator enable signal LDO_EN, or the enabled state of the voltage regulator 130, can be maintained for a minimum enable time MET of approximately 16ms. After the minimum enable time MET, when the input voltage VIN falls below the reference input voltage VREF_IN of approximately 4.5V, the regulator control block 170 can change the operating mode of the power management circuit 100 from the regulator enable mode to the regulator bypass mode.

[0074] In one embodiment, for example, Figure 5As shown in FIG. 1 , when a touch screen of an electronic device including power management circuit 100 is touched, input voltage VIN may fluctuate due to touch noises TN1, TN2, and TN3. When input voltage VIN becomes greater than or equal to reference input voltage VREF_IN of approximately 4.5V due to first touch noise TN1, regulator control block 170 may change the operating mode of power management circuit 100 from regulator bypass mode to regulator enable mode. In one embodiment, for example, in regulator enable mode, reference boost voltage VREF_BST may increase from approximately 1.2V to approximately 1.25V, boosted voltage VBST may increase from approximately 4.6V to approximately 4.8V, regulator enable signal LDO_EN may change from first voltage level VL1 to second voltage level VL2, regulated voltage VLDO of approximately 4.6V may be generated by regulating the increased boost voltage VBST of approximately 4.8V, and regulated voltage VLDO of approximately 4.6V may be output as pixel power supply voltage ELVDD. Even though the input voltage VIN falls below the reference input voltage VREF_IN of approximately 4.5V, the regulator enable mode, or the enabled state of the voltage regulator 130, may be maintained for a minimum enable time MET of approximately 16ms. After the minimum enable time MET, the regulator control block 170 may change the operating mode of the power management circuit 100 from the regulator enable mode to the regulator bypass mode. When the input voltage VIN becomes higher than or equal to the reference input voltage VREF_IN of approximately 4.5V due to the second touch noise TN2, the regulator control block 170 may change the operating mode of the power management circuit 100 from the regulator bypass mode to the regulator enable mode. Within the minimum enable time MET, the input voltage VIN may fall below the reference input voltage VREF_IN of approximately 4.5V and then may again become higher than or equal to the reference input voltage VREF_IN of approximately 4.5V due to the third touch noise TN3. In this case, the timing control block 190 may reset the counted time period and restart the counting operation. When the time period counted by the restarted counting operation becomes the shortest enable time MET of approximately 16 ms and the input voltage VIN becomes lower than the reference input voltage VREF_IN of approximately 4.5 V, the regulator control block 170 may change the operation mode of the power management circuit 100 from the regulator enable mode to the regulator bypass mode.

[0075] Figure 6A FIG shows the input voltage VIN and the pixel power supply voltage ELVDD in a conventional power management circuit, and Figure 6B An input voltage VIN and a pixel power supply voltage ELVDD in the power management circuit 100 according to an embodiment are illustrated.

[0076] like Figure 6AAs shown in FIG, when the input voltage VIN fluctuates, the pixel power supply voltage ELVDD generated by the conventional power management circuit may also fluctuate. However, in the embodiment of the power management circuit 100 according to the present invention, when the input voltage VIN is higher than or equal to the reference input voltage VREF_IN, the boosted voltage VBST can be increased, the voltage regulator 130 can be enabled to generate the regulated voltage VLDO by regulating the increased boosted voltage VBST, the regulated voltage VLDO can be output as the pixel power supply voltage ELVDD, and the enabled state of the voltage regulator 130 can be maintained for the minimum enablement time MET. Thus, as shown in FIG. Figure 6B As illustrated in FIG. 1 , the pixel supply voltage ELVDD generated by an embodiment of the power management circuit 100 may have a substantially constant or relatively constant voltage level even when the input voltage VIN fluctuates.

[0077] Figure 7 is a block diagram illustrating a power management circuit according to an alternative embodiment.

[0078] See also Figure 7 , an embodiment of the power management circuit 300 may include a boost converter 110, a voltage regulator 130, a bypass transistor 150, a regulator control block 170, an inverting buck-boost converter 320, and an additional boost converter 340. In such an embodiment, as Figure 7 As shown in Figure 7 The power management circuit 300 further includes an inverting buck-boost converter 320 and an additional boost converter 340. The power management circuit 300 can be used in conjunction with the above reference Figure 1 and Figure 2 The described embodiments of the power management circuit 100 are substantially the same.

[0079] In an embodiment of the power management circuit 300, the inverting buck-boost converter 320 can convert the input voltage VIN into a negative pixel supply voltage ELVSS for pixels of the display panel. In one embodiment, for example, the negative pixel supply voltage ELVSS can be, but is not limited to, in the range of approximately -6.6V to approximately -0.8V.

[0080] The additional boost converter 340 may convert the input voltage VIN into an analog power supply voltage AVDD. In an embodiment, the analog power supply voltage AVDD may be provided to the data driver. In one embodiment, for example, the analog power supply voltage AVDD may be, but is not limited to, in the range of approximately 6.8V to approximately 7.9V.

[0081] Figure 8 is a block diagram illustrating a display device including a power management circuit according to an embodiment.

[0082] See also Figure 8 , an embodiment of a display device 400 may include: a display panel 410 including pixels PX; a data driver 420 for providing a data signal DS to the pixels PX; a scan driver 430 for providing a scan signal SS to the pixels PX; a controller 440 for controlling the data driver 420 and the scan driver 430; and a power management circuit 450 for supplying a high pixel power supply voltage ELVDD and a low pixel power supply voltage ELVSS to the pixels PX.

[0083] The display panel 410 may include data lines, scan lines, and pixels PX coupled to the data lines and the scan lines. In an embodiment, each pixel PX may include at least two transistors, at least one capacitor, and an organic light emitting diode (OLED), and the display panel 410 may be an OLED display panel. In alternative embodiments, the display panel 410 may be a liquid crystal display ("LCD") panel or any other type of display panel.

[0084] The data driver 420 can generate a data signal DS based on the data control signal DCTRL and the output image data ODAT received from the controller 440, and can provide the data signal DS to the pixel PX through the data line. In an embodiment, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In an embodiment, the data driver 420 and the controller 440 can be implemented with a single integrated circuit, and the single integrated circuit can be referred to as a timing controller embedded data driver ("TED"). In an alternative embodiment, the data driver 420 and the controller 440 can be implemented with separate integrated circuits.

[0085] The scan driver 430 may generate a scan signal SS based on a scan control signal SCTRL received from the controller 440, and may provide the scan signal SS to the pixels PX row by row through the scan lines. In an embodiment, the scan control signal SCTRL may include, but is not limited to, a start signal and a scan clock signal. In an embodiment, the scan driver 430 may be integrated or formed as a single integrated circuit in the peripheral portion of the display panel 410. In an alternative embodiment, the scan driver 430 may be implemented using two or more integrated circuits.

[0086] The controller 440 (e.g., a timing controller (also referred to as TCON)) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., an application processor (“AP”), a graphics processing unit (“GPU”), or a graphics card). In an embodiment, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 440 may generate a data control signal DCTRL, output image data ODAT, and a scan control signal SCTRL based on the control signal CTRL and the input image data IDAT. The controller 440 may control the operation of the data driver 420 by providing the data control signal DCTRL and the output image data ODAT to the data driver 420, and may control the operation of the scan driver 430 by providing the scan control signal SCTRL to the scan driver 430.

[0087] The power management circuit 450 may convert the input voltage VIN into a high pixel power supply voltage ELVDD, a low pixel power supply voltage ELVSS, and / or an analog power supply voltage AVDD. In an embodiment, the high pixel power supply voltage ELVDD may be a positive pixel power supply voltage ELVDD, and the low pixel power supply voltage ELVSS may be a negative pixel power supply voltage ELVSS. The power management circuit 450 may supply the high pixel power supply voltage ELVDD and the low pixel power supply voltage ELVSS to the pixel PX, and may supply the analog power supply voltage AVDD to the data driver 420. According to an embodiment, the power management circuit 450 may be the same as that of the above reference circuit. Figure 1 and Figure 2 The power management circuit 100 described or referenced Figure 7 The embodiment of the power management circuit 300 described above is substantially the same. In the embodiment of the power management circuit 450, when the input voltage VIN is higher than or equal to the reference input voltage, the boosted voltage can be increased, the voltage regulator can be enabled to generate a regulated voltage by regulating the increased boosted voltage, the regulated voltage can be output as the high pixel power supply voltage ELVDD, and the enabled state of the voltage regulator can be maintained for a minimum enabled time. Thus, a high pixel power supply voltage ELVDD having a desired voltage level can be generated for a wide range of input voltages VIN.

[0088] Figure 9 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0089] See also Figure 9, an embodiment of the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output ("I / O") device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, other electronic devices, and the like.

[0090] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor ("AP"), a microprocessor, a central processing unit ("CPU"), or the like. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, or the like. In an embodiment, the processor 1110 may be further coupled to an expansion bus, such as a peripheral component interconnect ("PCI") bus.

[0091] The memory device 1120 may store data used for the operation of the electronic device 1100. In one embodiment, for example, the memory device 1120 may include at least one non-volatile memory device (e.g., an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (e.g., a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0092] The storage device 1130 may be a solid-state drive ("SSD") device, a hard disk drive ("HDD") device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may provide power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication link.

[0093] In an embodiment of the power management circuit of the display device 1160, when the input voltage is greater than or equal to the reference input voltage, the boosted voltage may be increased, the voltage regulator may be enabled to generate a regulated voltage by regulating the increased boosted voltage, the regulated voltage may be output as the pixel power supply voltage, and the enabled state of the voltage regulator may be maintained for a minimum enabled time. Thus, in this embodiment of the power management circuit of the display device 1160, a pixel power supply voltage having a desired voltage level may be generated for a wide range of input voltages.

[0094] The present invention can be applied to any electronic device 1100 including a display device 1160. In one embodiment, for example, the present invention can be applied to a mobile phone, a smart phone, a tablet computer, a virtual reality ("VR") device, a television ("TV"), a digital TV, a three-dimensional ("3D") TV, a wearable electronic device, a personal computer ("PC"), a home appliance, a portable computer, a personal digital assistant ("PDA"), a portable multimedia player ("PMP"), a digital camera, a music player, a portable game console, a navigation device, and the like.

[0095] The present invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0096] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A power management circuit for supplying a pixel power supply voltage to pixels of a display panel, the power management circuit comprising: a boost converter generating a boosted voltage at a boost node by boosting an input voltage using a reference boost voltage; a voltage regulator coupled to the boost node and an output node; a bypass transistor coupled between the boost node and the output node; as well as a regulator control block receiving the input voltage, outputting the reference boost voltage, and controlling the voltage regulator and the bypass transistor, wherein the regulator control block compares the input voltage with a reference input voltage, wherein, when the input voltage is higher than or equal to the reference input voltage, the regulator control block increases the reference boost voltage to increase the boosted voltage, enables the voltage regulator to generate a regulated voltage by regulating the increased boosted voltage, turns off the bypass transistor so that the regulated voltage is output as the pixel power supply voltage at the output node, and maintains the enabled state of the voltage regulator for a minimum enabled time; and When the input voltage is lower than the reference input voltage, the regulator control block disables the voltage regulator and turns on the bypass transistor so that the boosted voltage is output as the pixel power supply voltage at the output node.

2. The power management circuit according to claim 1, wherein: When the input voltage is lower than the reference input voltage, the regulator control block generates a regulator enable signal having a first voltage level, and The regulator control block generates the regulator enable signal having a second voltage level when the input voltage is higher than or equal to the reference input voltage.

3. The power management circuit according to claim 2, wherein: The voltage regulator is disabled in response to the regulator enable signal having the first voltage level, and The voltage regulator is enabled in response to the regulator enable signal having the second voltage level.

4. The power management circuit according to claim 2, wherein: The bypass transistor is turned on in response to the regulator enable signal having the first voltage level to connect the boost node to the output node, and The bypass transistor is turned off in response to the regulator enable signal having the second voltage level to disconnect the boost node from the output node.

5. The power management circuit according to claim 1, wherein: The regulator control block includes: an input voltage sensing block that senses the input voltage and compares the input voltage with the reference input voltage; and a timing control block that counts a time period starting from a point in time when the voltage regulator is enabled, and Wherein, when the input voltage is higher than or equal to the reference input voltage, The regulator control block generates a regulator enable signal having a second voltage level, The regulator control block maintains the regulator enable signal at the second voltage level until the counted time period becomes the shortest enable time, and After the counted period of time becomes the shortest enable time, when the input voltage becomes lower than the reference input voltage, the regulator control block changes the regulator enable signal from the second voltage level to the first voltage level.

6. The power management circuit according to claim 1, wherein: The voltage regulator comprises: a switch coupled between the boost node and the output node; a voltage divider coupled to the output node and generating a regulator feedback voltage by dividing the regulated voltage; and An amplifier controls the switch by comparing the regulator feedback voltage with a reference regulator voltage.

7. The power management circuit according to claim 1, wherein: The boost converter comprises: an inductor receiving the input voltage; a capacitor coupled to the boost node; a p-type transistor coupled between the inductor and the boost node; an n-type transistor coupled between the inductor and a ground voltage; a boost voltage divider coupled to the boost node and configured to generate a boost feedback voltage by dividing the boosted voltage; an error amplifier, amplifying a difference between the boost feedback voltage and the reference boost voltage; a comparator, comparing the output signal of the error amplifier with a ramp voltage; and A switch control block generates a first switch signal and a second switch signal for controlling the p-type transistor and the n-type transistor, respectively, based on an output signal of the comparator.

8. A method of generating a pixel power supply voltage to be supplied to a pixel of a display panel, the method comprising: The input voltage is compared with the reference input voltage by the regulator control block; When the input voltage is lower than the reference input voltage, generating a boosted voltage by boosting the input voltage using a reference boost voltage by a boost converter; disabling the voltage regulator by the regulator control block when the input voltage is lower than the reference input voltage; When the input voltage is lower than the reference input voltage, the regulator control block turns on the bypass transistor to output the boosted voltage as the pixel power supply voltage; When the input voltage is higher than or equal to the reference input voltage, the regulator control block increases the reference boost voltage; When the input voltage is higher than or equal to the reference input voltage, the boost converter generates an increased boosted voltage by boosting the input voltage using the increased reference boost voltage; generating a regulated voltage at the voltage regulator by regulating the increased boosted voltage when the input voltage is higher than or equal to the reference input voltage; When the input voltage is higher than or equal to the reference input voltage, the regulator control block turns off the bypass transistor to output the regulated voltage as the pixel power supply voltage; and When the input voltage is higher than or equal to the reference input voltage, the regulator control block maintains the enabled state of the voltage regulator for a minimum enabled time.

9. A display device comprising: a display panel including pixels; providing a data signal to a data driver of the pixel; providing a scan signal to a scan driver of the pixel; a controller for controlling the data driver and the scan driver; as well as a power management circuit for supplying a pixel supply voltage to said pixel, Wherein, the power management circuit includes: a boost converter generating a boosted voltage at a boost node by boosting an input voltage using a reference boost voltage; a voltage regulator coupled to the boost node and an output node; a bypass transistor coupled between the boost node and the output node; and a regulator control block receiving the input voltage, outputting the reference boost voltage, and controlling the voltage regulator and the bypass transistor, wherein the regulator control block compares the input voltage with a reference input voltage, wherein, when the input voltage is higher than or equal to the reference input voltage, the regulator control block increases the reference boost voltage to increase the boosted voltage, enables the voltage regulator to generate a regulated voltage by regulating the increased boosted voltage, turns off the bypass transistor so that the regulated voltage is output as the pixel power supply voltage at the output node, and maintains the enabled state of the voltage regulator for a minimum enabled time; and When the input voltage is lower than the reference input voltage, the regulator control block disables the voltage regulator and turns on the bypass transistor so that the boosted voltage is output as the pixel power supply voltage at the output node.

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