Semiconductor memory device

Abstract

A semiconductor memory device includes a buffer wafer, a memory wafer stacked on the buffer wafer, and a through silicon via. At least one of the memory wafer includes an array of memory cells, an error correction code (ECC) engine, an error information register, and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation. The control logic circuit is configured to record, in the error information register, a first address associated with a first codeword based on a generate signal and a first syndrome obtained by decoding the ECC code, and determine an error property of the first codeword based on a change in the first syndrome recorded in the error information register based on a plurality of read-modify-write operations.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0039597, filed on April 1, 2020, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to memory, and more specifically, to semiconductor memory devices capable of using error correction code (ECC) information when repairing defective cells. Background Technology

[0004] Both the capacity and speed of semiconductor memories that can be used as storage devices in memory systems are increasing. Therefore, various attempts are being made to manufacture memories with large capacities and small footprints, and to find ways to operate memories efficiently.

[0005] Recently, in order to improve the integration of semiconductor memories, 3D structures comprising multiple stacked memory chips have been used. However, due to the demand for large integration and high-capacity memories, the size of 3D stacked memory chip structures has been reduced. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a semiconductor memory device is provided, the semiconductor memory device comprising: a buffer wafer; a plurality of memory wafers stacked on the buffer wafer; and a plurality of through-silicon vias (TSVs) connecting the plurality of memory wafers to the buffer wafer, wherein at least one of the plurality of memory wafers includes: a memory cell array including a plurality of memory cell rows, each row including a plurality of volatile memory cells; an error correction code (ECC) engine; an error information register; and control logic circuitry configured to control the ECC engine to perform read-modify-write operations by means of the following steps: based on an access address and a command, from the buffer wafer... Data corresponding to a first codeword is read from a subpage in a first memory cell row of multiple memory cell rows; in response to detecting an error in the first codeword, ECC decoding is performed on the data to generate an error generation signal; the detected error in the first codeword is corrected; and the corrected first codeword is written to a first memory location corresponding to the subpage, wherein the control logic circuit is configured to: record a first address associated with the first codeword in an error information register based on the error generation signal and a first corrector obtained through ECC decoding; and determine the error attribute of the first codeword based on changes to the first corrector recorded in the error information register based on multiple read-modify-write operations.

[0007] According to an exemplary embodiment of the inventive concept, there is provided a semiconductor memory device, the semiconductor memory device comprising: an array of memory cells comprising a plurality of rows of memory cells, each row comprising a plurality of volatile memory cells; an ECC engine; an error information register; and control logic configured to control the ECC engine to perform a read-modify-write operation by: reading data corresponding to a first codeword from a sub-page in a first row of memory cells of the plurality of rows of memory cells based on an access address and a command; performing ECC decoding on the data to generate an error generation signal in response to detecting an error in the first codeword; correcting the detected error in the first codeword; and writing the corrected first codeword into a first memory location corresponding to the sub-page, wherein the control logic is configured to: record a first address associated with the first codeword in the error information register based on the error generation signal and a first syndrome obtained by the ECC decoding; and determine an error property of the first codeword based on changes in the first syndrome recorded in the error information register based on a plurality of read-modify-write operations.

[0008] According to an exemplary embodiment of the inventive concept, there is provided a semiconductor memory device, the semiconductor memory device comprising: an array of memory cells comprising a plurality of rows of memory cells, each row comprising a plurality of volatile memory cells; an ECC engine; an error information register; and control logic configured to control the ECC engine to perform a read-modify-write operation by: reading data corresponding to a first codeword from a sub-page in a first row of memory cells of the plurality of rows of memory cells based on an access address and a command from an external device; performing ECC decoding on the data to generate an error generation signal in response to detecting an error in the first codeword; correcting the detected error in the first codeword; and writing the corrected first codeword into a first memory location corresponding to the sub-page; and further comprising: a storage memory for storing a first address designating the first memory location as a hard failure or a progressive failure and its associated corrected data, wherein the control logic is configured to: record a first address associated with the first codeword in the error information register based on the error generation signal and a first syndrome obtained by the ECC decoding; and determine an error property of the first codeword based on changes in the first syndrome recorded in the error information register based on a plurality of read-modify-write operations. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0010] Figure 2 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0011] Figure 3 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 2 A block diagram of an example memory controller.

[0012] Figure 4 This is a block diagram illustrating an example embodiment of a data processing system according to a concept of the present invention.

[0013] Figure 5 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 2 A block diagram of an example of stacked memory devices.

[0014] Figure 6 An exemplary embodiment of the invention is shown. Figure 5 The operation of the interface circuitry in the stacked memory device.

[0015] Figure 7 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 6 A block diagram of an example interface circuit.

[0016] Figure 8 An exemplary embodiment of the invention is shown. Figure 7 An example of static random access memory (SRAM) in a computer.

[0017] Figure 9 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 4 A block diagram of an example of memory chips in a stacked memory device.

[0018] Figure 10 An exemplary embodiment of the invention is shown. Figure 9 An example of the first memory block in a memory chip.

[0019] Figure 11 An exemplary embodiment of the invention is shown. Figure 10 The relationship between the column selection lines and the bit lines is shown.

[0020] Figure 12 An exemplary embodiment of the invention is shown. Figure 9 An example of peripheral circuitry in a memory chip.

[0021] Figure 13 An exemplary embodiment of the invention is shown. Figure 9 The memory cell array, row decoder, and column decoder in the memory chip.

[0022] Figure 14 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 13a block diagram of a first one of the section information circuits in the section information circuit in the memory system.

[0023] Figure 15 is a block diagram illustrating an example of a repair circuit according to example embodiments of the inventive concept. Figure 13 a block diagram of a first one of the section information circuits in the section information circuit in the memory system.

[0024] Figure 16 is a block diagram illustrating an example of a memory system according to example embodiments of the inventive concept. Figure 12 an example of an error information register in the peripheral circuit in the memory system.

[0025] Figure 17 is a block diagram illustrating an example of an error correction code (ECC) engine in a memory die of the memory system according to example embodiments of the inventive concept. Figure 9

[0026] is an example of an ECC encoder in the ECC engine of the memory system according to example embodiments of the inventive concept. Figure 18 Figure 17 is an example of an ECC decoder in the ECC engine of the memory system according to example embodiments of the inventive concept.

[0027] Figure 19 Figure 17 , and

[0028] illustrate, respectively, that the control logic circuit determines an error attribute based on a change in value of the syndrome according to example embodiments of the inventive concept. Figure 20 Figure 21 Figure 22 is a block diagram illustrating an example of a semiconductor memory device in the memory system according to example embodiments of the inventive concept.

[0029] Figure 23 is a block diagram illustrating a semiconductor memory device according to example embodiments of the inventive concept. Figure 1

[0030] is a block diagram illustrating a semiconductor memory device according to example embodiments of the inventive concept. Figure 24

[0031] is a flowchart illustrating a method of operating a semiconductor memory device of the inventive concept. Figure 25

[0032] is a diagram illustrating a semiconductor package including stacked memory devices according to example embodiments of the inventive concept. Figure 26 DETAILED DESCRIPTION

[0033] Example embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.

[0034] Figure 1 ​​​is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

[0035] Referring to Figure 1 The memory system 10 includes a memory controller 20 and a semiconductor memory device 60. The memory controller 20 can include a central processing unit (CPU) 21, can provide a command (e.g., a signal) CMD and an address (e.g., a signal) ADDR to the semiconductor memory device 60, and can exchange main data MD with the semiconductor memory device 60.

[0036] The memory controller 20 can access the semiconductor memory device 60 based on a request from an external host. For example, the host can request the memory controller 20 to perform a read or write operation on the semiconductor memory device 60. The memory controller 20 can communicate with the host through various protocols. The CPU 21 can control the overall operation of the memory controller 20.

[0037] The semiconductor memory device 60 can include a memory cell array (MCA) 65, a control logic circuit 67, an error correction code (ECC) engine 500a, and an error information register (EIR) 580a.

[0038] The memory cell array 65 can include a plurality of memory cell rows, each of which includes a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines. The volatile memory cells lose stored information when power is off.

[0039] In a write operation of the semiconductor memory device 60, the ECC engine 500a can perform ECC encoding on the main data MD to store the main data MD and parity data in a target page of the memory cell array 65.

[0040] In a memory access operation on a first memory cell row of the plurality of memory cell rows, the control logic circuit 67 controls the ECC engine 500a to perform a read-modify-write operation. The ECC engine 500a performs the read-modify-write operation by reading data corresponding to a first codeword from a sub-page in the first memory cell row based on an access address and a command provided from the memory controller 20 (e.g., an external device), performing ECC decoding on the data in response to detecting an error in the first codeword to generate an error generation signal, correcting the detected error in the first codeword, and writing the corrected first codeword back into a first memory location corresponding to the first sub-page.

[0041] The memory access operation on the first memory cell row can include a normal read operation, a refresh operation, or a scrub operation.

[0042] In addition, the control logic circuit 67 can record a first address associated with the first codeword in the error information register 580a based on the error generation signal and the first syndrome obtained through the ECC decoding. In addition, based on the plurality of read-modify-write operations, the control logic circuit 67 can determine an error attribute of the first codeword based on a change in the first syndrome recorded in the error information register 580a. Here, the plurality of read-modify-write operations can refer to a read-modify-write operation performed a plurality of times.

[0043] When the control logic circuit 67 determines the error attribute as a hard failure or a progressive failure, the control logic circuit 67 can selectively repair the first memory location based on the determined error attribute. The control logic circuit 67 can repair the first memory location by replacing an address of the first memory location with an address of a redundant area. The control logic 67 can repair the first memory location by storing the address of the first memory location and the associated corrected data in a storage memory in the semiconductor memory device 60.

[0044] Figure 2 FIG. 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present inventive concept.

[0045] Referring to Figure 2 The memory system 10a includes a memory controller 20 and a semiconductor memory device 70. The semiconductor memory device 70 can include stacked memory devices, and can be referred to as a stacked memory device. Figure 2 The memory controller 20 in Figure 1 The memory controller 20 in

[0046] The stacked memory device 70 can include a buffer wafer 200 and a plurality of memory wafers 300 stacked on the buffer wafer 200. The buffer wafer 200 and the memory wafers 300 can be stacked on each other in order. The memory wafers 300 stacked on the buffer wafer 200 can be electrically connected to the buffer wafer 200 through conductive devices. The conductive devices can be one or more through silicon vias (TSVs) 220. The memory wafers 300 can store data.

[0047] The buffer wafer 200 can communicate with the memory controller 20, and each of the memory wafers 300 can be a dynamic random access memory (DRAM) device including a plurality of dynamic memory cells, such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM). Each of the memory wafers 300 can include an array of memory cells, an ECC engine, a control logic circuit, and an error information register. For example, each of the memory wafers 300 can include an array of memory cells, an ECC engine, a control logic circuit, and an error information register. Figure 1The illustrated memory cell array 65, ECC engine 500a, control logic circuit 67, and error information register 580a.

[0048] The buffer wafer 200 can include an interface circuit (IFC) 230, and the interface circuit 230 can include a storage memory. The interface circuit 230 is coupled to the TSV 220, and can perform post-package repair (PPR) by storing a failed address and associated corrected data provided from at least one of the memory wafers 300 via the TSV 220 in the storage memory. After the failed address and associated corrected data are stored in the storage memory, the interface circuit 230 can control the storage memory so that data is input / output via the storage memory when a second address from the memory controller 20 matches the failed address.

[0049] Figure 3 is a block diagram illustrating an example of a memory controller in Figure 2 according to an example embodiment of the inventive concept.

[0050] Referring to Figure 3 , the memory controller 20 can include a CPU 21, a data buffer 23, an ECC decoder 30, a command buffer 25, and an address buffer 27. In an example embodiment of the inventive concept, the ECC decoder 30 can not be included in the memory controller 20.

[0051] The CPU 21 receives a request REQ and data DTA from a host, and provides the data DTA to the data buffer 23.

[0052] The data buffer 23 buffers the data DTA to provide main data MD to the stacked memory device 70 (or semiconductor memory device 60).

[0053] In a read operation, the ECC decoder 30 receives the main data MD from the stacked memory device 70; performs ECC decoding on the main data MD to correct at least one error in the main data MD; and provides corrected data C_MD to the CPU 21.

[0054] The command buffer 25 stores a command CMD corresponding to the request REQ, and transmits the command CMD to the stacked memory device 70 under control of the CPU 21. The address buffer 27 stores an address ADDR corresponding to the request REQ, and transmits the address ADDR to the stacked memory device 70 under control of the CPU 21.

[0055] Figure 4 is a block diagram illustrating a data processing system according to an example embodiment of the inventive concept.

[0056] Referring toFigure 4 The data processing system (or memory system) 10b can include an application processor (AP) 20b and a stacked memory device (SMD) 70. The application processor 20b can include a memory control module 40. The memory control module 40 included in the application processor 20b and the stacked memory device 70 can constitute a memory system. The stacked memory device 70 includes a buffer wafer 200 and a memory wafer 300, and the memory wafer 300 includes a plurality of memory wafers 300a~300k stacked on top of each other.

[0057] The application processor 20b can perform a function of a host. Also, the application processor 20b can be implemented as a system on chip (SoC). The SoC can include a system bus to which a protocol having a predetermined standard bus specification is applied, and can include various types of intellectual property (IP) cores connected to the system bus.

[0058] The memory control module 40 can perform a function of the memory controller 20 in Figure 2

[0059] In an exemplary embodiment of the inventive concept, the application processor 20b can include a graphic processing unit (GPU) instead of the memory control module 40, and the GPU can perform a function of the memory controller 20 in Figure 2 The GPU can store data generated during image processing in the stacked memory device 70.

[0060] Figure 5 is a block diagram illustrating an example of the stacked memory device in Figure 2

[0061] In Figure 5 , a memory device formed in a high bandwidth memory (HBM) having an increased bandwidth by including a plurality of independent channels having independent interfaces is illustrated.

[0062] Referring to Figure 5 , the stacked memory device 70a can include a plurality of layers. For example, the stacked memory device 70a can include the buffer wafer 200 and one or more memory wafers 300 stacked on the buffer wafer 200. In an example of Figure 5 , although the first memory wafer 300a, the second memory wafer 300b, the third memory wafer 300c, and the fourth memory wafer 300d are illustrated, the number of core wafers can be variously changed.

[0063] Also, each of the memory wafers 300 can include one or more channels. In Figure 5 ​​In the example of FIG. 1, the single memory wafer includes two channels, and thus, an example in which the stacked memory device 70a has eight channels CH1, CH2, CH3, CH4, CH5, CH6, CH7, and CH8 is shown.

[0064] For example, the first memory wafer 300a can include the first channel CH1 and the third channel CH3, the second memory wafer 300b can include the second channel CH2 and the fourth channel CH4, the third memory wafer 300c can include the fifth memory channel CH5 and the seventh channel CH7, and the fourth memory wafer 300d can include the sixth channel CH6 and the eighth channel CH8.

[0065] The buffer wafer 200 can communicate with the memory controller 20 (e.g., an external device), receive commands, addresses, and data from the memory controller, and provide the received commands, addresses, and data to the memory wafers 300. The buffer wafer 200 can communicate with the memory controller 20 through conductive devices such as bumps formed on an outer surface thereof. The buffer wafer 200 can buffer the commands, addresses, and data, and thus, the memory controller 20 can be coupled with the memory wafers 300 only by driving a load of the buffer wafer 200.

[0066] Further, the stacked memory device 70a can include a plurality of TSVs 220 passing through the layers.

[0067] The TSVs 220 can be provided corresponding to the plurality of channels CH1 to CH8, can be provided passing through the first memory wafer 300a to the fourth memory wafer 300d, and each of the first memory wafer 300a to the fourth memory wafer 300d can include a transmitter / receiver connected to the TSVs 220. When a normal operation of inputting and outputting data is independently performed for each channel, only the transmitter / receiver of any one core wafer can be enabled with respect to each of the TSVs 220, and thus, each of the TSVs 220 can independently transfer data of only one of the memory wafers or any channel as an independent channel for the one memory wafer or channel. In other words, the individual TSVs 220 can be used as independent channels.

[0068] The buffer wafer 200 can include an internal command generator (ICG) 210, an interface circuit 230, a TSV region (TSVR) 212, a physical region (PHYR) 213, and a direct access region (DAR) 214. The internal command generator 210 can generate internal commands based on the commands CMD. The interface circuit 230 can include a storage memory such as a static random access memory (SRAM) device.

[0069] The TSV region 212 is a region in which TSVs 220 for communication with the memory chip 300 are formed. The physical region 213 is a region including a plurality of input / output (IO) circuits for communication with the external memory controller 20. Various types of signals from the memory controller 20 can be provided to the TSV region 212 through the physical region 213, and to the memory chip 300 through the TSVs 220.

[0070] The direct access region 214 can communicate directly with an external test device in a test mode for the stacked memory device 70a through a conductive device disposed on an outer surface of the stacked memory device 70a. Various types of signals provided from the external test device can be provided to the memory chip 300 through the direct access region 214 and the TSV region 212.

[0071] The interface circuit 230 can provide an address and data from an external device to a target memory chip (e.g., one of the memory chips 300a to 300d), and can provide main data from the target memory chip to the external device. In addition, the interface circuit 230 can store a failed address and associated corrected data from the target memory chip in a storage memory.

[0072] Figure 6 An operation of the interface circuit in the stacked memory device of FIG. 1 is illustrated according to an exemplary embodiment of the present inventive concept. Figure 5 An operation of the interface circuit in the stacked memory device of FIG. 1 is illustrated according to an exemplary embodiment of the present inventive concept.

[0073] Referring to Figure 5 and Figure 6 The buffer chip 200 includes an internal command generator 210 and an interface circuit 230. An internal command ICMD from the internal command generator 210 is provided to the memory chips 300 through command TSVs TSV_C provided independently for each channel. The internal command generator 210 can provide a mode signal MS specifying one of a plurality of operation modes to the interface circuit 230 based on a command CMD.

[0074] The interface circuit 230 can include an SRAM 260. In response to the mode signal MS, in a first mode of a write operation, the interface circuit 230 can provide main data MD to corresponding memory chips through data TSVs TSV_D commonly provided for each channel.

[0075] The interface circuit 230 can provide the host data MD provided from the target memory chip to the external device through the data TSV TSV_D. Also, in a memory access operation including a read operation, the interface circuit 230 can store the fail address information FAI provided from the target memory chip and the associated corrected data C_MD associated with the first memory location in the target memory chip in the SRAM 260. The error attribute of the first memory location can be determined as a hard failure or a progressive failure.

[0076] The SRAM 260 can be referred to as a storage memory, and can be replaced by another type of memory capable of storing the fail address information FAI and the associated corrected data C_MD.

[0077] The memory chips 300 can respectively include command decoders (CMDC) 311a, 311b, 311c, and 311d outputting internal control signals by decoding internal commands, and data input / output (I / O) buffers (DATA I / O B) 313a, 313b, 313c, and 313d performing processing operations on read data or data to be written.

[0078] Referring to one of the memory chips 300 (for example, the first memory chip 300a), the first memory chip 300a can perform a memory operation according to a decoding result of the command decoder 311a, for example, can read data of a plurality of bits stored in a memory cell region inside the first memory chip 300a, and can provide the same to the data I / O buffer 313a. The data I / O buffer 313a can process the plurality of bits of data in parallel, and output the parallel-processed data in parallel to a plurality of data TSVs TSV_D.

[0079] Figure 7 is a block diagram illustrating an example of an interface circuit in Figure 6 according to an exemplary embodiment of the inventive concept.

[0080] Referring to Figure 7 , the interface circuit 230 can include a first path control circuit 240, a second path control circuit 270, a switch 251, an address comparator 252, a controller 253, a demultiplexer 254, a multiplexer 255, and an SRAM 260.

[0081] The first path control circuit 240 includes buffers 241, 242, and 243, and the second path control circuit 270 includes buffers 271, 272, 273, 274, and 275.

[0082] Buffer 241 provides address ADDR to switch 251, and switch 251 can provide address ADDR to either buffer 271 or address comparator 252 in response to switch control signal SCS. Buffer 271 provides address ADDR to the target memory chip.

[0083] Buffer 272 can provide SRAM 260 with Failure Address Information (FAI) from the target memory chip. Buffer 273 can provide SRAM 260 with Correction Data C_MD from the target memory chip.

[0084] SRAM 260 can provide Failed Address Information (FAI) to Address Comparator 252 and can provide Corrected Data C_MD to Multiplexer 255. Address Comparator 252 can compare the address ADDR from an external device with the Failed Address Information (FAI) and can provide Address Comparison Signal ACS to Controller 253 based on the comparison result.

[0085] Based on the mode signal MS and the address comparison signal ACS, the controller 253 can provide the switch control signal SCS to the switch 251, the selection signal SS1 to the demultiplexer 254, and the selection signal SS2 to the multiplexer 255.

[0086] Buffer 275 can provide multiplexer 255 with master data MD from the target memory chip. Based on selection signal SS2, multiplexer 255 can provide master data MD to buffer 243 in normal mode and can provide corrected data C_MD to buffer 243 in repair mode. Buffer 243 can provide either master data MD or corrected data C_MD to an external device.

[0087] The target memory chip can incorporate an ECC engine (e.g., within the SRAM 260) Figure 1 The address of the first memory location identified as a hard fault or a progressive fault in 500a) is stored as Failure Address Information (FAI), and the correction data associated with the first memory location can be stored in SRAM 260.

[0088] Therefore, after storing the failed address information FAI and the associated correction data C_MD in SRAM 260, address comparator 252 compares address ADDR with the failed address information FAI and provides an address comparison signal ACS to controller 253 based on the comparison result. Controller 253 can output selection signals SS1 and SS2 with a logic high level in response to address ADDR that matches one of the failed addresses in the failed address information FAI.

[0089] In addition, when at least some of the fail address information FAI is programmed in the fuse circuit during an idle time of the stacked memory device, the controller 253 can reset the programmed some of the fail address information FAI in the SRAM 260.

[0090] Figure 8 FIG. 1 illustrates an example of a stacked memory device according to an example embodiment of the present inventive concept. Figure 7

[0091] Referring to Figure 8 , the SRAM 260 can include a storage table 261 storing the fail address information FAI and the corresponding corrected data C_MD.

[0092] Each of indexes (e.g., entries) Idx11, Indx12, …, Idx1g (g is a natural number greater than two) of the storage table 261 can include the fail address information FAI and the corresponding corrected data C_MD provided from at least some of the memory dies 300a ~ 300k.

[0093] The storage table 261 includes a first column 262 and a second column 263. The first column 262 can store chip identifiers / block addresses / row addresses / column addresses CID / BA / RA / CA_1, CID / BA / RA / CA_2, …, CID / BA / RA / CA_g associated with such memory dies as the fail address information FAI: the memory dies include defective memory locations (or regions) determined as hard failures or progressive failures by the control logic circuit (e.g., 67) in Figure 1 The second column 263 can store corrected data C_MD1, C_MD2, …, C_MDg associated with the chip identifiers / block addresses / row addresses / column addresses CID / BA / RA / CA_1, CID / BA / RA / CA_2, …, CID / BA / RA / CA_g, respectively, as the corrected data C_MD.

[0094] At least some of the chip identifiers / block addresses / row addresses / column addresses CID / BA / RA / CA_1, CID / BA / RA / CA_2, …, CID / BA / RA / CA_g can be associated with the same memory dies, and at least some of the chip identifiers / block addresses / row addresses / column addresses CID / BA / RA / CA_1, CID / BA / RA / CA_2, …, CID / BA / RA / CA_g can be associated with different memory dies.

[0095] Figure 9 FIG. 1 illustrates an example of a stacked memory device according to an example embodiment of the present inventive concept. Figure 4 FIG. 1 illustrates an example of a stacked memory device according to an example embodiment of the present inventive concept.​

[0096] In Figure 9 , a configuration of the memory wafer 300a is shown, and each configuration of the plurality of memory wafers 300b~300k can be substantially the same as the configuration of the memory wafer 300a.

[0097] Referring to Figure 9 , the memory wafer 300a includes a memory cell array 400a, a row decoder 361a, a column decoder 371a, and / or a peripheral circuit 301a, but the inventive concept is not limited thereto.

[0098] The memory cell array 400a can include a plurality of memory blocks MB1~MBq (where q is an integer greater than one), and each of the memory blocks MB1~MBq includes memory cells coupled to a word line WL and a bit line BL and a spare cell coupled to the word line WL and at least one spare bit line SBL. The plurality of memory blocks MB1~MBq can share the word line WL, but can not share the bit line BL and the spare bit line SBL. Data associated with each of the memory blocks MB1~MBq can be input / output through a corresponding input / output pad.

[0099] The memory wafer 300a can receive an activation command before receiving a write command and / or a read command from the outside (e.g., a memory controller and / or a test device, another external source device, etc.). All memory cells connected to the word line WL of the memory wafer 300a can be selected based on the activation command. Then, if the memory wafer 300a receives the write command and / or the read command, a plurality of bit lines BL can be selected. In an exemplary embodiment of the inventive concept, the bit lines BL shown in the memory blocks MB1~MBq can be selected by the write command and / or the read command. Data input / output can be performed on the memory cells coupled to the selected bit lines BL.

[0100] In addition, according to an exemplary embodiment of the inventive concept, parity data for correcting errors in data stored in at least one of the memory blocks MB1~MBq can be stored in some of the memory blocks MB1~MBq, but the inventive concept is not limited thereto.

[0101] The column decoder 371a can be connected to the memory cell array 400a through a column selection line CSL and a spare column selection line SCSL. The column decoder 371a can select the column selection line CSL and / or the spare column selection line SCSL based on the write command and / or the read command. If the column decoder 371a selects the column selection line CSL, a bit line BL is selected. When the column decoder 371a selects the spare column selection line SCSL, a spare bit line SBL is selected.

[0102] The peripheral circuit 301a can include command / address pads (CMD / ADDR) 303, input / output (or DQ) pads 305, and an ECC engine 500.

[0103] In an exemplary embodiment of the inventive concept, the ECC engine 500 can not be included in the peripheral circuit 301a. The peripheral circuit 301a can receive internal commands ICMD from the internal command generator 210, can receive addresses ADDR from the interface circuit 230, and can exchange main data MD with an external device. The peripheral circuit 301a can include a command decoder 311a and / or a mode register 312a.

[0104] The peripheral circuit 301a can provide column addresses CADDR to the column decoder 371a and / or can provide row addresses RADDR to the row decoder 361a according to commands CMD received from the outside (e.g., an external source). The peripheral circuit 301a can provide main data MD to the column decoder 371a (via DQ lines) in response to a write command and / or can receive main data MD from the column decoder 371a (via DQ lines) in response to a read command. The main data MD can be provided to an external device (e.g., a memory controller) through the input / output pads 305 and the interface circuit 230.

[0105] According to an exemplary embodiment of the inventive concept, the ECC engine 500 can perform ECC encoding on input data to generate parity data. The ECC engine 500 can store the input data and the parity data in one or more of the memory blocks MB1~MBq. The ECC engine 500 can perform ECC decoding on data read from one or more of the memory blocks MB1~MBq to correct at least one error in the read data. The ECC engine 500 can transmit the corrected data to the interface circuit 230 through the input / output pads 305.

[0106] The peripheral circuit 301a can provide failure address information FAI to the interface circuit 230 and the column decoder 371a.

[0107] The row decoder 361a can activate a first word line designated by the row address RADDR in response to the row address RADDR. The row decoder 361a can include a segment information generator (SBIG) 380, and the segment information generator 380 can generate anti-fuse information AFI indicating whether to use an idle bit line.

[0108] The column decoder 371a can receive the anti-fuse information AFI and the failure address information FAI, and can repair a defective memory area (or location) in each of the memory blocks MB1~MBq based on the anti-fuse information AFI and the failure address information FAI.

[0109] Figure 10 shows an example of a first memory block in a memory wafer according to an example embodiment of the inventive concept. Figure 9 shows an example of a first memory block in a memory wafer according to an example embodiment of the inventive concept.

[0110] Referring to Figure 10 , the first memory block MB1 includes a normal cell region NCR and / or a spare cell region SCR, etc. The normal cell region NCR includes a plurality of word lines WL1-WLm (m is a natural number greater than two), a plurality of bit lines BL1-BLn (n is a natural number greater than two), and a plurality of memory cells MC disposed at intersections between the word lines WL1-WLm and the bit lines BL1-BLn. The spare cell region SCR includes a plurality of spare bit lines SBL1-SBLy (y is a natural number greater than two), the word lines WL1-WLm, and a plurality of spare cells SMC disposed at intersections between the word lines WL1-WLm and the spare bit lines SBL1-SBLy. If some of the memory cells MC have defects, the defective memory cells MC can be repaired with the spare cells SMC.

[0111] The word lines WL1-WLm extend in a first direction D1, and the bit lines BL1-BLn and the spare bit lines SBL1-SBLy extend in a second direction D2 crossing the first direction D1. The first memory block MB1 can be divided into a plurality of segments by segments of row addresses in the second direction D2.

[0112] Figure 11 shows an example of a first memory block in a memory wafer according to an example embodiment of the inventive concept. Figure 10 shows a relationship between the column selection lines and the bit lines.

[0113] In Figure 11 , only the first memory block MB1 is shown in detail for simplicity. Each of the memory blocks MB2-MBq can be configured and / or implemented identically to the first memory block MB1, but is not limited thereto. In addition, in Figure 11 , only one word line WL is shown, and the peripheral circuit 301a and the row decoder 361a in Figure 9 are not shown.

[0114] The column decoder 371a can select the column selection lines CSL of each of the memory blocks MB1-MBq based on the write command and / or the read command. Each of the column selection lines CSL can be connected to the plurality of bit lines BL through the switch SW1. The column decoder 371a can selectively select the spare column selection lines SCSL of each of the memory blocks MB1-MBq instead of the column selection lines CSL based on the write command and / or the read command.

[0115] The idle column select line SCSL can be connected with the idle bit line SBL through the switch SW2. In an exemplary embodiment of the inventive concept, the column decoder 371a can selectively deselect the column select line CSL and the idle column select line SCSL of each of the memory blocks MB1 ~ MBq based on a write command and / or a read command.

[0116] Figure 12 An example of a peripheral circuit in a memory wafer according to an exemplary embodiment is shown. Figure 9

[0117] Referring to Figure 12 , the peripheral circuit 301a can include a control logic circuit 310a, an ECC engine 500, a data I / O buffer 313a, an error information register 580, a command / address pad 303, and an input / output pad 305. The control logic circuit 310a can include a command decoder 311a and a mode register 312a.

[0118] The command / address pad 303 can receive an internal command I CMD and an address ADDR, and can provide the internal command I CMD and the address ADDR to the control logic circuit 310a. The command decoder 311a can decode the internal command I CMD, and the mode register 312a can set an operation mode of the memory wafer 300a. The control logic circuit 310a can generate a first control signal CTL1 to control the ECC engine 500 and a second control signal CTL2 to control the error information register 580 by decoding the internal command I CMD.

[0119] The input / output pad 305 can provide a main data MD to the ECC engine 500 through the data I / O buffer 313a. The ECC engine 500 can perform ECC decoding on data corresponding to a first codeword from the memory cell array 400a, can provide an error generation signal EGS to the control logic circuit 310a in response to detecting an error in the data, and can provide syndrome information SDRI associated with the detected error to the error information register 580.

[0120] The control logic circuit 310a can provide, to the error information register 580, a first address of a first memory location associated with the detected error as error information EINF based on the error generation signal EGS.

[0121] The error information register 580 can store the first address associated with the detected error and the syndrome information SDRI.

[0122] ​Based on a plurality of read-modify-write operations (e.g., memory access operations), the control logic circuit 310a can determine an error attribute of the first codeword based on a change of the first syndrome associated with the first codeword recorded in the error information register 580. When the control logic circuit 310a determines the error attribute of the first codeword (e.g., the first memory location) as a hard failure or a progressive failure, the control logic circuit 310a controls the error information register 580 so that the first address of the first memory location is provided to the interface circuit 230 as the fail address information FAI. In addition, the control logic circuit 310a controls the ECC engine 500 so that the ECC engine 500 provides the corrected data C_MD read from the first memory location and corrected to the interface circuit 230.

[0123] Figure 13 A memory cell array, a row decoder, and a column decoder in a memory chip according to an exemplary embodiment of the present inventive concept are illustrated. Figure 9

[0124] Referring to Figure 13 In the memory cell array 400a, I subarray blocks SCB can be disposed in a first direction D1, and J subarray blocks SCB can be disposed in a second direction D2 substantially perpendicular to the first direction D1. The I subarray blocks SCB disposed in the first direction D1 and the J subarray blocks SCB disposed in a row in the first direction D1 can be referred to as a row block. A plurality of bit lines, a plurality of word lines, and a plurality of memory cells can be disposed in each of the subarray blocks SCB.

[0125] I+1 sub word line driver regions SWB can be disposed between the subarray blocks SCB in the first direction D1. Each of the subarray blocks SCB can correspond to a segment of each of the memory blocks. Sub word line drivers can be disposed in the sub word line driver regions SWB. For example, J+1 bit line sense amplifier regions BLSAB can be disposed between the subarray blocks SCB in the second direction D2. Bit line sense amplifiers that sense data stored in the memory cells can be disposed in the bit line sense amplifier regions BLSAB.

[0126] A plurality of coupling regions CONJ can be disposed adjacent to the sub word line driver regions SWB and the bit line sense amplifier regions BLSAB.

[0127] The row decoder 361a includes a segment information generation circuit 380, and the segment information generation circuit 380 can include a plurality of segment information circuits (SGIC1-SGICJ) 381-38J corresponding to segments in the second direction D2, etc. The segment information circuits 381-38J can output anti-fuse information AFI to the column decoder 371a in response to a row address RADDR. ​

[0128] The column decoder 371a can include a plurality of sub-column decoders (SCD1 ~SCDJ) 451 ~ 45I, a plurality of repair circuits 401 ~ 40I, and a register (REG) 460. The register 460 can store fail address information FAI provided from the error information register 580 in the memory chip 300a. The register 460 can be connected to the plurality of repair circuits 401 ~ 40I. A soft PPR can be performed on a defective memory area by the register 460 storing the fail address information FAI during operation of the memory chip 300a. Figure 12

[0129] Each of the sub-column decoders 451 ~ 45I can be connected to a corresponding memory block among the plurality of memory blocks, and the plurality of repair circuits 401 ~ 40I can correspond to the plurality of sub-column decoders 451 ~ 45I. Each of the repair circuits 401 ~ 40I can selectively activate a first repair signal CREN1 or a second repair signal CREN2 in response to the column address CADDR, the antifuse information AFI, and the fail address information FAI stored in the register 460, and provide the first repair signal CREN1 and / or the second repair signal CREN2 to a corresponding one of the sub-column decoders 451 ~ 45I.

[0130] Each of the sub-column decoders 451 ~ 45I can select one of the column selection line CSL and the idle column selection line SCSL in response to the first repair signal CERN1, and can deselect the column selection line CSL and the idle column selection line SCSL in response to the second repair signal CERN2.

[0131] For example, each of the sub-column decoders 451 ~ 45I can select the column selection line CSL in response to the first repair signal CERN1 being deactivated. Each of the sub-column decoders 451 ~ 45I can select the idle column selection line SCSL in response to the first repair signal CERN1 being activated. Each of the sub-column decoders 451 ~ 45I can deselect the column selection line CSL and the idle column selection line SCSL in response to the second repair signal CERN2 being activated. In other words, each of the sub-column decoders 451 ~ 45I can disable the column selection line CSL and the idle column selection line SCSL in response to the second repair signal CERN2 being activated.

[0132] Figure 14 is a block diagram illustrating a first section information circuit of a section information circuit in Figure 13 according to an exemplary embodiment of the inventive concept.

[0133] Referring to Figure 14 ​The first section information circuit 381 can store the antifuse information AFI associated with repair of the corresponding section, and can provide the antifuse information AFI indicating whether to use the spare bit line in the corresponding section to the column decoder 371a. The section information circuit 381 can be implemented with a fuse circuit.

[0134] Figure 15 is a block diagram illustrating a first repair circuit in repair circuits in a memory device according to an exemplary embodiment of the present inventive concept. Figure 13

[0135] The respective configurations of the repair circuits 402 to 40I can be substantially the same as that of the first repair circuit 401, but the present inventive concept is not limited thereto.

[0136] Referring to Figure 15 The first repair circuit 401 includes a failed address storage table 410, a first column address comparator 415, a second column address comparator 417, a fuse information storage circuit 420, and a repair signal generator 440.

[0137] The failed address storage table 410 can store failed column address information FCAI associated with column address information of defective cells of the corresponding memory block. The first column address comparator 415 can compare the column address CADDR with the failed column address information FCAI to output a first column match signal CMTH1 to the fuse information storage circuit 420 and the repair signal generator 440. The first column match signal CMTH1 can indicate whether the column address CADDR matches the failed column address information FCAI. The failed address storage table 410 can be implemented with an antifuse array including an antifuse.

[0138] The second column address comparator 417 can compare the column address CADDR with the failed address information FAI to output a second column match signal CMTH2 to the repair signal generator 440. The second column match signal CMTH2 can indicate whether the column address CADDR matches the column address of the failed address information FAI of the first memory location determined as a hard failure or a progressive failure.

[0139] The fuse information storage circuit 420 includes a plurality of cell groups 421, 422, and 423, etc. Each of the cell groups 421, 422, and 423 can include a first area 421a and a second area 421b, but is not limited thereto. The first area 421a can store spare bit line information SBI on a spare bit line to repair defective cells in each of the sections in the corresponding memory block, and the second area 421b can store antifuse information AFI associated with availability of the spare bit line of the corresponding section (e.g., availability of the spare bit line in different sections).

[0140] ​The fuse information storage circuit 420 can store the spare bit line information SBI and the anti-fuse information AFI. The fuse information storage circuit 420 can provide the spare bit line information SBI and the anti-fuse information AFI to the repair signal generator 440 in response to the first column match signal CMTH1.

[0141] The repair signal generator 440 can determine logic levels of the first repair signal CREN1 and the second repair signal CREN2 based on the first column match signal CMTH1, the second column match signal CMTH2, the spare bit line information SBI, and / or the anti-fuse information AFI.

[0142] For example, when the first column match signal CMTH1 indicates that the column address CADDR does not match the failed column address information FCAI, the repair signal generator 440 deactivates the first repair signal CREN1. In this case, Figure 13 The first sub-column decoder 451 in the repair signal generator 440 selects the column selection line CSL.

[0143] For example, when the first column match signal CMTH1 indicates that the column address CADDR matches the failed column address information FCAI, and the anti-fuse information AFI indicates that the spare bit line in the corresponding section is available, the repair signal generator 440 activates the first repair signal CREN1 with a high level (e.g., a high signal, a high voltage level, etc.). In this case, Figure 13 The first sub-column decoder 451 in the repair signal generator 440 selects the spare column selection line SCSL.

[0144] For example, when the second column match signal CMTH2 indicates that the column address CADDR matches the column address of the failed address information FAI, the repair signal generator 440 activates the second repair signal CREN2 with a high level. In this case, Figure 13 The first sub-column decoder 451 in the repair signal generator 440 deselects the column selection line CSL and the spare column selection line SCSL to cut off access to the memory cell array 400a.

[0145] In an exemplary embodiment of the inventive concept, the control logic circuit 310a can program the failed address information FAI stored in the register 460 in the failed address storage table 410 during a spare time of the stacked memory device 70a. The control logic circuit 310a can perform a hard PPR in a defective memory area by programming the failed address information FAI in the failed address storage table 410.

[0146] Figure 16 is an example of an error information register in a peripheral circuit in Figure 12 according to an exemplary embodiment of the inventive concept.

[0147] Referring to Figure 16Each of indexes (e.g., entries) Indx21, Indx22, …, Indx2u of the error information register 580 can include the failure address information FAI_CID1 of the first memory chip and the corresponding syndrome information SDRI. The indexes (e.g., entries) Indx21, Indx22, …, Indx2u of the error information register 580 can store the error attribute ATT of the defective memory area based on a change of the corresponding syndrome. The error information register 580 includes a first column 581, a second column 582, and a third column 583.

[0148] The first column 581 can store the failure address information BA / RA / CA_11, BA / RA / CA_12, …, BA / RA / CA_1u of the defective memory area. The second column 582 can store the syndrome SDR1, SDR2, …, SDRu of the codeword read from the defective memory area. The third column 583 can store the error attribute ATTa, ATTb, …, ATTc of the defective memory area based on a change of the syndrome (e.g., value of the syndrome).

[0149] The error attribute ATTa can represent a soft failure, the error attribute ATTb can represent a hard failure, and the error attribute ATTc can represent a progressive failure. The hard failure can refer to a case in which hardware of a memory cell is damaged. The soft failure can refer to a case in which the hardware of the memory cell is not damaged but data of the memory cell is temporarily transited due to an alpha particle or the like. The progressive failure can refer to a case in which the memory cell develops from the soft failure to the hard failure. In other words, the progressive failure can indicate that the soft failure is likely to become the hard failure.

[0150] Based on the multiple read-modify-write operations (memory access operations), the control logic circuit 310a can determine the error attribute of each of the defective memory areas based on a change of the syndrome associated with the codeword read from each of the defective memory areas recorded in the error information register 580. When the control logic circuit 310a determines the error attribute as the hard failure or the progressive failure, the control logic circuit 310a controls the error information register 580 and the ECC engine 500 such that the failure address information of the defective memory area and the associated syndrome data are stored in the storage memory (e.g., SRAM 260) in the interface circuit 230.

[0151] Figure 17 is a block diagram illustrating an example of an ECC engine in a memory chip according to an example embodiment of the present inventive concept. Figure 9

[0152] Referring to Figure 17 ​The ECC engine 500 can include an ECC encoder 510, an ECC decoder 530, and an (ECC) memory 515. The memory 515 can store an ECC 520. The ECC 520 can be a single error correction (SEC) code, or a single error correction / double error detection (SECDED) code, but is not limited thereto.

[0153] The ECC encoder 510 can generate parity data PRT with the ECC 520 associated with the write data WMD to be stored in the normal cell array NCA of the first block array BKAR1. The parity data PRT can be stored in the redundant cell array RCA of the first block array BKAR1.

[0154] The ECC decoder 530 can perform ECC decoding on the read data RMD based on the read data RMD and the parity data PRT read from the first block array BKAR1 with the ECC 520. When the read data RMD includes at least one error (bit) as a result of the ECC decoding, the ECC decoder 530 provides an error generation signal EGS to the control logic circuit 310a. In addition, the ECC decoder 530 can provide syndrome information SDRI associated with the at least one error to the error information register 580, and can selectively correct the error bit in the read data RMD to output corrected main data C_MD in the read operation.

[0155] Figure 18 An example of an ECC encoder in an ECC engine according to exemplary embodiments of the inventive concept is shown. Figure 17 An example of an ECC encoder in an ECC engine according to exemplary embodiments of the inventive concept is shown.

[0156] Referring to Figure 18 The ECC encoder 510 can include a parity generator 520. The parity generator 520 receives the write data WMD and the base bit BB, and generates the parity data PRT by, for example, performing an XOR array operation.

[0157] Figure 19 An example of an ECC decoder in an ECC engine according to exemplary embodiments of the inventive concept is shown. Figure 17 An example of an ECC decoder in an ECC engine according to exemplary embodiments of the inventive concept is shown.

[0158] Referring to Figure 19 The ECC decoder 530 can include a syndrome generation circuit 540, an error locator 560, a data corrector 570, and a syndrome buffer 575. The syndrome generation circuit 540 can include a check bit generator 541 and a syndrome generator 543.

[0159] The syndrome generator 543 generates the syndrome SDR by comparing corresponding bits of the parity data PRT and the check bits CHB. The error locator 560 generates the error location signal EPS indicating the position of the error bit in the read data RMD when all bits of the syndrome SDR are non-zero, and provides the error location signal EPS to the data corrector 570. In addition, the error locator 560 provides the error generation signal EGS to the control logic circuit 310a and the syndrome SDR to the syndrome buffer 575 when the read data RMD includes the error bit.

[0160] The syndrome buffer 575 stores the syndrome SDR and provides the stored syndrome SDR to the error information register 580. In other words, the syndrome buffer 575 provides the stored syndrome SDR as syndrome information SDRl to the error information register 580.

[0161] The data corrector 570 receives the read data RMD, corrects the error bit in the read data RMD based on the error location signal EPS when the read data RMD includes the error bit, and outputs the corrected main data C_MD.

[0162] The data corrector 570 receives the read data RMD, corrects the error bit in the read data RMD based on the error location signal EPS when the read data RMD includes the error bit, and outputs the corrected main data C_MD.

[0163] Figures 20 to 22 The control logic circuit is shown to determine the error attribute based on a change in the value of the syndrome according to exemplary embodiments of the inventive concept is shown, respectively.

[0164] In Figures 20 to 22 SDR_M_RD indicates the syndrome obtained by the Mth ECC decoding on the first memory location, and SDR_N_RD indicates the syndrome obtained by the Nth ECC decoding on the first memory location. Here, M is an integer greater than one, and N is an integer greater than M.

[0165] Referring to Figure 20 When the Mth value of the syndrome SDR_M_RD obtained by the Mth ECC decoding is '10001100' (which is non-zero) and the Nth value of the syndrome SDR_N_RD obtained by the Nth ECC decoding is '00000000' (which is zero), the control logic circuit 310a determines the error attribute to be the first error attribute ATTa corresponding to a soft failure.

[0166] Referring to Figure 21When the Mth value of the syndrome SDR M RD obtained by the Mth ECC decoding is '10001100' (which is non-zero) and the Nth value of the syndrome SDR N RD obtained by the Nth ECC decoding is '10001100' (which is non-zero), the Mth value is identical to the Nth value. Accordingly, the control logic circuit 310a determines the error attribute as a second error attribute ATTb corresponding to a hard failure.

[0167] Referring to Figure 22 When the Mth value of the syndrome SDR M RD obtained by the Mth ECC decoding is '10001100' (which is non-zero) and the Nth value of the syndrome SDR N RD obtained by the Nth ECC decoding is '10010000' (which is non-zero), the Mth value is different from the Nth value. Accordingly, the control logic circuit 310a determines the error attribute as a third error attribute ATTc corresponding to a progressive failure.

[0168] When the error attribute based on the change in the value of the syndrome corresponds to a hard failure or a progressive failure, the control logic circuit 310a can store the associated failed address information and corrected data in the SRAM 260. When the error attribute based on the change in the value of the syndrome corresponds to a soft failure, the control logic circuit 310a can control the ECC engine 500 to correct the error, instead of storing the associated failed address information and corrected data in the SRAM 260.

[0169] Figure 23 is a block diagram of an example of a semiconductor memory device in a memory system according to an exemplary embodiment of the present inventive concept. Figure 1 is a block diagram of an example of a semiconductor memory device in a memory system according to an exemplary embodiment of the present inventive concept.

[0170] Referring to Figure 23 The semiconductor memory device 600 includes a control logic circuit 610, an address register 620, a block control logic 630, a refresh control circuit 685, a row address multiplexer (RA MUX) 640, a column address latch 650, a row decoder 660, a column decoder 670, a memory cell array 700, a sense amplifier unit 785, an I / O gating circuit 690, an ECC engine 500a, a scrub control circuit 705, a data I / O buffer 695, an error information register 580a, and an SRAM 590a.

[0171] The memory cell array 700 includes a first block array 710 to an eighth block array 780. The row decoders 660 include a first row decoder 660a to an eighth row decoder 660h coupled to the first block array 710 to the eighth block array 780, respectively, the column decoders 670 include a first column decoder 670a to an eighth column decoder 670h coupled to the first block array 710 to the eighth block array 780, respectively, and the sense amplifier units 785 include a first sense amplifier 785a to an eighth sense amplifier 785h coupled to the first block array 710 to the eighth block array 780, respectively.

[0172] The first block array 710 to the eighth block array 780, the first row decoder 660a to the eighth row decoder 660h, the first column decoder 670a to the eighth column decoder 670h, and the first sense amplifier 785a to the eighth sense amplifier 785h can form a first block to an eighth block. Each of the first block array 710 to the eighth block array 780 includes a plurality of memory cells MC formed at intersection positions of a plurality of word lines WL and a plurality of bit lines BTL.

[0173] The address register 620 receives an address ADDR including a block address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 20. The address register 620 provides the received block address BANK_ADDR to the block control logic 630, provides the received row address ROW_ADDR to the row address multiplexer 640, and provides the received column address COL_ADDR to the column address latch 650.

[0174] The block control logic 630 generates a block control signal in response to the block address BANK_ADDR. One of the first row decoder 660a to the eighth row decoder 660h corresponding to the block address BANK_ADDR is activated in response to the block control signal, and one of the first column decoder 670a to the eighth column decoder 670h corresponding to the block address BANK_ADDR is activated in response to the block control signal.

[0175] The row address multiplexer 640 receives the row address ROW_ADDR from the address register 620 and receives a refresh row address REF_ADDR from the refresh control circuit 685. The row address multiplexer 640 selectively outputs the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexer 640 is applied to the first row decoder 660a to the eighth row decoder 660h.

[0176] The refresh control circuit 685 can output the refresh row address REF_ADDR in order in response to the first refresh control signal IREF1 or the second refresh control signal IREF2 provided from the control logic circuit 610.

[0177] When the command CMD from the memory controller 20 corresponds to the auto-refresh command, the control logic circuit 610 can apply the first refresh control signal IREF1 to the refresh control circuit 685 each time the control logic circuit 610 receives the auto-refresh command.

[0178] When the command CMD from the memory controller 20 corresponds to the self-refresh entry command, the control logic circuit 610 can apply the second refresh control signal IREF2 to the refresh control circuit 685. The second refresh control signal IREF2 is activated from a time point when the control logic circuit 610 receives the self-refresh entry command to a time point when the control logic circuit 610 receives the self-refresh exit command. The refresh control circuit 685 can increase or decrease the refresh row address REF_ADDR in order in response to receiving the first refresh control signal IREF1 or when the second refresh control signal IREF2 is activated.

[0179] One of the first to eighth row decoders 660a to 660h activated by the block control logic 630 decodes the row address RA output from the row address multiplexer 640 and activates a word line corresponding to the row address RA. For example, the activated block row decoder applies a word line driving voltage to the word line corresponding to the row address RA.

[0180] The column address latch 650 receives the column address COL_ADDR from the address register 620 and temporarily stores the received column address COL_ADDR. In an exemplary embodiment of the inventive concept, in a toggle mode, the column address latch 650 generates a column address increased from the received column address COL_ADDR. The column address latch 650 applies the temporarily stored or generated column address to the first to eighth column decoders 670a to 670h.

[0181] One of the first to eighth column decoders 670a to 670h activated by the I / O gate circuit 690 activates a sense amplifier corresponding to the block address BANK_ADDR and the column address COL_ADDR.

[0182] The I / O gate circuit 690 includes a circuit for gating input / output data, and further includes input data mask logic, read data latches for storing data output from the first to eighth block arrays 710 to 780, and write drivers for writing data to the first to eighth block arrays 710 to 780.

[0183] A codeword CW read from one of the first to eighth block arrays 710 to 780 is coupled to sensing of a sense amplifier of the one of the block arrays from which the data is read, and is stored in a read data latch. After ECC decoding is performed on the codeword CW by the ECC engine 500a, the codeword CW stored in the read data latch can be provided to the memory controller 20 via the data I / O buffer 695.

[0184] Main data MD to be written in one of the first to eighth block arrays 710 to 780 can be provided from the memory controller 20 to the data I / O buffer 695, and can be provided from the data I / O buffer 695 to the ECC engine 500a. In this case, the ECC engine 500a can perform ECC encoding on the main data MD to generate parity data, the ECC engine 500a can provide the main data MD and the parity data to the I / O gating circuit 690, and the I / O gating circuit 690 can write the main data MD and the parity data into subpages of a target page in the one of the block arrays by a write driver.

[0185] The data I / O buffer 695 can provide the main data MD from the memory controller 20 to the ECC engine 500a based on a clock signal CLK in a write operation of the semiconductor memory device 600, and can provide the main data MD from the ECC engine 500a to the memory controller 20 in a read operation of the semiconductor memory device 600.

[0186] The ECC engine 500a can perform operations similar to those of the ECC engine 500 in Figure 12 The ECC engine 500a performs ECC decoding on a codeword CW read from a subpage, provides an error generation signal EGS to the control logic circuit 610 in response to detection of an error based on the ECC decoding, and provides correction sub information SDRI associated with the detected error to the error information register 580a.

[0187] The scrub control circuit 705 can count refresh row addresses REF_ADDR changed in order, and can output a normal scrub address SCADDR each time the scrub control circuit 705 counts K refresh row addresses. Here, K is an integer greater than two. The normal scrub address SCADDR can include a scrub row address SRA and a scrub column address SCA. The scrub control circuit 705 can provide the scrub row address SRA and the scrub column address SCA to the row decoder 660 and the column decoder 670.

[0188] The control logic circuit 610 can control the operation of the semiconductor memory device 600. The control logic circuit 610 includes a command decoder 611 that decodes a command CMD received from the memory controller 20 and a mode register 612 that sets an operation mode of the semiconductor memory device 600.

[0189] For example, the command decoder 611 can generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, and the like.

[0190] The control logic circuit 610 can generate a first control signal CTL11 that controls the I / O gating circuit 690, a second control signal CTL12 that controls the ECC engine 500a, a third control signal CTL13 that controls the scrub control circuit 705, and a fourth control signal CTL14 that controls the error information register 580a.

[0191] The error information register 580a stores the error information EINF provided from the control logic circuit 610, provides the failed address information FAI to the SRAM 590a, and stores the syndrome information SDRI.

[0192] Based on a plurality of read-modify-write operations (memory access operations), the control logic circuit 610 can determine an error attribute of each of the defective memory regions based on a change in the syndrome recorded in the error information register 580a. When the control logic circuit 610 determines the error attribute as a hard failure or a progressive failure, the control logic circuit 610 controls the error information register 580a and the ECC engine 500a such that the failed address information FAI of the defective memory region and the associated corrected data C_MD are stored in the SRAM 590a.

[0193] The SRAM 590a can store the failed address information FAI and the associated corrected data C_MD.

[0194] When the second address from the memory controller 20 matches the failed address information FAI, the control logic circuit 610 controls the SRAM 590a such that data associated with the second address is input / output via the SRAM 590a. To accomplish such an operation, each of the first to eighth column decoders 670a to 670h can include Figure 15 the first column address comparator 415 and the second column address comparator 417 in the memory cell 400.

[0195] When each of the memory chips 300a to 300k employs Figure 23When the semiconductor memory device 600 of FIG. 6 is implemented, the SRAM 590a can be included in the buffer wafer 200, instead of being included in each of the memory wafers 300a ~ 300k.

[0196] Figure 24 FIG. 7 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present inventive concept.

[0197] Referring to Figure 24 The semiconductor memory device 800 can include a first group of wafers 810 and a second group of wafers 820 that provide a stacked chip structure.

[0198] The first group of wafers 810 can include at least one buffer wafer 811. In other words, the first group of wafers 810 can include only one wafer. The second group of wafers 820 can include a plurality of memory wafers 820-1 through 820-s stacked on the at least one buffer wafer 811 and transferring data through a plurality of substrate through via (or through silicon via (TSV)) lines. Here, s is an integer greater than two.

[0199] Each of the memory wafers 820-1 through 820-s can include a cell core 822 storing data and parity data, an ECC engine 824, an error information register 826, and a control logic circuit. Each of the control logic circuit, the ECC engine 824, and the error information register 826 can perform substantially the same operation as the corresponding one of the control logic circuit 310a, the ECC engine 500, and the error information register 580 in FIG. 5. Figure 12

[0200] The buffer wafer 811 can include an interface circuit 812, and the interface circuit 812 can include an ECC engine 814 and an SRAM 816. The interface circuit 812 can employ the interface circuit 230 in FIG. 2. The ECC engine 814 can be referred to as a via ECC engine, and can correct a transmission error provided from at least one of the memory wafers 820-1 through 820-s. Figure 7

[0201] The data TSV line group 832 formed at one memory wafer 820-s-1 can include a plurality of TSV lines L1 through Ls, and the parity TSV line group 834 can include a plurality of TSV lines L10 through Lt. The TSV lines L1 through Ls of the data TSV line group 832 and the parity TSV lines L10 through Lt of the parity TSV line group 834 can be connected to micro bumps MCB formed correspondingly in the memory wafers 820-1 through 820-s.

[0202] ​​At least one of the memory chips 820-1 to 820-s can include a DRAM cell each including at least one access transistor and one storage capacitor. The semiconductor memory device 800 can have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a host through a data bus B10. The buffer chip 811 can be connected with a memory controller through the data bus B10.

[0203] Figure 25 FIG. 1 is a flowchart illustrating a method of operating a semiconductor memory device according to an example embodiment of the present inventive concept.

[0204] Referring to Figures 5 to 25 A method of operating a semiconductor memory device including a buffer chip 200 and a plurality of memory chips 300a-300k stacked on the buffer chip 200 is provided. The buffer chip 200 and the memory chips 300a-300k can be stacked on each other in order. The memory chips 300a-300k are electrically connected to the buffer chip 200 through TSVs 220. Each of the memory chips 300a-300k includes a memory cell array, a control logic circuit, an ECC engine, and an error information register.

[0205] According to the method, the ECC engine performs ECC decoding on a first codeword read from a first sub-page in the memory cell array while performing a plurality of memory operations (e.g., access operations) on the memory cell array in a target memory chip among the memory chips 300a-300k (operation S110).

[0206] The control logic circuit stores a first address of the first codeword and the first codeword in the error information register in response to detecting an error in the first codeword based on a result of the ECC decoding (operation S130).

[0207] The control logic circuit determines an error attribute of a first memory location corresponding to the first sub-page based on a change of a syndrome associated with the first codeword (operation S150).

[0208] The control logic circuit selectively stores the first address and corrected data in an interface circuit in the buffer chip based on the determined error attribute (operation S170).

[0209] When the control logic circuit determines the error attribute as a hard failure or a progressive failure, the control logic circuit can perform a soft PPR in the first memory location by storing the first address and the corrected data in the interface circuit during operation of the semiconductor memory device.

[0210] Figure 26FIG. 1 is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment of the present inventive concept.

[0211] Referring to Figure 26 , the semiconductor package 900 can include one or more stacked memory devices 910 and a GPU 920.

[0212] The stacked memory devices 910 and the GPU 920 can be mounted on an interposer 930, and the interposer on which the stacked memory devices 910 and the GPU 920 are mounted can be mounted on a package substrate 940. The package substrate 940 can be mounted on solder balls 950.

[0213] The GPU 920 can perform the same operation as the memory controller 20 in Figure 2 , or can be included in the memory controller 20. The GPU 920 can include a first ECC engine using a first ECC. The GPU 920 can store data generated or used in graphics processing in the stacked memory device 910.

[0214] The stacked memory device 910 can be implemented in various forms, and the stacked memory device 910 can be a memory device in the form of a high bandwidth memory (HBM) in which a plurality of layers are stacked. Accordingly, the stacked memory device 910 can include a buffer wafer and a plurality of memory wafers. The buffer wafer can include an interface circuit.

[0215] Each of the memory wafers includes an array of memory cells, a control logic circuit, an ECC engine, and an error information register. Accordingly, the control logic circuit can control the ECC engine to perform a read-modify-write operation by reading data corresponding to a first codeword from a sub-page in a first memory cell row, perform ECC decoding on the data to generate an error generation signal in response to detecting an error in the first codeword, correct the detected error in the first codeword, and write the corrected first codeword back into a first memory location corresponding to the first sub-page.

[0216] In addition, the control logic circuit can record a first address associated with the first codeword in the error information register based on the error generation signal and the first corrected sub obtained through the ECC decoding, and can determine an error attribute of the first codeword based on a change in the first corrected sub recorded in the error information register based on a plurality of read-modify-write operations. When the control logic circuit determines that the error attribute is a hard failure or a progressive failure, the control logic circuit can perform a soft PPR in the interface circuit during operation of the stacked memory device 910 by storing the failure address information of the first memory location and the associated corrected data in a storage memory.

[0217] A plurality of stacked memory devices 910 can be mounted on the middle layer 930, and the GPU 920 can communicate with the plurality of stacked memory devices 910. For example, each of the stacked memory devices 910 and the GPU 920 can include a physical region, and communication can be performed between the stacked memory devices 910 and the GPU 920 through the physical region.

[0218] The exemplary embodiments of the present inventive concept can be applied to various systems employing semiconductor memory devices and stacked memory devices, and thus, can perform a soft PPR on defective memory cells based on error attributes while the semiconductor memory devices are operating.

[0219] While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present inventive concept as set forth by the following claims.

Claims

1. A semiconductor memory device comprising: a buffer wafer; a plurality of memory wafers stacked on the buffer wafer; and a plurality of through-silicon vias connecting the plurality of memory wafers to the buffer wafer, wherein at least one of the plurality of memory wafers comprises: an array of memory cells comprising a plurality of rows of memory cells, each row comprising a plurality of volatile memory cells; an error correction code engine; an error information register; and control logic configured to control the error correction code engine to perform a read-modify-write operation by: reading data corresponding to a first codeword from a sub-page in a first row of memory cells of the plurality of rows of memory cells based on an access address and a command; performing error correction code decoding on the data in response to detecting an error in the first codeword to produce an error generation signal; correcting the detected error in the first codeword; and writing the corrected first codeword into a first memory location corresponding to the sub-page, wherein the control logic is configured to: record in the error information register a first address associated with the first codeword based on the error generation signal and a first syndrome obtained by the error correction code decoding; and determine an error attribute of the first codeword based on a change in the first syndrome associated with the first codeword recorded in the error information register based on a plurality of read-modify-write operations.

2. The semiconductor memory device of claim 1, the buffer wafer comprises an interface circuit connected to the through-silicon vias and comprises a storage memory, and wherein wherein the control logic is configured to repair the first memory location based on the determined error attribute. when the first syndrome obtained by the error correction code decoding has a non-zero value, the control logic is configured to repair the first memory location by storing the first address and associated corrected data in the storage memory.

3. The semiconductor memory device of claim 2, wherein, when the first syndrome obtained based on the plurality of read-modify-write operations has a non-zero value and an Mth value of the first syndrome obtained by an Mth error correction code decoding is the same as an Nth value of the first syndrome obtained by an Nth error correction code decoding, 4. The semiconductor memory device of claim 2, wherein, the control logic is configured to: determine the error attribute as a hard failure; and repair the first memory location by storing the first address and associated corrected data in the storage memory, wherein M is an integer greater than one and N is an integer greater than M. when the first syndrome obtained based on the plurality of read-modify-write operations has a non-zero value and the Mth value of the first syndrome obtained by the Mth error correction code decoding is different from the Nth value of the first syndrome obtained by the Nth error correction code decoding, 5. The semiconductor memory device of claim 2, wherein, the control logic is configured to: determine the error attribute as a progressive failure; and repair the first memory location by storing the first address and associated corrected data in the storage memory, wherein M is an integer greater than one and N is an integer greater than M. ​ 6. The semiconductor memory device of claim 2, wherein, The control logic circuit is configured to repair a first memory cell row including the first memory location or a column associated with the first memory location based on the determined error attribute.

7. The semiconductor memory device of claim 2, wherein, The storage memory is configured to store a first address designating the first memory location as a hard failure or a progressive failure, associated corrected data, and a chip identifier of a corresponding memory die.

8. The semiconductor memory device of claim 7, wherein, The interface circuit is configured to control the storage memory such that the corrected data stored in the storage memory is input / output in response to a second address matching the first address after completion of the repair of the first memory location.

9. The semiconductor memory device of claim 1, wherein, The control logic circuit is configured to control the error information register such that a first address associated with the first memory location is provided to a column decoder coupled to the memory cell array through a bit line in response to the control logic circuit determining the error attribute as a hard failure or a progressive failure, and wherein the column decoder includes a register storing the first address.

10. The semiconductor memory device of claim 9, wherein, The column decoder is configured to deselect a normal bit line coupled to a normal cell and a spare bit line coupled to a spare cell in response to a new access address matching the first address.

11. The semiconductor memory device of claim 9, wherein, The control logic circuit is configured to program the first address stored in the register in a defective address storage table in a repair circuit in the column decoder during an idle time of the semiconductor memory device.

12. The semiconductor memory device of claim 1, wherein, The buffer die includes a through-hole error correction code engine configured to correct a transmission error in data provided from at least one of the memory dies through a through-silicon via.

13. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cell rows, each row including a plurality of volatile memory cells; an error correction code engine; an error information register; and a control logic circuit configured to control the error correction code engine to perform a read-modify-write operation by: reading data corresponding to a first codeword from a sub-page in a first memory cell row of the plurality of memory cell rows based on an access address and a command; performing error correction code decoding on the data in response to detecting an error in the first codeword to generate an error occurrence signal; correcting the detected error in the first codeword; and writing the corrected first codeword into a first memory location corresponding to the sub-page, wherein the control logic circuit is configured to: record a first address associated with the first codeword based on the error occurrence signal and a first syndrome obtained by the error correction code decoding in the error information register; and determine an error attribute of the first codeword based on a change in the first syndrome associated with the first codeword recorded in the error information register based on a plurality of read-modify-write operations.

14. The semiconductor memory device of claim 13, the control logic circuit is configured to repair the first memory location based on the determined error attribute during operation of the semiconductor memory device, and the control logic circuit is configured to repair the first memory location based on the determined error attribute during operation of the semiconductor memory device, and wherein, ​ wherein the control logic circuit is configured to repair the first memory location by copying the corrected data associated with the first codeword in a redundant area of the memory cell array or in a storage memory in the semiconductor memory device.

15. The semiconductor memory device of claim 14, wherein, when a first syndrome obtained based on the plurality of read-modify-write operations has a non-zero value, and an Mth value of the first syndrome obtained by Mth error correction code decoding is identical to an Nth value of the first syndrome obtained by Nth error correction code decoding, the control logic circuit is configured to determine the error attribute as a hard failure, and to repair the first memory location, wherein M is an integer greater than one, and N is an integer greater than M.

16. The semiconductor memory device of claim 14, wherein, when a first syndrome obtained based on the plurality of read-modify-write operations has a non-zero value, and an Mth value of the first syndrome obtained by Mth error correction code decoding is different from an Nth value of the first syndrome obtained by Nth error correction code decoding, the control logic circuit is configured to determine the error attribute as a progressive failure, and to repair the first memory location, wherein M is an integer greater than one, and N is an integer greater than M.

17. The semiconductor memory device of claim 14, wherein, the control logic circuit is configured to repair a first memory cell row including the first memory location or a column associated with the first memory location based on the determined error attribute.

18. The semiconductor memory device of claim 13, further comprising a storage memory for storing a first address designating the first memory location as a hard failure or a progressive failure and associated corrected data.

19. The semiconductor memory device of claim 18, wherein, the control logic circuit is configured to control the storage memory to input / output data via the storage memory in response to a second address matching the first address.

20. A semiconductor memory device, comprising: a memory cell array including a plurality of memory cell rows, each row including a plurality of volatile memory cells; an error correction code engine; an error information register; and a control logic circuit configured to control the error correction code engine to perform a read-modify-write operation by: reading data corresponding to a first codeword from a sub-page in a first memory cell row of the plurality of memory cell rows based on an access address and a command from an external device; performing error correction code decoding on the data in response to detecting an error in the first codeword to generate an error occurrence signal; correcting the detected error in the first codeword; and writing the corrected first codeword into a first memory location corresponding to the sub-page; and further comprising: a storage memory for storing a first address designating the first memory location as a hard failure or a progressive failure and its associated corrected data, wherein the control logic circuit is configured to: record in the error information register a first address associated with the first codeword based on the error occurrence signal and a first syndrome obtained by the error correction code decoding; and Based on a plurality of read-modify-write operations, determine an error property of the first codeword based on a change in a first syndrome associated with the first codeword recorded in the error information register.

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