Semiconductor device and method for manufacturing the same
By designing a sector-shaped edge with a 90-degree angle and a 90-degree angle on the side of the semiconductor chip, and using plasma etching to form a shell-like edge, the gap problem during the resin sealing process is solved, and the reliability of the semiconductor device is improved.
Patent Information
- Application Number
- CN202010787426.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-03-19
- Filing Date
- 2020-08-07
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2040-08-07
AI Technical Summary
The existing semiconductor devices tend to form voids during the resin sealing process, resulting in a decrease in reliability.
The first side surface of the semiconductor chip is designed to form a 90-degree angle with the substrate surface, the second side surface forms an angle smaller than the first side surface, and a shell-shaped fan edge is formed by plasma etching, and the resin is sealed at these edges to Ensure that the resin is in full contact and seals the electrode layer and chip.
The formation of voids is effectively suppressed, the reliability of the semiconductor device is improved, and the sealing effect is enhanced by optimizing the contact between the resin and the side surface.
Smart Images
Figure CN113496963B_ABST
Abstract
Description
[0001] Related Applications
[0002] This application claims the priority of Japanese Patent Application No. 2020-50007 (filing date: March 19, 2020) as a basic application, and the present application incorporates all the contents of the basic application by reference. Technical Field
[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art
[0004] Semiconductor devices having semiconductor chips such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are used for power conversion and the like. Such semiconductor chips are used by being sealed with resin. Preferably, the sealing state of the resin is good. Summary of the invention
[0005] Embodiments of the present invention provide a semiconductor device with high reliability and a method for manufacturing the same.
[0006] A semiconductor device in an embodiment comprises: a substrate; an electrode layer arranged on the substrate; a semiconductor chip, arranged on the electrode layer, having a first side portion forming a first angle relative to a substrate surface of the substrate and a second side portion arranged below the first side portion and forming a second angle smaller than the first angle relative to the substrate surface; and a resin, arranged around the electrode layer and the semiconductor chip, and connected to the first side portion and the second side portion. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment.
[0008] Figure 2 It is a schematic cross-sectional view of a main part of a semiconductor device according to an embodiment.
[0009] Figure 3 (a) to (c) are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the embodiment.
[0010] Figure 4 (a) to (c) are schematic cross-sectional views showing the manufacturing process of the main part of the semiconductor device according to the embodiment.
[0011] Figure 5 (a) to (c) are schematic cross-sectional views showing the manufacturing process of the main part of the semiconductor device according to the embodiment.
[0012] Figure 6(a) to (c) are schematic cross-sectional views showing the manufacturing process of a semiconductor device serving as a comparative embodiment. DETAILED DESCRIPTION
[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals are given to the same components and the like, and the description of the components and the like that have been described once will be appropriately omitted.
[0014] In this specification, in order to indicate the positional relationship of components, the upper direction of the drawings is described as "up", and the lower direction of the drawings is described as "down". In this specification, the concepts of "up" and "down" are not necessarily words that indicate the relationship with the direction of gravity.
[0015] (Implementation Method)
[0016] A semiconductor device in an embodiment comprises: a substrate; an electrode layer arranged on the substrate; a semiconductor chip, arranged on the electrode layer, having a first side portion forming a first angle relative to a substrate surface of the substrate and a second side portion arranged below the first side portion and forming a second angle smaller than the first angle relative to the substrate surface; and a resin, arranged around the electrode layer and the semiconductor chip, and connected to the first side portion and the second side portion.
[0017] Figure 1 1 is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 according to the embodiment is, for example, a MOSFET.
[0018] The semiconductor device 100 includes a substrate 2 , an electrode layer 6 , a semiconductor chip 10 , and a resin 20 .
[0019] The substrate 2 has a substrate surface 4. The substrate 2 includes, for example, a metal material or a semiconductor material. Here, the metal material is, for example, Cu (copper), Al (aluminum), Ni (nickel), Ag (silver), or Au (gold). In addition, the semiconductor material is, for example, Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), or GaN (gallium nitride). However, the substrate 2 may also be, for example, a resin substrate including a resin material.
[0020] The electrode layer 6 is provided on the substrate surface 4 of the substrate 2. The electrode layer 6 is bonded to the substrate surface 4, for example. The electrode layer 6 functions as a drain electrode of a MOSFET, for example. The electrode layer 6 includes a metal material. Here, the metal material is, for example, Cu (copper), Al (aluminum), Ni (nickel), Ag (silver) or Au (gold), but is not limited thereto. In addition, the electrode layer 6 may also be a part of the semiconductor chip 10.
[0021] The semiconductor chip 10 is disposed on the electrode layer 6. For example, the electrode layer 6 is the back electrode of the semiconductor chip 10. For example, the bottom surface of the semiconductor chip 10 is electrically connected to the electrode layer 6. The semiconductor chip 10 has a first side surface portion 12 and a second side surface portion 16 on the side surface. The first side surface portion 12 forms a first angle θ1 relative to the substrate surface 4. The first angle θ1 is, for example, 90 degrees. Figure 1 In the figure, the first angle θ1 is shown as 90 degrees, but the first angle θ1 is not limited to 90 degrees. The second side surface portion 16 is provided below the first side surface portion 12. The second side surface portion 16 forms a second angle θ2 with respect to the substrate surface 4 that is smaller than the first angle θ1. Figure 1 In the embodiment, the first angle θ1 and the second angle θ2 are both set to angles obtained by rotating counterclockwise from the substrate surface 4. Figure 2 The same is true in Chinese.
[0022] The resin 20 is provided around the electrode layer 6 and the semiconductor chip 10. The resin 20 is in contact with the substrate surface 4, the electrode layer 6, the upper surface of the semiconductor chip 10, the first side surface portion 12 and the second side surface portion 16, and seals the electrode layer 6 and the semiconductor chip 10. The resin 20 is, for example, a sealing resin such as epoxy resin. In addition, the resin 20 may also contain fillers such as silicon dioxide (SiO2). However, the type of the resin 20 is not limited thereto.
[0023] Figure 2 1 is a schematic cross-sectional view of a main part of a semiconductor device 100 according to an embodiment. Figure 2 In the figure, the resin 20 is omitted.
[0024] The first side surface portion 12 has a plurality of first scallops 14 formed at a first interval d1. Figure 2 14a, 14b, 14c, 14d, 14e, 14f, 14g, 14h, 14i and 14j are shown as the first fan-shaped edges 14. The second side surface portion 16 has a plurality of second fan-shaped edges 18 formed at a second pitch d2. Figure 2 The second fan-shaped edges 18a, 18b, 18c and 18d are shown as the plurality of second fan-shaped edges 18. The first spacing d1 and the second spacing d2 are preferably less than 10 μm. Moreover, the resin 20 is connected to the plurality of first fan-shaped edges 14 and the plurality of second fan-shaped edges 18. It is preferred that the second spacing d2 is greater than the first spacing d1, that is, d2>d1.
[0025] The plurality of first fan-shaped edges 14 and the plurality of second fan-shaped edges 18 are formed, for example, when the substrate 2 containing Si is cut by plasma etching. Here, such plasma etching is performed, for example, by repeatedly using isotropic etching of F (fluorine) radicals, forming a protective film containing CF4 (tetrafluorocarbon) radicals, and anisotropic etching using F ions, as described later. By such plasma etching, a fan-shaped edge having a shell-like shape is formed. Specifically, the plurality of first fan-shaped edges 14 are formed on the first side surface portion 12, and the plurality of second fan-shaped edges 18 are formed on the second side surface portion 16.
[0026] The first angle θ1 is an angle between a line segment formed by connecting a plurality of vertices 15 provided between the first sector sides 14 and the substrate surface 4. Figure 2 In FIG. 1 , vertices 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i are shown as vertices 15. In addition, the second angle θ2 is an angle between a line segment formed by connecting a plurality of vertices 19 provided between the second fan-shaped edges 18 and the substrate surface 4. Figure 2 In FIG. 1 , as the vertices 19 , vertices 19 a , 19 b , and 19 c are shown.
[0027] Figure 3 Schematic cross-sectional views showing the manufacturing process of the semiconductor device 100 according to the embodiment.
[0028] The manufacturing method of the semiconductor device of the embodiment uses a mask having a first opening portion 62 provided on a semiconductor substrate 70 having an electrode layer 6 thereunder and having a first width L1, performs a first etching of a first portion 72 of the semiconductor substrate provided below the first opening portion 62 to form a first gap 74 having a first side surface portion 12, and performs a second etching of a second portion 76 of the semiconductor substrate 70 below the first gap 74 to form a second gap 78 having an inverted cone shape having a second side surface portion 16. By forming the second gap 78, the semiconductor substrate 70 is disconnected to form a semiconductor chip 10, the electrode layer 6 and the semiconductor chip 10 are arranged on a substrate 2, and a resin 20 is formed around the semiconductor chip 10 on the substrate 2.
[0029] The semiconductor substrate 70 is a substrate on which the semiconductor chip 10 is formed. A mask 60, for example, as a photomask, is provided on the upper surface 70a of the semiconductor substrate. The mask 60 has a first opening 62 of a first width L1. An electrode layer 6 is provided below the lower surface 70b of the semiconductor substrate. The electrode layer 6 has a second opening 8 of a second width L2 longer than the first width L1. The second opening 8 is provided below the first opening 62. The first opening 62 and the second opening 8 are respectively score lines for cutting. The MOSFET included in the semiconductor chip 10 is formed, for example, on the upper surface 70a of the semiconductor substrate. The electrode layer 6 is fixed on a known dicing tape 90 ( Figure 3 (a)).
[0030] Here, the first portion 72 of the semiconductor substrate 70 provided below the first opening 62 is etched (an example of the first etching). Thus, a first gap 74 ( Figure 3 (b)). The first gap 74 is formed in a stripe shape, for example, parallel to the upper surface 70a or the lower surface 70b of the semiconductor substrate. The side surfaces of the first gap 74 of the semiconductor substrate 70 form the first side surface portion 12a and the second side surface portion 12b as the first side surface portion 12.
[0031] Next, etching of the second portion 76 of the semiconductor substrate 70 provided below the first gap 74 is performed (an example of the second etching). Thus, a second gap 78 having an inverted cone shape is formed. The second gap 78 connects the second opening 8 to the first gap 74. In addition, the second gap 78 is formed in a stripe shape, for example, parallel to the upper surface 70a or the lower surface 70b of the semiconductor substrate. Thus, the semiconductor substrate 70 is disconnected, and the semiconductor chip 10a and the semiconductor chip 10b are formed. The side surface of the second gap 78 becomes the second side surface portion 16a and the second side surface portion 16b ( Figure 3 (c)).
[0032] Next, the dicing tape 90 is peeled off from the electrode layer 6. Next, the electrode layer 6 and the semiconductor chip 10 are arranged on Figure 3 Next, an electrode layer 6 is formed on the substrate 2 and around the semiconductor chip. Figure 3 The resin 20 (not shown) is formed in this way. Thus, the semiconductor device 100 of the embodiment is obtained.
[0033] Figure 4 Schematic cross-sectional views showing the manufacturing process of the main part of the semiconductor device 100 according to the embodiment. Figure 4 It is a schematic cross-sectional view showing a manufacturing process of the first gap 74 .
[0034] A mask 60 having a first opening 62 with a first width L1 is provided on a semiconductor substrate 70. A gap 80a is formed below the first opening 62. A first fan-shaped edge 14a is formed on the side of the gap 80a. Here, a protective film 82a ( Figure 4 (a)).
[0035] Next, a portion of the protective film 82a formed on the bottom surface of the gap 80a is removed by anisotropic etching using, for example, F-type ions composed of SF6 (sulfur hexafluoride). Figure 4 (b)). In addition, use Figure 4 The anisotropic etching illustrated in (b) is an example of the third etching.
[0036] Next, under the bottom surface of the gap 80a, a gap 80b is formed by isotropic etching using, for example, F (fluorine) radicals composed of SF6. A first fan-shaped edge 14b is formed on the side surface of the gap 80b. Next, a protective film 82b ( Figure 4 (c)), in addition, use Figure 4 The isotropic etching illustrated in (c) is an example of the fourth etching.
[0037] By repeating the above steps, the first gap 74 is formed. That is, the first etching is a repetition of the third etching and the fourth etching.
[0038] Figure 5 Schematic cross-sectional views showing the manufacturing process of the main part of the semiconductor device 100 according to the embodiment. Figure 5 It is a schematic cross-sectional view showing a manufacturing process of the second gap 78 .
[0039] A second fan-shaped edge 18a is formed on the side of the gap 84a. Here, a protective film 86a ( Figure 5 (a)).
[0040] Next, for example, F-type ions composed of SF6 (sulfur hexafluoride) are used to anisotropically etch a portion of the protective film 86a formed on the bottom surface of the gap 84a. Figure 5 (b)). In addition, use Figure 5 The anisotropic etching illustrated in (b) is an example of the fifth etching.
[0041] Next, under the bottom surface of the gap 84a, a gap 84b is formed by isotropic etching using, for example, F (fluorine) radicals composed of SF6. A second fan-shaped edge 18b is formed on the side of the gap 84b. Here, for example, the isotropic etching time when forming the gap 84b is extended compared to the isotropic etching time when forming the gap 80b. Thus, if using Figure 2 As explained above, the second distance d2 becomes larger than the first distance d1 ( Figure 2 ). In addition, the shape of the second gap 78 becomes an inverted cone. Next, a protective film 86b ( Figure 5 (c)). In addition, use Figure 5 The isotropic etching illustrated in (c) is an example of the sixth etching.
[0042] By repeating the above steps, the second gap 78 is formed. That is, the second etching is a repetition of the fifth etching and the sixth etching. Moreover, the time of the sixth etching becomes longer each time it is repeated. Thus, the above-mentioned inverted cone shape is formed. In addition, the time of the sixth etching can also be extended in the form of adding a predetermined time each time it is repeated. In addition, the time of the sixth etching can also be extended each time it is repeated in other ways, and is not particularly limited.
[0043] Next, the effects of the embodiment will be described.
[0044] Figure 6 Schematic cross-sectional views showing the manufacturing process of a semiconductor device 800 serving as a comparative embodiment.
[0045] In cutting of the semiconductor substrate 70 having the electrode layer 6 thereunder, it is considered that after a portion of the electrode layer 6 is removed to form the second opening 8, a mask 60 having the first opening 62 is formed on the semiconductor substrate 70. Here, the first opening 62 and the second opening 8 are used as a scoring line, and thus the first opening 62 is formed to be arranged above the second opening 8.
[0046] When the mask 60 is formed and then cut, it is preferable to make the second width L2 of the second opening 8 longer than the first width L1 of the first opening 62. This is because it is difficult to observe the position of the second opening 8 from above the semiconductor substrate 70, so by lengthening the second width L2 in advance, the first opening 62 can be reliably formed above the second opening 8. In other words, this is because the alignment margin (positional deviation margin) of the electrode layer 6 relative to the second opening 8 is taken into consideration ( Figure 6 (a)).
[0047] However, if Figure 6As shown in (b), when the semiconductor substrate 70 is cut by forming a gap 92 perpendicular to the substrate surface, a portion where the electrode layer 6 is not formed is formed on the lower surface (bottom surface) of the semiconductor chip 10a and the semiconductor chip 10b. Therefore, when the resin 20 is used for sealing, the resin 20 cannot enter the periphery of the portion where the electrode layer 6 is not formed, and a gap V is formed. Therefore, there is a problem that cracks appear in the resin 20, and the reliability of the semiconductor device 100 is reduced.
[0048] Therefore, the semiconductor device 100 of the embodiment includes a semiconductor chip 10, which is provided on the electrode layer 6 and has: a first side surface portion 12, which forms a first angle θ1 with respect to the substrate surface 4 of the substrate 2; and a second side surface portion 16, which is provided below the first side surface portion 12 and forms a second angle θ2 smaller than the first angle θ1 with respect to the substrate surface 4. Since the second side surface portion 16 is provided, the resin 20 enters the second side surface portion 16 well, so that the formation of the gap V can be suppressed. Therefore, a semiconductor device with high reliability can be provided.
[0049] In addition, when plasma etching is performed as in the embodiment, a plurality of first fan-shaped edges 14 are formed on the first side portion 12, and a plurality of second fan-shaped edges 18 are formed on the second side portion 16. The first spacing d1 of the plurality of first fan-shaped edges 14 and the second spacing d2 of the plurality of second fan-shaped edges 18 are set to be as small as 10 μm or less, so when the resin 20 enters the first fan-shaped edges 14 and the second fan-shaped edges 18, the contact between the resin and the first side portion 12 or the second side portion 16 is improved, and higher reliability can be obtained. On the other hand, even if the resin 20 does not enter, the size of the gap formed is extremely small, so it will not affect the reliability. In addition, when the first spacing P1 of the plurality of first fan-shaped edges 14 and the second spacing P2 of the plurality of second fan-shaped edges 18 are larger than 10 μm, there is a possibility that gaps are formed and reliability is reduced.
[0050] In the manufacturing method of the embodiment, a mask having a first opening 62 with a first width L1 provided on a semiconductor substrate 70 having an electrode layer 6 thereunder is used, and a first etching is performed on a first portion 72 of the semiconductor substrate provided below the first opening 62, thereby forming a first gap 74 having a first side surface 12, and a second etching is performed on a second portion 76 of the semiconductor substrate 70 below the first gap 74, thereby forming a second gap 78 having an inverted tapered shape having a second side surface 16, and by forming the second gap 78, the semiconductor substrate 70 is cut off to form a semiconductor chip 10, the electrode layer 6 and the semiconductor chip 10 are arranged on a substrate 2, and a resin 20 is formed around the semiconductor chip 10 on the substrate 2. Then, by performing the first etching, a plurality of first fan-shaped edges 14 formed at a first pitch are formed on the first side surface 12 in a direction parallel to the first side surface 12, and by performing the second etching, a plurality of second fan-shaped edges 18 formed at a second pitch are formed on the second side surface 16 in a direction parallel to the second side surface 16. This can suppress the formation of the void V on the side surface of the semiconductor chip 10 and the lower surface (bottom surface) of the semiconductor chip 10 where the electrode layer 6 is not formed, thereby forming a semiconductor device with high reliability.
[0051] In addition, the first etching is a repetition of the third etching as anisotropic etching and the fourth etching as isotropic etching performed after the third etching. Furthermore, the second etching is a repetition of the fifth etching as anisotropic etching and the sixth etching as isotropic etching performed after the fifth etching. Furthermore, the time of the sixth etching is longer than the time of the fourth etching. Furthermore, the time of the sixth etching becomes longer each time it is repeated. Thus, a second gap having an inverted cone shape is formed, and the formation of the gap V can be suppressed. In addition, if the time of the sixth etching is made longer than the time of the fourth etching, the second spacing d2 is larger than the first spacing d1 (d2>d1).
[0052] Although several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of its equivalent.
Claims
1. A semiconductor device comprising: substrate; An electrode layer, disposed on the substrate; a semiconductor chip, arranged on the electrode layer, having a first side surface portion and a second side surface portion, the first side surface portion having a surface parallel to a first direction, the first direction being a direction intersecting with a substrate surface of the substrate at a first angle on a plane perpendicular to the substrate, the surface parallel to the first direction being perpendicular to the plane, the second side surface portion being arranged below the first side surface portion, having a surface parallel to a second direction, the second direction being a direction intersecting with the substrate surface at a second angle smaller than the first angle on the plane, the surface parallel to the second direction being perpendicular to the plane; as well as A resin is provided around the electrode layer and the semiconductor chip and is in contact with the first side surface and the second side surface. The first side surface has a plurality of first fan-shaped edges repeatedly formed at a first pitch in the first direction, The second side surface portion has a plurality of second fan-shaped sides that are repeatedly formed at a second pitch larger than the first pitch in the second direction.
2. The semiconductor device according to claim 1, The first pitch is less than 10 μm, and the second pitch is less than 10 μm.
3. A method for manufacturing a semiconductor device, comprising the following steps: A first etching is performed on a first portion of the semiconductor substrate disposed below the first opening using a mask to form a first gap having a first side surface portion having a plurality of first fan-shaped edges that are repeated at first intervals toward the bottom of the semiconductor substrate, the mask being disposed on the semiconductor substrate having an electrode layer thereunder and having the first opening of a first width, performing a second etching of a second portion of the semiconductor substrate below the first gap, thereby forming a second gap having an inverted tapered shape with a second side surface portion having a plurality of second fan-shaped edges that are repeated at a second interval greater than the first interval toward a lower side of the semiconductor substrate, By forming the second gap, the semiconductor substrate is disconnected to form a semiconductor chip. The electrode layer and the semiconductor chip are arranged on a substrate. forming a resin around the semiconductor chip on the substrate, The first etching is a repetition of a third etching which is anisotropic etching and a fourth etching which is isotropic etching performed after the third etching, The second etching is a repetition of the fifth etching which is anisotropic etching and the sixth etching which is isotropic etching performed after the fifth etching, The sixth etching time is longer than the fourth etching time, The time for the sixth etching is lengthened by adding a predetermined time each time the above repetition is performed.
4. The method for manufacturing a semiconductor device according to claim 3, The first pitch of the plurality of first fan-shaped edges is less than 10 μm, and the second pitch of the plurality of second fan-shaped edges is less than 10 μm.