Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, wherein the semiconductor structure comprises: a substrate, the substrate comprises a device region, the device region comprises a plurality of first regions, and a second region located between adjacent first regions, the first regions and the second regions being arranged along a first direction; a first interconnection structure located on the device region, the first interconnection structure comprises a plurality of first interconnection layers and a second interconnection layer extending along a second direction, in the second direction, the length of the first interconnection layer is greater than the length of the second interconnection layer, and the first direction and the second direction are perpendicular to each other; and a plurality of third interconnection layers located on the first interconnection structure, in the second direction, the length of the third interconnection layer is greater than the length of the second interconnection layer. Thus, the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the continuous progress of semiconductor integrated circuit manufacturing technology, while the performance is continuously improved, the process of device miniaturization and microminiaturization is also accompanied. More and more advanced processes require as many devices as possible to be realized in as small an area as possible.

[0003] In very large-scale integrated circuits, using metal interconnect layers is one of the methods to achieve electrical interconnection between devices.

[0004] However, the performance of the semiconductor structure is still poor. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, which reduce the parasitic capacitance of the electrical interconnection layer and improve the performance of the semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a device region, the device region includes a plurality of first regions, and a second region located between adjacent first regions, the first regions and the second region are arranged along a first direction; a first interconnect structure located on the device region, the first interconnect structure is electrically interconnected with the circuit of the device region, the first interconnect structure includes a plurality of first interconnect layers and second interconnect layers extending along a second direction, the first interconnect layers are located on the first regions, the second interconnect layers are located on the second region, in the second direction, the length of the first interconnect layer is greater than the length of the second interconnect layer, the first direction and the second direction are perpendicular to each other; a plurality of third interconnect layers located on the first interconnect structure, and the third interconnect layers are located on the second region, the third interconnect layers are electrically interconnected with the second interconnect layers, in the second direction, the length of the third interconnect layer is greater than the length of the second interconnect layer.

[0007] Optionally, it further includes: a dielectric layer surrounding the first interconnect structure and the third interconnect layers.

[0008] Optionally, in the second direction, the minimum value of the length of the second interconnect layer is 100 nanometers. Optionally, in the second direction, the length of the third interconnect layer is equal to the length of the first interconnect layer.

[0009] Optionally, in the direction perpendicular to the surface of the substrate, the minimum distance range between the top surface of the first interconnect structure and the bottom surface of the third interconnect layer is 400 nanometers to 500 nanometers.

[0010] Optionally, one of the first interconnect layers is located on one of the first regions, and one of the second interconnect layers is located on one of the second regions.

[0011] Optionally, in the first direction, the minimum value of the minimum pitch between adjacent first and second interconnect layers is 20 nanometers.

[0012] Optionally, more than two of the first interconnect layers are located on one of the first regions, and one of the second interconnect layers is located on one of the second regions.

[0013] Optionally, more than two of the first interconnect layers are located on one of the first regions, and more than two of the second interconnect layers are located on one of the second regions.

[0014] Optionally, further included is a fourth interconnect layer located between the second interconnect layer and the third interconnect layer. The fourth interconnect layer extends in the first direction and spans across all of the second interconnect layers, and the fourth interconnect layer is electrically interconnected with the second interconnect layer and the third interconnect layer respectively.

[0015] Optionally, further included are a number of first conductive plugs. Each first conductive plug is located between the fourth interconnect layer and one of the second interconnect layers, and the first conductive plug is electrically interconnected with the fourth interconnect layer and the second interconnect layer respectively.

[0016] Optionally, further included are a number of second conductive plugs. Each second conductive plug is located between the fourth interconnect layer and one of the third interconnect layers, and the second conductive plug is electrically interconnected with the fourth interconnect layer and the third interconnect layer respectively.

[0017] Optionally, the material of the first interconnect layer includes a metallic material.

[0018] Optionally, the material of the second interconnect layer includes a metallic material.

[0019] Optionally, the material of the third interconnect layer includes a metallic material.

[0020] Optionally, the material of the dielectric layer includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0021] Optionally, the substrate in the device region has a number of mutually discrete fin structures, and gate structures located on the surfaces of the fin structures. The fin structures extend in the first direction or the second direction.

[0022] Optionally, a fifth interconnect layer and a sixth interconnect layer are further provided in the substrate of the device region. The fifth interconnect layer is electrically interconnected with the circuits in the device region and the first interconnect layer respectively, and the sixth interconnect layer is electrically interconnected with the circuits in the device region and the second interconnect layer respectively.

[0023] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a device region, the device region includes a plurality of first regions, and a second region located between adjacent first regions, the first regions and the second region are arranged along a first direction; forming a first interconnect structure on the device region, the first interconnect structure is electrically interconnected with the circuits in the device region, the first interconnect structure includes a plurality of first interconnect layers and second interconnect layers extending along a second direction, the first interconnect layers are located on the first regions, the second interconnect layers are located on the second region, in the second direction, the length of the first interconnect layer is greater than the length of the second interconnect layer, the first direction and the second direction are perpendicular to each other; forming a plurality of third interconnect layers on the first interconnect structure, and the third interconnect layers are located on the second region, the third interconnect layers are electrically interconnected with the second interconnect layers, in the second direction, the length of the third interconnect layer is greater than the length of the second interconnect layer.

[0024] Optionally, it further includes: forming a dielectric layer surrounding the first interconnect structure and the third interconnect layers.

[0025] Optionally, it further includes: before forming the third interconnect layers, forming a fourth interconnect layer on the first interconnect structure, the fourth interconnect layer extends along the first direction and spans all the second interconnect layers, the fourth interconnect layer is electrically interconnected with the second interconnect layers and the third interconnect layers respectively.

[0026] Optionally, a plurality of mutually discrete fin structures and gate structures located on the surfaces of the fin structures are provided in the substrate of the device region, and the fin structures extend along the first direction or the second direction.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the semiconductor structure provided by the technical solution of the present invention, through the first interconnect structure and the third interconnect layer, the parasitic capacitance between the first interconnect layer and the second interconnect layer is reduced, the parasitic capacitance generated between the first interconnect layers located on adjacent first regions is reduced, and moreover, the parasitic capacitance between the third interconnect layer and the first interconnect layer is reduced. First, since the first interconnect layer is located on the first region, the second interconnect layer is located on the second region, and the length of the first interconnect layer is greater than the length of the second interconnect layer. Therefore, in the first direction, through the shorter second interconnect layer, the overlapping portion between the second interconnect layer and the first interconnect layer is less, thereby reducing the parasitic capacitance between the adjacent first interconnect layer and the second interconnect layer and reducing the RC delay. At the same time, since the first interconnect layer is located on the first region and there is a second region between adjacent first regions, the distance between the first interconnect layers on adjacent first regions is increased, thereby reducing the parasitic capacitance generated between the first interconnect layers located on adjacent first regions and reducing the RC delay. Not only that, since the third interconnect layer electrically interconnected with the second interconnect layer is located on the second region, the distance between the third interconnect layer and the first interconnect layer is increased, thereby reducing the parasitic capacitance between the third interconnect layer and the first interconnect layer and reducing the RC delay. In summary, through the first interconnect structure and the third interconnect layer, the parasitic capacitance of the electrical interconnect layers in the semiconductor structure is reduced and the RC delay is reduced, improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 and Figure 2 are schematic structural diagrams of a semiconductor structure;

[0030] Figures 3 to 10 are schematic cross-sectional structural diagrams of the steps of the method for forming the semiconductor structure according to the embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the performance of the existing semiconductor structure is still poor. The following will be analyzed and described in combination with specific embodiments.

[0032] It should be noted that the "surface" in this specification is used to describe the relative positional relationship in space and does not limit whether it is in direct contact.

[0033] Figure 1 and Figure 2 are schematic structural diagrams of a semiconductor structure.

[0034] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic top view structural diagram of a semiconductor structure, Figure 2 is Figure 1Schematic cross-sectional structure diagram along the B-B1 direction, the semiconductor structure includes: a substrate 10, the substrate 10 includes a device region A; a metal interconnect layer 20 located on the device region A, the metal interconnect layer 20 includes a number of mutually discrete first metal interconnect structures 21 and second metal interconnect structures 22, each of the second metal interconnect structures 22 is located between two adjacent first metal interconnect structures 21, the first metal interconnect structures 21 and the second metal interconnect structures 22 are arranged along a first direction X, and, the first metal interconnect structures 21 and the second metal interconnect structures 22 extend along a second direction Y; a dielectric layer 30 surrounding the metal interconnect layer 20.

[0035] However, in the above semiconductor structure, on the one hand, in order to increase the integration degree of the semiconductor structure, the spacing between the first metal interconnect structure 21 and the second metal interconnect structure 22 is relatively close. On the other hand, in order to meet the design requirements of the semiconductor structure, in the second direction Y, the length of the first metal interconnect structure 21 is the same as the length of the second metal interconnect structure 22. Therefore, a relatively large parasitic capacitance will be generated between the first metal interconnect structure 21 and the adjacent second metal interconnect structure 22 and the RC delay will be increased, thereby reducing the performance of the semiconductor structure.

[0036] To solve the above problems, the technical solution of the present invention provides a semiconductor structure. By forming a second interconnect structure with a shorter length, and forming a second interconnect layer electrically interconnected with the second interconnect structure, the parasitic capacitance between the first interconnect layers and the parasitic capacitance between the first interconnect layer and the second interconnect layer are reduced, the RC delay is reduced, and the performance of the semiconductor structure is improved.

[0037] To make the above objects, features and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0038] Figures 3 to 10 It is a schematic cross-sectional structure diagram of each step of the forming method of the semiconductor structure according to the embodiment of the present invention.

[0039] Please refer to Figure 3 and Figure 4 , Figure 3 is a top view structure diagram of the semiconductor structure according to the embodiment of the present invention, Figure 4 is Figure 3 a schematic cross-sectional structure diagram along the D-D1 direction, providing a substrate 100, the substrate 100 includes a device region C, the device region C includes a number of first regions 101, and a second region 102 located between adjacent first regions 101, the first regions 101 and the second regions 102 are arranged along a first direction X.

[0040] The material of the substrate 100 is a semiconductor material.

[0041] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0042] In this embodiment, a device layer (not shown) is provided in the substrate 100 of the device region C. The device layer may include a device structure, for example, a PMOS transistor or an NMOS transistor. The device layer may further include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

[0043] In this embodiment, a plurality of mutually discrete fin structures (not shown) and a gate structure (not shown) located on the surface of the fin structures are further provided in the substrate 100 of the device region C. The fin structures extend along the first direction X or the second direction Y, and the second direction Y is perpendicular to the first direction X.

[0044] In this embodiment, a first dielectric layer 110 is formed on the substrate 100 of the device region C.

[0045] The first dielectric layer 110 is used to provide a material for forming a dielectric layer subsequently.

[0046] In this embodiment, the process of forming the first dielectric layer 110 includes a thermal oxidation process, a deposition process, a spin coating process, or an epitaxial growth process.

[0047] In this embodiment, the material of the first dielectric layer 110 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0048] In this embodiment, a fifth interconnect layer (not shown) and a sixth interconnect layer (not shown) are further provided in the substrate 100 of the device region C. The fifth interconnect layer is electrically interconnected with the circuit of the device region C and a first interconnect layer to be formed subsequently, and the sixth interconnect layer is electrically interconnected with the circuit of the device region C and a second interconnect layer to be formed subsequently.

[0049] Please refer to Figure 5 and Figure 6 , Figure 5 is a schematic structural diagram based on Figure 3 and Figure 6 is a schematic structural diagram based on Figure 4Schematic structural diagram based on this, a first interconnect structure 120 is formed on the device region C, and the first interconnect structure 120 is electrically interconnected with the circuit in the device region C. The first interconnect structure 120 includes a plurality of first interconnect layers 121 and second interconnect layers 122 extending along the second direction Y. The first interconnect layer 121 is located on the first region 101, and the second interconnect layer 122 is located on the second region 102.

[0050] In this embodiment, 1 first interconnect layer 121 is located on 1 first region 101, and 1 second interconnect layer 122 is located on 1 second region 102.

[0051] In another embodiment, more than 2 first interconnect layers are located on 1 first region, and 1 second interconnect layer is located on 1 second region.

[0052] In yet another embodiment, more than 2 first interconnect layers are located on 1 first region, and more than 2 second interconnect layers are located on 1 second region.

[0053] In this embodiment, in the second direction Y, the length of the first interconnect layer 121 is greater than the length of the second interconnect layer 122.

[0054] Specifically, in this embodiment, in the second direction Y, the first interconnect layer 121 has a first length H1, the second interconnect layer 122 has a second length H2, and H1 is greater than H2.

[0055] In this embodiment, the minimum value of H2 is 100 nanometers.

[0056] In this embodiment, in the first direction X, the minimum value of the minimum spacing M1 between adjacent first interconnect layers 121 and second interconnect layers 122 is 20 nanometers.

[0057] In this embodiment, the method for forming the first interconnect structure 120 includes: forming a first patterned layer (not shown) on the surface of the first dielectric layer 110, the first patterned layer exposing the surface of the first dielectric layer 110 on the first region 101 and the second region 102; using the first patterned layer as a mask to etch the first dielectric layer 110 until the surface of the substrate 100 is exposed, so as to form a first opening (not shown) in the first dielectric layer 110 of the first region 101 and a second opening (not shown) in the first dielectric layer 110 of the second region 102; after forming the first opening and the second opening, removing the first patterned layer; after removing the first patterned layer, forming a first interconnect structure material layer (not shown) in the first opening, the second opening and on the surface of the first dielectric layer 110; back-etching the first interconnect structure material layer until the surface of the first dielectric layer 110 is exposed, so as to form a first interconnect layer 121 in the first opening and a second interconnect layer 122 in the second opening.

[0058] In this embodiment, the process of etching the first dielectric layer 110 includes a wet etching process or a dry etching process.

[0059] In this embodiment, the process of forming the first interconnect structure material layer includes an epitaxial growth process or a deposition process.

[0060] In this embodiment, the process of back-etching the first interconnect structure material layer includes a wet etching process or a dry etching process.

[0061] In this embodiment, the material of the first interconnect structure material layer includes a metal material, for example, a metal material such as copper, aluminum or titanium. Therefore, the materials of the first interconnect layer 121 and the second interconnect layer 122 are the same, the material of the first interconnect layer 121 includes a metal material, for example, a metal material such as copper, aluminum or titanium, and the material of the second interconnect layer 122 includes a metal material, for example, a metal material such as copper, aluminum or titanium.

[0062] In another embodiment, the first interconnect layer and the second interconnect layer are formed separately, and the materials of the first interconnect layer and the second interconnect layer are different.

[0063] Please refer to Figure 7 and Figure 8 , Figure 7 is a schematic structural diagram based on Figure 5 and Figure 8 is a schematic structural diagram based on Figure 6Schematic structural diagram based thereon. A fourth interconnect layer 141 is formed on the first interconnect structure 120. The fourth interconnect layer 141 extends along the first direction X and spans across all of the second interconnect layers 122. The fourth interconnect layer 141 is electrically interconnected with the second interconnect layers 122 and the subsequently formed third interconnect layer respectively.

[0064] It should be noted that, for the convenience of understanding, Figure 7 the positions of the first interconnect layer 121 and the second interconnect layer 122 are indicated by dashed lines in [].

[0065] In this embodiment, before forming the fourth interconnect layer 141, a second dielectric layer 131 is formed on the surface of the first dielectric layer 110 and the surface of the first interconnect structure 120.

[0066] The second dielectric layer 131 is used to provide materials for the subsequent formation of dielectric layers.

[0067] In this embodiment, the process for forming the second dielectric layer 131 includes a thermal oxidation process, a deposition process, a spin coating process, or an epitaxial growth process.

[0068] In this embodiment, the material of the second dielectric layer 131 is the same as that of the first dielectric layer 110.

[0069] In other embodiments, the material of the second dielectric layer is different from that of the first dielectric layer.

[0070] In this embodiment, the material of the second dielectric layer 131 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0071] In this embodiment, after forming the second dielectric layer 131 and before forming the fourth interconnect layer 141, a plurality of first conductive plugs 142 are formed in the second dielectric layer 131, and each of the second interconnect layers 122 has more than 1 of the first conductive plugs 142.

[0072] The first conductive plugs 142 are electrically interconnected with the second interconnect layers 122 and the fourth interconnect layer 141 respectively.

[0073] In this embodiment, the method for forming the first conductive plug 142 includes: forming a second patterned layer (not shown) on the surface of the second dielectric layer 131, where the second patterned layer exposes the surface of the second dielectric layer 131 on the second interconnect layer 122; using the second patterned layer as a mask to etch the second dielectric layer 131 until the surface of the second interconnect layer 122 is exposed to form a first conductive plug opening (not shown); after forming the first conductive plug opening, removing the second patterned layer; after removing the second patterned layer, forming a first conductive plug 142 in the first conductive plug opening, and the surface of the second dielectric layer 131 exposes the surface of the first conductive plug 142.

[0074] In this embodiment, the material of the first conductive plug 142 includes metal materials, such as metal materials like copper, aluminum, or titanium.

[0075] In this embodiment, the process for forming the first conductive plug 142 includes an epitaxial growth process or a deposition process.

[0076] In this embodiment, after forming the first conductive plug 142 and before forming the fourth interconnect layer 141, a third dielectric layer 132 is formed on the surface of the second dielectric layer 131 and the surface of the first conductive plug 142.

[0077] The third dielectric layer 132 is used to provide materials for subsequent formation of dielectric layers.

[0078] In this embodiment, the process for forming the third dielectric layer 132 includes a thermal oxidation process, a deposition process, a spin coating process, or an epitaxial growth process.

[0079] In this embodiment, the material of the third dielectric layer 132 is the same as the material of the first dielectric layer 110.

[0080] In other embodiments, the material of the third dielectric layer is different from the material of the first dielectric layer.

[0081] In this embodiment, the material of the third dielectric layer 132 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0082] In this embodiment, the method for forming the fourth interconnect layer 141 includes: forming a third patterned layer (not shown) on the surface of the third dielectric layer 132, where the third patterned layer exposes the surface of the second interconnect layer 122 and the third dielectric layer 132 on the first conductive plug 142; using the third patterned layer as a mask to etch the third dielectric layer 132 until the surface of the first conductive plug 142 is exposed to form a fourth opening (not shown); after forming the fourth opening, removing the third patterned layer; and after removing the third patterned layer, forming the fourth interconnect layer 141 in the fourth opening.

[0083] In this embodiment, the process of etching the third dielectric layer 132 includes a wet etching process or a dry etching process.

[0084] In this embodiment, the process of forming the fourth interconnect layer 141 includes an epitaxial growth process or a deposition process.

[0085] In this embodiment, the material of the fourth interconnect layer 141 includes a metal material, for example, metal materials such as copper, aluminum, or titanium.

[0086] Please refer to Figure 9 and Figure 10 , Figure 9 is a schematic structural diagram based on Figure 7 . Figure 10 is a schematic structural diagram based on Figure 8 . On the first interconnect structure 120, a plurality of third interconnect layers 151 are formed, and the third interconnect layers 151 are located on the second region 102. The third interconnect layers 151 are electrically interconnected with the second interconnect layer 122. In the second direction Y, the length H3 of the third interconnect layer 151 is greater than the length H2 of the second interconnect layer 122.

[0087] It should be noted that for the sake of easy understanding, Figure 9 the positions of the first interconnect layer 121 and the second interconnect layer 122 are shown by dashed lines.

[0088] Specifically, in the second direction Y, the third interconnect layer 151 has a third length H3, and the third length H3 is greater than the second length H2.

[0089] In this embodiment, the third length H3 is equal to the first length H1.

[0090] In other embodiments, the third length is between the first length and the second length.

[0091] In this embodiment, in the direction perpendicular to the substrate surface, the minimum distance D1 between the top surface of the first interconnect structure 120 and the bottom surface of the third interconnect layer 151 ranges from 400 nanometers to 500 nanometers.

[0092] In this embodiment, the projection of the second interconnect layer 122 on the substrate 100 is within the projection range of the third interconnect layer 151 on the substrate 100.

[0093] In this embodiment, after forming the fourth interconnect layer 141 and before forming the third interconnect layer 151, a fourth dielectric layer 161 is formed on the surface of the third dielectric layer 132 and the surface of the fourth interconnect layer 141.

[0094] The fourth interconnect layer 141 is used to provide materials for subsequent formation of dielectric layers.

[0095] In this embodiment, the process of forming the fourth dielectric layer 161 includes a thermal oxidation process, a deposition process, a spin coating process, or an epitaxial growth process.

[0096] In this embodiment, the material of the fourth dielectric layer 161 is the same as the material of the first dielectric layer 110.

[0097] In other embodiments, the material of the fourth dielectric layer is different from the material of the first dielectric layer.

[0098] In this embodiment, the material of the fourth dielectric layer 161 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0099] In this embodiment, after forming the fourth dielectric layer 161 and before forming the third interconnect layer 151, a plurality of second conductive plugs 152 are formed in the fourth dielectric layer 161 on the fourth interconnect layer 141.

[0100] The second conductive plugs 152 are electrically interconnected with the fourth interconnect layer 141 and the third interconnect layer 151 respectively.

[0101] In this embodiment, the method for forming the second conductive plug 152 includes: forming a fourth patterned layer (not shown) on the surface of the fourth dielectric layer 161, the fourth patterned layer exposing the surface of the fourth dielectric layer 161 on the fourth interconnect layer 141; using the fourth patterned layer as a mask to etch the fourth dielectric layer 161 until the surface of the fourth interconnect layer 141 is exposed to form a second conductive plug opening (not shown); after forming the second conductive plug opening, removing the fourth patterned layer; after removing the fourth patterned layer, forming a second conductive plug 152 in the second conductive plug opening, and the surface of the fourth interconnect layer 141 exposes the surface of the second conductive plug 152.

[0102] In this embodiment, the material of the second conductive plug 152 includes a metal material, for example, a metal material such as copper, aluminum, or titanium.

[0103] In this embodiment, the process for forming the second conductive plug 152 includes an epitaxial growth process or a deposition process.

[0104] In this embodiment, after forming the second conductive plug 152 and before forming the third interconnect layer 151, a fifth dielectric layer 162 is formed on the surface of the fourth dielectric layer 161 and the surface of the second conductive plug 152.

[0105] The first dielectric layer 110, the second dielectric layer 131, the third dielectric layer 132, the fourth dielectric layer 161, and the fifth dielectric layer 162 constitute: a dielectric layer surrounding the first interconnect structure 120 and the third interconnect layer 151.

[0106] In this embodiment, the process for forming the fifth dielectric layer 162 includes a thermal oxidation process, a deposition process, a spin coating process, or an epitaxial growth process.

[0107] In this embodiment, the material of the fifth dielectric layer 162 is the same as the material of the first dielectric layer 110.

[0108] In other embodiments, the material of the fifth dielectric layer is different from the material of the first dielectric layer.

[0109] In this embodiment, the material of the fifth dielectric layer 162 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0110] In this embodiment, the method for forming the third interconnect layer 151 includes: forming a fifth patterned layer (not shown) on the surface of the fifth dielectric layer 162, where the fifth patterned layer exposes the surface of the second interconnect layer 122 and the fifth dielectric layer 162 on the second conductive plug 152; using the fifth patterned layer as a mask to etch the fifth dielectric layer 162 until the surface of the second conductive plug 152 and the fourth dielectric layer 161 are exposed, so as to form a plurality of third openings (not shown); after forming the third openings, removing the fifth patterned layer; after removing the fifth patterned layer, forming the third interconnect layer 151 in the third openings.

[0111] In this embodiment, the process for etching the fifth dielectric layer 162 includes a wet etching process or a dry etching process.

[0112] In this embodiment, the process for forming the third interconnect layer 151 includes an epitaxial growth process or a deposition process.

[0113] In this embodiment, the material of the third interconnect layer 151 includes metal materials, for example, metal materials such as copper, aluminum, or titanium.

[0114] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 9 and Figure 10 , which includes: a substrate 100, the substrate 100 includes a device region C, the device region C includes a plurality of first regions 101, and a second region 102 located between adjacent first regions 101, the first regions 101 and the second region 102 are arranged along a first direction X; a first interconnect structure 120 located on the device region C, the first interconnect structure 120 is electrically interconnected with the circuit of the device region C, the first interconnect structure 120 includes a plurality of first interconnect layers 121 and a second interconnect layer 122 extending along a second direction Y, the first interconnect layer 121 is located on the first region 101, the second interconnect layer 122 is located on the second region 102, in the second direction Y, the length H1 of the first interconnect layer 121 is greater than the length H2 of the second interconnect layer 122, and the first direction X and the second direction Y are perpendicular to each other; a plurality of third interconnect layers 151 located on the first interconnect structure 120, and the third interconnect layer 151 is located on the second region 102, the third interconnect layer 151 is electrically interconnected with the second interconnect layer 122, and in the second direction Y, the length H3 of the third interconnect layer 151 is greater than the length H2 of the second interconnect layer 122.

[0115] Through the first interconnect structure 120 and the third interconnect layer 151, the parasitic capacitance between the first interconnect layer 121 and the second interconnect layer 122 is reduced, the parasitic capacitance generated between the first interconnect layers 121 located on adjacent first regions 101 is reduced, and the parasitic capacitance between the third interconnect layer 151 and the first interconnect layer 121 is reduced.

[0116] First, since the first interconnect layer 121 is located on the first region 101, the second interconnect layer 122 is located on the second region 102, and the length of the first interconnect layer 121 is greater than the length of the second interconnect layer 122, therefore, along the first direction X, through the shorter second interconnect layer 122, the overlapping portion between the second interconnect layer 122 and the first interconnect layer 121 is less, thereby reducing the parasitic capacitance between the adjacent first interconnect layer 121 and the second interconnect layer 122 and reducing the RC delay.

[0117] Second, since the first interconnect layer 121 is located on the first region 101 and there is a second region 102 between adjacent first regions 101, the spacing between the first interconnect layers 121 on adjacent first regions 101 is increased, thereby reducing the parasitic capacitance generated between the first interconnect layers 121 located on adjacent first regions 101 and reducing the RC delay.

[0118] Third, since the third interconnect layer 151 electrically interconnected with the second interconnect layer 122 is located on the second region 102, the spacing between the third interconnect layer 151 and the first interconnect layer 121 is increased, thereby reducing the parasitic capacitance between the third interconnect layer 151 and the first interconnect layer 121 and reducing the RC delay.

[0119] In summary, through the first interconnect structure 120 and the third interconnect layer 151, the parasitic capacitance of the electrical interconnect layers in the semiconductor structure is reduced and the RC delay is reduced, improving the performance of the semiconductor structure.

[0120] The material of the substrate 100 is a semiconductor material.

[0121] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0122] In this embodiment, a device layer (not shown) is provided within the substrate 100 of the device region C. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may further include an interconnect structure electrically connected to the device structures, and an insulating layer surrounding the device structures and the interconnect structure.

[0123] In this embodiment, a number of mutually discrete fin structures (not shown) are further provided within the substrate 100 of the device region C, and a gate structure (not shown) is located on the surface of the fin structures. The fin structures extend along the first direction X or the second direction Y, and the second direction Y is perpendicular to the first direction X.

[0124] In this embodiment, a fifth interconnect layer (not shown) and a sixth interconnect layer (not shown) are further provided within the substrate 100 of the device region C. The fifth interconnect layer is electrically interconnected to the circuit of the device region C and the first interconnect layer formed subsequently, and the sixth interconnect layer is electrically interconnected to the circuit of the device region C and the second interconnect layer formed subsequently.

[0125] Specifically, in the second direction Y, the first interconnect layer 121 has a first length H1, the second interconnect layer 122 has a second length H2, and the third interconnect layer 151 has a third length H3. Moreover, the first length H1 is greater than the second length H2, and the third length H3 is greater than the second length H2.

[0126] In this embodiment, the minimum value of H2 is 100 nanometers.

[0127] In this embodiment, the third length H3 is equal to the first length H1.

[0128] In other embodiments, the third length is between the first length and the second length.

[0129] In this embodiment, in the first direction X, the minimum value of the minimum spacing M1 between adjacent first interconnect layer 121 and second interconnect layer 122 is 20 nanometers.

[0130] In this embodiment, in the direction perpendicular to the substrate surface, the minimum distance D1 between the top surface of the first interconnect structure 120 and the bottom surface of the third interconnect layer 151 ranges from 400 nanometers to 500 nanometers.

[0131] If the minimum distance D1 is too small, the minimum spacing between the first interconnect layer 121 and the third interconnect layer 151 is too small, and the effect on reducing the parasitic capacitance between the first interconnect layer 121 and the third interconnect layer 151 is limited. If the minimum distance D1 is too large, the aspect ratio of the conductive plug located between the second interconnect layer 122 and the third interconnect layer 151 is large, reducing the process window sizes of processes such as etching, deposition, and epitaxy for forming the conductive plug, and it is difficult to form a conductive plug with a good morphology. Therefore, selecting the range of the minimum distance D1 can, while being beneficial to reducing parasitic capacitance, form a conductive plug with a good morphology between the second interconnect layer 122 and the third interconnect layer 151.

[0132] In this embodiment, the projection of the second interconnect layer 122 on the substrate 100 is within the projection range of the third interconnect layer 151 on the substrate 100.

[0133] In this embodiment, the semiconductor structure further includes: a first dielectric layer 110 located on the substrate 100 in the device region C.

[0134] In this embodiment, the material of the first dielectric layer 110 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0135] Specifically, in this embodiment, the first interconnect layer 121 is located within the first dielectric layer 110 on the first region 101, and the second interconnect layer 122 is located within the first dielectric layer 110 on the second region 102.

[0136] In this embodiment, one first interconnect layer 121 is located on one first region 101, and one second interconnect layer 122 is located on one second region 102.

[0137] In another embodiment, two or more first interconnect layers are located on one first region, and one second interconnect layer is located on one second region.

[0138] In yet another embodiment, two or more first interconnect layers are located on one first region, and two or more second interconnect layers are located on one second region.

[0139] In this embodiment, the material of the first interconnect layer 121 includes a metal material, for example, a metal material such as copper, aluminum, or titanium.

[0140] In this embodiment, the material of the second interconnect layer 122 includes a metal material, for example, a metal material such as copper, aluminum, or titanium.

[0141] In this embodiment, the material of the third interconnect layer 151 includes a metal material, for example, a metal material such as copper, aluminum, or titanium.

[0142] In this embodiment, the semiconductor structure further includes: a second dielectric layer 131 on the surfaces of the first dielectric layer 110 and the first interconnect structure 120; a plurality of first conductive plugs 142 in the second dielectric layer 131; a third dielectric layer 132 on the surfaces of the second dielectric layer 131 and the first conductive plugs 142; and a fourth interconnect layer 141 in the third dielectric layer 132. The fourth interconnect layer 141 is located between the second interconnect layer 122 and the third interconnect layer 151, extends along the first direction X, and spans across all of the second interconnect layer 122. The fourth interconnect layer 141 is electrically interconnected with the second interconnect layer 122 and the third interconnect layer 151 respectively.

[0143] Since the fourth interconnect layer 141 is located between the second interconnect layer 122 and the third interconnect layer 151, the aspect ratio of the conductive plugs used for electrical interconnection between the second interconnect layer 122 and the third interconnect layer 151 can be reduced. Thus, the process window of processes such as deposition, etching, or epitaxy for forming the conductive plugs (the first conductive plugs 142 and the second conductive plugs 152) is increased, and conductive plugs with better morphology and quality are formed.

[0144] Specifically, each of the first conductive plugs 142 is located between the fourth interconnect layer 141 and one of the second interconnect layers 122, and the first conductive plug 142 is electrically interconnected with the fourth interconnect layer 141 and the second interconnect layer 122 respectively. Thus, the electrical interconnection between the fourth interconnect layer 141 and the second interconnect layer 122 is achieved.

[0145] In this embodiment, the material of the fourth interconnect layer 141 includes metal materials, such as metal materials like copper, aluminum, or titanium.

[0146] In this embodiment, the material of the first conductive plugs 142 includes metal materials, such as metal materials like copper, aluminum, or titanium.

[0147] In this embodiment, the material of the second dielectric layer 131 is the same as that of the first dielectric layer 110, and the material of the third dielectric layer 132 is the same as that of the first dielectric layer 110.

[0148] In other embodiments, the material of the second dielectric layer is different from that of the first dielectric layer, and the material of the third dielectric layer is different from that of the first dielectric layer.

[0149] In this embodiment, the material of the second dielectric layer 131 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride.

[0150] In this embodiment, the material of the third dielectric layer 132 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or silicon carbon oxynitride.

[0151] In this embodiment, the semiconductor structure further includes: a fourth dielectric layer 161 on the surfaces of the third dielectric layer 132 and the fourth interconnect layer 141; a plurality of second conductive plugs 152 within the fourth dielectric layer 161 on the fourth interconnect layer 141; and a fifth dielectric layer 162 on the surfaces of the fourth dielectric layer 161 and the second conductive plugs 152, and the third interconnect layer 151 is within the fifth dielectric layer 162.

[0152] The first dielectric layer 110, the second dielectric layer 131, the third dielectric layer 132, the fourth dielectric layer 161, and the fifth dielectric layer 162 constitute a dielectric layer surrounding the first interconnect structure 120 and the third interconnect layer 151.

[0153] Specifically, each of the second conductive plugs 152 is located between the fourth interconnect layer 141 and one of the third interconnect layers 151, and the second conductive plug 152 is electrically interconnected with the fourth interconnect layer 141 and the third interconnect layer 151, respectively. Thus, electrical interconnection between the fourth interconnect layer 141 and the third interconnect layer 151 is achieved.

[0154] In this embodiment, the material of the second conductive plug 152 includes a metal material, such as a metal material like copper, aluminum, or titanium.

[0155] In this embodiment, the material of the fourth dielectric layer 161 is the same as the material of the first dielectric layer 110, and the material of the fifth dielectric layer 162 is the same as the material of the first dielectric layer 110.

[0156] In other embodiments, the material of the fourth dielectric layer is different from the material of the first dielectric layer, and the material of the fifth dielectric layer is different from the material of the first dielectric layer.

[0157] In this embodiment, the material of the fourth dielectric layer 161 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or silicon carbon oxynitride.

[0158] In this embodiment, the material of the fifth dielectric layer 162 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or silicon carbon oxynitride.

[0159] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a device region, the device region comprising a plurality of first regions and second regions located between adjacent first regions, the first regions and the second regions being arranged along a first direction; a first interconnect structure located on the device region, the first interconnect structure being electrically interconnected with the circuit of the device region, the first interconnect structure comprising a plurality of first interconnect layers and second interconnect layers extending along a second direction, the first interconnect layer and the second interconnect layer being located on the same layer, the first interconnect layer being located on the first region, the second interconnect layer being located on the second region, the length of the first interconnect layer being greater than the length of the second interconnect layer in the second direction, and the first direction and the second direction being perpendicular to each other; A plurality of third interconnect layers are located on the first interconnect structure, and the third interconnect layers are located on the second region, the third interconnect layers are electrically interconnected with the second interconnect layers, and in the second direction, the length of the third interconnect layers is greater than the length of the second interconnect layers.

2. The semiconductor structure according to claim 1, wherein: Also includes: A dielectric layer surrounds the first interconnect structure and the third interconnect layer.

3. The semiconductor structure according to claim 1, wherein: In the second direction, a minimum length of the second interconnect layer is 100 nanometers.

4. The semiconductor structure according to claim 1, wherein: In the second direction, a length of the third interconnect layer is equal to a length of the first interconnect layer.

5. The semiconductor structure according to claim 1, wherein: In a direction perpendicular to the substrate surface, a minimum distance between a top surface of the first interconnect structure and a bottom surface of the third interconnect layer ranges from 400 nanometers to 500 nanometers.

6. The semiconductor structure according to claim 1, wherein: One first interconnect layer is located on one first region, and one second interconnect layer is located on one second region.

7. The semiconductor structure according to claim 6, wherein: In the first direction, a minimum value of a minimum distance between adjacent first interconnection layers and second interconnection layers is 20 nanometers.

8. The semiconductor structure according to claim 1, wherein: Two or more of the first interconnection layers are located on one of the first regions, and one of the second interconnection layers is located on one of the second regions.

9. The semiconductor structure according to claim 1, wherein: Two or more of the first interconnection layers are located on one of the first regions, and two or more of the second interconnection layers are located on one of the second regions.

10. The semiconductor structure according to claim 1, wherein: Also includes: A fourth interconnection layer is located between the second interconnection layer and the third interconnection layer, the fourth interconnection layer extends along the first direction and spans across the entire second interconnection layer, and the fourth interconnection layer is electrically interconnected with the second interconnection layer and the third interconnection layer respectively.

11. The semiconductor structure according to claim 10, characterized in that Also includes: A plurality of first conductive plugs are provided, each of the first conductive plugs is located between the fourth interconnection layer and one of the second interconnection layers, and the first conductive plugs are electrically interconnected with the fourth interconnection layer and the second interconnection layer respectively.

12. The semiconductor structure according to claim 10, wherein: Also includes: A plurality of second conductive plugs, each of which is located between the fourth interconnection layer and one of the third interconnection layers, and the second conductive plug is electrically interconnected with the fourth interconnection layer and the third interconnection layer respectively.

13. The semiconductor structure according to claim 1, wherein: The material of the first interconnection layer includes a metal material.

14. The semiconductor structure according to claim 1, wherein: The material of the second interconnection layer includes a metal material.

15. The semiconductor structure according to claim 1, wherein: The material of the third interconnection layer includes a metal material.

16. The semiconductor structure according to claim 2, wherein: The material of the dielectric layer includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

17. The semiconductor structure according to claim 1, wherein: A plurality of mutually separate fin structures and a gate structure located on the surface of the fin structure are provided in the substrate of the device region, and the fin structure extends along the first direction or the second direction.

18. The semiconductor structure according to claim 1, wherein: The substrate in the device area also has a fifth interconnection layer and a sixth interconnection layer. The fifth interconnection layer is electrically interconnected with the circuit in the device area and the first interconnection layer respectively, and the sixth interconnection layer is electrically interconnected with the circuit in the device area and the second interconnection layer respectively.

19. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a device region, the device region comprising a plurality of first regions and second regions located between adjacent first regions, the first regions and the second regions being arranged along a first direction; forming a first interconnect structure on the device region, the first interconnect structure being electrically interconnected with the circuit of the device region, the first interconnect structure comprising a plurality of first interconnect layers and second interconnect layers extending along a second direction, the first interconnect layer and the second interconnect layer being located at the same layer, the first interconnect layer being located on the first region, the second interconnect layer being located on the second region, the length of the first interconnect layer being greater than the length of the second interconnect layer in the second direction, and the first direction and the second direction being perpendicular to each other; A plurality of third interconnect layers are formed on the first interconnect structure. The third interconnect layers are located on the second region, are electrically interconnected with the second interconnect layers, and are longer than the second interconnect layers in the second direction.

20. The method for forming a semiconductor structure according to claim 19, wherein: Also includes: A dielectric layer is formed surrounding the first interconnect structure and the third interconnect layer.

21. The method for forming a semiconductor structure according to claim 19, wherein: Also includes: Before forming the third interconnection layer, a fourth interconnection layer is formed on the first interconnection structure. The fourth interconnection layer extends along the first direction and spans across the entire second interconnection layer. The fourth interconnection layer is electrically interconnected with the second interconnection layer and the third interconnection layer respectively.

22. The method for forming a semiconductor structure according to claim 19, wherein: A plurality of mutually separate fin structures and a gate structure located on the surface of the fin structure are provided in the substrate of the device region, and the fin structure extends along the first direction or the second direction.

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