Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution containing ions of a second metal material. Furthermore, the method includes forming a plurality of metal particles containing the second metal material on a portion of the first surface of the first metal layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Copper-to-copper bonding is a step in semiconductor device manufacturing. Copper-to-copper bonding is typically performed through an annealing process. However, conventional annealing processes are performed at temperatures exceeding 250°C, which can damage semiconductor devices, wafers, or other electronic components. Therefore, new methods are needed to improve the yield of semiconductor device manufacturing. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including ions of a second metal material. Additionally, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.

[0004] According to some embodiments of the present disclosure, a semiconductor device includes a substrate and a conductive element. The conductive element is disposed on the substrate. The conductive element includes a first metal layer, a second metal layer, and an alloy layer. The first metal layer includes a first metal material. The second metal layer includes a second metal material. The alloy layer includes the first metal material and the second metal material and is disposed between the first metal layer and the second metal layer. The first metal layer and the second metal layer are arranged alternately along a certain direction.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a substrate and a conductive element. The conductive element is disposed on the substrate. The conductive element has a side surface. The conductive element includes a first metal layer, a plurality of metal particles, and a plurality of alloy shells. The first metal layer includes a first metal material. The plurality of metal particles include a second metal material. At least one metal particle among the plurality of metal particles is embedded in the first metal layer. At least one metal particle among the plurality of metal particles has a portion protruding from the side surface of the first metal layer. The plurality of alloy shells include the first metal material and the second metal material. Each of the plurality of alloy shells covers a corresponding metal particle. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When with Figure 1When reading the following detailed description, various aspects of the present disclosure can be easily understood based on the following detailed description. It should be noted that various features may not necessarily be drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0007] Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2A yes Figure 1 A partially enlarged view of the semiconductor device shown in FIG.

[0009] Figure 2B 、 Figure 2C and Figure 2D is a cross-sectional view of a conductive element according to some embodiments of the present disclosure.

[0010] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D and Figure 8E Various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure are presented.

[0012] Figure 9A and Figure 9B Improved metal liners according to some embodiments of the present disclosure are presented.

[0013] Throughout the drawings and detailed description, the same reference numerals are used to refer to the same or similar components. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be restrictive. In the present disclosure, references to forming or arranging a first feature on or on a second feature in the following description may include embodiments in which the first and second features are formed or arranged as direct contacts, and may also include embodiments in which additional features may be formed or arranged between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] The following describes embodiments of the present disclosure in detail. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0016] Figure 1 1 is a cross-sectional view of a semiconductor device 1 a according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 1 a includes a substrate 10 , a substrate 20 , and a conductive element 30 .

[0017] The substrate 10 may include a printed circuit board (PCB), a wafer, a redistribution layer (RDL), a package substrate, an interposer, or other substrate. The PCB may include a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. In some embodiments, the substrate 10 may also include a lead frame. In some embodiments, the substrate 10 may include a wafer die, such as a silicon wafer die, a fan-out wafer die, a glass wafer die, or a combination thereof.

[0018] Substrate 20 faces substrate 10. Substrate 20 may include a printed circuit board (PCB), a wafer, a redistribution layer (RDL), a package substrate, an interposer, or other substrate. The PCB may include a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. In some embodiments, substrate 20 may also include a lead frame. In some embodiments, substrate 20 may include a wafer die, such as a silicon wafer die, a fan-out wafer die, a glass wafer die, or a combination thereof.

[0019] A conductive element 30 is disposed on substrate 10. Conductive element 30 is disposed between substrates 10 and 20. Conductive element 30 is configured to function as, for example, an electrode, a conductive pad, a dummy pad, a conductive column, a dummy column, or a combination thereof, and the present disclosure is not limited thereto. In some embodiments, conductive element 30 includes a metal layer 31, a metal layer 32, and an interface layer 33.

[0020] Metal layer 31 is disposed on substrate 10. Metal layer 31 includes at least a first metal material. The first metal material may include copper (Cu), aluminum (Al), iron (Fe), zinc (Zn), nickel (Ni), tin (Sn), lead (Pb), silver (Ag), mercury (Hg), gold (Au), or a combination thereof. In some exemplary embodiments, copper is selected as an example of the first metal material.

[0021] Metal layer 32 is disposed on substrate 20. In some embodiments, metal layer 32 comprises at least a first metal material. In some embodiments, the material of metal layer 32 is the same as the material of metal layer 31.

[0022] In some embodiments, the interface layer 33 is disposed on the metal layer 31. In some embodiments, the interface layer 33 is disposed between the metal layers 31 and 32. Figure 2A and Figure 2B Details of the interface layer 33 are disclosed.

[0023] In some embodiments, semiconductor device 1a further includes a passivation layer 60. Passivation layer 60 is disposed between substrate 10 and substrate 20. Passivation layer 60 may surround conductive element 30. Passivation layer 60 may be configured to protect conductive element 30 from damage or contamination. Passivation layer 60 may include an inorganic dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride, an organic dielectric material such as polyimide (PI), polybenzoxazole (PBO), or benzocyclobutene (BCB), or other suitable materials.

[0024] Figure 2A According to some embodiments of the present disclosure Figure 1FIG2 is an enlarged view of region R in semiconductor device 1 a shown in FIG3 . In some embodiments, interface layer 33 includes an alloy layer 331 and a metal layer 332. Metal layer 332 includes at least a second metal material different from the first metal material. In some embodiments, the reduction potential of the second metal material is greater than or exceeds the reduction potential of the first metal material. In some embodiments, the reduction potential of ions of the second metal material is greater than or exceeds the reduction potential of the first metal material. In some embodiments, the second metal material includes copper, aluminum, iron, nickel, tin, lead, silver, mercury, gold, platinum, or a combination thereof. In some exemplary embodiments, copper is used as an example of the first metal material and silver is used as an example of the second metal material.

[0025] The alloy layer 331 is disposed between the metal layer 31 and the metal layer 332. The alloy layer 331 is an alloy of a first metal material and a second metal material, such as a copper-silver alloy.

[0026] In some embodiments, the combined thickness T1 of the alloy layer 331 and the metal layer 332 is in a range of about 30 nm to about 50 nm. In some embodiments, the thickness T1 is in a range of about 50 nm to about 100 nm. In some embodiments, the thickness T1 is in a range of about 100 nm to about 200 nm. In some embodiments, the thickness T1 is in a range of about 200 nm to about 400 nm.

[0027] Figure 2B According to other embodiments of the present disclosure Figure 1 FIG. 1 is an enlarged view of a region R in a semiconductor device 1 a shown in FIG.

[0028] like Figure 2B As shown, the interface layer 33 may include a plurality of metal particles 332' and an alloy shell 331'. Each metal particle in the metal particles 332' is separated from each other. Each alloy shell in the alloy shell 331' covers or seals the corresponding metal particle 332'. In some embodiments, the metal particles 332' may be arranged in a direction from one side of the conductive element 30 to the other side of the conductive element 30. In some embodiments, the metal particles 332' and the first metal layer 31 may be arranged alternately in a direction from one side of the conductive element 30 to the other side of the conductive element 30. In some embodiments, each metal particle in the metal particles 332' is embedded in the metal layer 31 or in the metal layer 32. In some embodiments, each alloy shell in the alloy shell 331' is embedded in the metal layer 31 or in the metal layer 32.

[0029] The outline of the metal particles 332' can be circular, oval, or irregular. In some embodiments, the alloy shell 331' covers or seals the metal particles 332'. The metal particles 332' are separated from the metal layer 31 by the alloy shell 331'. In some embodiments, the alloy shell 331' can conformally cover the metal particles 332'.

[0030] In some embodiments, the combined diameter T2 of the metal particles 332' and the corresponding alloy shell 331' is in a range of about 10 nm to about 50 nm. In some embodiments, the diameter T2 is in a range of about 50 nm to about 100 nm. In some embodiments, the diameter T2 is in a range of about 100 nm to about 500 nm.

[0031] In some embodiments, the diameter of the metal particles 332' is in a range of about 10 nm to about 50 nm. In some embodiments, the diameter of the metal particles 332' is in a range of about 50 nm to about 100 nm.

[0032] In some embodiments, the amount of the first metal material (e.g., copper) in the alloy layer 331 or in the alloy shell 331' is in a range of about 20 wt% to about 40 wt%. In some embodiments, the amount of copper in the alloy layer 331 or in the alloy shell 331' is in a range of about 40 wt% to about 70 wt%. In some embodiments, the amount of copper in the alloy layer 331 or in the alloy shell 331' is in a range of about 70 wt% to about 90 wt%.

[0033] In some embodiments, the amount of the second metal material (e.g., silver) in the alloy layer 331 or in the alloy shell 331' is in a range of about 5 wt% to about 20 wt%. In some embodiments, the amount of silver in the alloy layer 331 or in the alloy shell 331' is in a range of about 20 wt% to about 50 wt%. In some embodiments, the amount of silver in the alloy layer 331 or in the alloy shell 331' is in a range of about 50 wt% to about 80 wt%.

[0034] In some embodiments, there is no boundary between metal layer 31 and metal layer 32 , and metal layer 31 and metal layer 32 may be considered as a single metal layer including the first metal material.

[0035] The alloy layer 331 or the alloy shell 331 ′ may further include additional elements, such as carbon (C), oxygen (O), or other elements. In some embodiments, the amount of the additional elements is in a range of about 0 wt % to about 10 wt %.

[0036] refer to Figure 2CThe metal layer 332 may be thinner at the central portion of the conductive element 30 and thicker at both sides. The alloy layer 331 may be conformally formed on the metal layer 332 .

[0037] refer to Figure 2D The metal layer 332 may have substantially the same thickness from one side of the conductive element 30 to the other side of the conductive element 30 and may have a concave surface or a convex surface. In some embodiments, the alloy layer 331 may have a concave surface or a convex surface corresponding to the metal layer 332.

[0038] Figure 3 FIG2 is a cross-sectional view of a semiconductor device 1b according to some embodiments of the present disclosure. The semiconductor device 1b may include a liner 71. The liner 71 may be disposed on the substrate 10. The liner 71 may comprise a conductive material such as a metal or alloy. The semiconductor device 1b may include a passivation layer 81. The passivation layer 81 may be disposed on the substrate 10, covering a portion of the liner 71. The passivation layer 81 may comprise a nitride, oxide, oxynitride, or other suitable material.

[0039] Semiconductor device 1b may include a liner 72. The liner 72 may be disposed on substrate 20. The liner 72 may include a conductive material such as a metal or alloy. Semiconductor device 1b may include a passivation layer 82. The passivation layer 82 may be disposed on substrate 20 and cover a portion of the liner 72. The passivation layer 82 may include a nitride, an oxide, an oxynitride, or other suitable material.

[0040] Conductive element 30 is electrically connected to pad 71. Conductive element 30 is electrically connected to pad 72. Metal layer 31 may have exposed side surface 31b. In this embodiment, interface layer 33 may be disposed on upper surface 31a of metal layer 31. Interface layer 33 may extend along a first direction parallel to the X-axis. Interface layer 33 may extend across conductive element 30 from one side surface to the other side surface of conductive element 30 along the first direction. In some embodiments, upper surface 31a may be perpendicular to side surface 31b. In some embodiments, upper surface 31a may be inclined relative to side surface 31b.

[0041] Although Figure 3 The interface layer 33 is shown as a single continuous layer extending along the first direction, but the interface layer 33 may include, for example, Figure 2B The metal particles 332' of the interface layer 33 are arranged along the X axis. The metal particles 332' can be placed on the upper surface 31a of the metal layer 31. The interface layer 33 can also include the following according to some embodiments: Figure 2A 、 Figure 2C and Figure 2D The metal layer 332 and the alloy layer 331 are shown in FIG.

[0042] Figure 4 FIG is a cross-sectional view of a semiconductor device 1c according to some embodiments of the present disclosure. In addition to the fact that the interface layer 33' of the semiconductor device 1c can be further disposed on the side of the conductive element 30, Figure 4 The structure of the semiconductor device 1c is similar to Figure 3 Structure of the semiconductor device 1b.

[0043] In some embodiments, the interface layer 33 ′ may be further disposed on the side surface 31 b of the metal layer 31 along a second direction parallel to the Y-axis.

[0044] Although Figure 4 The interface layer 33' is shown as a single continuous layer, but the interface layer 33' may include, for example, Figure 2B . In some embodiments, the metal particles 332' of the interface layer 33' disposed on the side 31b may have a portion protruding from the side 31b. In some embodiments, the alloy shell 331' of the interface layer 33' disposed on the side 31b may have a portion protruding from the side 31b.

[0045] Figure 5 is a cross-sectional view of a semiconductor device 1d according to some embodiments of the present disclosure. In addition to the fact that the interface layer 33″ of the semiconductor device 1d may extend from the passivation layer 81 to the passivation layer 82, Figure 5 The structure of the semiconductor device 1d is similar to Figure 4 Structure of semiconductor device 1c.

[0046] Figure 6 is a cross-sectional view of a semiconductor device 1e according to some embodiments of the present disclosure. In addition to the fact that the metal layer 32' of the semiconductor device 1e may have a concave surface for accommodating the first metal layer 31, Figure 6 The structure of the semiconductor device 1e is similar to Figure 4 structure of the semiconductor device 1c. In some embodiments, the concave surface of the metal layer 32' may correspond to the upper surface 31a and the side surface 31b of the metal layer 31. In some embodiments, the profile of the metal layer 32' is different from the profile of the metal layer 31. In some embodiments, the interface layer 33'' of the semiconductor device 1e may be disposed on the upper surface 31a and the side surface 31b of the metal layer 31. A portion of the interface layer 33'' is exposed from the metal layer 32'. In this embodiment, the interface layer 33'' may be U-shaped. In this embodiment, the arrangement of the metal particles 331' may be U-shaped.

[0047] Figure 7 3 is a cross-sectional view of a semiconductor device 1f according to some embodiments of the present disclosure. In addition to the semiconductor device 1f further comprising a barrier layer 34, a metal layer 35, a barrier layer 36, and a metal layer 37, Figure 7 The structure of the semiconductor device 1f is similar to Figure 3 Structure of the semiconductor device 1b.

[0048] Metal layer 35 may be in direct contact with pad 72. Metal layer 37 may be in direct contact with pad 71. Barrier layer 34 may be disposed between metal layer 32 and metal layer 35. Barrier layer 36 may be disposed between metal layer 31 and metal layer 37. Metal layer 37 may be made of a third metal material different from the first metal material. The third metal material may include copper, aluminum, iron, nickel, tin, lead, silver, gold, or other suitable materials. Metal layer 35 may be made of the same material as metal layer 37.

[0049] Barrier layer 36 can be configured to prevent the second metal material in interface layer 33 from diffusing into metal layer 37 during the formation of conductive element 30. Barrier layer 36 can be made of titanium or tantalum. For example, barrier layer 36 can be made of titanium nitride or other suitable materials. Barrier layer 34 can be made of the same material as barrier layer 36.

[0050] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D and Figure 8E Various stages of a method for manufacturing a semiconductor device 1 a according to some embodiments of the present disclosure are shown.

[0051] refer to Figure 8A , providing a substrate 10. A passivation layer 61 is formed on the substrate 10. The passivation layer 61 may include nitride, oxide, oxynitride, or other suitable materials. In some embodiments, the passivation layer 61 may be deposited on the upper surface of the substrate 10, and then a patterning process may be performed on the passivation layer 61 to form a plurality of openings.

[0052] A metal layer 31 including or made of a first metal material may be formed in the opening of the passivation layer 61. The metal layer 31 may be formed by, for example, a sputtering process, an electroplating process, or other suitable processes.

[0053] refer to Figure 8B, the substrate 10 can be immersed in a solution 90. In some embodiments, the solution 90 containing ions of the second metal material can be sprayed or coated on the upper surface 31a of the metal layer 31 or the upper surface of the passivation layer 61. In some embodiments, the solution 90 can be a silver nitrate (AgNO3) solution containing a plurality of silver ions dispersed in a nitrite solution. In some embodiments, when the passivation layer 61 is not formed, the solution 90 can be further coated on the side 31b of the metal layer 31.

[0054] In some embodiments, pretreatment may be performed on the upper surface 31a of the metal layer 31 or the upper surface of the passivation layer 61. The pretreatment may be used to remove native oxide formed on the upper surface 31a. The pretreatment may include, for example, a cleaning process or other suitable processes.

[0055] In some embodiments, solution 90 may include AuCN, AgCN, CuSO 4 , NiSO 4 , ZnSO 4 or other suitable salts or materials. In some embodiments, the concentration of solution 90 may be in the range of about 0.001 M to about 0.1 M. In some embodiments, the concentration of solution 90 may be in the range of about 0.01 M to about 0.05 M.

[0056] refer to Figure 8C , a plurality of metal particles 91 comprising a second metal material or made of a second metal material may be formed on the upper surface 31a of the metal layer 31. In some embodiments, the metal particles 91 may comprise silver. When the reduction potential of the ions of the second metal material is greater than or exceeds the reduction potential of the first metal material, a Galvanic replacement reaction will occur. The Galvanic replacement reaction oxidizes the first metal material into ions of the first metal material and reduces the ions of the second metal material into the second metal material. Therefore, metal particles 91 may be formed on the upper surface 31a of the metal layer 31. For example, when a silver nitrate solution is applied to copper, the silver ions are reduced to form silver nanoparticles, and the copper is oxidized to form copper ions. The reaction may be presented as follows:

[0057] 2AgNO 3(aq) +Cu (s) →2Ag (s) +Cu(NO3) 2(aq)

[0058] The galvanic replacement reaction can occur at a specific temperature. For example, copper can be replaced with silver at a temperature between about 25°C and about 100°C. In some embodiments, the size of each of the plurality of metal particles 91 is in the range of about 20 nm to about 35 nm. In some embodiments, the size of each of the plurality of metal particles 91 is in the range of about 35 nm to about 50 nm. In some embodiments, the size of each of the plurality of metal particles 91 is in the range of about 50 nm to about 70 nm. In some embodiments, the size of each of the plurality of metal particles 91 is in the range of about 70 nm to about 90 nm. When the size of the metal particles 91 is within this range, the interface layer 33 will be formed at a lower temperature.

[0059] In some embodiments, when the passivation layer 61 is not present, metal particles 91, such as silver particles, may be further formed on the side 31 b of the metal layer 31. In some embodiments, the roughness of the upper surface of the metal layer 31 is in a range of about 1 nm to about 10 nm. In some embodiments, the roughness of the upper surface of the metal layer 31 is in a range of about 10 nm to about 50 nm.

[0060] refer to Figure 8D , providing a substrate 20. A metal layer 32 and a passivation layer 62 may be formed on the substrate 20. The processes for forming the metal layer 32 and the passivation layer 62 may be similar or identical to those for forming the metal layer 31 and the passivation layer 61 and are not repeated herein. In some embodiments, metal particles 91 may be formed on the surface of the metal layer 32.

[0061] refer to Figure 8E , forming metal-to-metal bonding (e.g., bonding of metal layer 31 to metal layer 32), and producing semiconductor device 1a. Metal layer 31 and metal layer 32 can be bonded by a heating process that can be performed, for example, at a temperature below 200°C. When performing the heating process, interface layer 33 is formed. In some embodiments, passivation layer 61 is bonded to passivation layer 62 to form passivation layer 60.

[0062] In addition, the passivation layer 61 is bonded to the passivation layer 62, and a boundary S1 is formed. In this step, hybrid bonding is performed on the Figures 8D to 8E The hybrid bonding comprises two different types of bonding. More specifically, Figures 8D to 8E The step of forming a bond between metal layers and forming a bond between passivation layers includes forming a bond between metal layers and forming a bond between passivation layers. Metal particles 91 can be selectively formed on metal layer 31, and the metal particles can therefore improve the bond between metal layer 31 and metal layer 32 without adversely affecting the bond between passivation layer 61 and passivation layer 62.

[0063] In some embodiments, the first metal material is copper and the second metal material is silver. In this embodiment, copper and silver can form an alloy that inhibits or prevents the formation of intermetallic compounds (IMCs). As a result, the resistance of conductive element 30 is reduced. In addition, the process for forming a metal-metal bond (e.g., the bond between metal layer 31 and metal layer 32) can be performed at a lower temperature and / or in a shorter time.

[0064] In this embodiment, metal particles 91 are formed on the metal layer by a galvanic replacement reaction, which can eliminate the need for a plasma treatment before bonding the metal layer 31 to the metal layer 32. Plasma treatment may damage the surface of the passivation layer 61, thereby making the bonding between the passivation layers 61 and 62 more difficult. In this embodiment, the upper surface of the passivation layer 61 is not damaged by the plasma process, so the bonding between the passivation layers 61 and 62 is stronger. Compared with the process of treating the metal layer and the passivation layer by plasma, the embodiment of the present disclosure using the galvanic replacement reaction can form a stronger hybrid bonding. In a comparative example in which metal particles 91 are not formed, a plasma process is performed on the surface of the copper liner to generate voids thereon, thereby accelerating the diffusion rate of copper atoms in the subsequent annealing, and then an annealing process is performed for the copper-copper bonding process. However, the plasma process is not selective for the material and the surface of the passivation layer is also bombarded by the plasma, which makes the bonding of the passivation layer to the passivation layer more difficult. In some embodiments of the present disclosure, the galvanic displacement reaction is selective for the metal layer 31 and the passivation layers 61 and 62. That is, metal particles 91 are formed only on the interface of the metal layer 31 and not on the passivation layers 61 and 62, thereby reducing contamination on the passivation layers 61 and 62. As a result, passivation layer-passivation layer bonding is more easily formed.

[0065] In addition, the metal particles 91 can help to bond two metal layers with different shapes (such as Figure 6 ), thereby improving the yield of semiconductor devices.

[0066] Figure 9A and Figure 9B Improved metal liners according to some embodiments of the present disclosure are presented. Figure 9A or Figure 9B The improved metal liner shown in Figure 8C , a structure including a metal layer 31 and a plurality of metal particles 91 formed on an upper surface 31 a of the metal layer 31 is shown.

[0067] like Figure 9AAs shown in FIG, the improved metal liner may include a plurality of metal particles 91a located on the upper surface 31a of the metal layer 31. The plurality of metal particles 91a may be separated from each other. In some embodiments, the metal particles 91a may be randomly distributed on the upper surface 31a of the metal layer 31.

[0068] like Figure 9B As shown in FIG, the improved metal liner may include a plurality of metal particles 91b located on the upper surface 31a of the metal layer 31. The arrangement of the metal particles 91b on the upper surface 31a of the metal layer 31 may be in a dendritic shape. The arrangement of the particles may be determined by the process time, process temperature, and the ion content (e.g., Ag). + ) is controlled by the concentration of the solution 90. In this embodiment, the metal particles or alloy shells formed after bonding of the metal layer 31 to the metal layer 32 may be arranged in a dendritic shape.

[0069] The dendritic shape of the arrangement may help form metal particles 91 b with smaller sizes and reduce the process temperature during bonding of the metal layer 31 and the metal layer 32 .

[0070] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly indicates otherwise.

[0071] As used herein, the terms "conductive," "electrically conductive," and "electrical conductivity" refer to the ability to carry an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of electrical conductivity is Siemens per meter (S / m). Typically, a conductive material is one having an electrical conductivity exceeding approximately 104 S / m, such as at least 105 S / m or at least 106 S / m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0072] In addition, amounts, ratios and other numerical values are sometimes presented herein in a range format. It should be understood that such range format is used for convenience and brevity and should be construed flexibly to include the values explicitly designated as the limits of the range, and also to include all individual values or subranges encompassed within the range, as if each value and subrange were explicitly designated.

[0073] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present disclosure as defined by the claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically shown. The description and drawings should be regarded as illustrative and not restrictive. Modifications may be made to adapt specific circumstances, materials, material compositions, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or rearranged to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A semiconductor device comprising: substrate; A conductive element is disposed on the substrate, the conductive element has a side surface, and the conductive element comprises: a first metal layer, the first metal layer comprising a first metal material; a plurality of metal particles, the plurality of metal particles comprising a second metal material, at least one metal particle of the plurality of metal particles being embedded in the first metal layer, the at least one metal particle of the plurality of metal particles having a portion protruding from the side surface of the first metal layer; and A plurality of alloy shells are provided, each of the alloy shells including the first metal material and the second metal material, and each of the alloy shells covers corresponding metal particles.

2. The semiconductor device according to claim 1 , wherein an amount of the first metal material in each of the plurality of alloy shells is in a range of 20 wt % to 90 wt %, and an amount of the second metal material in each of the plurality of alloy shells is in a range of 5 wt % to 80 wt %. 3 . The semiconductor device according to claim 1 , wherein a diameter of a sum of each alloy shell and corresponding metal particles in the plurality of alloy shells is in a range of 10 nm to 400 nm. The semiconductor device according to claim 1 , wherein the plurality of alloy shells are distributed in a dendrite shape.

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