Image sensor device

Abstract

An image sensor device is disclosed that blocks noise in a pad region. The image sensor device includes a substrate, a pad, and an impurity region. The substrate includes a first surface and a second surface, and includes a first conductive impurity. The pad is disposed at the first surface of the substrate. The impurity region is formed in the substrate to overlap with the pad in a first direction, and the impurity region includes a second conductive impurity different from the first conductive impurity.

Description

Technical Field

[0001] The present invention relates generally to image sensor technology, and more particularly to a technology for blocking noise or minimizing parasitic capacitance of a pad area of ​​an image sensor. Background Art

[0002] Image sensors convert optical images into electrical signals. Recently, due to increased research and development in the computer industry and the communications industry, the demand for high-quality, high-performance image sensors has increased rapidly in various applications and fields such as digital cameras, camcorders, personal communication systems (PCS), game consoles, surveillance cameras, medical miniature cameras, etc.

[0003] Specifically, MOS image sensors can be driven more easily and can be implemented using more scanning schemes. MOS image sensors may include: one or more photoelectric conversion elements configured to sense the size of incident light; and a multi-layer metal wire layer configured to output the optical signal stored in the photoelectric conversion element. However, the incident light may be reflected by the metal wire layer and may be absorbed by the interlayer insulating film, resulting in reduced sensitivity. In addition, the reflected light may be absorbed into adjacent (or neighboring) pixels, resulting in crosstalk. Summary of the invention

[0004] Various embodiments of the disclosed technology are directed to an image sensor device for reducing noise and parasitic capacitance of a pad area. The image sensor may be a BSI image sensor.

[0005] According to an embodiment of the disclosed technology, an image sensor device may include: a substrate including a first surface and a second surface, the substrate being configured to have a first conductive impurity; a pad disposed at the first surface of the substrate; and an impurity region formed in the substrate to overlap with the pad in a first direction, the impurity region being configured to have a second conductive impurity different from the first conductive impurity.

[0006] According to another embodiment of the disclosed technology, an image sensor device may include: a substrate including a first surface and a second surface, the substrate being configured to have a first conductive impurity; a pad disposed at the first surface of the substrate; and an impurity region including a second conductive impurity different from the first conductive impurity and disposed at both ends of the substrate relative to a first direction within the substrate.

[0007] According to another embodiment of the disclosed technology, an image sensor device may include: a substrate in which a pad area and a circuit area adjacent to the pad area are defined, the substrate being configured to include a first conductive impurity; a pad disposed at a first surface of the substrate in the pad area; and an impurity region formed below the pad in the pad area, the impurity region being configured to have a second conductive impurity different from the first conductive impurity and formed in the substrate.

[0008] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further description of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0010] Figure 1 is a schematic plan view showing an example of an image sensor device based on various implementations of the disclosed technology.

[0011] Figure 2 is a block diagram showing examples of some constituent elements of an image sensor device based on various implementations of the disclosed technology.

[0012] Figure 3 It is a diagram showing various implementations based on the disclosed technology. Figure 1 A cross-sectional view of an example of a pad of an image sensor device is shown.

[0013] Figures 4 to 8 It is a diagram showing various implementations based on the disclosed technology. Figure 1 Cross-sectional views of other examples of pads of an image sensor device are shown.

[0014] Fig. 9 It is a diagram showing various implementations based on the disclosed technology. Figure 8 A plan view of an example of an image sensor device is shown.

[0015] Symbols of various components in the drawings

[0016] M1~M4: Multiple lines

[0017] 101: Substrate

[0018] 108: Conductive film

[0019] 110: Pad DETAILED DESCRIPTION

[0020] Various implementations and examples of image sensor devices are provided, which solve one or more problems caused by limitations and disadvantages of the prior art. Various implementations of the disclosed technology relate to an image sensor device capable of reducing or blocking pad area noise and parasitic capacitance and solving the above-mentioned problems of the prior art.

[0021] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used throughout the drawings to refer to the same or like parts.

[0022] The advantages and features of the disclosed technology and the methods for realizing the advantages and features of the disclosed technology will be clearly understood from the embodiments described below in conjunction with the accompanying drawings. However, the disclosed technology is not limited to the following embodiments and can be implemented in various different forms. These embodiments are provided only to fully disclose the technology and enable ordinary technicians in the field to which the disclosed technology belongs to fully understand the present disclosure. That is, the disclosed technology is limited only by the claims. In the drawings, the sizes or relative sizes of layers and regions may be exaggerated for clarity of description.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the disclosed technology. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form. It will also be understood that when used in this specification, the terms "include" and / or "comprise" indicate the presence of the constituent elements, steps, operations and / or components, but do not exclude the presence or addition of one or more other constituent elements, steps, operations and / or their components. The term "and / or" may include any one of a combination of multiple items or multiple items. The same reference numerals will be used throughout this specification to represent the same or similar constituent elements.

[0024] In the description of the disclosed technology, the terms "first", "second", etc. may be used to describe various elements, components and / or sections, but the elements, components and / or sections are not limited by these terms. These terms can be used to distinguish one component, one constituent element or one section from another component, another constituent element or another section. Therefore, without departing from the scope of the disclosed technology, the first element, the first constituent element or the first section may also be referred to as the second element, the second constituent element or the second section.

[0025] When an element or layer is referred to as being "on" another element or layer, it can be directly on the element or layer, or one or more intervening elements or layers may also be present. Conversely, when an element or layer is referred to as being "directly on" another element or layer, it means that there are no intervening elements or layers. The term "and / or" may include a combination of a plurality of items or any one of the plurality of items.

[0026] Spatially relative terms such as "below," "beneath," "below," "above," or "upper" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the elements during use or operation of the elements in addition to the orientations depicted in the figures. Whenever possible, the same reference numerals will be used throughout the specification to refer to the same or similar elements.

[0027] In addition, the embodiments described herein may be understood with reference to various cross-sectional views and plan views. Therefore, the form of the drawings may change according to manufacturing techniques and / or tolerances. Therefore, the embodiments of the disclosed technology are not limited to the specific forms shown, but may include changes in form produced according to the manufacturing process. Therefore, the regions shown in the drawings have schematic properties, and the shapes of the regions shown are intended to illustrate the specific forms of the regions of the elements (or devices), rather than to limit the scope of the disclosed technology.

[0028] Figure 1 is a plan view showing an example of an image sensor device 100 based on various implementations of the disclosed technology. Figure 2 is a block diagram showing examples of some constituent elements of an image sensor device 100 based on various implementations of the disclosed technology.

[0029] Reference Figure 1 and Figure 2 , the image sensor device 100 may include a pixel area PXA, a circuit area CA, and a pad area PA.

[0030] The pixel area PXA may include a pixel array 10 in which a plurality of unit pixels 12 are arranged in a matrix shape. Each of the plurality of unit pixels 12 may include a photoelectric conversion element (not shown).

[0031] The circuit area CA may be formed around the pixel area PXA and may include a plurality of circuits 20. The circuit area CA may include a plurality of CMOS transistors (not shown). The circuit area CA may transmit a predetermined signal to each unit pixel 12 of the pixel array 10, or may control an output signal at each unit pixel 12. The pad area PA may include a plurality of pads 30 disposed adjacent to the circuit area CA. For example, Figure 1 As shown, a plurality of pads 30 may be spaced apart from each other in a single file in the pad area PA. However, the present invention may not be limited to this approach. For example, in other implementations of the present invention, a double file or other configuration of the pads 30 may be adopted.

[0032] Reference Figure 1, the circuit area CA may be defined as surrounding the pixel area PXA, and the pad area PA may be defined as surrounding the circuit area CA, but is not limited thereto. For example, in a variation of the described implementation, the circuit area CA may not surround the pixel area PXA. In addition, the pad area PA may not be formed on all sides of the circuit area. For example, the pad area may be formed only on three sides of the circuit area CA, or only on two sides, or only on one side. In an implementation, for example, the circuit area CA may not surround the pixel area PXA, and the pad area PA may be formed only on one side of the circuit area CA.

[0033] Reference Figure 2 , the plurality of circuits 20 formed in the circuit area CA may include a timing generator 21, a row decoder 22, a row driver 23, a correlated double sampler (CDS) circuit 24, an analog-to-digital converter (ADC) circuit 25, a latch circuit 26, and a column decoder 27.

[0034] The pixel array 10 included in the pixel area PXA may receive a plurality of drive signals (e.g., a row selection signal, a reset signal, a charge transfer signal, etc.) from the row driver 23, and may be driven by the received drive signals. In addition, the electrical signal obtained by photoelectric conversion in the pixel array 10 may be provided to the CDS circuit 24.

[0035] The timing generator 21 may send a timing signal and a control signal to the row decoder 22 and the column decoder 27. Upon receiving the decoding result from the row decoder 22, the row driver 23 may send a plurality of driving signals required to drive the plurality of unit pixels 12 to the pixel array 10 of the pixel area PXA. If the plurality of unit pixels 12 are arranged in a matrix, the row driver 23 may provide a driving signal for each row of the matrix.

[0036] The CDS circuit 24 may receive an output signal from the pixel array 10 of the pixel area PXA, and may hold and sample the received output signal. That is, the CDS circuit 24 may perform double sampling of a signal level and a specific noise level caused by each output signal, and thus may output a level difference corresponding to the difference between the noise level and the signal level.

[0037] The ADC circuit 25 can convert the analog signal corresponding to the level difference into a digital signal, and thus can output the digital signal. The latch circuit 26 can latch the digital signal, and can sequentially output the latched signal to the image signal output circuit (not shown) in response to the decoding result obtained by the column decoder 27.

[0038] In some implementations, the image sensor device 100 may be a backside illumination (BSI) image sensor. In addition, light may be incident on the pixel area PXA from the same surface as the exposed surface where the plurality of pads 30 are exposed to the outside among the plurality of exposed surfaces of the image sensor device 100 .

[0039] The plurality of pads 30 may be electrically coupled to the plurality of wells formed in the circuit area CA via connection lines. In some implementations, the plurality of pads 30 may be formed of metal, metal nitride, or a combination thereof. In some implementations, the plurality of pads 30 formed in the pad area PA may send electrical signals to and receive electrical signals from an external device. In other implementations, the plurality of pads 30 may be used to transmit a driving power source (e.g., a power supply voltage or a ground voltage received from the outside) to a circuit included in the circuit area CA via connection lines.

[0040] Figure 3 It is a diagram showing various implementations based on the disclosed technology. Figure 1 1 is a cross-sectional view of an example of an image sensor device 100. In more detail, Figure 3 It is shown in Figure 1 1 is a cross-sectional view of the pad area PA taken along line AA′ in the image sensor device 100 .

[0041] Reference Figure 3 , a circuit area CA and a pad area PA adjacent to each other in the first direction X may be defined in the substrate 101. For convenience of description, the substrate including the pad area PA of the pad 110 will be denoted by reference numeral "101" below, and the substrate including the circuit area CA will be denoted by reference numeral "101a" below. The circuit area CA and the pad area PA may be adjacent to each other in the first direction X.

[0042] The substrate 101 may include a front side (FS) and a back side (BS) arranged to face each other. One side of the substrate 101 may be defined as the front side (FS), and the other side of the substrate 101 may be defined as the back side (BS), but is not limited thereto. For example, a unit element may be formed above the front side (FS) of the substrate 101, and light may be emitted to the back side (BS) of the substrate 101.

[0043] The substrate 101 may be any suitable substrate. For example, the substrate 101 may be a P-type bulk substrate. In addition, for example, the substrate 101 may be an N-type bulk substrate. The substrate may include an epitaxial layer grown on a bulk substrate. The epitaxial layer may be a P-type epitaxial layer. The epitaxial layer may be an N-type epitaxial layer. For example, the substrate may be a substrate formed by growing a P-type or N-type epitaxial layer on an N-type bulk substrate or a P-type bulk substrate. The substrate 101 may be formed of an organic plastic substrate rather than a semiconductor substrate. Examples of organic plastic substrates may include substrates made of organic small molecules or polymers. For example, the organic small molecules may include polycyclic aromatic compounds such as pentacene, anthracene, and rubrene. For example, suitable polymers may include fluoropolymers such as PVDF (polyvinylidene fluoride) or PVDF copolymers such as copolymers of PVDF and trifluoroethylene. In some implementations, a P-well 102 may be formed on the front side (FS) included in the P-type substrate 101.

[0044] A plurality of wires M1 to M4 for signal transmission may be disposed above the front side (FS) of the substrate 101. The plurality of wires M1 to M4 may be sequentially stacked above an interlayer insulating film (not shown). In this case, each of the plurality of wires M1 to M4 may include a metal. For example, the plurality of wires M1 to M4 may include copper (Cu), platinum (Pt), tungsten (W), aluminum (Al), an alloy layer formed of the above materials, and the like. The number of layers of the plurality of wires M1 to M4 and the structural type of the plurality of wires M1 to M4 may not be limited thereto, and the plurality of wires M1 to M4 may be formed with various numbers of layers and various structural types according to a device design method.

[0045] The conductive film 108 may be disposed above the back side (BS) of the substrate 101. The conductive film 108 may be formed above the substrate 101. The conductive film 108 may be formed to cover the top surface of the back side (BS) of the substrate 101. The conductive film 108 may be formed to be longer than the pad 110 in the X-axis direction parallel to the substrate 101. In an embodiment, the conductive film 108 may be formed to be in direct contact with the top surface of the back side (BS) of the substrate 101. The conductive film 108 may be formed to be thinner than the pad 110 in the Y-axis direction. The Y-axis may be perpendicular to the X-axis. The conductive film 108 may extend to at least partially cover both sides of the pad 110, and may be connected to the top surface of the through silicon via (TSV) 106. The conductive film 108 may be disposed in a trench (T) formed to expose some portions of the back side (BS) of the substrate 101.

[0046] The conductive film 108 may be formed to prevent the substrate 101 from being damaged in a patterning process for forming the pad 110. For example, the conductive film 108 may include a metal such as tungsten (W).

[0047] The pad 110 may be disposed above the conductive film 108 of the substrate 101. In an embodiment, the pad 110 may be directly formed on the conductive film 108 of the substrate 101. The pad 110 may be Figure 1 The pad 110 corresponds to a constituent element shown. The pad 110 may be formed along the top surface and sidewall of the conductive film 108 that may be conformally formed in the trench (T). In addition, the pad 110 and the plurality of wires M1 to M4 may be electrically coupled to each other through a through silicon via (TSV) formed to penetrate the substrate 101. In this case, the pad 110 may include a metal material such as aluminum (Al), copper (Cu), or the like.

[0048] The insulating layer 107 may be formed at the sidewall of the through silicon via (TSV) 106, and may also be formed under the conductive film 108. The insulating layer 107 may be formed as an isolation pattern, and the through silicon via (TSV) 106 and the substrate 101 may be electrically isolated from each other by the insulating layer 107. The insulating layer 107 may be formed to prevent the through silicon via (TSV) 106 and the conductive film 108 from being electrically coupled to (i.e., short-circuited to) the substrate 101.

[0049] In this case, the insulating layer 107 may be formed of only one insulating material. In another example, the insulating layer 107 may be formed by stacking at least two insulating patterns. The insulating layer 107 may be formed of an oxide material such as silicon oxide and metal oxide, or may be formed of a nitride material such as silicon nitride.

[0050] The through silicon via (TSV) 106 may be formed on one side of the substrate 101 and may be formed to penetrate the substrate 101. The bottom surface of the through silicon via (TSV) 106 may contact the plurality of lines M1 to M4. The through silicon via (TSV) 106 may have a sidewall slope such that the inner width of the through silicon via (TSV) 106 decreases in a downward direction from the back side (BS) of the substrate 101. Alternatively, although not shown in the figure, the through silicon via (TSV) 106 may also have a vertical sidewall slope as required.

[0051] A contact hole (not shown) penetrating the substrate 101 may be formed, and the contact hole (not shown) may be filled with a conductive material, thereby forming a through silicon via (TSV) 106. The through silicon via (TSV) 106 may also be formed to fill the contact hole (not shown), and may also be conformally formed along the sidewall of the contact hole. The through silicon via (TSV) 106 may be formed in any shape in which the conductive film 108 can be easily connected to the plurality of wires M1 to M4.

[0052] The image sensing device 100 based on some implementations of the disclosed technology may include a noise blocking impurity region 105 disposed in the substrate 101 below the pad 110. That is, the image sensing device 100 based on some implementations of the disclosed technology may be formed as a second conductive (e.g., N-type) doped region of the substrate 101 disposed below the pad 110 by impurity implantation.

[0053] Typically, the circuit area CA may not be disposed in the lower region of the pad 110 to prevent physical damage, and the lower region of the pad 110 is doped with the same type of conductive material as the conductive material in the substrate 101. In this case, parasitic capacitance may be formed between the pad 110 and the substrate 101.

[0054] Specifically, in the case of using a backside illumination (BSI) image sensor, a signal applied to the pad 110 may be transmitted to the lower lines M1 to M4 through the through silicon via (TSV) 106. Therefore, an excessive capacitance may be formed between the pad 110 and the substrate 101. If such capacitance between the pad 110 and the substrate 101 increases, the transition speed of one or more input signals may be slowed down. In addition, if a fast digital transition signal is input to the pad 110, noise may be introduced into the substrate 101 through the pad 110.

[0055] The image sensor device 100 may include the impurity region 105 in the substrate 101 so that parasitic capacitance generated between the pad 110 and the substrate 101 may be reduced.

[0056] The first parasitic capacitance (CP) may be generated by the insulating layer 107 (i.e., dielectric material) present between the pad 110 and the substrate 101. In this case, when the substrate 101 disposed below the pad 110 is doped with a second conductive (e.g., N-type) material, a second parasitic capacitance (CJ) caused by a reverse PN junction may occur in a boundary region between the impurity region 105 and the substrate 101a.

[0057] That is, a depletion region of a PN junction may be formed in a boundary region between the impurity region 105 and the substrate 101a, so that a second parasitic capacitance (CJ) may appear. The first parasitic capacitance (CP) and the second parasitic capacitance (CJ) may be connected in series.

[0058] That is, the size of the boundary region between the pad 110 and the substrate 101 may be relatively large, and the size of another boundary region between the impurity region 105 and the substrate 101a may be relatively small. Therefore, the second parasitic capacitance (CJ) may be smaller than the first parasitic capacitance (CP).

[0059] That is, the first parasitic capacitor (CP) having a relatively high capacitance may be connected in series to the second parasitic capacitor (CJ) having a relatively low capacitance. Therefore, the total capacitance between the pad 110 and the substrate 101 may be significantly reduced compared to the case where only the first parasitic capacitor (CP) exists. In other words, the total capacitance of the substrate 101 may be reduced by the second parasitic capacitor (CJ) having a lower capacitance value among the first parasitic capacitor (CP) and the second parasitic capacitor (CJ). Therefore, as the thickness of the depletion region of the PN junction in the second parasitic capacitor (CJ) is greater than the thickness of the dielectric material of the substrate 101, the total capacitance generated in the substrate 101 may be reduced.

[0060] In some other implementations, a bias voltage may be applied between pad 110 and each of substrates 101 and 101a so that noise between pad 110 and substrates 101 and 101a may be reduced. For example, a first well bias may be applied to the image sensor device through substrate 101a. In addition, a second well bias may be applied to the image sensor device through impurity region 105 of substrate 101. The voltage level of the first well bias may be different from the voltage level of the second well bias.

[0061] For example, when the impurity region 105 is formed of a second conductive (e.g., N-type) material, the second well bias may be a power supply voltage (VDDIO). When the substrate 101a is formed of a first conductive (e.g., P-type) material, the first well bias may be a ground voltage (VSS). Therefore, the connection between the pad 110 and the substrate 101 is cut off, so that the noise introduced into the substrate 101 through the pad 110 can be reduced.

[0062] Figure 4 It is a diagram showing various implementations based on the disclosed technology. Figure 1 A cross-sectional view of another example of an image sensor device is shown. Figure 4 In order to facilitate description and better understand the disclosed technology, Figure 3 The same constituent elements will be used to refer to the same or similar parts, and thus redundant contents thereof will be omitted herein for the sake of brevity.

[0063] Reference Figure 4 The impurity region 105 may be formed by stacking a plurality of doping regions. For example, the impurity region 105 may include an impurity layer (NW) 102 and another impurity layer (DNW) 104.

[0064] During an impurity implantation process for implanting impurities into a circuit (eg, a transistor) included in the circuit area (CA), a second conductive (eg, N-type) impurity may be implanted into the impurity region 105 through the front side (FS) of the substrate 101 .

[0065] The substrate 101 may include a first conductive (e.g., P-type) impurity. A second conductive (e.g., N-type) impurity layer 102 and another second conductive (e.g., N-type) impurity layer 104 may be formed in the substrate 101. In this case, the impurity layers 102 and 104 may have various types of arrangements, shapes, densities, etc. as required.

[0066] In some implementations, the impurity layer 104 may be stacked on the impurity layer 102. The impurity layer 102 and the other impurity layer 104 may be formed to have the same size in the X-axis direction. Each of the impurity layer 102 and the impurity layer 104 may be larger than the pad 110 in the X-axis direction, that is, the size in the X-axis direction may be larger than the X-axis size of the pad 110. The impurity layer 102 and the impurity layer 104 may have the same second conductive (e.g., N-type) impurities. The impurity layer 102 and the impurity layer 104 may have a conductive material different from the conductive material of the substrate 101. The impurity layer 104 may be formed as a deep well.

[0067] Figure 5 Some implementations based on the disclosed technology are shown in Figure 1 A cross-sectional view of another example of an image sensor device is shown. Figure 5 In order to facilitate description and better understand the disclosed technology, Figure 3 The same constituent elements will be used to refer to the same or similar parts, and thus redundant contents thereof will be omitted herein for the sake of brevity.

[0068] Reference Figure 5 , the impurity region 105 may be formed as a second conductive (eg, N-type) doped region. Figure 5 In the embodiment, during an impurity implantation process for implanting impurities into a photoelectric conversion element (not shown) included in the pixel area PXA, a second conductive (e.g., N-type) impurity may be implanted into the impurity region 105 in a direction of either the front side (FS) or the back side (BS) of the substrate 101. That is, there is no need to use a separate process for forming the impurity region 105, and the impurity region 105 may be formed simultaneously with the impurity implantation process of the pixel area PXA.

[0069] The photoelectric conversion element (not shown) may include a photodiode (PD) that accumulates photocharges generated in response to incident light in its internal region. The photodiode (PD) may be an example of a photoelectric conversion element and may be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0070] In some implementations, the impurity region 105 may be formed as a stacked structure of a plurality of doped regions. For example, the impurity region 105 may include an impurity layer (PDN) 112 and an impurity layer (PDW) 114 .

[0071] The substrate 101 may include a first conductive (e.g., P-type) impurity. A second conductive (e.g., N-type) impurity layer 112 and another second conductive (e.g., N-type) impurity layer 114 may be formed in the substrate 101. In this case, the impurity layers 112 and 114 may have various types of arrangements, shapes, densities, etc. as needed.

[0072] In some implementations, the impurity layer 114 may be stacked above the impurity layer 112. The impurity layer 112 and the other impurity layer 114 may be formed to have the same size in the X-axis direction. Each of the impurity layer 112 and the impurity layer 114 may be larger than the pad 110 in the X-axis direction. The impurity layer 112 and the impurity layer 114 may have the same second conductive (e.g., N-type) impurities. The impurity layer 112 and the impurity layer 114 may have a conductive material different from the conductive material of the substrate 101.

[0073] Figure 6 It is a diagram showing various implementations based on the disclosed technology. Figure 1 A cross-sectional view of another example of an image sensor device is shown. Figure 6 In order to facilitate description and better understand the disclosed technology, Figure 3 The same constituent elements will be used to refer to the same or similar parts, and thus redundant contents thereof will be omitted herein for the sake of brevity.

[0074] Reference Figure 6 , in order to allow the impurity region 105 to be formed of the second conductive (e.g., N-type) impurities, the impurities may be implanted into the front side (FS) and the back side (BS) of the substrate 101. That is, during the impurity implantation process for implanting impurities into the circuit area (CA), the second conductive (e.g., N-type) impurities may be implanted into the impurity region 105 in the direction of either the front side (FS) or the back side (BS) of the substrate 101. In addition, during the impurity implantation process for implanting impurities into the pixel area (PXA), the second conductive (e.g., N-type) impurities may be implanted into the impurity region 105 through the back side (BS) of the substrate 101.

[0075] In some implementations, the impurity region 105 may be formed as a stacked structure of a plurality of doped regions. For example, the impurity region 105 may include an impurity layer (NW) 116, an impurity layer (PDN) 118, and an impurity layer (PDW) 120. In this case, the impurity layer 116 may be formed of impurities implanted into the front side (FS) of the substrate 101, and each of the impurity layers 118 and 120 may be formed of impurities implanted into the back side (BS) of the substrate 101.

[0076] The substrate 101 may include a first conductive (e.g., P-type) impurity. A second conductive (e.g., N-type) impurity layer 116, a second conductive (e.g., N-type) impurity layer 118, and a second conductive (e.g., N-type) impurity layer 120 may be formed in the substrate 101. In this case, the impurity layers 116, 118, and 120 may have various types of arrangements, shapes, densities, etc. as needed.

[0077] In some implementations, the impurity layer 118 and the impurity layer 120 may be sequentially stacked on the impurity layer 116. The impurity layer 116, the impurity layer 118, and the impurity layer 120 may be formed to have the same size in the X-axis direction. Each of the impurity layer 116, the impurity layer 118, and the impurity layer 120 may be larger than the pad 110 in the X-axis direction. The impurity layer 116, the impurity layer 118, and the impurity layer 120 may have the same second conductive (e.g., N-type) impurities. The impurity layer 116, the impurity layer 118, and the impurity layer 120 may have a conductive material different from the conductive material of the substrate 101.

[0078] Figure 7 It is a diagram showing various implementations based on the disclosed technology. Figure 1 A cross-sectional view of another example of an image sensor device is shown. Figure 7 In order to facilitate description and better understand the disclosed technology, Figure 3 The same constituent elements will be used to refer to the same or similar parts, and thus redundant contents thereof will be omitted herein for the sake of brevity.

[0079] Reference Figure 7 , in order to allow the impurity region 105 to be formed of the second conductive (e.g., N-type) impurities, the impurities may be implanted into the front side (FS) and the back side (BS) of the substrate 101. That is, during the impurity implantation process for implanting impurities into the circuit area (CA), the second conductive (e.g., N-type) impurities may be implanted into the impurity region 105 in the direction of either the front side (FS) or the back side (BS) of the substrate 101. In addition, during the impurity implantation process for implanting impurities into the pixel area (PXA), the second conductive (e.g., N-type) impurities may be implanted into the impurity region 105 in the direction of either the front side (FS) or the back side (BS) of the substrate 101.

[0080] In some implementations, the impurity region 105 may be formed as a stacked structure of a plurality of doped regions. For example, the impurity region 105 may include an impurity layer (NW) 122, an impurity layer (DNW) 124, and an impurity layer (PDW) 126. In this case, the impurity layers 122 and 124 may be formed by impurities implanted into the front side (FS) of the substrate 101, and the impurity layer 126 may be formed by impurities implanted into the back side (BS) of the substrate 101.

[0081] The substrate 101 may include a first conductive (e.g., P-type) impurity. A second conductive (e.g., N-type) impurity layer 122, a second conductive (e.g., N-type) impurity layer 124, and a second conductive (e.g., N-type) impurity layer 126 may be formed in the substrate 101. In this case, the impurity layers 122, 124, and 126 may have various types of arrangements, shapes, densities, etc. as needed.

[0082] In some implementations, the impurity layer 124 and the impurity layer 126 may be sequentially stacked on the impurity layer 122. The impurity layer 122, the impurity layer 124, and the impurity layer 126 may be formed to have the same size in the X-axis direction. Each of the impurity layer 122, the impurity layer 124, and the impurity layer 126 may be larger than the pad 110 in the X-axis direction. The impurity layer 122, the impurity layer 124, and the impurity layer 126 may have the same second conductive (e.g., N-type) impurities. The impurity layer 122, the impurity layer 124, and the impurity layer 126 may have a conductive material different from the conductive material of the substrate 101.

[0083] Figure 8 It is a diagram showing various implementations based on the disclosed technology. Figure 1 A cross-sectional view of another example of an image sensor device is shown. Figure 8 In order to facilitate description and better understand the disclosed technology, Figure 6 The same constituent elements will be used to refer to the same or similar parts, and thus redundant contents thereof will be omitted herein for the sake of brevity.

[0084] Reference Figure 8 Each of the impurity regions 105a and 105b may be formed as a stacked structure of a plurality of doping regions. For example, each of the impurity regions 105a and 105b may include an impurity layer (NW) 128, an impurity layer (PDN) 130, and an impurity layer (PDW) 132.

[0085] The impurity regions 105a and 105b may not be disposed in a lower region of the pad 110 with respect to the Y-axis direction. The impurity regions 105a and 105b may be disposed at both ends of the substrate 101.

[0086] That is, each of the impurity regions 105a and 105b may be formed into a bank (or stripe) structure, so that the bank-shaped impurity regions 105a and 105b may be disposed at both ends of the substrate 101. One impurity region 105a may be formed on one side of the substrate 101 in the X-axis direction. The other impurity region 105b may be formed on the other side of the substrate 101 in the X-axis direction.

[0087] That is, the impurity region 105a may be disposed in the outer edge region of the through silicon via (TSV) 106 in the X-axis direction. The impurity region 105b may be disposed in the outer edge region of the pad region PA in the X-axis direction. For example, the impurity region 105b may be disposed in the circuit region CA. In some implementations, as required, the impurity region 105b may also be disposed in the pad region PA instead of the circuit region CA in the X-axis direction. Each of the impurity regions 105a and 105b may be smaller than the pad 110 in the X-axis direction.

[0088] Each of the impurity regions 105a and 105b may allow parasitic capacitance (CP) to be transferred from the pad 110 to the substrate 101. Parasitic capacitances C1 and C2 may be transferred from the substrate 101 to the impurity region 105b. Parasitic capacitances C3 and C4 may be transferred from the substrate 101 to the impurity region 105a.

[0089] Therefore, the impurity region 105b may include a parasitic capacitance (CP) and two capacitances C1 and C2, so that the impurity region 105b may be formed by a series connection of a total of three capacitances CP, C1 and C2. Therefore, the total capacitance of the substrate 101 may be reduced not only by the parasitic capacitance (CP) but also by the smaller one of the two parasitic capacitances C1 and C2.

[0090] The impurity region 105a may include a parasitic capacitance (CP) and two capacitances C3 and C4, so that the impurity region 105a may be formed by a series connection of a total of three capacitances CP, C3 and C4. Therefore, the total capacitance of the substrate 101 may be reduced not only by the parasitic capacitance (CP) but also by the smaller one of the two parasitic capacitances C3 and C4.

[0091] Fig. 9 It is a diagram showing various implementations based on the disclosed technology. Figure 8 A plan view of an example of an image sensor device is shown. In more detail, Fig. 9 It is shown Figure 8 Schematic plan view of constituent elements of the image sensor device shown in FIG. 1 is used to describe the arrangement relationship between the impurity layer 132 and the conductive film 108. Fig. 9 In order to facilitate description and better understand the disclosed technology, Figure 8 The same constituent elements will be used to refer to the same or similar parts, and thus redundant contents thereof will be omitted herein for the sake of brevity.

[0092] Reference Fig. 9 The pad 110 may be formed above the conductive film 108. A through silicon via (TSV) 106 may be formed below the conductive film 108. A second conductive impurity layer 132 of a complete shape may be formed in a peripheral region of the pad 110.

[0093] That is, the impurity regions 105a and 105b including the impurity layer 132 may be formed to surround the conductive film 108 in all directions. In other words, each of the impurity regions 105a and 105b including the impurity layer 132 may be formed in a rectangular belt shape including the conductive film 108 in the central region.

[0094] As is apparent from the above description, an image sensor device based on various implementations of the disclosed technology can reduce noise and parasitic capacitance of a pad region.

[0095] Those skilled in the art will appreciate that, without departing from the spirit and essential characteristics of the present disclosure, the embodiments may be performed in a specific manner other than that described herein. Therefore, the above-described embodiments will be interpreted as illustrative and not restrictive in all respects. The scope of the present disclosure should be determined by the attached claims and their legal equivalents, rather than by the above description. In addition, all changes falling within the meaning and equivalent scope of the attached claims are intended to be included therein. In addition, those skilled in the art will appreciate that claims that are not explicitly referenced to each other in the attached claims may be presented as an embodiment combination, or included as a new claim by subsequent amendments after the application is submitted.

[0096] Although many exemplary embodiments have been described, it should be understood that those skilled in the art may devise many other modifications and embodiments that will fall within the spirit and scope of the principles of the present disclosure. Specifically, many changes and modifications may be made in the components and / or arrangements within the scope of the present disclosure, the drawings, and the appended claims. In addition to changes and modifications in the components and / or arrangements, alternative uses will also be apparent to those skilled in the art.

[0097] CROSS-REFERENCE TO RELATED APPLICATIONS

[0098] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0039787, filed on Apr. 1, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. An image sensor device, the image sensor device comprising: a substrate in which a pad region and a circuit region adjacent to the pad region are defined, the substrate comprising a first surface and a second surface and the substrate being configured to have a first conductive impurity; a pad, the pad being arranged at the first surface of the substrate in the pad region; as well as an impurity region formed in a lower portion of the pad to overlap the pad in a first direction, the impurity region being formed in a partial region of the substrate in the pad region, the impurity region being configured to have a second conductive impurity different from the first conductive impurity, The substrate formed in the circuit region and the impurity region formed in the pad region are in contact with each other through a boundary region, and parasitic capacitance occurs in the boundary region between the substrate in the circuit region and the impurity region in the pad region.

2. The image sensor device according to claim 1, further comprising: A conductive film is provided at the first surface of the substrate to cover a top surface of the substrate at a lower portion of the pad.

3. The image sensor device according to claim 2, wherein: The conductive film is formed to be larger than the pad in a second direction perpendicular to the first direction.

4. The image sensor device according to claim 2, wherein: The conductive film is formed in the grooves exposing a plurality of regions of the substrate.

5. The image sensor device according to claim 4, wherein: The pad is formed along a top surface and a side surface of the conductive film.

6. The image sensor device according to claim 2, further comprising: A through silicon via is disposed on one side of the substrate and is configured to penetrate the substrate in the first direction.

7. The image sensor device according to claim 6, wherein: The through silicon via is electrically coupled to the pad through the conductive film.

8. The image sensor device according to claim 1, wherein: The impurity region is formed as a stacked structure of a plurality of impurity layers including the second conductive impurity.

9. The image sensor device according to claim 8, wherein: At least one of the plurality of impurity layers is formed as a deep well.

10. The image sensor device according to claim 8, wherein: The plurality of impurity layers are formed to have the same size in a second direction perpendicular to the first direction.

11. The image sensor device according to claim 8, wherein: The plurality of impurity layers are formed to be larger than the pad in a second direction perpendicular to the first direction.

12. The image sensor device according to claim 8, wherein: At least one of the plurality of impurity layers is formed by implanting the second conductive impurity through the second surface in an impurity implantation process for implanting impurities into a circuit region.

13. The image sensor device according to claim 8, wherein: At least one of the plurality of impurity layers is formed by implanting the second conductive impurity through the first surface in an impurity implantation process for implanting impurities into a pixel region.

14. The image sensor device according to claim 1, wherein: The impurity region includes: a first impurity layer formed in the substrate; and A second impurity layer is stacked over the first impurity layer and is configured to have the same conductive impurities as those of the first impurity layer.

15. The image sensor device according to claim 14, wherein: The impurity region also includes: A third impurity layer is stacked over the second impurity layer and is configured to have the same conductive impurities as those of the second impurity layer.

16. The image sensor device according to claim 1, wherein: applying a first well bias to the substrate; and A second well bias having a voltage level different from that of the first well bias is applied to the impurity region.

17. An image sensor device, the image sensor device comprising: a substrate including a first surface and a second surface, the substrate being configured to have a first conductive impurity; A pad, the pad being arranged on the first surface of the substrate; a circuit area, the circuit area being arranged adjacent to the pad; as well as an impurity region including a second conductive impurity different from the first conductive impurity, and the impurity region is disposed at both ends of the pad in the substrate relative to a first direction, the first direction being parallel to the substrate, The impurity region and the substrate formed in the circuit region are in contact with each other through a boundary region, and parasitic capacitance occurs in the boundary region between the impurity region and the substrate in the circuit region.

18. The image sensor device according to claim 17, wherein: The impurity region is formed to be smaller than the pad in the first direction.

19. An image sensor device, the image sensor device comprising: a substrate in which a pad region and a circuit region adjacent to the pad region are defined, and the substrate is configured to include a first conductive impurity; a pad disposed at the first surface of the substrate in the pad region; as well as an impurity region, the impurity region being formed below the pad in the pad region, the impurity region being configured to have a second conductive impurity different from the first conductive impurity and being formed in the substrate, The substrate formed in the circuit region and the impurity region formed in the pad region are in contact with each other through a boundary region, and parasitic capacitance occurs in the boundary region between the impurity region and the substrate in the circuit region.

20. The image sensor device according to claim 19, wherein: The impurity region is formed as a stacked structure of a plurality of impurity layers including the second conductive impurity.

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