LDMOS device and LED driver chip

Abstract

An LDMOS device and an LED driver chip. In the LDMOS device, a field oxide layer is disposed on the upper surface of the drift region, and a resistor bar is disposed on the upper surface of the field oxide layer. The resistor bar is not in contact with the drift region. The first end of the resistor bar is connected to the drain electrode, and the second end of the resistor bar is close to the source electrode of the LDMOS device. Thus, while integrating the resistor bar in the LDMOS device, the influence of the resistor bar on the drift region is avoided, the electric field distribution at each point in the drift region is ensured to be uniform, the reduction of the breakdown voltage of the LDMOS is avoided, and the problem in the traditional technical solution that an LDMOS device integrating a drift region resistor cannot be provided is solved. The LED driver chip integrates a constant power circuit and an LDMOS device with an internal resistor, saving the space of the LED driver chip and the system where it is located while achieving constant power regulation of the light source.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to an LDMOS device and an LED driving chip. Background Art

[0002] At present, in order to enable the LED lamp to maintain a stable brightness when the grid voltage fluctuates, in recent years, a load constant power function has been added to the design of linear LED driving chips. When the grid voltage becomes higher, the drain voltages of the LED lamp and the LDMOS (Laterally Diffused Metal Oxide Semiconductor) device will both increase. At this time, through a resistor at the drain end of the LDMOS device, the drain voltage is fed back to the pre-stage circuit. After processing, the gate voltage of the LDMOS is adjusted downwards, so that the current of the LED lamp decreases and the power of the LED lamp is kept constant. However, the existing technical solutions generally achieve this by externally connecting a resistor to the LDMOS device.

[0003] Therefore, in the traditional technical solution, there is a problem that an LDMOS device integrating a drift region resistor cannot be provided. Summary of the Invention

[0004] The purpose of this application is to provide an LDMOS device and an LED driving chip, aiming to solve the problem in the traditional technical solution that an LDMOS device integrating a drift region resistor cannot be provided.

[0005] The first aspect of the embodiment of this application provides an LDMOS device, including:

[0006] A semiconductor substrate, and a drift region formed on the upper surface of the semiconductor substrate;

[0007] A field oxide layer, which is arranged on the upper surface of the drift region; and

[0008] A resistor bar, which is arranged on the upper surface of the middle section of the field oxide layer. The first end of the resistor bar is connected to the drain electrode of the device and the drain electrode of the LDMOS device, and the second end of the resistor bar is close to the source electrode of the LDMOS device.

[0009] In one embodiment, it further includes:

[0010] An insulating layer provided with a plurality of through holes, which is arranged on the upper surfaces of the two end sections of the field oxide layer and the upper surface of the resistor bar. The first end of the resistor bar is connected to the drain electrode through the conductive material in the first through hole of the insulating layer.

[0011] In one embodiment, it further includes:

[0012] A contact layer, which is disposed on the upper surface of the insulating layer, and the contact layer is connected to the second end of the resistor bar through the conductive material in the second through hole of the insulating layer.

[0013] In one embodiment, the drift region includes an arc drift region and a straight drift region, and the resistor bar is disposed above the arc drift region or above the straight drift region.

[0014] In one embodiment, it includes: the shape of the resistor bar is straight, serpentine, zigzag or spiral.

[0015] In one embodiment, the material of the resistor bar is polysilicon, and the doping type of the resistor bar is P-type or N-type.

[0016] In one embodiment, it further includes:

[0017] A first doping region, which is of a second conductivity type different from the first conductivity type, and the first doping region is formed on the upper surface of the drift region and is in contact with the field oxide layer;

[0018] A second doping region, which is of the first conductivity type, and the second doping region is formed on the upper surface of the drift region at intervals with the first doping region and is offset relative to the field oxide layer;

[0019] The first end of the resistor bar is disposed above the region between the first doping region and the second doping region.

[0020] In one embodiment, it further includes:

[0021] A well region of the second conductivity type, which is formed on the upper surface of the semiconductor substrate and is adjacent to the drift region along a first direction;

[0022] A third doping region of the first conductivity type, which is disposed on the upper surface of the well region; and

[0023] A fourth doping region of the second conductivity type, which is disposed on the upper surface of the well region and is adjacent to the third doping region along the first direction, and a PN junction is formed between the third doping region and the fourth doping region, and the PN junction is connected to the source electrode through the conductive material in the third through hole of the insulating layer.

[0024] In one embodiment, it further includes: a polysilicon gate, which is disposed above the well region and the drift region, the polysilicon gate is connected to the gate electrode through the conductive material in the fourth through hole of the insulating layer, and the polysilicon gate is electrically connected to the field oxide layer.

[0025] The above-mentioned LDMOS device arranges the field oxide layer on the upper surface of the drift region and arranges the resistor bar on the upper surface of the field oxide layer. The resistor bar does not contact the drift region, and connects the first end of the resistor bar to the drain electrode. Thus, while integrating the resistor bar in the LDMOS device, the influence of the resistor bar on the drift region is avoided, ensuring uniform electric field distribution at each point in the drift region, avoiding the reduction of the breakdown voltage between the drain and source of the LDMOS, and solving the problem in the traditional technical solution that it is impossible to provide an LDMOS device integrating a drift region resistor.

[0026] The second aspect of the embodiments of the present application provides an LED driving chip, including:

[0027] A constant power circuit for outputting a driving signal with a constant power; and

[0028] For the LDMOS device as claimed in claim 9, the drain electrode of the LDMOS device is used to connect to a light source, the contact layer of the LDMOS device is connected to the input end of the constant power circuit, the gate electrode of the LDMOS device is connected to the output end of the constant power circuit, and the source electrode of the LDMOS device is used for grounding.

[0029] In the above-mentioned LED driving chip, by adding a constant power circuit and an LDMOS device with an internally integrated resistor bar, when the supply voltage of the light source becomes higher due to the fluctuation of the input voltage and the light source voltage and the drain electrode voltage of the LDMOS device are raised, at this time, the contact layer of the LDMOS device feeds back the drain electrode voltage of the LDMOS device to the constant power circuit, and then reduces the gate voltage of the LDMOS device, thereby reducing the light source current, and further making the power of the light source constant. That is, the resistor bar built in the LDMOS device can be used as a sampling resistor. That is, the LED driving chip in this embodiment realizes the constant power regulation of the light source by the built-in resistor, and saves the space of the LED driving chip and the system where it is located. Description of the Drawings

[0030] Figure 1 It is a schematic structural diagram of the second direction of the LDMOS device provided by an embodiment of the present application;

[0031] Figure 2-a It is Figure 1 The schematic structural diagram of the first direction of the LDMOS device shown;

[0032] Figure 2-b It is Figure 1 The schematic structural diagram of the first direction of the LDMOS device shown;

[0033] Figure 3-a It is Figure 1Schematic diagram of the first-direction structure of the resistor bar of the LDMOS device shown;

[0034] Figure 3-b is Figure 1 Schematic diagram of the first-direction structure of the resistor bar of the LDMOS device shown;

[0035] Figure 3-c is Figure 1 Schematic diagram of the first-direction structure of the resistor bar of the LDMOS device shown;

[0036] Figure 3-d is Figure 1 Schematic diagram of the first-direction structure of the resistor bar of the LDMOS device shown;

[0037] Figure 4 is Figure 1 Schematic diagram of the second-direction structure of the LDMOS device shown;

[0038] Figure 5 Schematic diagram of the circuit structure of the LED driving chip provided by an embodiment of the present application. Detailed implementation manners

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0041] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0042] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more, unless otherwise specifically defined.

[0043] Figure 1 FIG. 4 shows a schematic structural diagram of the second direction of the LDMOS device provided by the embodiment of the present application. For the convenience of description, only the parts related to this embodiment are shown and are described in detail as follows:

[0044] The LDMOS device in this embodiment includes: a semiconductor substrate 10, a drift region 11, a field oxide layer 17, and a resistor bar 18; the drift region 11 is formed on the upper surface of the semiconductor substrate 10; the field oxide layer 17 is disposed on the upper surface of the drift region 11; the resistor bar 18 is disposed on the upper surface of the middle section of the field oxide layer 17. The first end of the resistor bar 18 is connected to the drain electrode 34 of the device, and the second end of the resistor bar 18 is close to the source electrode of the LDMOS transistor device.

[0045] The drift region 11 is of the first conductivity type (for example, N-type). Specifically, the ions doped in the drift region 11 are N-ions; when viewed in the direction perpendicular to the upper surface of the semiconductor substrate 10, the length of the resistor bar 18 is less than the length of the field oxide layer 17, and the length of the field oxide layer 17 is less than the length of the drift region 11. It should be understood that the first end of the resistor bar 18 is close to the drain end of the LDMOS and is connected to the drain electrode 34, and the second end of the resistor bar 18 is close to the source electrode of the LDMOS device. Specifically, the second end of the resistor bar 18 is led out from a position above the LDMOS source. The LDMOS source in this embodiment is the regions shown in FIGS. 15 and 16. It should be understood that the second end of the resistor bar 18 is far from the first end of the resistor bar 18, that is, the first end and the second end of the resistor bar 18 are the two opposite ends of the resistor bar 18 in the same direction, and the first end of the resistor bar 18 is far from the source electrode of the LDMOS device.

[0046] The semiconductor substrate 10 may be a P-type substrate; alternatively, the semiconductor substrate 10 may be a compound semiconductor substrate 10. Specifically, the compound semiconductor substrate 10 includes a bulk substrate (for example, a P-type substrate), an oxygen-doped crystalline semiconductor layer, and an insulating layer 20. The oxygen-doped crystalline semiconductor layer is configured as a rich well layer, and the oxygen-doped crystalline semiconductor layer includes one or more crystalline materials configured to capture carriers. The crystalline materials may include polycrystalline semiconductor materials (for example, polysilicon).

[0047] In the LDMOS device of this embodiment, by disposing the field oxide layer 17 on the upper surface of the drift region 11, disposing the resistor bar 18 on the upper surface of the field oxide layer 17, and connecting the first end of the resistor bar 18 to the drain electrode 34 of the device, and the second end of the resistor bar 18 being close to the source of the LDMOS device, the integration of the resistor bar 18 in the LDMOS device is achieved, and the influence of the resistor bar 18 on the drift region 11 is avoided. Because the potentials of points on the drift region 11 are synchronized with the underlying LDMOS device, when a high voltage is applied to the resistor bar 18, the resistor bar 18 will not change the potential and electric field distribution of the underlying LDMOS device through the field oxide layer 17, avoiding the influence of the resistor bar 18 on the drift region 11, ensuring uniform electric field distribution at each point in the drift region 11, avoiding a decrease in the breakdown voltage of the LDMOS, and solving the problem in the traditional technical solution that an LDMOS device integrating a drift region resistor cannot be provided.

[0048] Please refer to Figure 1 , in one embodiment, the LDMOS device further includes: an insulating layer 20 provided with a plurality of through holes, the insulating layer 20 is disposed on the upper surfaces of the two end sections of the field oxide layer 17 and the upper surface of the resistor bar 18, and the first end 18-1 of the resistor bar 18 is connected to the drain electrode 34 through the conductive material filled in the first through hole 21 of the insulating layer 20.

[0049] The conductive material can be metal or other conductive materials; the insulating layer 20 is used to insulate the area it covers from the remaining area or the outside world, and through holes are opened in the insulating layer 20 to ensure electrical connection between the areas at both ends of the through holes. The insulating layer 20 can be divided into any number of sub-regions or sub-layers, and the sub-regions and sub-layers can be of any geometric shape adapted to the area or device they cover. The insulating layer 20 can be composed of an insulating dielectric material.

[0050] In this embodiment, by designing the position of the resistor bar 18, the first end of the resistor bar 18 is close to the drain end of the LDMOS and is connected to 34, and the second end of the resistor bar 18 is close to the source end of the LDMOS, avoiding the influence of the resistor bar 18 on the potential and electric field distribution below the field oxide layer 17.

[0051] Please refer to Figure 1 , in one embodiment, the LDMOS device further includes: a contact layer 33, the contact layer 33 is disposed on the upper surface of the insulating layer 20, and the contact layer 33 is connected to the second end 18-2 of the resistor bar 18 through the second through hole 22 of the insulating layer 20.

[0052] Optionally, the contact layer 33 includes a metal plate, and the contact layer 33 is used as the sampling current output end of the LDMOS transistor, that is, the contact layer 33 is used to output the current flowing through the second end 18-2 of the resistor bar 18 to an external connecting device.

[0053] Please refer to Figure 2-a and Figure 2-b , in one embodiment, the drift region 11 includes an arc drift region 17-2 and a straight drift region 17-1, and the resistor bar 18 is disposed above the arc drift region 17-2 or above the straight drift region 17-1.

[0054] It should be understood that, along a first direction parallel to the upper surface of the semiconductor substrate 10, looking down from above, the resistor bar 18 is disposed above the arc drift region 17-2 or above the straight drift region 17-1, and a first end 18-1 of the resistor bar 18 is connected to the drain electrode 34 of the device, and a second end 18-2 of the resistor bar 18 is close to the source (15-16) of the device, but is not connected to the source of the device.

[0055] In one embodiment, it further includes: the current direction of the resistor bar 18 is from the first end 18-1 of the resistor bar 18 to the second end.

[0056] It should be understood that the first end 18-1 of the resistor bar 18 is the high-potential end of the resistor bar 18, and the second end 18-2 of the resistor bar 18 is the low-potential end of the resistor bar 18. Optionally, the resistance value of the resistor bar 18 in this embodiment can be set to a high resistance value, such as 1 Mohm, so as to ensure that the static power consumption of the LDMOS device is a normal value.

[0057] Please refer to Figure 3-a , 3-b , 3-c, 3-d, in one embodiment, it further includes: the shape of the resistor bar 18 is a straight bar shape ( Figure 3-a ), a serpentine shape ( Figure 3-b ), a zigzag shape ( Figure 3-c ) or a spiral shape ( Figure 3-d ).

[0058] It should be understood that the Figure 3-a , 3-b , 3-c, 3-d only give one example case under the corresponding shape, and the specific size ratio, number of turns of the loop, etc. are not unique.

[0059] In one embodiment, the doping type of the resistor bar 18 is a first conduction type (N-type) or a second conduction type (P-type). Optionally, the material of the resistor bar 18 can be a polysilicon material, that is, the resistor bar 18 can be P-type Poly (Polysilicon) or N-type Poly.

[0060] Please refer to Figure 4, in one embodiment, it further includes: a first doping region 13 and a second doping region 14. The first doping region 13 is formed on the upper surface of the drift region 11 and is adjacent to the field oxide layer 17; the second doping region 14 is formed on the upper surface of the drift region 17 at an interval from the first doping region 13 and is offset relative to the field oxide layer 17; the first end of the resistor bar 18 is disposed above the region between the first doping region 13 and the second doping region 14.

[0061] The first doping region 13 is of a second conduction type (P type) different from the first conduction type (N type). Specifically, the first doping region 13 is a Ptop layer, so that the LDMOS device in this embodiment can be used as an ultra-high voltage LDMOS device; the second doping region 14 is of the first conduction type (N type). Specifically, the ions doped in the second doping region 14 are N+.

[0062] It should be understood that the first doping region 13 is located between the drift region 11 and the field oxide layer 17, the second doping region 14 is disposed adjacent to the field oxide layer 17 and is located below the field oxide layer 17, and the upper surface of the second doping region 14 is on the same plane as the upper surface of the first doping region 13; the first end 18-1 of the resistor bar 18 is disposed between the first doping region 13 and the second doping region 14 and is located above the first doping region 13 and the second doping region 14. It should be understood that ions of the second conduction type are doped above the drift region 11 by photolithography and ion implantation to form the first doping region 13, and the upper surface of the first doping region 13 is covered by the field oxide layer 17; ions of the first conduction type are doped above the drift region 11 by photolithography and ion implantation to form the second doping region 14. The second doping region 14 serves as the source electrode 31 of the LDMOS device. The upper surface of the second doping region 14 is covered by the insulating layer 20, and a through hole 26 is formed in the insulating layer 20, so that the second doping region 14 is connected to the drain electrode 34 through the conductive material filled in the through hole 26.

[0063] Please refer to Figure 4 , in one embodiment, it further includes: a well region 12 of the second conduction type, a third doping region 15 of the first conduction type, and a fourth doping region 16 of the second conduction type; the well region 12 is formed on the upper surface of the semiconductor substrate 10 and is disposed adjacent to the drift region along the first direction; the third doping region 15 is disposed on the upper surface of the well region 12, the fourth doping region 16 is disposed on the upper surface of the well region 12 and is adjacent to the third doping region 15 along the first direction. A PN junction is formed between the third doping region 15 and the fourth doping region 16, and the PN junction is connected to the source electrode 31 through the conductive material filled in the third through hole 23 of the insulating layer 20.

[0064] It should be understood that the upper surfaces of the third doping region 15 and the fourth doping region 16 in this embodiment are covered by the insulating layer 20, so as to be insulated from the devices above, and through the third through hole 23 opened in the insulating layer 20, the electrical connection with the source electrode 31 is realized, ensuring that in the second direction, the PN junction can be connected to the source electrode 31 through the conductive material filled in the third through hole 23 of the insulating layer 20 and insulated from the other electrodes.

[0065] It should be understood that the PN junction (the third doping region 15 and the fourth doping region 16) in this embodiment forms the source of the LDMOS device. The first end of the third through hole 23 is located at the center of the upper surface of the PN junction, and the other end of the third through hole 23 is located at the source electrode 31, and the source electrode 31 includes a conductive metal plate.

[0066] Please refer to Figure 4 , in one embodiment, it further includes a polysilicon gate 19, the polysilicon gate 19 is arranged above the well region 12 and the drift region 11, the polysilicon gate 19 is connected to the gate electrode 32 through the conductive material of the fourth through hole 24 of the insulating layer 20, and a part of the polysilicon gate 19 is located above the field oxide layer 17.

[0067] Optionally, the forming process of the resistor bar 18 is the same as that of the polysilicon gate, and the resistor bar 18 can be formed simultaneously with the polysilicon gate.

[0068] Optionally, the following is an example to illustrate the manufacturing process of an LDMOS device:

[0069] The drift region 11 and the well region 12 are formed on the upper surface of the semiconductor substrate 10 by photolithography and ion implantation, and the drift region 11 and the well region 12 are arranged adjacent to each other;

[0070] The first doping region 13 (Ptop layer, the second conduction type) is formed on the upper surface of the drift region 11;

[0071] The field oxide layer 17 is formed on the upper surface of the first doping region 13, the field oxide layer 17 is opposite to the first doping region 13, the field oxide layer 17 is opposite to the second doping region 14, and in the first direction, the length of the field oxide layer 17 is greater than the length of the first doping region 13 and less than the length of the drift region;

[0072] The gate oxide layer is grown above the center line of the drift region 11 and the well region 12 and close to one end of the field oxide layer 17;

[0073] The resistor bar 18 is arranged on the upper surface of the field oxide layer 17, and the gate is arranged on the upper surface of the gate oxide layer. The resistor bar 18 and the gate are made of the same material, such as polysilicon;

[0074] A second doped region 14 (first conduction type) is formed on the upper surface of the drift region 11. The first doped region 13 and the second doped region 14 are arranged at intervals, and the second doped region 14 serves as the drain of the LDMOS device; a third doped region 15 and a fourth doped region 16 are formed on the upper surface of the well region 12. The third doped region 15 and the fourth doped region 16 are adjacent to each other in the first direction and thus form a PN junction, and this PN junction serves as the source of the LDMOS device;

[0075] An insulating layer 20 is covered above the above-mentioned stacked structure, and a plurality of through holes are opened in the insulating layer 20, and conductive substances are filled in the respective through holes for connecting the first end 18-1 of the resistor bar 18 and the drain electrode 34, the second end 18-2 of the resistor bar 18 and the contact layer 33, the second doped region 14 and the drain electrode 34, the gate and the gate electrode 32, and the source and the source electrode 31 respectively. Among them, the drain electrode 34, the contact layer 33, the gate electrode 32, and the source electrode 31 are all arranged on the upper surface of the insulating layer 20.

[0076] Please refer to Figure 5 , a second aspect in the embodiments of the present invention provides an LED driving chip, including: a constant power circuit 200 and an LDMOS device as in the first aspect of this embodiment. The constant power circuit 200 is used to output a driving signal with a constant power; the drain electrode 34 of the LDMOS device is used to connect to the light source 300, the contact layer 33 of the LDMOS device is connected to the input end of the constant power circuit 200, the gate electrode 32 of the LDMOS device is connected to the output end of the constant power circuit 200, and the source electrode 31 of the LDMOS device is used for grounding.

[0077] It should be understood that the constant power circuit 200 in this embodiment can be composed of a constant power chip, such as the constant power LED driving chip SM2510p. In other embodiments, other models of constant power chips can also be used; the light source 300 can be an LED lamp or a lamp string composed of multiple LEDs, and the light source 300 is powered by the grid voltage or other power sources.

[0078] In the LED driving chip of this embodiment, by adding a constant power circuit 200 and an LDMOS device with a resistor bar 18 integrated therein, when the supply voltage VIN of the light source 300 becomes higher due to the fluctuation of the input voltage, and the voltage of the light source 300 and the drain electrode 34 voltage of the LDMOS device are elevated, at this time, the contact layer 33 of the LDMOS device feeds back the drain electrode 34 voltage of the LDMOS device to the constant power circuit 200, and then reduces the gate voltage of the LDMOS device, thereby reducing the current of the light source 300, and further making the power of the light source 300 constant. That is, the resistor bar 18 built into the LDMOS device can be used as a sampling resistor. That is, the LED driving chip in this embodiment realizes the constant power regulation of the light source 300 by building in a sampling resistor, and saves the space of the LED driving chip and the system where it is located.

[0079] It should be understood that the first conduction type in the embodiments of the present invention is N-type, and the second conduction type is P-type. In other embodiments, the first conduction type may be P-type and the second conduction type may be N-type; the first direction in this embodiment is the direction parallel to the upper surface of the semiconductor substrate 10, and the second direction is the direction perpendicular to the upper surface of the semiconductor substrate 10. The descriptions of above, below, upper surface, etc. in this embodiment are the up and down directions viewed in the second direction.

[0080] The above-described embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An LDMOS device, characterized in that, Comprising: A semiconductor substrate, a drift region formed on the upper surface of the semiconductor substrate; A field oxide layer, the field oxide layer disposed on the upper surface of the drift region; And A resistor bar, the resistor bar disposed on the upper surface of the middle section of the field oxide layer, a first end of the resistor bar connected to the drain electrode of the LDMOS device, and a second end of the resistor bar close to the source electrode of the LDMOS device; Further comprising: A first doped region, the first doped region being of a second conductivity type different from the first conductivity type, the first doped region formed on the upper surface of the drift region and in contact with the field oxide layer; A second doped region, the second doped region being of the first conductivity type, the second doped region formed on the upper surface of the drift region at an interval from the first doped region and offset relative to the field oxide layer; the second doped region is adjacent to the field oxide layer and located below the field oxide layer, and the upper surface of the second doped region is in the same plane as the upper surface of the first doped region; The first end of the resistor bar is disposed above the region between the first doped region and the second doped region.

2. The LDMOS device according to claim 1, characterized in that, Further comprising: An insulating layer provided with a plurality of through holes, the insulating layer disposed on the upper surfaces of the two end sections of the field oxide layer and the upper surface of the resistor bar, and the first end of the resistor bar is connected to the drain electrode through the conductive material in the first through hole of the insulating layer.

3. The LDMOS device according to claim 2, characterized in that, Further comprising: A contact layer, the contact layer disposed on the upper surface of the insulating layer, and the contact layer is connected to the second end of the resistor bar through the conductive material in the second through hole of the insulating layer.

4. The LDMOS device according to claim 1, characterized in that, Comprising: The drift region includes an arc drift region and a straight drift region, and the resistor bar is disposed above the arc drift region or above the straight drift region.

5. The LDMOS device according to any one of claims 1-4, characterized in that, Comprising: The shape of the resistor bar is straight, serpentine, serrated or spiral.

6. The LDMOS device according to any one of claims 1-4, characterized in that, Comprising: The material of the resistor bar is polysilicon, and the doping type of the resistor bar is P-type or N-type.

7. The LDMOS device according to claim 3, characterized in that, Further comprising: A well region of the second conductivity type, the well region formed on the upper surface of the semiconductor substrate and disposed adjacent to the drift region along a first direction; A third doped region of the first conductivity type, the third doped region disposed on the upper surface of the well region; And A fourth doped region of the second conductivity type, the fourth doped region disposed on the upper surface of the well region and adjacent to the third doped region along the first direction, a PN junction is formed between the third doped region and the fourth doped region, and the PN junction is connected to the source electrode through the conductive material in the third through hole of the insulating layer.

8. The LDMOS device according to claim 7, characterized in that, Further comprising: polysilicon A gate, the polysilicon gate disposed above the well region and the drift region, and the polysilicon gate is connected to the gate electrode through the conductive material in the fourth through hole of the insulating layer.

9. An LED driving chip, characterized in that, Comprising: A constant power circuit, the constant power circuit for outputting a driving signal of constant power; And The LDMOS device according to claim 8, wherein the drain electrode of the LDMOS device is used to connect to a light source, the contact layer of the LDMOS device is connected to the input end of the constant power circuit, the gate electrode of the LDMOS device is connected to the output end of the constant power circuit, and the source electrode of the LDMOS device is used for grounding.

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