Wire Flex Control for Memory Applications

Abstract

A method for reducing word line flexure in a memory cell comprises: a) providing a substrate comprising a plurality of word lines, the plurality of word lines being arranged adjacent to each other and above a plurality of transistors; b) depositing a film layer on the plurality of word lines using a deposition process; c) measuring the word line flexure after depositing the film layer; d) comparing the word line flexure with a predetermined range; e) adjusting at least one of a nucleation delay and a grain size of the deposition process based on the word line flexure; and f) repeating (b) to (e) one or more times using one or more substrates, respectively, until the word line flexure is within the predetermined range.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 773,689, filed on November 30, 2018. The entire disclosure of the above-referenced application is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to substrate processing systems and, more particularly, to methods of controlling wire deflection in memory applications. Background Art

[0004] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed.

[0005] Electronic devices such as laptops, tablets, smartphones, etc. contain memory such as dynamic random access memory (DRAM) or vertical NAND (VNAND) memory. Memory is generally implemented by an integrated circuit (IC) containing memory cells. As electronic devices continue to shrink in size and use more data, the cost, density, and access speed of memory cells become increasingly important. As a result, feature sizes have shrunk significantly and aspect ratios have increased.

[0006] Substrate processing systems for performing deposition and / or etching on substrates such as semiconductor wafers generally include a processing chamber having a pedestal. The substrate is disposed on the pedestal during processing. A processing gas mixture containing one or more precursors may be introduced into the processing chamber to deposit a layer on the substrate or to etch the substrate. In some substrate processing systems, a radio frequency (RF) plasma may be ignited in the processing chamber and / or an RF bias on the pedestal may be used to activate a chemical reaction. Summary of the invention

[0007] A method for reducing word line flexure in a memory cell comprises: a) providing a substrate comprising a plurality of word lines, the plurality of word lines being arranged adjacent to each other and above a plurality of transistors; b) depositing a film layer on the plurality of word lines using a deposition process; c) measuring the word line flexure after depositing the film layer; d) comparing the word line flexure with a predetermined range; e) adjusting at least one of a nucleation delay and a grain size of the deposition process based on the word line flexure; and f) repeating (b) to (e) one or more times using one or more substrates, respectively, until the word line flexure is within the predetermined range.

[0008] In other features, (e) includes adjusting at least one of a temperature and a pressure of the deposition process to adjust the nucleation delay. The film layer is selected from the group consisting of molybdenum, tungsten, ruthenium, and cobalt.

[0009] In other features, the method further includes configuring a liner layer between the plurality of word lines and the membrane layer. The liner layer comprises titanium nitride. The temperature of the deposition process is adjusted in e). The pressure of the deposition process is adjusted in e). The temperature and the pressure of the deposition process are adjusted in e). The temperature of the deposition process is reduced in e) to increase the nucleation delay. The pressure of the deposition process is reduced in e) to increase the nucleation delay. The temperature and the pressure of the deposition process are reduced in e) to increase the nucleation delay.

[0010] In other features, (e) includes: if the word line deflection is greater than the predetermined range, increasing the nucleation delay. In other features, (e) includes: if the word line deflection is less than the predetermined range, decreasing the nucleation delay.

[0011] In other features, (e) includes: using an inhibitor substance to adjust the nucleation delay. The inhibitor substance is selected from the group consisting of molecular nitrogen and ammonia. The concentration of the inhibitor substance is increased in (e) to increase the nucleation delay. The exposure time of the inhibitor substance is increased in (e) to increase the nucleation delay. The concentration and exposure time of the inhibitor substance are increased in (e) to increase the nucleation delay.

[0012] In other features, (e) includes adjusting precursor chemistry or changing a mixture of precursors to adjust the nucleation delay. In other features, (e) includes using at least one of temperature and pressure to control grain size.

[0013] In other features, (e) includes using impurities to control grain size. In other features, (e) includes using in-situ gases to control grain size and film roughness.

[0014] Further scope of applicability of the present disclosure will become apparent from the detailed description, claims and drawings.The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present disclosure will be more fully understood from the detailed description and accompanying drawings, in which:

[0016] Figures 1 to 5 is a side cross-sectional view of an example of a substrate including a word line of a memory cell, deposition of a layer on the word line, and flexure of the word line;

[0017] Figures 6 to 10 is a side cross-sectional view of an example of a substrate including a word line of a memory cell and a deposition of a layer on the word line wherein deflection of the word line is significantly reduced according to the present disclosure;

[0018] Fig.11 is a flow chart of an exemplary method for reducing wordline deflection when depositing a layer on the wordline;

[0019] Fig. 12A is a graph depicting the variation of Mo thickness with ALD cycles at different temperatures;

[0020] Fig. 12B It is a graph depicting the variation of molybdenum resistivity with thickness at different temperatures;

[0021] Fig.13A is a graph depicting the variation of Mo thickness with ALD cycles at different pressures; and

[0022] Fig. 13B It is a graph depicting the change of molybdenum resistivity with thickness at different pressures.

[0023] Among the drawings, reference numerals may be repeated to identify similar and / or identical elements. DETAILED DESCRIPTION

[0024] The substrate processing system can be used to manufacture integrated circuits such as memories including multiple memory cells. As aspect ratios increase and critical dimensions decrease, problems may arise during the manufacturing process. For example, high aspect ratio features such as word lines in VNAND and DRAM memory cells may experience flexure during film deposition on the word lines. The flexure may cause various problems such as alignment of the word lines relative to other features, performance variations, and / or other defects.

[0025] The present disclosure relates to methods for reducing the deflection of high aspect ratio features of a substrate during film deposition. For example, the method can be used to reduce the deflection of adjacent word lines in memory cells such as VNAND and DRAM. Line deflection occurs due to stress and cohesion of materials during film deposition (metal / dielectric).

[0026] The method includes adjusting the nucleation delay of the deposition process to control word line deflection. For example, the method includes selecting process parameters for film deposition. Process parameters such as temperature and pressure are generally optimized to provide a smooth film with a small grain size and low nucleation delay. However, in the case of small feature sizes and high aspect ratios, line deflection occurs when depositing a smooth film.

[0027] Methods according to the present disclosure include: selecting deposition process parameters, depositing a film, and measuring wire deflection. In some examples, if the wire deflection is outside a predetermined range, adjusting (e.g., reducing) the temperature and / or pressure to delay nucleation and increase grain size to provide a rougher film. In some examples, the temperature is adjusted within a range from 300° C. to 700° C. In some examples, the pressure is adjusted within a range from 5 Torr to 80 Torr.

[0028] The film is deposited in this manner, reducing line deflection at the expense of fill. The deposition process is repeated at new temperature and pressure values ​​and the line deflection is measured. The process is repeated until the line deflection is within a predetermined tolerance. In some examples, the method according to the present disclosure can significantly reduce the line deflection of word lines in memory devices such as VNAND and DRAM memory cells.

[0029] Reference now Figures 1 to 5 , shows an example of word line deflection during layer deposition. Figure 1 In the embodiment of the present invention, substrate 100 includes an underlying layer 114 (including transistors) and a plurality of word lines 112. In some examples, the plurality of word lines 112 are part of a memory cell such as a DRAM memory cell, which includes a capacitor and a transistor. The plurality of word lines provide connections to the gates of the transistors. The plurality of word lines 112 control the flow of current in the transistor channels. In some examples, a liner layer 113 is configured on the plurality of word lines 112 as a barrier layer prior to metal deposition. By way of example only, the liner layer 113 may be made of titanium nitride (TiN). In some examples, the plurality of word lines 112 may include an outer layer 118 made of a dielectric such as SiO2 and an inner layer 119 made of a material such as silicon (Si). Figure 1 The adjacent word line 120 is shown in dashed lines in FIG. 1 , but omitted elsewhere for clarity), but other configurations may be used.

[0030] The spacing between the plurality of word lines 112 is predefined. For example, the plurality of word lines 112 may be fabricated to have a uniform spacing d1 between the plurality of word lines 112. In other examples, different spacings may be defined between some of the plurality of word lines 112. It is generally desirable to maintain the predefined spacing between the plurality of word lines 112 after additional processing to maintain alignment with other features, thereby preventing short circuits and / or maintaining performance parameters such as resistance and / or capacitance.

[0031] exist Figure 2In some examples, layer 116 is deposited to fill the gaps between the plurality of word lines 112. In some examples, layer 116 includes tungsten (W), ruthenium (Ru), cobalt (Co), or molybdenum (Mo). In some examples, liner layer 113 and layer 116 are deposited using atomic layer deposition (ALD). In other examples, chemical vapor deposition (CVD) or other deposition processes are used. In some examples, plasma may be used to enhance chemical reactions during the deposition process. In some examples, deposition process parameters for layer 116 are selected to produce the following features: layer 116 is conformal and has low nucleation delay and small grain size. In other words, it is generally desirable to deposit a smooth film rather than a rougher film on the plurality of word lines 112. In some examples, one or more liner layers may be deposited between layer 116 and the plurality of word lines 112.

[0032] exist Figure 3 In FIG. 1 , since layer 116 is deposited with these features, line bending may occur. Some of the plurality of word lines 112 bend toward an adjacent one of the plurality of word lines 112, while others of the plurality of word lines 112 bend away from an adjacent one of the plurality of word lines 112. Thus, the predefined spacing is no longer maintained. Figure 4 In the embodiment, additional deposition is performed to fill the gaps between the plurality of word lines 112 .

[0033] exist Figure 5 In the embodiment of the present invention, etching and / or other processes may be performed to expose the upper surface of the plurality of word lines 112 and / or the top surface of the material 119 (to allow contact). Additional layers (not shown) are deposited and contact the material 119. As can be seen, the distances d2 and d3 between adjacent ones of the plurality of word lines 112 are different from each other and from d1. When the additional layers are deposited, misalignment may occur. In addition, performance parameters such as resistance and capacitance may be adversely affected by the variation in spacing between the plurality of word lines 112.

[0034] Reference now Figures 6 to 10 , shows an example of a method for reducing word line deflection during layer deposition. Figure 6 In the embodiment of the present invention, substrate 600 includes an underlying layer 114 and a plurality of word lines 112. The spacing between the plurality of word lines 112 is predefined. For example, the plurality of word lines 112 are fabricated with uniform spacing d1 between the plurality of word lines 112. In other examples, different spacings may be defined between some of the plurality of word lines 112. It is generally desirable to maintain the predefined spacing between the plurality of word lines 112 after additional processing to maintain alignment with other features, thereby preventing short circuits and / or maintaining performance parameters such as resistance and / or capacitance.

[0035] exist Figure 7In some examples, layer 616 is deposited to fill the gaps between the plurality of word lines 112. In some examples, layer 616 is deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition processes. In some examples, plasma can be used to enhance chemical reactions during the deposition process. In some examples, deposition process parameters for layer 616 are selected to produce the following characteristics: layer 616 is conformal and has a high nucleation delay and a large grain size. As will be further described below, depositing a film using a high nucleation delay and a large grain size will result in rougher film characteristics, but will avoid line bending. In other words, the methods described herein violate the usual goal of depositing a smooth film on the plurality of word lines 112.

[0036] exist Figure 8 In , since layer 616 is deposited with these features, line deflection is significantly reduced. Fig. 9 In the embodiment, additional deposition is performed to fill the gaps between the plurality of word lines 112 .

[0037] exist Fig.10 In the embodiment, etching and / or another process may be performed to expose the upper surfaces of the plurality of word lines 112. Fig.10 As can be seen in FIG. 1 , additional layers (not shown) may be deposited on upper surface 1010 and may need to be aligned with the top surface of material 119. As can be seen, a predefined distance (e.g., d1 in this example) between adjacent ones of the plurality of word lines 112 is maintained. Thus, substantial alignment may be maintained as additional layers are deposited. Furthermore, performance parameters such as resistance and capacitance are not adversely affected by variations in spacing between the plurality of word lines 112 (as in FIG. 1 ). Figures 1 to 5 ).

[0038] Reference now Fig.11 , shows a method 1100 for reducing deflection of a feature such as a word line when depositing a layer over the feature. The method 1100 includes: at 1110, selecting process parameters for depositing a film. Generally, process parameters such as temperature and pressure are optimized to provide a smooth film with a small grain size and low nucleation delay. However, in the case of small feature sizes and high aspect ratios, line deflection may occur when depositing a smooth film.

[0039] After selecting the process parameters, the method includes depositing the film at 1114. At 1118, the wire deflection is measured and compared to a predetermined range. If the wire deflection is outside of the predetermined range, such as determined at 1118, the nucleation delay and / or grain size is adjusted. In some examples, the temperature or pressure used during the deposition process is changed as described herein, but other methods are described below.

[0040] For example, when the wire deflection is above a predetermined range, the pressure and / or temperature is reduced. The process is performed again with the adjustment at 1126. The method returns to 1118 and the wire deflection is measured again. The process can be repeated one or more times until the wire deflection is within the predetermined range as determined at 1118. In other words, the balance of film roughness and wire deflection can be optimized. When 1118 is true, the process is used to produce a substrate.

[0041] Reference now Fig. 12A and 12B , lowering the temperature during deposition increases nucleation delay, grain size, and film roughness. Thus, wordline deflection is reduced. Fig. 12A In FIG. 1 , the graph depicts the variation of platinum thickness with ALD cycles at different temperatures. In this example, the higher temperature corresponds to 590°C, while the lower temperature corresponds to 550°C. As can be seen, the nucleation delay at the lower temperature is increased relative to the higher temperature (from about 33 ALD cycles to about 62 ALD cycles in this example). The grain size and film roughness are also improved. In some examples, the word line deflection is reduced from 9.6nm to 1.7nm. ... Fig. 12B In the graph, the resistivity of molybdenum varies with thickness at different temperatures. The different temperatures have approximately the same resistance.

[0042] Reference Fig.13A and 13B , lowering the pressure during deposition increases nucleation delay, grain size, and film roughness. Thus, wordline deflection is reduced. Fig.13A In Figure 1, the graph depicts the change in platinum thickness over ALD cycles at different pressures. In this example, the higher pressure corresponds to 60 Torr and the lower pressure corresponds to 40 Torr. As can be seen, the nucleation delay at the lower pressure is increased relative to the higher pressure (from about 39 ALD cycles to about 59 ALD cycles in this example). The grain size and film roughness also increase. In some examples, the word line deflection is reduced from 9.9nm to 1.6nm. ... Fig. 13B In the graph, the resistivity of molybdenum varies with thickness at different pressures. The resistance is approximately the same at different pressures.

[0043] As can be appreciated, a combination of temperature and pressure changes can be used to increase nucleation delay, grain size, and roughness and reduce wire deflection.

[0044] Although the examples described above describe adjusting the nucleation delay by changing the temperature and / or pressure, there are other ways to adjust the nucleation delay. For example, the nucleation delay can be adjusted by selecting a different deposition process (atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma enhanced (PE) ALD), selecting a different conductor (molybdenum (Mo), tungsten (W), ruthenium (Ru), or cobalt (Co)) or a different precursor for the conductive layer, introducing impurities before or during the deposition process to change the grain size or nucleation delay, or using a surface treatment such as molecular nitrogen (N2) or ammonia (NH3) before deposition. The surface treatment may include the use of a plasma.

[0045] When using the ALD process, the precursor molecules need to be chemically adsorbed to the surface before film growth can begin. The surface contains limited nucleation sites where the precursor molecules can adsorb. When these sites are competitively blocked by molecules that can also adsorb to the surface but have little interaction with the precursor molecules, these sites are no longer available for precursor adsorption.

[0046] By varying the concentration of inhibitor molecules, the nucleation delay, and thus the film roughness and line deflection, can be controlled. Small nitrogen-containing molecules such as molecular nitrogen (N2) or ammonia (NH3) can be effective inhibitors. In other examples, larger nitrogen-containing molecules such as hydrazine or organic hydrazines can be used. Larger molecules are more effective as inhibitors due to the additional effect of steric hindrance.

[0047] Some of the examples described above start with a smooth film and reduce the temperature and / or pressure until a desired line deflection threshold is reached. In other examples, the method may initially be performed with a rougher film and the temperature and / or pressure may be increased until a desired amount of line deflection is reached. In other words, the desired tradeoff between line deflection and roughness may be determined from smooth to rough or from rough to less rough. For example, a predetermined threshold range may be used. The word line deflection is compared to a predetermined threshold range. If the word line deflection is less than the predetermined threshold range, the nucleation delay is reduced until the word line deflection is within the predetermined threshold range. If the word line deflection is greater than the predetermined threshold range, the nucleation delay is increased until the word line deflection is within the predetermined threshold range.

[0048] The foregoing description is merely illustrative in nature and is by no means intended to limit the present disclosure, its application or use. The broad teachings of the present disclosure can be implemented in various forms. Therefore, although the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited, because when studying the drawings, the specification and the appended claims, other modifications will become apparent. It should be understood that, without changing the principles of the present disclosure, one or more steps in the method can be performed in different orders (or simultaneously). In addition, although each embodiment is described above as having certain features, any one or more of those features described relative to any embodiment of the present disclosure can be implemented in the features of any other embodiment and / or combined with the features of any other embodiment, even if the combination is not clearly described. In other words, the described embodiments are not mutually exclusive, and the replacement of one or more embodiments with each other remains within the scope of the present disclosure.

[0049] Various terms are used to describe the spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless the relationship between a first and a second element is explicitly described as "direct," when such a relationship is described in the above disclosure, the relationship can be a direct relationship, in which there are no other intervening elements between the first and second elements, but can also be an indirect relationship, in which there are one or more intervening elements (spatially or functionally) between the first and second elements. As used herein, the phrase "at least one of A, B, and C" should be interpreted to mean a logical (A or B or C), using a non-exclusive logical OR, and should not be interpreted to mean "at least one of A, at least one of B, and at least one of C."

Claims

1. A method of reducing word line flexure in a memory cell, comprising: a) providing a substrate, the substrate comprising a plurality of word lines, the plurality of word lines being arranged adjacent to each other and above a plurality of transistors; b) depositing a film layer on the plurality of word lines using a deposition process; c) measuring word line deflection after depositing the film layer; d) comparing the word line deflection to a threshold tolerance range; e) adjusting at least one of a nucleation delay and a grain size of the deposition process based on the word line deflection; as well as f) using one or more substrates, repeating b) to e) one or more times respectively until the word line deflection is within the threshold tolerance range.

2. The method of claim 1, wherein (e) comprises adjusting at least one of a temperature and a pressure of the deposition process to adjust the nucleation delay.

3. The method of claim 1, wherein the film layer is selected from the group consisting of molybdenum, tungsten, ruthenium, and cobalt. 4 . The method according to claim 1 , further comprising disposing a liner layer between the plurality of word lines and the membrane layer. The method of claim 4 , wherein the liner layer comprises titanium nitride. The method according to claim 2 , wherein the temperature of the deposition process is adjusted in e). The method according to claim 2 , wherein the pressure of the deposition process is adjusted in e).

8. The method of claim 2, wherein the temperature and the pressure of the deposition process are adjusted in e).

9. The method of claim 2, wherein the temperature of the deposition process is reduced in e) to increase the nucleation delay.

10. The method of claim 2, wherein the pressure of the deposition process is reduced in e) to increase the nucleation delay.

11. The method of claim 2, wherein the temperature and the pressure of the deposition process are reduced in e) to increase the nucleation delay.

12. The method of claim 1, wherein (e) comprises increasing the nucleation delay if the word line deflection is greater than the threshold tolerance range.

13. The method of claim 1, wherein (e) comprises reducing the nucleation delay if the word line flexure is less than the threshold tolerance range.

14. The method of claim 1, wherein (e) comprises: using an inhibitor substance to adjust the nucleation delay.

15. The method of claim 14, wherein the inhibitor species is selected from the group consisting of molecular nitrogen and ammonia.

16. The method of claim 14, wherein the concentration of the inhibitor species is increased in (e) to increase the nucleation delay.

17. The method of claim 14, wherein the exposure time of the inhibitor substance is increased in (e) to increase the nucleation delay.

18. The method of claim 14, wherein the concentration of the inhibitor substance and the exposure time are increased in (e) to increase the nucleation delay.

19. The method of claim 1, wherein (e) comprises adjusting precursor chemistry or changing a mixture of precursors to adjust the nucleation delay.

20. The method of claim 1, wherein (e) comprises using at least one of temperature and pressure to control grain size.

21. The method of claim 1, wherein (e) comprises using an impurity to control grain size.

22. The method of claim 1, wherein (e) comprises using an in-situ gas to control grain size and film roughness.

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