Transistor bias adjustment for optimizing third order intercept point in cascode amplifier

Abstract

Methods and apparatus for amplifying an input RF signal according to at least two gain states are described. According to one aspect, a multi-gain amplifier circuit including a low noise amplifier having a stack of transistors is used to amplify an input RF signal. When switching from a low gain state to a high gain state, the drain-source voltage of the output transistor of the stack is increased to affect the operating region of the output transistor, thereby reducing nonlinearity at the output of the amplifier. When switching from a high gain state to a low gain state, the drain-source voltage of the input transistor of the stack is increased to affect the operating region of the input transistor, thereby reducing nonlinearity at the output of the amplifier.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 294,637, filed March 6, 2019, entitled “Transistor Bias Adjustment For Optimization Of Third Order Intercept Point In A Cascode Amplifier,” the contents of which are incorporated herein by reference in their entirety.

[0003] This application may relate to U.S. Patent No. 9,929,701B1, issued March 27, 2018, entitled "LNA with Programmable Linearity," the disclosure of which is incorporated herein by reference in its entirety. This application may also relate to U.S. Patent No. 9,941,849B1, issued April 10, 2018, entitled "Programmable Optimized Band Switching LNA for Operation in Multiple Narrow-Band Frequency Ranges," the disclosure of which is incorporated herein by reference in its entirety. This application may also relate to U.S. Patent No. 10,110,166, issued October 23, 2018, entitled "LNA with Variable Gain and Switched Degeneration Inductor," the disclosure of which is incorporated herein by reference in its entirety. This application may also relate to U.S. Patent No. 8,987,792B2, published March 24, 2015, entitled "Merged Active Devices on a Common Substrate," the disclosure of which is incorporated herein by reference in its entirety. This application may also relate to U.S. Patent No. 7,248,120B2, published July 24, 2007, entitled "Stacked Transistor Method and Apparatus," the disclosure of which is incorporated herein by reference in its entirety. This application may also relate to published U.S. Application No. 2015 / 0270806A1, published September 24, 2015, entitled "Bias Control for Stacked Transistor Configuration," the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] This teaching relates to RF (radio frequency) circuits. More specifically, this teaching relates to methods and apparatus for optimizing the third-order cutoff point (IP3) in a cascode amplifier comprising multiple stacked transistors, the cascode amplifier operating according to at least two gain states. Background Technology

[0005] Radio frequency (RF) devices, such as cellular telephone receivers, are becoming increasingly complex due to the need to operate in different modes of operation, which are associated with, for example, additional frequency bands, more complex modulation schemes, higher modulation bandwidths, and data throughput improvement schemes, such as simultaneous RF transmission and / or reception in the same or different but closely spaced frequency bands or channels within the same frequency band (e.g., voice, data) and aggregated reception of information multiplexed over parallel RF transmissions.

[0006] To support these different operating modes, the use of a mode-specific amplifier can be an option, where the amplifier's performance can be tuned according to a specific mode. One such tuning can be related to the amplifier's gain, where the gain is tuned or changed according to the amplifier's specific operating mode to obtain different levels of amplification through the amplifier.

[0007] A well-known amplifier configuration is the cascode configuration, in which multiple transistors connected in series (including an input transistor and a stack of one or more cascode transistors) are used to amplify the input RF signal. Figure 1A and Figure 1B Simplified schematic representations of prior art RF amplifiers are shown, which utilize stacks of two series-connected transistors arranged in a cascode configuration (input transistor M1 and cascode transistor M2, where M2 is the output transistor) and stacks of N series-connected transistors arranged in a cascode configuration (input transistor M1 and cascode transistors M2, ..., MN, where MN is the output transistor), each amplifier having a common-source input transistor M1. Further description of this cascode configuration, including stacked transistors and associated biases, can be found, for example, in US 8,987,792 B2, US 7,248,120 B2, and US 2015 / 0270806 A1, the disclosures of which are incorporated herein by reference in their entirety.

[0008] like Figure 1C As shown in the exemplary amplifier configuration (100C), the degraded inductor L DEGThe source node of input transistor Ml, which can be coupled to a stack of transistors operating as an amplifier, can be coupled to a source node of input transistor M2. Such a configuration and the associated benefits, including input impedance matching and the benefits of linear performance and noise figure performance of the amplifier configuration (100C), are well known to those skilled in the art. In particular, such benefits make the amplifier configuration (100C) a design choice for implementations of, for example, low noise amplifiers (LNAs) used in receiver portions of RF front-end communication systems (e.g., shown at 200). Figure 2

[0009] The LNA is responsible for providing first stage amplification for signals received by the communication system. The operational specifications of the LNA are important to the overall quality of the communication system receiver portion. Any noise or distortion introduced by the LNA can degrade the overall receiver performance. That is, the sensitivity of the receiver can be largely determined by the quality of the LNA. The sensitivity of the receiver, in turn, can determine the amount of information that can be transmitted (e.g., via a transmitter) at a predetermined bit rate (e.g., in bits per second) with a predetermined bit error rate in a predetermined amount of time.

[0010] The quality of the LNA is generally characterized by parameters such as gain, linearity (i.e., third order intercept point (IP3), as measured by input IP3 (IIP3) or output IP3 (OIP3)), and 1 dB compression point (PI dB)), noise figure (NF), input impedance matching, output impedance matching, and power consumption (i.e., supply voltage and current). These characteristics indicate the amount of distortion that can be imposed on signals received and processed by the receiver portion of the communication system, the strength of the signal that is needed, and the signal to interference plus noise ratio (SINR) that is needed to recover information transmitted at a particular data rate. As the demand for higher data rates continues to grow, such higher data rates can require higher demodulation accuracy on signals received by the receiver. The amount of gain that can be applied without imposing excessive distortion on the received signal can limit the data rate at which information modulated on the signal can be accurately demodulated from the once-received signal.

[0011] The receiver (e.g., a receiver within a cellular telephone) used in a wireless communication system (e.g., a cellular telephone) can be configured as an amplifier configuration (100C) as shown in FIG. 1C. The receiver can be configured as an amplifier configuration (100C) to provide a low noise amplifier (LNA) implementation. Figure 2 ​Such receivers must also be able to handle a wide range of input signal levels, as in the case of 200) shown in the middle. Therefore, the LNAs used in such receivers can have programmable gain, current and / or linearity. Furthermore, such LNAs are expected to meet specific input and output matching requirements and gain, linearity and noise figure per programmable gain state. Some exemplary implementations of such LNAs with programmable gain and / or linearity control can be found, for example, in the above-mentioned US 9,929,701 B1, US 9,941,849 B1 and US 10,110,166 B1, the disclosures of which are incorporated herein by reference in their entirety. As can be seen from such references, gain and linearity adjustment of the LNA can be provided via adjustable bias current levels through the stacked transistors of the LNA and / or via adjustable / switchable attenuator stages coupled to the input and / or output of the LNA, and / or via adjustable / switchable capacitances coupled to the gates and / or sources of the stacked transistors of the LNA, and / or via adjustable / switchable degeneration impedances coupled to the input transistor of the stacked transistors of the LNA.

[0012] As the multiple adjustable / switchable elements used in optimizing the linearity performance of the LNA with respect to different gain states of the LNA can require an increased complexity in the design, optimization and physical layout of the respective circuit, it can be desirable to reduce such complexity. Therefore, it is an object of the present disclosure to provide a simple solution for optimizing the linearity performance with respect to different gain states of the LNA without the need for such adjustable / switchable elements. SUMMARY

[0013] The teachings according to the present disclosure are based on the Applicant’s observation that the main contributor to non-linearity and thus to IP3 in low gain states of the LNA is the input transistor (e.g. M1 of Figure 1C , while in high gain states of the LNA the main contributor to non-linearity is the output transistor (e.g. M2 of Figure 1CM2). Based on such observations and in accordance with various embodiments of the present disclosure, optimization of LNA performance to reduce nonlinearity and thus increase IP3 can be provided by increasing the drain-source voltage of the input transistor of the stack when operating in the low gain state and by increasing the drain-source voltage of the output transistor when operating in the high gain state. In accordance with further embodiments of the present disclosure, such control of the drain-source voltage can be provided by controlling the gate voltage of the first cascode transistor coupled to the stack of the input transistor, and / or controlling the gate voltage to the last cascode transistor of the stack that is the output transistor. In the case where the LNA includes a stack of two transistors (the input transistor and a cascode output transistor), optimization of LNA performance to reduce nonlinearity can be provided by controlling the gate voltage to the cascode output transistor to provide a greater proportion of the supply voltage to the stack across the drain and source nodes of the input transistor when switching from operation in the high gain state to operation in the low gain state, and controlling the gate voltage to the cascode output transistor to provide a greater proportion of the supply voltage to the stack across the drain and source nodes of the output transistor when switching from operation in the low gain state to operation in the high gain state.

[0014] According to a first aspect of the present disclosure, there is presented a multi-gain state amplifier circuit for operating according to at least a low gain state and a high gain state, the multi-gain amplifier circuit comprising: i) a low noise amplifier (LNA) comprising: a stack of a plurality of series connected transistors comprising an input transistor and one or more cascode transistors including an output transistor, the stack being coupled between a substantially fixed supply voltage and a reference ground; and ii) a gain decoder and bias control circuit configured to selectively generate a bias voltage to the gates of the one or more cascode transistors to operate according to the low gain state and the high gain state, wherein: the bias voltage increases a drain-source voltage of the output transistor to operate according to the high gain state when switching from the low gain state to the high gain state, and the bias voltage increases a drain-source voltage of the input transistor to operate according to the low gain state when switching from the high gain state to the low gain state.

[0015] According to a second aspect of the disclosure, a method for optimizing the third order intercept point (IP3) in a multi-gain state amplifier comprising at least a low gain state and a high gain state is presented, the method comprising: biasing the cascode transistors of the multi-gain state amplifier to obtain an optimized value of the IP3 when operating in the low gain state; biasing the cascode transistors of the multi-gain state amplifier to obtain an optimized value of the IP3 when operating in the high gain state; wherein the optimized value of the IP3 when operating in the high gain state is obtained by increasing the drain-source voltage of the output transistor when switching from the low gain state to the high gain state, wherein the optimized value of the IP3 when operating in the low gain state is obtained by increasing the drain-source voltage of the input transistor when switching from the high gain state to the low gain state, and wherein the multi-gain state amplifier comprises a low noise amplifier (LNA) comprising a stack of a plurality of serially connected transistors, the stack comprising an input transistor and one or more cascode transistors comprising an output transistor, the stack being coupled between a substantially fixed supply voltage and a reference ground. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and together with the description, explain the principles and implementations of the disclosure.

[0017] Figure 1A A simplified schematic representation of a prior art RF common source amplifier circuit using a stack of two serially connected transistors arranged in a cascode configuration is shown.

[0018] Figure 1B A simplified schematic representation of a prior art RF common source amplifier circuit using a stack of a plurality (N) of serially connected transistors arranged in a cascode configuration is shown.

[0019] Figure 1C A simplified schematic representation of a prior art common source degeneration amplifier configuration based on a cascode configuration of Figure 1A is shown.

[0020] Figure 1D A simplified schematic representation of a prior art common source degeneration amplifier configuration based on a cascode configuration of Figure 1B is shown for the case of three serially connected transistors.

[0021] Figure 2 A block diagram of a receive path of a prior art multi-mode RF front-end communication system of an RF device used for example in a cellular phone is shown, wherein band-specific low noise amplifiers (LNAs) are used in the corresponding receive paths.

[0022] Figure 3A block diagram of a multi-gain state amplifier circuit including an LNA according to an exemplary embodiment of the present disclosure is shown.

[0023] Figure 4A The following is shown in accordance with this disclosure: Figure 3 An exemplary embodiment of the multi-gain state amplifier circuit shown is illustrated, wherein the LNA is Figure 1C Common-source degenerate amplifier.

[0024] Figure 4B The following is shown in accordance with this disclosure: Figure 4A An exemplary embodiment of the multi-gain state amplifier circuit shown is provided, wherein the output of the LNA is coupled to an impedance matching circuit.

[0025] Figure 4C This shows what will be used in the high-gain state. Figure 4A The input IP3 of the multi-gain state amplifier circuit is represented as a graph of the changing gate voltage of the output transistor of the amplifier.

[0026] Figure 4D This shows what will be used in the low-gain state. Figure 4A The input IP3 of the multi-gain state amplifier circuit is represented as a graph of the changing gate voltage of the output transistor of the amplifier.

[0027] Figure 5 The following is shown in accordance with this disclosure: Figure 3 An exemplary embodiment of the multi-gain state amplifier circuit shown is provided, wherein the LNA is a common-source degraded amplifier comprising a stack of three series-connected transistors arranged in a cascode configuration.

[0028] Figure 6 This is a process diagram illustrating a method for optimizing the third-order cutoff point (IP3) in a multi-gain state amplifier that includes at least a low-gain state and a high-gain state. Detailed Implementation

[0029] Throughout this description, embodiments and variations are described to illustrate the use and implementation of the inventive concept. The illustrative description should be understood as presenting examples of the inventive concept and not as limiting the scope of the concept disclosed herein.

[0030] This disclosure describes a circuit (circuit arrangement) in an electronic device (e.g., a cellular phone, a radio) having multiple devices (e.g., transistors (e.g., MOSFETs)). Those skilled in the art will understand that such a circuit including transistors can be arranged as an amplifier.

[0031] As used herein, the term "amplifier" is intended to refer to an amplifier comprising stacked transistors configured as amplifiers and can be used, for example, as a power amplifier (PA) and / or a low-noise amplifier (LNA). An amplifier can refer to a device configured to amplify a signal input to the device to generate an output signal with an amplitude greater than that of the input signal. Stacked transistor amplifiers, particularly stacked transistor amplifiers operating in a cascode configuration, are described, for example, in U.S. Patent Application No. 7,248,120, entitled "Stacked Transistor Method and Apparatus," published July 24, 2007, the disclosure of which is incorporated herein by reference in its entirety. As used herein, and as is known to those skilled in the art, the term "amplifier" can also be applied to amplifier modules and / or power amplifier modules having any number of stages (e.g., pre-drivers, drivers, final stages). As used herein, the terms "low-noise amplifier" or "LNA" are intended to refer to an amplifier comprising a degradation impedance, which includes an inductor. The techniques of this invention may also be applied to common-gate input topologies.

[0032] Figure 1A A simplified schematic representation of a prior art RF amplifier circuit (100A) using a stack of two series-connected transistors (M1, M2) arranged in a cascode configuration is shown. Figure 1A As shown, the RF amplifier (100A) includes an input transistor M1 and an output (cascode) transistor M2 connected in series. This type of RF amplifier (100A) using a stack configuration is well known to those skilled in the art and extensively discussed in the foregoing references, the disclosure of which is incorporated herein by reference in its entirety. In particular, it is well known to those skilled in the art... Figure 1A The operating principle of the common source and common gate configuration shown is beyond the scope of this disclosure.

[0033] Continue to refer to Figure 1A The input RF is provided at the gate terminal of the input transistor M1 of the amplifier (100A) through the coupling capacitor C10. IN Amplified by amplifier (100A). The corresponding amplified output RF signal RF OUT Provided at the drain of output transistor M2 and routed to the amplifier's output terminal via coupling capacitor C20. Coupling capacitors C10 and C20 can be used to couple the low-frequency (e.g., DC) bias voltage supplied to the transistor stack (transistor stack) to the RF... IN Signals and RF OUT Signal decoupling. Power supply voltage V DDThe drain of the output transistor M2 is supplied through the inductor L20, and a reference voltage (e.g., GND) is connected to the source of the input transistor Ml. A supply voltage V DD The regulated voltage can be fixed or substantially fixed.

[0034] The bias voltage at the nodes (Vgl, Vg2) of the RF amplifier (100A) is provided to the respective gates of the stacked transistors (Ml, M2). Such bias voltage can be used to bias the respective transistors according to a desired operating condition (e.g., point), or even to completely disable (i.e., substantially no current conduction) the respective transistors in case, for example, the amplifier (100A) is not used (e.g., standby operating mode). In particular, biasing the voltage Vgl to the gate of the input transistor can establish a DC current through the stacked transistors and thus an output power (e.g., gain) of the RF amplifier (100A), as known to those skilled in the art. Various biasing circuits to generate such bias voltage to the RF amplifier (100A) are described, for example, in the above cited U.S. Patent No. 9,219,445, U.S. Patent No. 8,487,706 B2, published U.S. Application No. 2014 / 0184335 Al, published U.S. Application No. US2014 / 0184336 Al, published U.S. Application No. 2014 / 0184337 Al, and published U.S. Application No. 2015 / 0270806.

[0035] Figure 1B A simplified schematic representation of a prior art RF amplifier circuit (100B) is shown that uses a stack of multiple (N) series-connected transistors (Ml,..., MN) arranged in a cascode configuration. The principle of operation of the configuration (100B) is similar to the principle described above with respect to the configuration (100A) of Figure 1A The skilled person will appreciate that a larger stack height of the RF amplifier defined by the integer N (where N = 2, 3, 4,..., 8,...) can allow for a larger voltage at the drain of the output transistor MN, since such voltage can be distributed among the N stacked transistors. The voltage distribution at the drain of the output transistor MN can in turn limit the voltage across any two nodes (source, drain, gate) of the transistors in the stack to be within a safe operating range (e.g., within the withstand voltage of the transistors).

[0036] Figure 1C A simplified schematic representation of an exemplary prior art cascode degeneration amplifier configuration (100C) is shown. Such exemplary configuration uses the amplifier (100A) with the source node of the input transistor Ml coupled to ground via a degeneration inductor L DEG and the input RF signal RF INThe depicted RF system is coupled to a coupling capacitor C10 via an input inductor L10. As described above, the amplifier configuration (100C) is for example used in a later described Figure 2 design choice for the implementation of the LNA used in the receive path of the depicted RF system. It should be noted that the number of stacked transistors of the configuration (100C) can be an integer N, where N = 2, 3, 4,..., 8, as described above with reference to Figure 1B The depicted configuration (100C) is described, for example, in dependence of the maximum voltage at the drain node of the output transistor. Figure 1D An exemplary case is shown, where N = 3.

[0037] Figure 2 A simplified block diagram of a prior art RF front-end communication system (200) is shown, which can be used for RF reception of multi-mode and multi-band signals via an antenna (260). The skilled person will be aware that Figure 2 The depicted block diagram can also include a transmit path (not shown) coupled to the antenna (260) for RF transmission of multi-mode and multi-band signals via the same antenna (260).

[0038] As Figure 2 shown, an antenna switch (250) can be used to switch the input RF signal RF IN detected at the antenna (260) to one of a plurality of selectable receive paths, each comprising for example a filter (2301,..., 230n) and a low noise amplifier LNA, (2101,..., 210p), wherein each of the plurality of selectable receive paths processes the detected RF IN signal according to a corresponding mode of operation and / or frequency band. The output processed by each of the receive paths can be selectively routed for downstream processing (for example, via a transceiver, not shown) by an output switch (260). The control of the antenna switch (250) and the output switch (260) by a control signal CTL can be provided via a controller knowing the selected mode and / or frequency band of operation of the RF front-end communication system (200A), for example a transceiver unit (not shown). In certain cases, as Figure 2 shown, the same LNA (for example, 2101) can be used to selectively process the detected RF signal RF IN according to different modes and / or frequency bands via for example a switch (255).

[0039] As described above, in order to support a wide range of RF signal levels, the LNAs (2101, ..., 210p) of the system (200) can have programmable gains. As used herein, programmable gain refers to the ability of an amplifier such as an LNA to be selectively configured to operate in one of at least two gain states, each gain state corresponding to a different amplification of the input signal provided at the amplifier's output to the amplifier. Thus, a multi-gain-state amplifier can refer to a programmable gain amplifier having multiple (N) gain states, where N is an integer equal to or greater than two.

[0040] Figure 3 A block diagram of a multi-gain amplifier circuit (300) according to an embodiment of the present disclosure is shown. Figure 3 As shown, the multi-gain amplifier circuit (300) includes a low-noise amplifier LNA (305), which includes a receiver for the input RF signal RF. IN The input terminals and the amplified version of the RF for outputting input RF signals. OUT The output terminal. According to another embodiment of the present disclosure, the control of the amplification level (gain) of the multi-gain amplifier circuit (300) is provided by a block (310), which is configured to generate gate bias voltages (315, 325) of the transistors to the LNA (305) in response to an input control signal Gain State to the block (310).

[0041] Continue to refer to Figure 3 According to exemplary embodiments of the present disclosure, a multi-gain amplifier circuit (300) can be controlled to operate at least according to a low-gain state and a high-gain state. According to some non-limiting exemplary embodiments of the present disclosure, the low-gain state may correspond to a gain of about 6 dB or lower (RF). OUT_POWER / RF IN_POWER The high-gain state can correspond to a gain of approximately 16 dB or higher. According to some embodiments of this disclosure, the block (310) according to the teachings can be used as a gain decoder and bias control circuit, which decodes the target gain state of the LNA (305) from the input control signal Gain State and generates corresponding gate bias voltages (315, 325) to operate the LNA (305) according to the target gain state, while minimizing / reducing the nonlinearity at the output of the LNA (325) specific to the target gain state (e.g., increasing IP3).

[0042] Those skilled in the art will clearly understand Figure 3The input control signal Gain State of the multi-gain amplifier circuit (300) can be one or more analog signals, one or more digital signals, or a combination thereof, as long as a desired and unique gain state among the multiple gain states of the multi-gain amplifier circuit (300) can be described / coded by the Gain State signal and accurately / uniquely decoded by the gain state decoder circuit (labeled as Gain Decoder in Figure 3

[0043] Further reference is made to the multi-gain amplifier circuit (300) of Figure 3 , the block (310) can generate the gate bias voltages (315, 325) so as to: a) configure the LNA (305) according to the gain state (amplification level) represented by the input control signal Gain State; and b) minimize / reduce the non-linearity at the output RF signal RF OUT out at the output of the LNA (305) associated with different bias conditions (e.g., bias voltages) of the LNA (305) used to provide the gain state. As mentioned above, such non-linearity can be based on IP3 parameter values as measured from the input IP3 (IIP3) or the output IP3 (OIP3).

[0044] According to some exemplary embodiments of the present disclosure, the gate bias voltage (315) can control the gain of the LNA (305), e.g., via controlling the static (DC) current through the LNA (305), and the gate bias voltage (325) can control / minimize gain-specific non-linearity. Note that the gate bias voltage (325) can also change the current through the LNA (305) to some extent, but less efficiently compared to the gate bias voltage (315). According to further embodiments of the present disclosure, the generation of the voltage levels of such gate bias voltages (315, 325) can be provided for each of the multiple programmable amplification levels of the multi-gain amplifier circuit (300) by first decoding the input control signal Gain State and then generating the corresponding levels of the gate bias voltages (315, 325) based on the decoding. It should be noted that many circuits for generating such voltage levels based on decoding the gain state can be known to those skilled in the art. Some non-limiting exemplary circuits can use a combination of one or more of analog-to-digital conversion circuits, digital-to-analog conversion circuits, digital circuits, analog circuits, and memory circuits that fetch the decoded input control signal Gain State and generate the appropriate and corresponding levels of the gate bias voltages (315, 325). According to preferred embodiments of the present disclosure, the input control signal Gain State can be a digital signal that uniquely specifies a gain state among the multiple gain states supported by the multi-gain amplifier circuit (300).

[0045] ​Figure 4A The following is shown in accordance with this disclosure: Figure 3 An exemplary embodiment (400A) of the multi-gain state amplifier circuit shown is provided, wherein the LNA (305) is Figure 1C The common-source degenerate amplifier (100C), Figure 1C The common-source degenerate amplifier (100C) consists of a stack of two transistors: an input transistor M1, whose source is connected to a degenerate inductor L. DEG Coupled to a reference voltage (e.g., GND); and the output cascode transistor M2, whose drain is coupled to the supply voltage V through inductor L20. DD Those skilled in the art will understand that the gate bias voltage Vg2 and the power supply voltage V DD The drain-source voltages Vds1 and Vds2 of each of transistors M1 and M2 are determined by combination. Specifically, for the supply voltage V... DD The levels are basically fixed / adjustable, and the drain-source voltages Vds1 and Vds2 are mainly determined by the gate bias voltage Vg2.

[0046] like Figure 4A As shown, the gate bias voltage (315) provides bias to the gate of the input transistor M1, and the gate bias voltage (325) provides bias to the gate of the cascode output transistor M2. As described above, the gate bias voltage (315) can control the gain of the LNA (100C) (e.g., the quiescent current I). DD Furthermore, the gate bias voltage (325) can control / reduce the output RF signal. OUT The nonlinearity at that point. It should be noted that, according to some exemplary embodiments, and as... Figure 4B As shown, the output of the LNA (100C) can be coupled to an impedance matching circuit (430), which is designed to couple the output impedance of the LNA (100C) to the load impedance Z. L Matching. In this case, if needed, the gate bias voltage (315, 325) can be set to control the gain and control / reduce the load Z. L The nonlinearity at the location. Furthermore, as is known in the art, the impedance matching circuit (430) can be a tunable circuit, which can be based, for example, on the received RF signal RF. IN The associated operating mode and / or frequency band can also be tuned based on the gain of the LNA (100C).

[0047] Continue to refer to Figure 4AThe applicant of this disclosure has observed that in the low-gain state of the LNA (100C), the main contributor to nonlinearity (and therefore IP3) is the input transistor M1, while in the high-gain state of the LNA, the main contributor to nonlinearity is the output transistor M2. This reversal in the contribution of nonlinearity between the low-gain and high-gain states may be due to the degradation of the inductor (impedance) L... DEG The existence of this factor is noteworthy. It should be noted that, generally speaking, the degraded inductor LDEG may affect the linearity and relative contribution of M1 and M2 to different gain states. Those skilled in the art will clearly recognize that, although the source of the cascode transistor M2 is not directly connected to the degraded inductor L... DEG However, the source of M2 effectively withstands the degraded impedance based on the output impedance of M1, and the output impedance of M1 is partly based on the degraded inductance L. DEG However, this is also based on the operating region of the input transistor M1 (e.g., set by the IV curve). Since the operating region of the input transistor M1 can be varied based on the gain state of the LNA (100C), which in this case is based on the gate bias voltage Vgl, the contribution of the cascode transistor M2 to the nonlinearity may differ depending on the gain of the LNA (100C), and is more or less related to the contribution from the input transistor M1. Having identified the major contributors to the nonlinearity (e.g., IP3) between the low-gain and high-gain states of the LNA (100C), the applicant has determined the range of gate bias voltage Vg2 values ​​that reduce the nonlinearity through simulation and circuit analysis. Figure 4C The diagram shows a representative image of the high-gain state, and Figure 4D The diagram shows a representative figure of the low-gain state.

[0048] Figure 4C It shows that Figure 4A For the high-gain state of the amplifier circuit (400A), the multi-gain state amplifier circuit (400A) IIP3 (i.e., input IP3) is represented as the changing gate voltage Vg2 of the output (cascode) transistor M2 of the amplifier (and for a fixed supply voltage equal to 1.2 volts Vg2). DD The graph is a function of Vg2. According to a non-limiting embodiment, the change in gate voltage Vg2 can be provided via a Vg2_Control signal (e.g., a byte, word, or other numeric code). Figure 4CIn the exemplary case of the plot depicted, the Vg2_Control signal can vary from a value of 0 to a value of 15 in discrete steps to control the Vg2 voltage from approximately 0.78 volts to approximately 1 volt. This control of Vg2 can be provided as part of the input control signal Gain State or via a separate control signal not shown in the figure within block (310). Those skilled in the art will appreciate that for a substantially fixed supply voltage V DD , varying the gate voltage Vg2 will also cause the same variation in the drain voltage Vdl of the input transistor Ml as shown in Figure 4C . Finally, since the supply voltage is substantially fixed (e.g., regulated), the variation in the drain voltage Vdl will also cause the same variation in the drain-source voltage Vds2 of M2 (same magnitude, opposite sign) as shown in Figure 4C , and a complementary variation in the drain-source voltage Vdsl of Ml so that at all times, Vds1 + Vds2 = V DD .

[0049] With further reference to Figure 4C , as noted above, in the high gain state, the nonlinearity (e.g., IP3) is dominated by the cascode transistor M2. Thus, a reduction in the nonlinearity contributed by the cascode device M2 can be based on the impedance (i.e., degeneration impedance) experienced by the source of M2 and / or the operating region of M2. As Figure 4CAs shown, scanning the Vg2_Control signal from 0 to 15 causes the gate voltage Vg2 to vary (linearly) from approximately 0.78 volts to 1 volt. IIP3 improves with the initial scan value of Vg2_Control (higher values ​​indicate lower nonlinearity) and decreases with the final scan value. When Vg2_Control equals 0, the drain voltage Vd1 is low, so the input transistor M1 operates near its transistor operating region. When operating in the transistor operating region, M1 has low output impedance, so the cascode transistor M2 experiences lower degradation impedance, which may result in higher nonlinearity (lower IIP3). As the gate voltage Vg2 increases with the value of Vg2_Control and therefore Vd1, the operating region of the input transistor M1 gradually transitions from the transistor to the saturation region, resulting in a significant (at least an order of magnitude) increase in the output impedance of the input transistor M1. Conversely, the cascode device M2 experiences higher degradation impedance, which in turn reduces the nonlinearity contributed by M2 (higher IIP3), with a peak in IIP3 observed at a Vg2_Control value of 7 (i.e., Vg2 is approximately 0.88 V). Finally, as the gate voltage Vg2 is further increased with even higher Vg2_Control values, the difference between the gate-source voltage Vgs2 and the drain-source voltage Vds2 of M2 decreases, and this results in M2 operating closer to its transistor operating region, which directly leads to more nonlinear components and is therefore observed at... Figure 4C The graph shows a decrease in IIP3.

[0050] Figure 4D It shows that Figure 4A For the low-gain state of the amplifier circuit (400A), the multi-gain state amplifier circuit (400A) represents the variable gate voltage Vg2 leading to the output (cascode) transistor M2 of the amplifier (and for a fixed supply voltage equal to 1.2 volts Vg2). DD The curve of the function ). Figure 4D The graph represents the curve described above. Figure 4C The parameters are the same as those in the curve, but are used for the low-gain state. As mentioned above, the change in gate voltage Vg2 can be provided via the Vg2_Control signal, which scans from, for example, a value of 0 to a value of 15.

[0051] Further reference Figure 4D As mentioned above, in the low-gain state, the nonlinearity (e.g., IP3) is dominated by the input device M1. (Referring to the above reference...) Figure 4C Unlike the case of M2 in a high-gain state, the source (degenerate) impedance of M1 is purely passive (i.e., L). DEG) and is not affected by the output impedance of Ml. Thus, the reduction of non-linearity contributed by the input device Ml can be based on the operating region of Ml only. As Figure 4D shown, by sweeping the Vg2_Control signal from 0 to 15, which causes the gate voltage Vg2 to vary from approximately 0.78 volts to 1 volt, the IIP3 improves significantly with the initial sweep values of Vg2_Control (higher values indicate lower non-linearity) to peak at Vg2_Control equal to 9 (i.e., Vg2 is approximately 0.92 volts) and drops with the last sweep values (e.g., Vg2_Control between 10-15). Overall, it can be observed that better IP3 performance (higher IIP3 values) is obtained for drain voltages Vdl higher than approximately 0.4 volts (i.e., Vg2_Control equal to or greater than 6) compared to drain voltages Vdl lower than 0.4 volts (i.e., Vg2_Control between 0-5).

[0052] With continued reference to Figure 4D , when Vg2_Control is equal to 0 (lower gate voltage Vg2), Vdl is low, the input transistor Ml operates in its triode operating region, thus directly leading to more non-linear components causing a drop in IIP3 as shown in the 4D plot. As the gate voltage Vg2 increases with the increase in Vg2_Control values and thus Vdl values (Vg2_Control > 0 to 9), the operating region of the input transistor Ml gradually transitions from triode to saturation region and thus reduces its contribution to non-linearity to obtain better IP3 performance. With further increase in the gate voltage Vg2 (Vg2_Control > 9), thus further increase in the drain voltage Vdl, the non-linear components of the cascode transistor M2 are affected, thus M2 directly leads to more non-linear components, thus a drop in IIP3 is observed as per the plot of 4D. It should be noted that the description in accordance with this paragraph relates to the observed effects that can be controlled and have an impact on linearity. However, it would be clear to a person skilled in the art that there can be other contributors to the linearity of the RF amplifier that are not described in this disclosure. Figure 4D

[0053] With reference to Figure 4C and Figure 4D , it would be clear to a person skilled in the art that in order to reduce the non-linearity, or keep the non-linearity at lower possible values, lower Vg2 values should be used in the high gain state (e.g., corresponding to Vg2_Control = 7) and higher Vg2 values should be used in the low gain state of the multi-gain state amplifier circuit (400A) (e.g., corresponding to Vg2_Control = 9). As a consequence, in accordance with embodiments of the present disclosure, Figure 4A ​the high gain state to the low gain state, the drain voltage Vdl of the input transistor Ml increases and the drain-source voltage Vdsl thus increases, while from the low gain state to the high gain state, the drain voltage Vdl of the input transistor Ml decreases and the drain-source voltage Vdsl thus decreases. Similarly, since Vdsl + Vds2 is constant, the drain-source voltage Vds2 of the output cascode transistor M2 decreases when switching from the high gain state to the low gain state, and increases when switching from the low gain state to the high gain state.

[0054] Since the main contributor to non-linearity is the output cascode transistor M2 in the high gain state, and the main contributor to non-linearity is the input transistor Ml in the low gain state, based on the foregoing, it will be clear to those skilled in the art that the block (310) of the present teachings generates the gate bias voltage Vg2 so as to increase the drain-source voltage of the transistor that is the main contributor to non-linearity when switching gain states. In other words, when switching from the low gain state to the high gain state where the output cascode transistor M2 is the main contributor, the drain-source voltage Vds2 of M2 increases, and when switching from the high gain state to the low gain state where the input transistor Ml is the main contributor, the drain-source voltage Vdsl of Ml increases. Naturally, in the exemplary case of a stack (Ml, M2) of two transistors, increasing or decreasing one of Vdsl and Vds2 always affects the other by the same amount, but with opposite sign, since Vdsl + Vds2 is constant. Figure 4A

[0055] Since Vdsl and Vds2 affect the operating region of Ml and M2, respectively, the present teachings describe changing / affecting the operating region of the device that is the main contributor to non-linearity in the gain state being targeted. In other words, when switching from the low gain state to the high gain state where the output cascode transistor M2 is the main contributor, the operating region of M2 changes to enter more into the saturation region, and when switching from the high gain state to the low gain state where the input transistor Ml is the main contributor, the operating region of Ml changes to enter more into the saturation region. Furthermore, it should be noted that in the high gain state, when M2 is fully in the saturation region, the source impedance experienced by M2 also becomes important, as does the operating region (operating region) of Ml. Therefore, a trade-off between Vdsl and Vds2 can be provided.

[0056] As mentioned above, the teachings according to the present disclosure can equally apply to configurations where the LNA comprises more than two transistors connected in series. Figure 5 is shown according to the present disclosure​Figure 3 An exemplary embodiment (500) of a multi-gain state amplifier circuit is shown, wherein the LNA (305) is a stack of three series-connected transistors (M1, M2, M3) arranged in a cascode configuration Figure 1D A cascode amplifier (100D) is shown. As Figure 5 The multi-gain state amplifier circuit (500) is shown to comprise an input transistor M1, whose source is coupled to a reference voltage (e.g., GND) through a degeneration inductor L DEG , and series-connected cascode transistors M2 and M3. The transistor M3, which is the output cascode transistor, is coupled to a supply voltage V DD The skilled person will appreciate that the gate bias voltages Vg2 and Vg3, together with the supply voltage V DD The drain-source voltages Vdsl, Vds2 and Vds3 of each transistor M1, M2 and M3 are determined in combination. In particular, for a substantially fixed / regulated level of the supply voltage V DD The drain-source voltages Vdsl, Vds2 and Vds3 are determined by the gate bias voltages Vg2 and Vg3, for a substantially fixed / regulated level of the supply voltage V

[0057] With continued reference to Figure 5 , similar to the case of the two-stack of transistors described above with reference to Figure 4A The applicants of the present disclosure have observed that the main contributor to non-linearity, and thus IP3, in the low-gain state of the LNA (100D) is the input transistor M1, while in the high-gain state of the LNA (100D) the main contributor to non-linearity is the output transistor M3. In other words, the intermediate cascode transistor M2 does not substantially affect the non-linearity (e.g., IP3) in the low or high-gain state of the LNA (100D), and therefore, the intermediate cascode transistor M2 can be used as a means to isolate the effect of the control voltages (e.g., Vg2, Vg3) on M1 and M3 for reducing gain state non-linearity. In other words, since the gain state non-linearity can be reduced by changing the drain-source voltages Vdsl and Vds3, the drain-source voltage Vds2 of the intermediate transistor M2 can be used as a buffer between Vdsl and Vds3, so that Vdsl and Vds3 can be freely used independently to control the operating regions of Ml and M3, respectively, to reduce the respective non-linearity without affecting each other. This is different from the case of the two-stack of transistors described with reference to Figure 4A , where Vdsl and Vds2 are intrinsically related. As a result, more freedom to control the respective operating regions of M1 and M3 can be obtained, and possibly more reduction of the corresponding non-linearity of the target gain state. The skilled person will appreciate that the amount of freedom can be subject to the supply voltage V DDthe level of the power supply voltage V DD A greater freedom of control of the respective operating regions of Ml and M3 can be provided without affecting the operation of M2, while a lower level of the power supply voltage can limit the control of the respective operating regions due to possibly limited Vds2.

[0058] With continued reference to Figure 5 As the main contributor of nonlinearity in the high gain state is the output cascode transistor M3, while in the low gain state the main contributor of nonlinearity is the input transistor Ml, based on the above, it will be clear to those skilled in the art that the block (310) of the present teachings generates the gate bias voltage Vg2 to increase the drain source voltage Vdsl of the input transistor Ml when switching from the high gain state to the low gain state and generates the gate bias voltage Vg3 to increase the drain source voltage Vds3 of the output cascode transistor M3 when switching from the low gain state to the low gain state. As the control of Vdsl and Vds3 can be provided independently due to the presence of the intermediate cascode transistor M2, further adjustment of Vdsl when switching to the high gain state and of Vds3 when switching to the low gain state can be provided. If desired, such further switching can be to adjust other performance of the multi-gain amplifier circuit (500).

[0059] As Vdsl and Vds3 affect the operating regions of Ml and M3, respectively, the present teachings describe changing / affecting the operating region of one device that is the main contributor of nonlinearity in the gain state of interest. In other words, when switching from the low gain state to the high gain state where the output cascode transistor M3 is the main contributor, the operating region of M3 changes to enter more into the saturation region, and when switching from the high gain state to the low gain state where the input transistor Ml is the main contributor, the operating region of Ml changes to enter more into the saturation region.

[0060] Figure 6is a process diagram (600) illustrating various steps of a method for optimizing the third order intercept point (IP3) in a multi-gain state amplifier according to the present teachings. As can be seen from the process diagram (600), the method comprises: providing, in step (610), a multi-gain state amplifier comprising at least a low gain state and a high gain state; biasing, in step (620), the cascode transistor of the multi-gain state amplifier to obtain an optimized value of the IP3 when operating in the low gain state; biasing, in step (630), the cascode transistor of the multi-gain state amplifier to obtain an optimized value of the IP3 when operating in the high gain state; wherein the optimized value of the IP3 when operating in the high gain state is obtained by increasing, in step (640), the drain-source voltage of the output transistor when switching from the low gain state to the high gain state; and wherein the optimized value of the IP3 when operating in the low gain state is obtained by increasing, in step (650), the drain-source voltage of the input transistor when switching from the high gain state to the low gain state.

[0061] Based on the above description, the skilled person will recognize that the above described multi-gain amplifier circuit can not only be used in the receive path of a multi-band and / or multi-mode RF communication system, but also in any radio frequency system where one or more (weak) radio frequency signals need to be amplified according to different gains.

[0062] The advantage of reduced layout size provided by the configurations according to the present teachings can allow to further reduce monolithic integrated circuits using such configurations. The skilled person will recognize that monolithic integration of the whole or parts of any of the above described configurations is also possible, depending on the desired implementation goals.

[0063] Applications of the novel apparatuses and systems, which can include various embodiments, include electronic circuits used in high-speed computers, communications and signal processing circuits, modems, single or multi-processor modules, single or multi-core embedded processors, data switches, and application-specific modules, including multi-layer, multi-chip modules. Such apparatuses and systems can also be included as subcomponents in various electronic systems, such as televisions, cell phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), and others. Some embodiments can include multiple methods.

[0064] As used in this disclosure, the term “MOSFET” refers to any field effect transistor (FET) having an insulated gate and including a metal or metal-like, an insulator, and a semiconductor structure. The term “metal” or “metal-like” includes at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconducting material.

[0065] Those of ordinary skill in the art will readily understand that various embodiments of the application can be implemented to meet a variety of specifications. Unless otherwise noted above, selecting appropriate component values is a matter of design choice, and various embodiments of the application can be implemented in any suitable IC technology, including but not limited to MOSFET structures, or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, the application can be implemented in other transistor technologies, such as bipolar, GaAS HBT, GaN HEMT, GaAS pHEMT, and MESFET technologies. However, the above inventive concepts are particularly useful for SOI-based fabrication processes, including SOS, as well as fabrication processes with similar characteristics. CMOS fabrication on SOI or SOS enables low power consumption, ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and beyond 50 GHz). Monolithic IC implementation is particularly useful because, with careful design, parasitic capacitances can generally be kept low (or at least, consistent across all cells, allowing them to be compensated for).

[0066] Voltage levels or inversion voltages and / or logic signal polarities can be adjusted according to particular specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities can be adjusted as needed, for example, by adjusting device sizes, “stacking” components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0067] A number of embodiments according to the present disclosure have been described. Various modifications can be made without departing from the spirit and scope of these embodiments. For example, some of the steps described above can be independent of sequence, and therefore can be performed in an order other than that described. Again, some of the above described steps can be optional. The various activities described with regard to the methods described above can be performed in repetitive, serial, or parallel fashion.

[0068] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the disclosure, which is defined by the scope of the following claims. Other embodiments are within the scope of the following claims. (Note that the parenthetical references to claim elements are for ease of referencing those elements, and do not themselves indicate a particular ordering or enumeration of elements as required; further, such references can be repeated in dependent claims as references to additional elements, rather than being seen as a sequence of conflicting markers).

Claims

1. A multi-gain state amplifier circuit for operating in accordance with at least a low gain state and a high gain state, the multi-gain state amplifier circuit comprising: i) a low noise amplifier (LNA) comprising: a stack of a plurality of series connected transistors including an input transistor and one or more cascode transistors including an output transistor, the stack coupled between a substantially fixed supply voltage and a reference ground; and ii) a gain decoder and bias control circuit configured to selectively generate a bias voltage to gates of the one or more cascode transistors to operate in accordance with the low gain state and the high gain state, wherein: when switching from the low gain state to the high gain state, the bias voltage increases a drain-source voltage of the output transistor to operate in accordance with the high gain state, and when switching from the high gain state to the low gain state, the bias voltage increases a drain-source voltage of the input transistor to operate in accordance with the low gain state.

2. The multi-gain state amplifier circuit of claim 1, wherein: the increase in the drain-source voltage of the output transistor reduces a non-linearity of an RF signal amplified by the LNA during operation in the high gain state, and the increase in the drain-source voltage of the input transistor reduces a non-linearity of the RF signal amplified by the LNA during operation in the low gain state.

3. The multiple gain state amplifier circuit of claim 2, wherein, the non-linearity includes a third order intercept point (IP3) that is increased when the non-linearity is reduced.

4. The multi-gain state amplifier circuit of claim 1, wherein: the one or more cascode transistors consists of one cascode transistor that is the output transistor, when switching from the low gain state to the high gain state, the gain decoder and bias control circuit decreases a bias voltage to the gate of the output transistor, and when switching from the high gain state to the low gain state, the gain decoder and bias control circuit increases the bias voltage to the gate of the output transistor.

5. The multiple gain state amplifier circuit of claim 4, wherein, the substantially fixed supply voltage is a regulated voltage of about 1.2 volts.

6. The multi-gain state amplifier circuit of claim 1, wherein: the one or more cascode transistors include the output transistor and at least one additional cascode transistor coupled to the input transistor, and when switching from the low gain state to the high gain state, the gain decoder and bias control circuit decreases a bias voltage to the gate of the output transistor.

7. The multi-gain state amplifier circuit of claim 1, wherein: the one or more cascode transistors include the output transistor and at least one additional cascode transistor coupled to the input transistor, and when switching from the high gain state to the low gain state, the gain decoder and bias control circuit increases a bias voltage to the gate of the at least one additional cascode transistor.

8. The multi-gain state amplifier circuit of claim 1, wherein: The one or more common-source common-gate transistors include the output transistor and at least one additional common-source common-gate transistor coupled to the input transistor, when switching from the low-gain state to the high-gain state, the gain decoder and bias control circuit reduces a bias voltage to a gate of the output transistor, and when switching from the high-gain state to the low-gain state, the gain decoder and bias control circuit increases a bias voltage to a gate of the at least one additional common-source common-gate transistor.

9. The multiple gain state amplifier circuit of claim 8, wherein, The substantially fixed supply voltage is a regulated voltage of about 1.8 volts.

10. The multi-gain state amplifier circuit of claim 2, wherein: when switching from the low-gain state to the high-gain state, the bias voltage further drives the input transistor into a corresponding saturation operating region, thereby increasing a degeneration impedance experienced by the output transistor to reduce the non-linearity.

11. The multiple gain state amplifier circuit of claim 1, wherein, The multi-gain state amplifier circuit has a gain equal to or less than 6 dB during operation in the low-gain state, and a gain equal to or greater than 16 dB during operation in the high-gain state.

12. The multiple gain state amplifier circuit of claim 1, wherein, During operation in the low-gain state and the high-gain state, respective gains of the multi-gain state amplifier circuit are provided to a gate of the input transistor via a bias voltage selectively generated by the gain decoder and bias control circuit.

13. The multiple gain state amplifier circuit of claim 1, wherein, The gain decoder and bias control circuit selectively generates the bias voltage based on an input control signal, the input control signal being one of: a) a digital signal, b) an analog signal, and c) a combination of a) and b).

14. The multiple gain state amplifier circuit of claim 13, wherein, The gain decoder and bias control circuit includes: a) a gain decoder circuit that decodes the input control signal into a target gain state including the low-gain state and the high-gain state; and b) a bias control circuit that generates the bias voltage based on the target gain state, the bias control circuit including one or more of: b1) an analog-to-digital conversion circuit, b2) a digital-to-analog conversion circuit, b3) a digital circuit, b4) an analog circuit, and b5) a memory circuit.

15. The multiple gain state amplifier circuit of claim 1, wherein, The transistors in the plurality of series-connected transistors are metal-oxide-semiconductor (MOS) field-effect transistors (FETs).

16. The multiple gain state amplifier circuit of claim 15, wherein, The transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, b) silicon-on-sapphire (SOS) technology, and c) bulk silicon (Si) technology.

17. An electronic module comprising the multi-gain state amplifier circuit of claim 1.

18. A radio frequency (RF) front-end communication system comprising: a receiver portion for receiving RF signals, the receiver portion including the electronic module of claim 17.

19. A method of using an electronic module comprising: The electronic module of claim 17 for use in one or more electronic systems comprising: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a radio, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.

20. A method for optimizing a third order intercept point (IP3) in a multi-gain state amplifier comprising at least a low gain state and a high gain state, the method comprising: biasing cascode transistors of the multi-gain state amplifier to obtain an optimized value of the third order intercept point when operating in the low gain state; biasing cascode transistors of the multi-gain state amplifier to obtain an optimized value of the third order intercept point when operating in the high gain state; wherein the optimized value of the third order intercept point when operating in the high gain state is obtained by increasing a drain-source voltage of an output transistor when switching from the low gain state to the high gain state, wherein the optimized value of the third order intercept point when operating in the low gain state is obtained by increasing a drain-source voltage of an input transistor when switching from the high gain state to the low gain state, and wherein the multi-gain state amplifier comprises a low noise amplifier (LNA) comprising a stack of a plurality of series connected transistors, the stack comprising the input transistor and one or more cascode transistors comprising the output transistor, the stack coupled between a substantially fixed supply voltage and a reference ground.

21. A multi-gain state amplifier circuit for operating at least according to a low gain state and a high gain state, the multi-gain state amplifier circuit comprising: i) a low noise amplifier (LNA) comprising: a stack of a plurality of series connected transistors comprising an input transistor and one or more cascode transistors comprising an output transistor, the stack coupled between a substantially fixed supply voltage and a reference ground; and ii) a gain decoder and bias control circuit configured to selectively generate a bias voltage to gates of the one or more cascode transistors to operate according to the low gain state and the high gain state, wherein during operation in the high gain state, the bias voltage is configured to provide a drain-source voltage of the output transistor that is higher than a drain-source voltage of the output transistor during operation in the low gain state, and wherein during operation in the low gain state, the bias voltage is configured to provide a drain-source voltage of the input transistor that is higher than a drain-source voltage of the input transistor during operation in the high gain state.

22. The multi-gain state amplifier circuit of claim 21, wherein: the increase in the drain-source voltage of the output transistor reduces nonlinearity of an RF signal amplified by the LNA during operation in the high gain state, and the increase in the drain-source voltage of the input transistor reduces nonlinearity of the RF signal amplified by the LNA during operation in the low gain state. An increase in drain-to-source voltage of the input transistor reduces a non-linearity of an RF signal amplified by the LNA during operation in the low gain state.

23. The multiple gain state amplifier circuit of claim 22, wherein, The non-linearity includes an increased third order intercept point (IP3) as the non-linearity is reduced.

24. The multi-gain state amplifier circuit of claim 21, wherein: the one or more cascode transistors consist of one cascode transistor that is the output transistor, during operation in the high gain state, the gain decoder and bias control circuit is configured to reduce a bias voltage to a gate of the output transistor to provide an increased drain-to-source voltage of the output transistor, and during operation in the low gain state, the gain decoder and bias control circuit is configured to increase a bias voltage to a gate of the output transistor to provide an increased drain-to-source voltage of the input transistor.

25. The multiple gain state amplifier circuit of claim 24, wherein, the substantially fixed supply voltage is a regulated voltage of about 1.2 volts.

26. The multi-gain state amplifier circuit of claim 21, wherein: the one or more cascode transistors include the output transistor and at least one additional cascode transistor coupled to the input transistor, and during operation in the high gain state, the gain decoder and bias control circuit is configured to reduce a bias voltage to a gate of the output transistor to provide an increased drain-to-source voltage of the output transistor.

27. The multi-gain state amplifier circuit of claim 21, wherein: the one or more cascode transistors include the output transistor and at least one additional cascode transistor coupled to the input transistor, and during operation in the low gain state, the gain decoder and bias control circuit is configured to increase a bias voltage to a gate of the at least one additional cascode transistor to provide an increased drain-to-source voltage of the input transistor.

28. The multi-gain state amplifier circuit of claim 21, wherein: the one or more cascode transistors include the output transistor and at least one additional cascode transistor coupled to the input transistor, during operation in the high gain state, the gain decoder and bias control circuit is configured to reduce a bias voltage to a gate of the output transistor to provide an increased drain-to-source voltage of the output transistor, and during operation in the low gain state, the gain decoder and bias control circuit is configured to increase a bias voltage to a gate of the at least one additional cascode transistor to provide an increased drain-to-source voltage of the input transistor.

29. The multiple gain state amplifier circuit of claim 28, wherein, the substantially fixed supply voltage is a regulated voltage of about 1.8 volts.

30. The multi-gain state amplifier circuit of claim 22, wherein: during operation in the high gain state, the bias voltage further drives the input transistor into a corresponding saturation region of operation, thereby increasing a degeneration impedance experienced by the output transistor to reduce the non-linearity.

31. The multiple gain state amplifier circuit of claim 21, wherein, The multi-gain state amplifier circuit has a gain equal to or less than 6 dB during operation in the low gain state and a gain equal to or greater than 16 dB during operation in the high gain state.

32. The multiple gain state amplifier circuit of claim 21, wherein, During operation in the low gain state and the high gain state, respective gains of the multi-gain state amplifier circuit are provided to gates of input transistors via a bias voltage selectively generated by the gain decoder and bias control circuit.

33. The multiple gain state amplifier circuit of claim 21, wherein, The gain decoder and bias control circuit selectively generates the bias voltage based on an input control signal, the input control signal being one of: a) a digital signal, b) an analog signal, and c) a combination of a) and b).

34. The multiple gain state amplifier circuit of claim 33, wherein, The gain decoder and bias control circuit includes: a) a gain decoder circuit that decodes the input control signal into a target gain state including the low gain state or the high gain state; and b) a bias control circuit that generates the bias voltage based on the target gain state, the bias control circuit including one or more of: b1) an analog-to-digital conversion circuit, b2) a digital-to-analog conversion circuit, b3) a digital circuit, b4) an analog circuit, and b5) a memory circuit.

35. The multiple gain state amplifier circuit of claim 21, wherein, The transistors in the plurality of series-connected transistors are metal-oxide-semiconductor (MOS) field-effect transistors (FETs).

36. The multiple gain state amplifier circuit of claim 35, wherein, The transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, b) silicon-on-sapphire (SOS) technology, and c) bulk silicon (Si) technology.

37. The multiple gain state amplifier circuit of claim 21, wherein, The low noise amplifier (LNA) is a single-stage amplifier.

38. An electronic module comprising the multi-gain state amplifier circuit of claim 21.

39. A radio frequency (RF) front-end communication system comprising: a receiver portion for receiving RF signals, the receiver portion including the electronic module of claim 38.

40. A method of using an electronic module comprising: using the electronic module of claim 38 in one or more electronic systems including: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a radio, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.

41. A method for optimizing a third-order intercept point (IP3) in a multi-gain state amplifier including at least a low gain state and a high gain state, the method comprising: biasing a cascode transistor of the multi-gain state amplifier to an optimized value of the third-order intercept point during operation in the low gain state; biasing a cascode transistor of the multi-gain state amplifier to an optimized value of the third-order intercept point during operation in the high gain state; wherein the optimized value of the third-order intercept point during operation in the high gain state is obtained by providing a drain-source voltage of an output transistor that is higher than a drain-source voltage of the output transistor during operation in the low gain state, wherein the optimized value of the third order intercept point during operation in the low gain state is obtained by providing a drain to source voltage of the input transistor that is higher than a drain to source voltage of the input transistor during operation in the high gain state, and wherein the multi-gain state amplifier comprises a low noise amplifier (LNA) comprising a stack of a plurality of series connected transistors, the stack comprising the input transistor and one or more cascode transistors including the output transistor, the stack coupled between a substantially fixed supply voltage and a reference ground.

42. A multi-gain state amplifier circuit for operating in accordance with at least a low gain state and a high gain state, the multi-gain state amplifier circuit comprising: i) a low noise amplifier (LNA) comprising: a stack of a plurality of series connected transistors comprising an input transistor and one or more cascode transistors including an output transistor, the stack coupled between a substantially fixed supply voltage and a reference ground; and ii) a gain decoder and bias control circuit configured to selectively generate a bias voltage to gates of the one or more cascode transistors to operate in accordance with the low gain state and the high gain state, wherein during operation in the high gain state, the bias voltage is configured to provide a drain to source voltage of the output transistor that is higher than a drain to source voltage of the output transistor during operation in the low gain state, wherein the gain decoder and bias control circuit selectively generates the bias voltage based on an input control signal, the input control signal being one of: a) a digital signal, b) an analog signal, or c) a combination of a) and b), and wherein the gain decoder and bias control circuit comprises: a gain decoder circuit that decodes the input control signal into a target gain state comprising the low gain state or the high gain state; and a bias control circuit that generates the bias voltage based on the target gain state, the bias control circuit comprising one or more of: p) an analog to digital conversion circuit, q) a digital to analog conversion circuit, r) a digital circuit, s) an analog circuit, or t) a memory circuit. iii) a gain decoder and bias control circuit configured to selectively generate a bias voltage to gates of the one or more cascode transistors to operate in accordance with the low gain state and the high gain state, wherein during operation in the high gain state, the bias voltage is configured to provide a drain to source voltage of the output transistor that is higher than a drain to source voltage of the output transistor during operation in the low gain state, wherein the gain decoder and bias control circuit selectively generates the bias voltage based on an input control signal, the input control signal being one of: a) a digital signal, b) an analog signal, or c) a combination of a) and b), and wherein the gain decoder and bias control circuit comprises: a gain decoder circuit that decodes the input control signal into a target gain state comprising the low gain state or the high gain state; and a bias control circuit that generates the bias voltage based on the target gain state, the bias control circuit comprising one or more of: p) an analog to digital conversion circuit, q) a digital to analog conversion circuit, r) a digital circuit, s) an analog circuit, or t) a memory circuit.

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