Semiconductor device and method of manufacturing the same

Abstract

Semiconductor devices and methods of manufacturing the same. A semiconductor device includes a first semiconductor structure including a memory array, a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor, a first insulating layer between the first semiconductor structure and the second semiconductor structure, a second insulating layer between the second semiconductor structure and the first insulating layer, a first bonding pad electrically connected to the memory array, the first bonding pad being located in the first insulating layer, and a second bonding pad electrically connected to the first transistor, the second bonding pad being located in the second insulating layer. The first bonding pad and the second bonding pad are in contact with each other. At least one of a plurality of sidewalls of the first bonding pad and the second bonding pad includes a curved portion.

Description

TECHNICAL FIELD

[0001] The disclosure relates generally to an electronic device, and more particularly, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] A semiconductor device includes an integrated circuit configured in a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rule of the semiconductor device gradually decrease, miniaturization of the MOSFET is gradually accelerated.

[0003] Miniaturization of the MOSFET can cause a short channel effect or the like, and thus, the operating characteristics of the semiconductor device can be deteriorated. Accordingly, various methods have been researched to form a semiconductor device having improved performance while overcoming the limitations due to the high integration of the semiconductor device.

[0004] In addition, such an integrated circuit pursues operating reliability and low power consumption. Accordingly, methods of forming a device having higher reliability and lower power consumption with a smaller form factor have been researched. SUMMARY

[0005] According to an embodiment of the disclosure, a semiconductor device includes a first semiconductor structure including a memory array, a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor, a first insulating layer between the first semiconductor structure and the second semiconductor structure, a second insulating layer between the second semiconductor structure and the first insulating layer, a first bonding pad electrically connected to the memory array, the first bonding pad being located in the first insulating layer, and a second bonding pad electrically connected to the first transistor, the second bonding pad being located in the second insulating layer, wherein the first bonding pad and the second bonding pad contact each other, and wherein at least one of a plurality of sidewalls of the first bonding pad and the second bonding pad includes a curved portion.

[0006] According to another embodiment of the present disclosure, a semiconductor device includes: a first semiconductor structure including a stack structure, a channel structure penetrating the stack structure, and a bit line electrically connected to the channel structure; a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor; a first insulating layer between the first semiconductor structure and the second semiconductor structure; a second insulating layer between the second semiconductor structure and the first insulating layer; a first bonding pad located in the first insulating layer, the first bonding pad electrically connected to the channel structure; and a second bonding pad located in the second insulating layer, the second bonding pad electrically connected to the first transistor, the second bonding pad being in contact with the first bonding pad, wherein the first bonding pad includes: a first portion in contact with the second bonding pad; a second portion in contact with the bit line; and a third portion between the first portion and the second portion, wherein a sidewall of the third portion is curved.

[0007] According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device includes the steps of: forming an insulating layer; forming a hard mask layer including a first opening on the insulating layer; forming a second opening in the insulating layer by etching the insulating layer using the hard mask layer as an etching barrier; enlarging the first opening of the hard mask layer; after the first opening is enlarged, forming a third opening and a fourth opening in the insulating layer by etching the insulating layer using the hard mask layer as an etching barrier; and forming a bonding pad in the third opening and the fourth opening, wherein a width of the fourth opening is greater than a width of the third opening, wherein the third opening and the fourth opening overlap each other, wherein a corner between the third opening and the fourth opening of the insulating layer is curved.

[0008] According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device includes the steps of: forming an insulating layer; forming a hard mask layer including a first opening on the insulating layer; forming a second opening by etching the insulating layer using the hard mask layer as an etching barrier; exposing a top surface of the insulating layer by enlarging the first opening of the hard mask layer; after the first opening is enlarged, forming a third opening and a fourth opening in the insulating layer by etching the insulating layer using the hard mask layer as an etching barrier; and forming a bonding pad in the third opening and the fourth opening, wherein a width of the fourth opening is greater than a width of the third opening, wherein the third opening and the fourth opening overlap each other. BRIEF DESCRIPTION OF DRAWINGS

[0009] Example embodiments are described herein below with reference to the drawings; however, they can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0010] In the drawings, the size of some of the elements can be exaggerated and not to scale for illustrative clarity. It will be understood that when an element is referred to as being "on" another element, it can be directly on the element or an intervening element can also be present. Like reference numerals refer to like elements throughout.

[0011] FIG. 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0012] FIG. 1B is a cross-sectional view taken along the line A-A' shown in FIG. 1A

[0013] FIG. 2A to FIG. 2F is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 1A FIG. 1B

[0014] FIG. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0015] FIG. 4 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0016] FIG. 5A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0017] FIG. 5B is a plan view of a second bonding structure of a first region viewed along the line B-B' shown in FIG. 5A

[0018] FIG. 5C is a plan view of a second bonding structure of a second region viewed along the line B-B' shown in FIG. 5A

[0019] FIG. 6 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0020] FIG. 7A to FIG. 7H is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5C

[0021] FIG. 8 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0022] FIG. 9 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] ​​​​​​To describe embodiments according to the concepts of the present disclosure, the specific configurations and functional descriptions disclosed herein are only illustrative. Embodiments according to the concepts of the present disclosure can be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein.

[0024] Some embodiments relate to a semiconductor device capable of improving operation reliability and a manufacturing method of the semiconductor device.

[0025] FIG. 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 1B is a cross-sectional view taken along FIG. 1A the line A-A' shown.

[0026] Referring to FIG. 1A and FIG. 1B , the semiconductor device can include a first insulating layer 110, a second insulating layer 120, a conductor CB, and a bonding pad BP.

[0027] The first insulating layer 110 can have a shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can be different intersecting directions. In an example, the first direction D1 and the second direction D2 can be orthogonal to each other. The first insulating layer 110 can include an insulating material. In an example, the first insulating layer 110 can include an oxide or a nitride.

[0028] The conductor CB can be disposed in the first insulating layer 110. The conductor CB can extend in the second direction D2. A top surface of the conductor CB can be located on the same plane as a top surface of the first insulating layer 110. The conductor CB can include an electrically conductive material. In an example, the conductor CB can include copper, aluminum, or tungsten.

[0029] The second insulating layer 120 can be disposed on the first insulating layer 110. The second insulating layer 120 can have a shape of a plate extending along a plane defined by the first direction D1 and the second direction D2. The second insulating layer 120 can include an insulating material. In an example, the second insulating layer 120 can include SiCN.

[0030] The bonding pad BP can be disposed in the second insulating layer 120. The bonding pad PB can penetrate the second insulating layer 120 in a third direction D3. The third direction D3 can intersect the first direction D1 and the second direction D2. In an example, the third direction D3 can be orthogonal to the first direction D1 and the second direction D2.

[0031] The bonding pad BP can include a conductive portion BP_C and a barrier portion BP_B. The barrier portion BP_B can be disposed on a surface of the second insulating layer 120. The conductive portion BP_C can be disposed on a surface of the barrier portion BP_B. The barrier portion BP_B can be disposed between the conductive portion BP_C and the second insulating layer 120. The conductive portion BP_C and the second insulating layer 120 can be spaced apart from each other by the barrier portion BP_B.

[0032] The conductive portion BP_C can include a conductive material. In an example, the conductive portion BP_C can include copper, aluminum, or tungsten. In an example, the barrier portion BP_B can include titanium, titanium nitride, tantalum, or tantalum nitride.

[0033] The bonding pad BP can include first side walls SW1 facing each other in the first direction D1 and second side walls SW2 facing each other in the second direction D2. The first side walls SW1 and the second side walls SW2 can be connected to each other. The second side walls SW2 can connect the first side walls SW1 to each other. The first side walls SW1 can connect the second side walls SW2 to each other. The first side walls SW1 and the second side walls SW2 of the bonding pad BP can be defined by a surface of the barrier portion BP_B.

[0034] Each of the first side walls SW1 of the bonding pad BP can include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2. The first flat portion F1 can be connected to the first curved portion C1. The first curved portion C1 can be connected to the second curved portion C2. The second flat portion F2 can be connected to the second curved portion C2. The first flat portion F1, the first curved portion C1, the second curved portion C2, and the second flat portion F2 are connected to constitute the first side wall SW1 of the bonding pad BP.

[0035] The first flat portion F1 can be connected to the bottom surface BS of the bonding pad BP. The second flat portion F2 can be connected to the top surface TS of the bonding pad BP. From a cross-sectional angle shown in FIG. 6A, the first flat portion F1 and the second flat portion F2 can be represented as straight lines. In an example, from a cross-sectional angle shown in FIG. 6B, the first flat portion F1 and the second flat portion F2 can be represented as curved lines. FIG. 1B FIG. 1B From a cross-sectional angle shown in FIG. 6A, a first center of curvature C1_C of the first curved portion C1 can be located outside the bonding pad BP. In an example, from a cross-sectional angle shown in FIG. 6B, the first center of curvature C1_C of the first curved portion C1 can be located inside the bonding pad BP. FIG. 1B From a cross-sectional angle shown in FIG. 6A, a second center of curvature C2_C of the second curved portion C2 can be located inside the bonding pad BP.

[0036] ​The first curved portions C1 and the second curved portions C2 can be curved in different directions. In an example, the first curved portions C1 can be curved such that the central portions of the first curved portions C1 protrude toward the inside of the bond pad BP (in a convex shape), and the second curved portions C2 can be curved such that the central portions of the second curved portions C2 protrude toward the outside of the bond pad BP (in a convex shape).

[0037] A distance between the first flat portions F1 in the first direction D1 can be defined as a first distance L1. The first distance L1 can decrease as the first flat portions F1 get closer to the conductor CB. A distance between the second flat portions F2 in the first direction D1 can be defined as a second distance L2. The second distance L2 can decrease as the second flat portions F2 get closer to the conductor CB. Alternatively, the second distance L2 can be constant at all levels. The second distance L2 can be greater than the first distance L1.

[0038] A distance between the first curved portions C1 in the first direction D1 and a distance between the second curved portions C2 in the first direction D1 can be defined as a third distance L3. The third distance L3 can decrease as the first curved portions C1 and the second curved portions C2 get closer to the conductor CB. A maximum value of the third distance L3 can be equal to a minimum value of the second distance L2. A minimum value of the third distance L3 can be equal to a maximum value of the first distance L1.

[0039] The bond pad BP can include a first portion PA1, a second portion PA2, and a third portion PA3. The first portion PA1 can be a portion connected to the conductor CB. The second portion PA2 can be a portion connected to the first portion PA1. The third portion PA3 can be a portion connected to the second portion PA2. The second portion PA2 can be disposed between the first portion PA1 and the third portion PA3.

[0040] A sidewall of the first portion PA1 can be defined by the first flat portions F1. The sidewall of the first portion PA1 can be flat. A sidewall of the second portion PA2 can be defined by the first curved portions C1 and the second curved portions C2. The sidewall of the second portion PA2 can be curved. The first curved portions C1 can be formed at a portion of the sidewall of the second portion PA2 connected to the first portion PA1. The second curved portions C2 can be formed at a portion of the sidewall of the second portion PA2 connected to the third portion PA3. A sidewall of the third portion PA3 can be defined by the second flat portions F2. The sidewall of the third portion PA3 can be flat.

[0041] A width of the first portion PA1 can decrease as the first portion PA1 gets closer to the conductor CB. In an example, a width of the first portion PA1 in the first direction D1 can decrease as the first portion PA1 gets closer to the conductor CB. The width of the first portion PA1 in the first direction D1 can be equal to the first distance L1.

[0042] The width of the second portion PA2 can decrease as the second portion PA2 gets closer to the conductor CB. In an example, the width of the second portion PA2 in the first direction D1 can decrease as the second portion PA2 gets closer to the conductor CB. The width of the second portion PA2 in the first direction D1 can be equal to the third distance L3.

[0043] The width of the third portion PA3 can decrease as the third portion PA3 gets closer to the conductor CB. In an example, the width of the third portion PA3 in the first direction D1 can decrease as the third portion PA3 gets closer to the conductor CB. The width of the third portion PA3 in the first direction D1 can be equal to the second distance L2.

[0044] Similar to the first side wall SW1, each second side wall SW2 of the bonding pad BP can include a curved portion and a flat portion.

[0045] In the semiconductor device according to the embodiment, the side wall of the bonding pad BP includes a curved portion, and the width of the third portion PA3 as the upper portion of the bonding pad BP is relatively large. Thus, the bonding pad BP can have improved gap fill characteristics, and the bonding pad BP can be formed without any void. Further, since the width of the first portion PA1 as the lower portion of the bonding pad BP is relatively small, an overlap margin between the conductor CB and the bonding pad BP can be ensured.

[0046] FIG. 2A to FIG. 2F is a cross-sectional view illustrating FIG. 1A and FIG. 1B a manufacturing method of the semiconductor device. For simplicity, redundant descriptions of components already described with reference to FIG. 1A and FIG. 1B will be omitted.

[0047] The manufacturing method described below is merely an embodiment of a manufacturing method of the semiconductor memory device shown in FIG. 1A and FIG. 1B , and the manufacturing method of the semiconductor memory device shown in FIG. 1A and FIG. 1B is not limited to the manufacturing method described below.

[0048] With reference to FIG. 2A , the conductor CB can be formed in the first insulating layer 110. The trench can be formed by etching the first insulating layer 110, and the conductor CB can be formed in the trench. The conductor CB can be an interconnection structure. In an example, the conductor CB can be a bit line, a contact plug, or a wire.

[0049] The first insulating layer 110 can include an insulating material. In an example, the first insulating layer 110 can include an oxide or a nitride. The conductor CB can include a conductive material. In an example, the conductor CB can include copper, aluminum, or tungsten.

[0050] A second insulating layer 120 can be formed on the first insulating layer 110. The second insulating layer 120 can include an insulating material. In an example, the second insulating layer 120 can include SiCN. In an example, the second insulating layer 120 can be a single layer.

[0051] A first hard mask layer MA1 can be formed on the second insulating layer 120. A thickness of the first hard mask layer MA1 can be greater than a thickness of the second insulating layer 120. A length of the first hard mask layer MA1 in the third direction D3 can be greater than a length of the second insulating layer 120 in the third direction D3. In an example, the first hard mask layer MA1 can include amorphous carbon.

[0052] A second hard mask layer MA2 can be formed on the first hard mask layer MA1. The second hard mask layer MA2 can include an insulating material. In an example, the second hard mask layer MA2 can include SiON.

[0053] Referring to FIG. 2B A photoresist pattern PR can be formed on the second hard mask layer MA2. After forming a photoresist layer on the second hard mask layer MA2, the photoresist pattern PR can be formed by patterning the photoresist layer through an exposure process and a development process.

[0054] Subsequently, the second hard mask layer MA2 and the first hard mask layer MA1 can be etched using the photoresist pattern PR as an etching barrier. Accordingly, the first hard mask layer MA1 and the second hard mask layer MA2 can be patterned, and a first opening OP1 can be formed in the first hard mask layer MA1.

[0055] Subsequently, the second insulating layer 120 can be etched using the first hard mask layer MA1 as an etching barrier. Accordingly, the second insulating layer 120 can be patterned, and a second opening OP2 can be formed in the second insulating layer 120.

[0056] The second opening OP2 can be formed such that the conductor CB is not exposed. The second opening OP2 can penetrate a portion of the second insulating layer 120. The second opening OP2 can not completely penetrate the second insulating layer 120.

[0057] A bottom surface OP2_B of the second opening OP2 can be defined by the second insulating layer 120. A level of the bottom surface OP2_B of the second opening OP2 can be higher than a level of a bottom surface of the second insulating layer 120. The bottom surface OP2_B of the second opening OP2 can be spaced apart from the conductor CB in the third direction D3. A portion of the second insulating layer 120 can be disposed between the bottom surface OP2_B of the second opening OP2 and the conductor CB.

[0058] A width of the second opening OP2 in the first direction D1 can be defined as a first width W1. The first width W1 can be substantially equal to a width of the conductor CB in the first direction D1. A width of the first opening OP1 can be substantially equal to a width of the second opening OP2. A width of the first opening OP1 in the first direction D1 can be equal to the first width W1.

[0059] In an embodiment, as shown in the figures, the photoresist pattern PR and the second hard mask layer MA2 that are left after forming the first opening OP1 and the second opening OP2 can be removed. In another embodiment, unlike shown in the figures, the second opening OP2 can be formed after forming the first opening OP1 and removing the photoresist pattern PR and the second hard mask layer MA2. The second hard mask layer MA2 can protect the first hard mask layer MA1 when the photoresist pattern PR is removed. When the photoresist pattern PR and the second hard mask layer MA2 are removed after forming the first opening OP1, a top surface of the first hard mask layer MA1 can be exposed in the process of forming the second opening OP2, and a portion of the top surface of the first hard mask layer MA1 can be etched.

[0060] Referring to FIG. 2C The first opening OP1 of the first hard mask layer MA1 can be enlarged. By etching the first hard mask layer MA1, the first hard mask layer MA1 can be reduced, and the first opening OP1 can be enlarged. In an example, the first hard mask layer MA1 can be etched using an isotropic etching process. According to the etching process, a length (height) of the first hard mask layer MA1 in the third direction D3 can be reduced, and a width of the first opening OP1 can be increased. In an example, a width of the first opening OP1 in the first direction D1 can be increased to a second width W2. The second width W2 can be greater than the first width W1. When the first opening OP1 is enlarged, a top surface of the second insulating layer 120 can be exposed. When the first opening OP1 is enlarged, a first corner CO1 between the top surface of the second insulating layer 120 and a sidewall of the second opening OP2 can be exposed. When the first opening OP1 is enlarged, a first contact point PC between the top surface of the second insulating layer 120 and a sidewall of the first hard mask layer MA1 can be defined. The first contact point PC can be a contact point between the top surface of the second insulating layer 120 and the sidewall of the enlarged first opening OP1.

[0061] Referring to FIG. 2D The second insulating layer 120 can be etched using the first hard mask layer MA1 as an etching barrier. The second insulating layer 120 can be etched through the first opening OP1.

[0062] The second insulating layer 120 can be etched simultaneously with the downward transfer of the first opening OP1 and the second opening OP2. During the transfer of the second opening OP2, a third opening OP3 can be formed in the second insulating layer 120. The third opening OP3 can be formed to expose the conductor CB. During the transfer of the first opening OP1, a fourth opening OP4 can be formed in the second insulating layer 120. The third opening OP3 and the fourth opening OP4 can overlap each other. In this example, the third opening OP3 and the fourth opening OP4 can overlap perpendicularly to each other.

[0063] The width of the third opening OP3 in the first direction D1 can be defined as the third width W3. The width of the fourth opening OP4 in the first direction D1 can be defined as the fourth width W4. The fourth width W4 can be greater than the third width W3. When the third opening OP3 and the fourth opening OP4 are formed, a T-shaped opening can be formed in the second insulating layer 120. The sidewall OP3_S of the third opening OP3 can be flat. The sidewall OP4_S of the fourth opening OP4 can be flat.

[0064] When the second insulating layer 120 is etched, a second corner CO2 and a third corner CO3 can be formed in the second insulating layer 120. The second corner CO2 and the third corner CO3 can be defined by a third opening OP3 and a fourth opening OP4. The second corner CO2 can be formed at the portion where the third opening OP3 and the fourth opening OP4 are connected to each other, and the third corner CO3 can be formed at the portion where the bottom surface OP4_B and the sidewall OP4_S of the fourth opening OP4 are connected to each other.

[0065] CO2 can be released at the second corner of the second insulating layer 120 at the first corner ( FIG. 2C The CO1 shown is formed when it shifts downwards, and at the first corner ( FIG. 2C The CO1 shown is correspondingly provided. CO3 at the third corner of the second insulating layer 120 can be located at the first contact point ( FIG. 2C The PC shown is formed as it moves downwards, and forms contact with the first contact point ( FIG. 2C The settings corresponding to the PC shown.

[0066] In the etching process, due to the first corner ( FIG. 2C The CO1 shown is relatively prominent, so the first corner ( FIG. 2C The CO1 shown can be relatively highly exposed to the etching environment, and the first corner ( FIG. 2C The etching amount of CO1 shown can be relatively large. Therefore, the first corner ( FIG. 2C The CO1 shown can be transferred downwards while rounding, and can form a curved second corner CO2.

[0067] In the etching process, the first contact point ( FIG. 2CThe PC) shown can be relatively lowly exposed to the etching environment, and the first contact point (CP1) can be relatively small. Thus, the PC) shown can be relatively small in size. FIG. 2C The PC) shown can be relatively lowly exposed to the etching environment, and the first contact point (CP1) can be relatively small. Thus, the PC) shown can be relatively small in size. FIG. 2E The PC) shown can be relatively lowly exposed to the etching environment, and the first contact point (CP1) can be relatively small. Thus, the PC) shown can be relatively small in size.

[0068] A bottom surface OP4_B of the fourth opening OP4 can be connected between the second corner CO2 and the third corner CO3 of the second insulating layer 120. The bottom surface OP4_B of the fourth opening OP4 can be flat or curved. The second corner CO2 can be formed between the bottom surface OP4_B of the fourth opening OP4 and the sidewall OP3_S of the third opening OP3. The third corner CO3 can be formed between the bottom surface OP4_B of the fourth opening OP4 and the sidewall OP4_S of the fourth opening OP4.

[0069] A center of curvature of the second corner CO2 can be located in the second insulating layer 120. A center of curvature of the third corner CO3 can be located in the fourth opening OP4.

[0070] Referring to FIG. 1A, a first hard mask layer MA1 can be formed on the first insulating layer 110. The first hard mask layer MA1 can include a first portion PA1, a second portion PA2, and a third portion PA3. The first portion PA1 of the first hard mask layer MA1 can be formed in the third opening OP3. The second portion PA2 and the third portion PA3 of the first hard mask layer MA1 can be formed in the fourth opening OP4. FIG. 2F The first hard mask layer MA1 can be removed. In an example, the first hard mask layer MA1 can be removed by a cleaning process.

[0071] Referring to FIG. 1A, a first hard mask layer MA1 can be formed on the first insulating layer 110. The first hard mask layer MA1 can include a first portion PA1, a second portion PA2, and a third portion PA3. The first portion PA1 of the first hard mask layer MA1 can be formed in the third opening OP3. The second portion PA2 and the third portion PA3 of the first hard mask layer MA1 can be formed in the fourth opening OP4. FIG. 3 The bonding pad BP can be formed in the second insulating layer 120. A first portion PA1 of the bonding pad BP can be formed in the third opening OP3. A second portion PA2 and a third portion PA3 of the bonding pad BP can be formed in the fourth opening OP4.

[0072] The bonding pad BP can include a conductive portion BP_C and a barrier portion BP_B.

[0073] A first sidewall SW1 of the bonding pad BP can include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2. A sidewall of the first portion PA1 of the bonding pad BP can be flat while being in contact with the sidewall OP3_S of the third opening OP3 of the second insulating layer 120. A sidewall of the second portion PA2 of the bonding pad BP can be curved while being in contact with the second corner CO2 and the third corner CO3 of the second insulating layer 120 and the bottom surface OP4_B of the fourth opening OP4. A sidewall of the third portion PA3 of the bonding pad BP can be flat while being in contact with the sidewall OP4_S of the fourth opening OP4 of the second insulating layer 120.

[0074] When the bonding pad BP is formed in the second insulating layer 120, a width of the third portion PA3 as an upper portion of the bonding pad BP in the first direction D1 can be greater than a width of the first portion PA1 as a lower portion of the bonding pad BP.

[0075] Since the fourth opening OP4 of the second insulating layer 120 has a relatively large width, the bonding pad BP can be formed without any void. Since the third opening OP3 of the second insulating layer 120 has a relatively small width, an overlap margin between the bonding pad BP and the conductor CB can be secured.

[0076] In the method of manufacturing the semiconductor device according to the embodiment, the second opening OP2 in the second insulating layer 120 and the first opening OP1 in the first hard mask layer MA1 are formed, and then the first opening OP1 is enlarged. Subsequently, the second insulating layer 120 is etched through the enlarged first opening OP1. Thus, the third opening OP3 and the fourth opening OP4 having different widths are formed as a single layer in the second insulating layer 120.

[0077] The third opening OP3 and the fourth opening OP4 are formed by one etching process, so that the cost and time of the etching process can be reduced, and the curved second corner CO2 and the third corner CO3 can be formed in the second insulating layer 120. The bonding pad BP is formed in the second insulating layer 120 in which the curved second corner CO2 and the third corner CO3 are formed, so that the gap fill property of the bonding pad BP can be improved, and the bonding pad BP can be formed without any void.

[0078] FIG. 1A is a cross-sectional view of a semiconductor device according to an embodiment of the disclosure.

[0079] The semiconductor device according to the embodiment can be similar to the semiconductor device shown in FIG. 1B and FIG. 3 except for the following parts.

[0080] Referring to FIG. 4 , the semiconductor device according to the embodiment can include a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, and a fourth insulating layer 140.

[0081] The first conductor CB1 can be disposed in the first insulating layer 110, the first bonding pad BP1 can be disposed in the second insulating layer 120, the second bonding pad BP2 can be disposed in the third insulating layer 130, and the second conductor CB2 can be disposed in the fourth insulating layer 140.

[0082] The first conductor CB1 can be connected to the first bonding pad BP1, the first bonding pad BP1 can be connected to the second bonding pad BP2, and the second bonding pad BP2 can be connected to the second conductor CB2. The first conductor CB1 and the second conductor CB2 can be electrically connected to each other through the first bonding pad BP1 and the second bonding pad BP2.

[0083] The first bonding pad BP1 can include a conductive portion BP1_C and a barrier portion BP1_B. The second bonding pad BP2 can include a conductive portion BP2_C and a barrier portion BP2_B. A sidewall of each of the first bonding pad BP1 and the second bonding pad BP2 can include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2.

[0084] The first flat portion F1 of each of the first bonding pad BP1 and the second bonding pad BP2 can be connected to the first conductor CB1 or the second conductor CB2. The second flat portion F2 of the first bonding pad BP1 can be connected to the third insulating layer 130. The second flat portion F2 of the second bonding pad BP2 can be connected to the first bonding pad BP1.

[0085] A portion of a top surface of the first bonding pad BP1 can be in contact with a bottom surface of the second bonding pad BP2. Another portion of the top surface of the first bonding pad BP1 can be in contact with a portion of a bottom surface of the third insulating layer 130. A width of the top surface of the first bonding pad BP1 in the first direction D1 can be greater than a width of the bottom surface of the second bonding pad BP2 in the first direction D1.

[0086] FIG. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the disclosure.

[0087] The semiconductor device according to the embodiment can be similar to the semiconductor device shown in FIG. 4 except for the following portions.

[0088] Referring to FIG. 5A , the semiconductor device according to the embodiment can include a first insulating layer 110, a second insulating layer 120, a fifth insulating layer 150, a sixth insulating layer 160, and a seventh insulating layer 170.

[0089] The first conductor CB1 can be disposed in the first insulating layer 110, the first bonding pad BP1 can be disposed in the second insulating layer 120, the third bonding pad BP3 can be disposed in the fifth insulating layer 150, the contact CT can be disposed in the sixth insulating layer 160, and the second conductor CB2 can be disposed in the seventh insulating layer 170.

[0090] The first conductor CB1 can be connected to the first bonding pad BP1, the first bonding pad BP1 can be connected to the third bonding pad BP3, the third bonding pad BP3 can be connected to the contact CT, and the contact CT can be connected to the second conductor CB2. The first conductor CB1 and the second conductor CB2 can be electrically connected to each other through the contact CT, the third bonding pad BP3, and the first bonding pad BP1.

[0091] The first bonding pad BP1 can include a conductive portion BP1_C and a barrier portion BP1_B. The third bonding pad BP3 can include a conductive portion BP3_C and a barrier portion BP3_B. The contact CT can include a conductive portion CT_C and a barrier portion CT_B.

[0092] The sidewall SW of the first bonding pad BP1 can include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2. The sidewall of the third bonding pad BP3 can be flat. The sidewall of the contact CT can be flat.

[0093] FIG. 5B is a cross-sectional view of a semiconductor device according to an embodiment of the disclosure. FIG. 5A is a plan view of a second bonding structure of the first region viewed along FIG. 5C the line B-B’. FIG. 5A is a plan view of a second bonding structure of the second region viewed along FIG. 5A the line B-B’.

[0094] Referring to FIG. 5B , a semiconductor device according to the embodiment can include a first semiconductor structure SEM1, a second semiconductor structure SEM2, a first bonding structure BDS1, and a second bonding structure BDS2.

[0095] The first semiconductor structure SEM1 and the second semiconductor structure SEM2 can be spaced apart from each other. The first semiconductor structure SEM1 and the first bonding structure BDS1 can be connected to each other, the first bonding structure BDS1 and the second bonding structure BDS2 can be connected to each other, and the second bonding structure BDS2 and the second semiconductor structure SEM2 can be connected to each other. The first semiconductor structure SEM1 and the second semiconductor structure SEM2 can be electrically connected to each other through the first bonding structure BDS1 and the second bonding structure BDS2.

[0096] The semiconductor device can include a first region RG1 and a second region RG2. Each of the first semiconductor structure SEM1, the second semiconductor structure SEM2, the first bonding structure BDS1, and the second bonding structure BDS2 can be divided into the first region RG1 and the second region RG2.

[0097] The first semiconductor structure SEM1 can include a substrate 100, a first transistor TR1 and a second transistor TR2 in the substrate 100, and a first connection structure CNS1.

[0098] The first transistor TR1 can be disposed in the substrate 100 of the first region RG1. In an example, the first transistor TR1 can be a transistor constituting a page buffer. In an example, the substrate 100 can be a semiconductor substrate.

[0099] Each first transistor TR1 can include a first impurity region IR1 and a first gate structure. In an example, the first impurity region IR1 can be formed by doping the substrate 100 with an impurity. In an example, the first gate structure can include a gate electrode GE and a gate insulating layer GI between the gate electrode GE and the substrate 100.

[0100] An isolation layer 101 can be provided in the substrate 100 of the first region RG1. The isolation layer 101 can electrically isolate the first transistors TR1 from each other. The isolation layer 101 can include an insulating material.

[0101] The first connection structure CNS1 can include a first insulating layer 111, a first contact CT1, and a first conductor CB1’. The first insulating layer 111 can be formed on the substrate 100. The first contact CT1 and the first conductor CB1’ can be provided in the first insulating layer 111 of the first region RG1.

[0102] The first insulating layer 111 can include an insulating material. The first contact CT1 and the first conductor CB1’ can include an electrically conductive material.

[0103] The first contact CT1 and the first conductor CB1’ can be electrically connected to the first transistors TR1 in the substrate 100.

[0104] The first bonding structure BDS1 can include a second insulating layer 121, a third insulating layer 131, a second contact CT2, and a first bonding pad BP1’. The second insulating layer 121 can be formed on the first insulating layer 111, and the third insulating layer 131 can be formed on the second insulating layer 121.

[0105] The second contact CT2 can be provided in the second insulating layer 121 of the first region RG1. The first bonding pad BP1’ can be provided in the third insulating layer 131 of the first region RG1. Each of the second contact CT2 and the first bonding pad BP1’ can include an electrically conductive portion and a barrier portion. A sidewall of each of the second contact CT2 and the first bonding pad BP1’ can be flat.

[0106] The second insulating layer 121 and the third insulating layer 131 can include an insulating material. The second contact CT2 and the first bonding pad BP1’ can include an electrically conductive material. The second contact CT2 can be connected to the first conductor CB1’, and the first bonding pad BP1’ can be connected to the second contact CT2.

[0107] The second bonding structure BDS2 can include a fourth insulating layer 141 and a second bonding pad BP2’. The fourth insulating layer 141 can be formed on the third insulating layer 131.

[0108] A second bonding pad BP2' can be disposed in the fourth insulating layer 141 of the first region RG1. Each second bonding pad BP2' can include a conductive portion and a barrier portion. A sidewall of the second bonding pad BP2' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The first curved portion C1' and the second curved portion C2' can be disposed between the first flat portion F1' and the second flat portion F2'.

[0109] The fourth insulating layer 141 can include an insulating material. In an example, the fourth insulating layer 141 can include SiCN. The second bonding pad BP2' can include a conductive material. The second bonding pad BP2' can be connected to the first bonding pad BP1'.

[0110] The second semiconductor structure SEM2 can include a memory array AR and a second connection structure CNS2.

[0111] The second connection structure CNS2 can include a fifth insulating layer 151, a sixth insulating layer 161, a seventh insulating layer 171, a bit line BL, a third contact CT3, and a fourth contact CT4.

[0112] The fifth insulating layer 151 can be formed on the fourth insulating layer 141, the sixth insulating layer 161 can be formed on the fifth insulating layer 151, and the seventh insulating layer 171 can be formed on the sixth insulating layer 161.

[0113] The bit line BL can be disposed in the fifth insulating layer 151 and the sixth insulating layer 161 of the first region RG1. The third contact CT3 can be disposed in the sixth insulating layer 161 and the seventh insulating layer 171 of the first region RG1. The fourth contact CT4 can be disposed in the seventh insulating layer 171 of the first region RG1.

[0114] The fifth to seventh insulating layers 151, 161, and 171 can include an insulating material. In an example, the fifth insulating layer 151 and the seventh insulating layer 171 can include an oxide. In an example, the sixth insulating layer 161 can include a nitride. The third contact CT3 and the fourth contact CT4 can include a conductive material. The bit line BL can include a conductive material.

[0115] The bit line BL can be connected to the second bonding pad BP2', the third contact CT3 can be connected to the bit line BL, and the fourth contact CT4 can be connected to the third contact CT3.

[0116] A width of the bit line BL can be equal to a width of a bottom surface of the second bonding pad BP2'. In an example, a width of the bit line BL in the first direction D1 can be equal to a width of the bottom surface of the second bonding pad BP2' in the first direction D1.

[0117] Referring to FIG. 5AThe bit lines BL can extend in a second direction D2. The bit lines BL can be spaced apart from each other in a first direction D1. The second bonding pad BP2’ can overlap with the plurality of bit lines BL.

[0118] Referring back to FIG. 5C The memory array AR can be disposed on the second connection structure CNS2. The memory array AR can include the stack structure STA, the channel structure CS, and the memory layer ML.

[0119] The stack structure STS can be disposed on the seventh insulating layer 171. The stack structure STS can include conductive patterns CP and insulating patterns IP alternately stacked. The conductive patterns CP can include a conductive material. In an example, the conductive patterns CP can include at least one of a doped silicon layer, a metal silicide layer, tungsten, nickel, and cobalt. The insulating patterns IP can include an insulating material. In an example, the insulating patterns IP can include an oxide.

[0120] The channel structure CS and the memory layer ML can penetrate the stack structure STS. The channel structure CS can include a fill layer FI and a channel layer CL surrounding the fill layer FI. The memory layer ML can include a tunnel insulating layer TL surrounding the channel structure CS, a data storage layer DL surrounding the tunnel insulating layer TL, and a blocking layer BKL surrounding the data storage layer DL.

[0121] The fill layer FI can include an insulating material. In an example, the fill layer FI can include an oxide. The channel layer CL can include a semiconductor material. In an example, the channel layer CL can include polysilicon. The tunnel insulating layer TL can include a material through which charges can tunnel. In an example, the tunnel insulating layer TL can include an oxide. In an example, the data storage layer DL can include a nitride that can trap charges. However, the material included in the data storage layer DL is not limited to a nitride and can vary according to different data storage methods. In an example, the data storage layer DL can include silicon, a phase change material, or a nanodot. The blocking layer BKL can include a material capable of blocking the movement of charges. In an example, the blocking layer BKL can include an oxide.

[0122] The channel structure CS can be connected to the fourth contact CT4. The channel structure CS can be electrically connected to the first transistor TR1 in the substrate 100 through the fourth contact CT4, the third contact CT3, the bit line BL, the second bonding pad BP2’, the first bonding pad BP1’, the second contact CT2, the first conductor CB1’, and the first contact CT1.

[0123] The memory array AR can be electrically connected to the fourth contact CT4, the third contact CT3, the bit line BL, the second bonding pad BP2’, the first bonding pad BP1’, the second contact CT2, the first conductor CB1’, and the first contact CT1 to be electrically connected to the first transistor TR1 in the substrate 100.

[0124] The second transistor TR2 can be disposed in the substrate 100 of the second region RG2. In an example, the second transistor TR2 can be a pass transistor connected to an X decoder.

[0125] Each second transistor TR2 can include a second impurity region IR2 and a second gate structure. In an example, the second impurity region IR2 can be formed by doping the substrate 100 with an impurity. In an example, similar to the first gate structure, the second gate structure can include a gate electrode and a gate insulating layer between the gate electrode and the substrate 100.

[0126] An isolation layer 101 can be disposed in the substrate 100 of the second region RG2. The isolation layer 101 can electrically isolate the second transistors TR2 from each other.

[0127] A fifth contact CT5 and a second conductor CB2' can be disposed in the first insulating layer 111 of the second region RG2. The fifth contact CT5 can be connected to the second transistor TR2. The second conductor CB2' can be connected to the fifth contact CT5.

[0128] A sixth contact CT6 can be disposed in the second insulating layer 121 of the second region RG2. A third bonding pad BP3' can be disposed in the third insulating layer 131 of the second region RG2. Each of the sixth contact CT6 and the third bonding pad BP3' can include a conductive portion and a barrier portion. The sixth contact CT6 and the third bonding pad BP3' can include a conductive material.

[0129] The sixth contact CT6 can be connected to the second conductor CB2'. The third bonding pad BP3' can be connected to the sixth contact CT6. A sidewall of each of the sixth contact CT6 and the third bonding pad BP3' can be flat.

[0130] A fourth bonding pad BP4' can be disposed in the fourth insulating layer 141 of the second region RG2. The fourth bonding pad BP4' can include a conductive portion and a barrier portion. A sidewall of the fourth bonding pad BP4' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The first curved portion C1' and the second curved portion C2' can be disposed between the first flat portion F1' and the second flat portion F2'.

[0131] The fourth bonding pad BP4' can include a conductive material. The fourth bonding pad BP4' can be connected to the third bonding pad BP3'.

[0132] The third conductor CB3' can be provided in the fifth insulating layer 151 and the sixth insulating layer 161 of the second region RG2. The seventh contact CT7 can be provided in the sixth insulating layer 161 and the seventh insulating layer 171 of the second region RG2. The eighth contact CT8 can be provided in the seventh insulating layer 171 of the second region RG2.

[0133] Referring to FIG. 5A , the third conductor CB3' can include first to third portions CB3'_a, CB3'_b, and CB3'_c. The first portion CB3'_a and the third portion CB3'_c can extend in the second direction D2. The second portion CB3'_b can extend in the first direction D1 and connect the first portion CB3'_a and the third portion CB3'_c. The first portion CB3'_a can be connected to the fourth bonding pad BP4'. The fourth bonding pad BP4' can overlap with the first portion CB3'_a of the third conductor CB3'.

[0134] Referring back to FIG. 6 , the third conductor CB3', the seventh contact CT7, and the eighth contact CT8 can include a conductive material. The third conductor CB3' can be connected to the fourth bonding pad BP4', the seventh contact CT7 can be connected to the third conductor CB3', and the eighth contact CT8 can be connected to the seventh contact CT7.

[0135] The eighth insulating layer 181 can be provided on the seventh insulating layer 171 of the second region RG2. The stacked structure STS can be provided on the eighth insulating layer 181. The eighth insulating layer 181 can include an insulating material.

[0136] The stacked structure STS of the second region RG2 can have a stepped structure. The insulating pattern IP and the conductive pattern CP of the stacked structure STS of the second region RG2 are formed in the shape of a step, so that a stepped structure can be formed.

[0137] The ninth contact CT9 can be provided in the seventh insulating layer 171 and the eighth insulating layer 181. The ninth contact CT9 can be connected to the eighth contact CT8. The ninth contact CT9 can be connected to the conductive pattern CP of the stacked structure STS. The ninth contact CT9 can include a conductive material.

[0138] The conductive pattern CP can be electrically connected to the second transistor TR2 through the ninth contact CT9, the eighth contact CT8, the seventh contact CT7, the third conductor CB3', the fourth bonding pad BP4', the third bonding pad BP3', the sixth contact CT6, the second conductor CB2', and the fifth contact CT5.

[0139] In the semiconductor device according to the embodiment, since the width of the portion of the second bonding pad BP2' connected to the bit line BL is relatively small, an overlap margin between the bit line BL and the second bonding pad BP2' can be secured.

[0140] In the semiconductor device according to this embodiment, since the portion of the fourth bonding pad BP4' connected to the third conductor CB3' is relatively small in width, an overlap margin between the third conductor CB3' and the fourth bonding pad BP4' can be ensured.

[0141] FIG. 5A to FIG. 5C is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0142] The semiconductor device according to this embodiment can be similar to the semiconductor device shown in FIG. 6 except for the following portions.

[0143] Referring to FIG. 7A to FIG. 7H In the semiconductor device according to this embodiment, the first bonding structure BDS1 can include a ninth insulating layer 191. The ninth insulating layer 191 can be disposed between the first insulating layer 111 and the fourth insulating layer 141.

[0144] A fifth bonding pad BP5' can be disposed in the ninth insulating layer 191 of the first region RG1. A sidewall of the fifth bonding pad BP5' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The fifth bonding pad BP5' can be connected to the second bonding pad BP2' of the second bonding structure BDS2.

[0145] A sidewall of the second bonding pad BP2' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'.

[0146] A sixth bonding pad BP6' can be disposed in the ninth insulating layer 191 of the second region RG2. A sidewall of the sixth bonding pad BP6' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The sixth bonding pad BP6' can be connected to the fourth bonding pad BP4' of the second bonding structure BDS2.

[0147] A sidewall of the fourth bonding pad BP4' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'.

[0148] The fifth bonding pad BP5' can be connected to the first transistor TR1 through the first conductor CB1' and the first contact CT1 of the first connection structure CNS1. In an example, the first transistor TR1 can be a transistor constituting a page buffer.

[0149] The sixth bonding pad BP6' can be connected to the second transistor TR2 through the second conductor CB2' and the fifth contact CT5 of the first connection structure CNS1. In an example, the second transistor TR2 can be a pass transistor connected to an X decoder.

[0150] FIG. 5A to FIG. 5C is a cross-sectional view illustrating FIG. 5A to FIG. 5C a manufacturing method of a semiconductor device.

[0151] For simplicity, redundant descriptions of components already described with reference to FIG. 5A to FIG. 5C will be omitted.

[0152] The manufacturing method described below is merely FIG. 5A to FIG. 5C an embodiment of a manufacturing method of a semiconductor memory device, FIG. 7A the manufacturing method of a semiconductor memory device illustrated in FIG. 12 is not limited to the manufacturing method described below.

[0153] Referring to FIG. 7B , a second semiconductor structure SEM2 can be formed. The second semiconductor structure SEM2 can include a memory array AR and a second connection structure CNS2.

[0154] A fourth insulating layer 141 can be formed on the second connection structure CNS2, a first hard mask layer MA1' can be formed on the fourth insulating layer 141, and a second hard mask layer MA2' can be formed on the first hard mask layer MA1'. In an example, the fourth insulating layer 141 can be a single layer.

[0155] Referring to FIG. 7C , a photoresist pattern PR' can be formed on the second hard mask layer MA2'.

[0156] Subsequently, the second hard mask layer MA2' and the first hard mask layer MA1' can be etched using the photoresist pattern PR' as an etching barrier. Accordingly, the first hard mask layer MA1' and the second hard mask layer MA2' can be patterned, and a first opening OP1' can be formed in the first hard mask layer MA1'.

[0157] Subsequently, the fourth insulating layer 141 can be etched using the first hard mask layer MA1' as an etching barrier. Accordingly, the fourth insulating layer 141 can be patterned, and a second opening OP2' can be formed in the fourth insulating layer 141.

[0158] In an embodiment, as illustrated in the drawing, the photoresist pattern PR' and the second hard mask layer MA2' remaining after the formation of the first opening OP1' and the second opening OP2' can be removed. In another embodiment, unlike as illustrated in the drawing, the second opening OP2' can be formed after the formation of the first opening OP1' and the photoresist pattern PR' and the second hard mask layer MA2' are removed.

[0159] Referring to FIG. 7D The first opening OP1' of the first hard mask layer MA1' can be enlarged. The first hard mask layer MA1' can be reduced and the first opening OP1' can be enlarged by etching the first hard mask layer MA1'. When the first opening OP1' is enlarged, a top surface of the fourth insulating layer 141 can be exposed.

[0160] Referring to FIG. 7C The fourth insulating layer 141 can be etched using the first hard mask layer MA1' as an etching barrier. The fourth insulating layer 141 can be etched through the first opening (OP1') of the first hard mask layer MA1'. FIG. 7C The fourth insulating layer 141 can be etched through the first opening (OP1') of the first hard mask layer MA1'.

[0161] When the fourth insulating layer 141 is etched, the first opening (OP1') and the second opening (OP2') can be transferred in the fourth insulating layer 141. When the second opening (OP2') is transferred, a third opening OP3' can be formed in the fourth insulating layer 141. When the first opening (OP1') is transferred, a fourth opening OP4' can be formed in the fourth insulating layer 141. FIG. 7C FIG. 7C The third opening OP3' of the first region RG1 can be formed to expose the bit line BL. The third opening OP3' of the second region RG2 can be formed to expose the third conductor CB3' electrically connected to the conductive pattern CP of the stacked structure STS. FIG. 7C FIG. 7E The sidewall of the third opening OP3' and the sidewall of the fourth opening OP4' can be flat. A surface of the fourth insulating layer 141 connecting the third opening OP3' and the fourth opening OP4' can be curved. The curved sidewall can be formed in the fourth insulating layer 141 when the fourth insulating layer 141 is etched.

[0162] The first hard mask layer MA1' can be removed.

[0163] The first hard mask layer MA1' can be removed.

[0164] Referring to FIG. 7F The first hard mask layer MA1' can be removed.

[0165] Referring to FIG. 7G The second bonding pad BP2' can be formed in the fourth insulating layer 141 of the first region RG1. The second bonding pad BP2' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The second bonding pad BP2' can be connected to the bit line BL.

[0166] ​​A fourth bonding pad BP4' can be formed in the fourth insulating layer 141 of the second region RG2. The fourth bonding pad BP4' can include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The fourth bonding pad BP4' can be connected to the third conductor CB3' that is electrically connected to the conductive pattern CP of the stacked structure STS. When the second bonding pad BP2' and the fourth bonding pad BP4' are formed, a second bonding structure BDS2 can be formed.

[0167] Referring to FIG. 7H A first semiconductor structure SEM1 and a first bonding structure BDS1 can be formed. The first semiconductor structure SEM1 can include the substrate 100, the first transistor TR1 and the second transistor TR2 in the substrate 100, and a first connection structure CNS1.

[0168] The first bonding structure BDS1 can include a second insulating layer 121 and a third insulating layer 131. A first bonding pad BP1' can be disposed in the third insulating layer 131 of the first region RG1. A third bonding pad BP3' can be disposed in the third insulating layer 131 of the second region RG2. The sidewalls of the first bonding pad BP1' and the third bonding pad BP3' can be flat.

[0169] Referring to FIG. 8 The first bonding structure BDS1 and the second bonding structure BDS2 can be bonded to each other. The first bonding structure BDS1 and the second bonding structure BDS2 can be bonded to each other after the second semiconductor structure SEM2 and the second bonding structure BDS2 are rotated. In an example, the second semiconductor structure SEM2 and the second bonding structure BDS2 can be rotated by 180 degrees.

[0170] When the first bonding structure BDS1 and the second bonding structure BDS2 are bonded to each other, the first semiconductor structure SEM1 and the second semiconductor structure SEM2 can be electrically connected to each other.

[0171] The first bonding pad BP1' of the first bonding structure BDS1 and the second bonding pad BP2' of the second bonding structure BDS2 can be bonded to each other. When the first bonding pad BP1' of the first bonding structure BDS1 and the second bonding pad BP2' of the second bonding structure BDS2 are bonded to each other, the channel structure CS can be electrically connected to the first transistor TR1. In an example, the channel structure CS can be connected to a transistor constituting a page buffer. When the first bonding pad BP1' of the first bonding structure BDS1 and the second bonding pad BP2' of the second bonding structure BDS2 are bonded to each other, the memory array AR can be electrically connected to the first transistor TR1.

[0172] The third bonding pad BP3' of the first bonding structure BDS1 and the fourth bonding pad BP4' of the second bonding structure BDS2 can be bonded to each other. When the third bonding pad BP3' of the first bonding structure BDS1 and the fourth bonding pad BP4' of the second bonding structure BDS2 are bonded to each other, the conductive pattern CP of the stacked structure STS can be electrically connected to the second transistor TR2. In an example, the conductive pattern CP of the stacked structure STS can be connected to a pass transistor connected with an X decoder.

[0173] FIG. 8 is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the disclosure.

[0174] Referring to FIG. 1A , the memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0175] The memory device 1120 can include a structure described with reference to FIG. 1B and FIG. 3 , FIG. 4 , FIG. 5A to FIG. 5C , FIG. 6 or FIG. 9 . The memory device 1120 can be a multi-chip package configured with a plurality of flash memory chips.

[0176] The memory controller 1110 is configured to control the memory device 1120, and can include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation of data exchange with the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected with the memory system 1100. The ECC circuit 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. In addition, the memory controller 1110 can further include a ROM for storing code data, etc. for the host interface.

[0177] The memory system 1100 configured as described above can be a memory card or a solid state drive (SSD) in which the memory device 1120 is combined with the controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0178] FIG. 9 FIG. 1 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0179] Referring to FIG. 8 , the computing system 1200 can include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210, which are electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 can also be included, and an application chip set, a camera image processor, a mobile D-RAM, etc. can also be included.

[0180] The memory system 1210 can be configured with a memory device 1212 and a memory controller 1211 as described with reference to ​

[0181] In the semiconductor device according to the present disclosure, the sidewall of the bonding pad includes a curved portion. Thus, the bonding pad can be formed without any gap, and an overlap margin between the bonding pad and the conductor can be secured.

[0182] Although the present disclosure is illustrated and described with reference to specific embodiments, those skilled in the art will appreciate that various changes in form and detail can be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by not only the appended claims but also equivalents thereof.

[0183] ​In the above-described embodiments, all the steps can be selectively performed, or some steps can be omitted. In each of the embodiments, the steps are not necessarily performed in the order described, but can be rearranged. The embodiments disclosed in the specification and drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made based on the technical idea of the present disclosure.

[0184] Furthermore, embodiments of the present disclosure have been shown and described in the accompanying drawings and specification. Although specific terms have been used herein to describe the embodiments of the present disclosure, those terms are used only for the purpose of describing the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many changes can be made within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that various modifications can be made based on the technical idea of the present disclosure, in addition to the embodiments disclosed herein.

[0185] Cross Reference to Related Applications

[0186] This application claims priority to Korean Patent Application No. 10-2020-0044168, filed on April 10, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device comprising: a first semiconductor structure including a memory array; a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor; a first insulating layer between the first semiconductor structure and the second semiconductor structure; a second insulating layer between the second semiconductor structure and the first insulating layer; a first bonding pad electrically connected to the memory array, the first bonding pad being located in the first insulating layer; and a second bonding pad electrically connected to the first transistor, the second bonding pad being located in the second insulating layer, wherein the first bonding pad and the second bonding pad are in contact with each other, wherein at least one of the first bonding pad and the second bonding pad includes a first portion having a flat sidewall, a second portion having a flat sidewall, and a third portion having a curved sidewall and located between the first portion and the second portion, wherein the first portion, the second portion, and the third portion of the first bonding pad are formed within the first insulating layer as a single layer, and wherein a width of the first portion is greater than a width of the second portion. the memory array includes:

2. The semiconductor device according to claim 1, wherein a stacked structure including an insulating pattern and a conductive pattern; and a trench structure penetrating the stacked structure. the first semiconductor structure further includes a bit line electrically connected to the trench structure, 3. The semiconductor device according to claim 2, wherein wherein the bit line is in contact with the first bonding pad. a width of a bottom surface of the first bonding pad is equal to a width of the bit line.

4. The semiconductor device according to claim 3, wherein the first transistor is a transistor constituting a page buffer.

5. The semiconductor device according to claim 2, wherein 6. A semiconductor device comprising: a first semiconductor structure including a stacked structure, a trench structure penetrating the stacked structure, and a bit line electrically connected to the trench structure; a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor; a first insulating layer between the first semiconductor structure and the second semiconductor structure; a second insulating layer between the second semiconductor structure and the first insulating layer; a first bonding pad located in the first insulating layer, the first bonding pad being electrically connected to the trench structure; and a second bonding pad located in the second insulating layer, the second bonding pad being electrically connected to the first transistor, the second bonding pad being in contact with the first bonding pad, wherein the first bonding pad includes: a first portion in contact with the second bonding pad; a second portion in contact with the bit line; and a third portion between the first portion and the second portion, wherein a sidewall of the third portion is curved, wherein the first portion, the second portion, and the third portion are formed within the first insulating layer as a single layer, wherein sidewalls of the first portion and the second portion are flat, and wherein a width of the first portion is greater than a width of the second portion. the sidewall of the third portion includes a first curved portion and a second curved portion, ​ 7. The semiconductor device according to claim 6, wherein ​ wherein a center of curvature of the first curved portion is located inside the first bonding pad, wherein a center of curvature of the second curved portion is located outside the first bonding pad.

8. The semiconductor device according to claim 6, wherein A sidewall of the second bonding pad is curved.

9. A method of manufacturing a semiconductor device, the method comprising the steps of: forming an insulating layer; forming a hard mask layer including a first opening on the insulating layer; forming a second opening in the insulating layer by etching the insulating layer using the hard mask layer as an etching barrier; enlarging the first opening of the hard mask layer; after the first opening is enlarged, forming a third opening and a fourth opening in the insulating layer by etching the insulating layer using the hard mask layer as an etching barrier; and forming a bonding pad in the third opening and the fourth opening, wherein a width of the fourth opening is greater than a width of the third opening, wherein the third opening and the fourth opening overlap each other, wherein a corner between the third opening and the fourth opening of the insulating layer is curved, wherein the bonding pad includes a first portion having a flat sidewall, a second portion having a flat sidewall, and a third portion having a curved sidewall and located between the first portion and the second portion, wherein the first portion, the second portion, and the third portion are formed within the insulating layer as a single layer, wherein a width of the first portion is greater than a width of the second portion.

10. The method of claim 9, wherein, The step of enlarging the first opening includes the step of etching a top surface and a sidewall of the hard mask layer.

11. The method of claim 9, wherein, The step of forming the third opening and the fourth opening includes the step of transferring the second opening and the first opening in the insulating layer.

12. The method of claim 9, wherein, A bottom surface of the second opening is horizontally higher than a bottom surface of the insulating layer.

13. The method of claim 9, wherein, The step of forming the third opening and the fourth opening includes the step of exposing a conductor below the insulating layer.

14. The method of claim 9, wherein, A corner between a bottom surface and a sidewall of the fourth opening is curved.

15. A method of manufacturing a semiconductor device, the method comprising the steps of: forming an insulating layer; forming a hard mask layer including a first opening on the insulating layer; forming a second opening by etching the insulating layer using the hard mask layer as an etching barrier; exposing a top surface of the insulating layer by enlarging the first opening of the hard mask layer; after the first opening is enlarged, forming a third opening and a fourth opening in the insulating layer by etching the insulating layer using the hard mask layer as an etching barrier; and forming a bonding pad in the third opening and the fourth opening, wherein a width of the fourth opening is greater than a width of the third opening, wherein the third opening and the fourth opening overlap each other, wherein the bonding pad includes a first portion having a flat sidewall, a second portion having a flat sidewall, and a third portion having a curved sidewall and located between the first portion and the second portion, wherein the first portion, the second portion, and the third portion are formed within the insulating layer as a single layer, and The first portion has a width greater than a width of the second portion.

16. The method of claim 15, wherein, The step of forming the third opening and the fourth opening includes a step of forming a first corner curved between the third opening and the fourth opening of the insulating layer.

17. The method of claim 16, wherein, The step of expanding the first opening includes a step of exposing a second corner between a top surface of the insulating layer and a sidewall of the second opening, The first corner is formed while transferring the second corner.

18. The method of claim 16, wherein, A center of curvature of the first corner is located inside the insulating layer.

19. The method of claim 15, wherein, The step of forming the third opening and the fourth opening includes a step of forming a third corner curved between a sidewall and a bottom surface of the fourth opening.

20. The method of claim 19, wherein, The step of expanding the first opening includes a step of forming a contact point between a top surface of the insulating layer and a sidewall of the expanded first opening, The third corner is formed while transferring the contact point.

21. The method of claim 19, wherein, A center of curvature of the third corner is located inside the fourth opening.

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