Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: thinning the substrate from the second surface until the surface of the first isolation layer is exposed; forming a second isolation layer in each active area, wherein the projection of the second isolation layer on the substrate surface is located between the projections of adjacent word line gate structures on the substrate surface; forming a plurality of bit lines on the first surface, and forming a plurality of capacitors on the second surface after the thinning process, wherein the bit lines are parallel to the second direction, and each bit line is electrically connected to a plurality of active areas, and each active area is electrically connected to two capacitors; or forming a plurality of bit lines on the thinned second surface, and forming a plurality of capacitors on the first surface, wherein the bit lines are parallel to the second direction, and each bit line is electrically connected to a plurality of active areas, and each active area is electrically connected to two capacitors, thereby simplifying the difficulty of the process and improving the integration level of the chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of technology today, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory. For applications that store large amounts of data, DRAM is the most commonly used solution.

[0003] The basic storage unit of a dynamic random access memory is composed of a storage transistor and a storage capacitor, and the storage array is composed of multiple storage units. The storage capacitor is used to store charges representing the stored information. The storage transistor is a switch that controls the inflow and release of charges in the storage capacitor. The storage transistor is also connected to the internal circuit in the storage and receives the control signal of the internal circuit. Among them, an active region, a drain region and a gate are formed in the storage transistor. The gate is used to control the flow of current between the source region and the drain region and is connected to the word line. The drain region is used to form a bit line contact region to connect to the bit line. The source region is used to form a storage node contact region to connect to the storage capacitor. With the continuous development of integrated circuit manufacturing technology, it is necessary to further improve the device density of memory chips to obtain a larger data storage capacity.

[0004] In summary, the existing dynamic random access memory needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the memory.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate, the substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active areas and a first isolation layer arranged in an array along a first direction and a second direction, the first isolation layer being located between adjacent active areas, the second direction being at an acute angle to the first direction, the projection pattern of each active area on the first surface or the second surface being a rectangle, and the long side direction of the rectangle being perpendicular to the first direction; a plurality of first grooves located in the substrate, the first grooves extending from the first surface to the second surface, the plurality of first grooves being arranged in parallel along a third direction, the third direction being perpendicular to the first direction, each first groove being located between two adjacent rows of active areas, and the first grooves being disposed along two sides of the third direction. The first groove also runs through several active areas, and the sidewalls and bottom of the first groove expose part of the surface of the active area; a word line gate structure located in the first groove; a second isolation layer located in each of the active areas, and the projection of the second isolation layer on the substrate surface is located between the projections of adjacent word line gate structures on the substrate surface; several bit lines located on the first surface and several capacitors located on the second surface, the bit lines are parallel to the second direction, and each bit line is electrically connected to a group of several active areas, and each active area is electrically connected to two capacitors; or, bit lines located on the second surface and several capacitors located on the first surface, the bit lines are electrically connected to the active areas, the bit lines are parallel to the second direction and arranged along the first direction, and each active area is electrically connected to two capacitors.

[0007] Optionally, the plurality of bit lines are located on the first surface, the plurality of capacitors are located on the second surface, and further include: a plurality of second grooves located in the substrate, the second isolation layer is located in the second grooves, the plurality of second grooves extend from the second surface to the first surface, the plurality of second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, and the second grooves penetrate through the plurality of active areas along the first direction, the projection of the second groove on the substrate surface is located between the projections of adjacent word line gate structures on the substrate surface, the size of the second groove along the normal direction of the substrate surface is smaller than the size of the first isolation layer along the normal direction of the substrate surface; first source and drain regions in the active areas on both sides of the second isolation layer, and one of the capacitors is electrically connected to one of the first source and drain regions.

[0008] Optionally, the bit line is located on the second surface, and the plurality of capacitors are located on the first surface, and further include: a plurality of second grooves located in the substrate, the second isolation layer is located in the second grooves, the second grooves extend from the first surface to the second surface, the plurality of second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, and the second grooves penetrate through the plurality of active areas along the first direction, the projection of the second groove on the substrate surface is located between the projections of adjacent word line gate structures on the substrate surface, the size of the second groove along the normal direction of the substrate surface is smaller than the size of the first isolation layer along the normal direction of the substrate surface; first source and drain regions located in the active areas on both sides of the second isolation layer, the first source and drain regions extend from the first surface to the second surface, and one of the capacitors is electrically connected to one of the first source and drain regions.

[0009] Correspondingly, the technical solution of the present invention also provides a method for forming the above-mentioned semiconductor structure, comprising: providing a substrate, the substrate having a first surface and a second surface relative to each other, the substrate comprising a plurality of active areas and a first isolation layer arranged along a first direction and a second direction, the first isolation layer being located between adjacent active areas, the second direction being at an acute angle to the first direction, the projection pattern of each active area on the first surface or the second surface being a rectangle, and the long side direction of the rectangle being perpendicular to the first direction; forming a plurality of first grooves in the substrate, the first grooves extending from the first surface to the second surface, the plurality of first grooves being arranged in parallel along a third direction, the third direction being perpendicular to the first direction, each first groove being located between two adjacent rows of active areas, and the first grooves also passing through a plurality of active areas on both sides along the third direction, and the sidewalls and A portion of the active area surface is exposed at the bottom; a word line gate structure is formed in the first groove; the substrate is thinned from the second surface until the surface of the first isolation layer is exposed; a second isolation layer is formed in each active area, and the projection of the second isolation layer on the substrate surface is located between the projections of adjacent word line gate structures on the substrate surface; a plurality of bit lines are formed on the first surface, and a plurality of capacitors are formed on the second surface after the thinning process, the bit lines are parallel to the second direction, and each bit line is electrically connected to a plurality of active areas, and each active area is electrically connected to two capacitors; or a plurality of bit lines are formed on the thinned second surface, and a plurality of capacitors are formed on the first surface, the bit lines are parallel to the second direction, and each bit line is electrically connected to a plurality of active areas, and each active area is electrically connected to two capacitors.

[0010] Optionally, the plurality of bit lines are located on the first surface, and the plurality of capacitors are located on the second surface; the method for forming the second isolation layer comprises: after the thinning process and before forming the plurality of capacitors, forming a plurality of second grooves in the substrate, the plurality of second grooves extending from the second surface to the first surface, the plurality of second grooves being arranged along a third direction, the third direction being perpendicular to the first direction, and the second grooves passing through the plurality of active areas along the first direction, the projection of the second groove on the substrate surface being located between the projections of adjacent word line gate structures on the substrate surface, the size of the second groove along the normal direction of the substrate surface being smaller than the size of the first isolation layer along the normal direction of the substrate surface; forming a second isolation layer in the second groove.

[0011] Optionally, after forming the second isolation layer and before forming the plurality of capacitors, the method further includes: implanting first doping ions into the active region from the second surface to form a first source and drain region in the active region.

[0012] Optionally, the method for forming the plurality of capacitors includes: after forming the first source and drain regions, forming a first dielectric layer on the second surface and the first source and drain regions; forming a plurality of third grooves in the first dielectric layer, the third grooves exposing the surfaces of the first source and drain regions; forming the plurality of capacitors in the third grooves, one of the capacitors being electrically connected to one of the first source and drain regions.

[0013] Optionally, a capacitor plug is provided between the capacitor and the first source and drain region; a method for forming the capacitor plug comprises: a first opening is provided in the third groove, the first opening exposes the surface of the first source and drain region; and the capacitor plug is formed in the first opening.

[0014] Optionally, the bit line is located on the first surface, and the method for forming the bit line includes: forming a second dielectric layer on the first surface; forming a plurality of fourth grooves in the second dielectric layer, the fourth grooves extending along the second direction, and one of the fourth grooves exposing a portion of the surface of a plurality of the active areas; and forming the bit line in the fourth groove.

[0015] Optionally, after forming the word line gate structure and before forming the bit line, the method further includes: implanting second doping ions into the active region from the first surface to form a second source and drain region in the active region.

[0016] Optionally, a bit line plug is provided between the bit line and the active area, and a projection of the bit line plug on the substrate surface is located between projections of adjacent word line gate structures on the substrate surface; a method for forming the bit line plug comprises: a second opening is provided in the fourth groove, and the second opening exposes the second source and drain region; and the bit line plug is formed in the second opening.

[0017] Optionally, the plurality of capacitors are located on the first surface; the method for forming the second isolation layer comprises: forming a plurality of second grooves in the substrate, the second grooves extending from the first surface to the second surface, the plurality of second grooves being arranged along a third direction, the third direction being perpendicular to the first direction, and the plurality of second grooves passing through the plurality of active areas along the first direction, the projection of the second groove on the substrate surface being located between the projections of adjacent word line gate structures on the substrate surface, the size of the second groove along the normal direction of the substrate surface being smaller than the size of the first isolation layer along the normal direction of the substrate surface; and forming a second isolation layer in the second groove.

[0018] Optionally, after forming the second isolation layer and before forming the plurality of capacitors, the method further includes: implanting first doping ions into the active region from the first surface to form a first source and drain region in the active region.

[0019] Optionally, the method for forming the plurality of capacitors includes: after forming the first source and drain regions, forming a first dielectric layer on the first surface and the first source and drain regions; forming a plurality of third grooves in the first dielectric layer, the third grooves exposing the surfaces of the first source and drain regions; forming the capacitors in the third grooves, one of the capacitors being electrically connected to one of the first source and drain regions.

[0020] Optionally, a capacitor plug is provided between the capacitor and the first source and drain region, and a method for forming the capacitor plug comprises: providing a first opening in the third groove, wherein the first opening exposes a surface of the first source and drain region; and forming the capacitor plug in the first opening.

[0021] Optionally, the bit line is located on the second surface, and the method for forming the bit line includes: forming a second dielectric layer on the second surface after the thinning process; forming a plurality of fourth grooves in the second dielectric layer, the fourth grooves extending along the second direction, and one of the fourth grooves exposing a portion of the surface of a plurality of the active areas; and forming the bit line in the fourth groove.

[0022] Optionally, after forming the word line gate structure and before forming the bit line, the method further includes: implanting second doping ions into the active region from the second surface to form a second source and drain region in the active region.

[0023] Optionally, a bit line plug is provided between the bit line and the active area, and a projection of the bit line plug on the substrate surface is located between projections of adjacent word line gate structures on the substrate surface; a method for forming the bit line plug comprises: a second opening is provided in the fourth groove, and the second opening exposes the second source and drain region; and the bit line plug is formed in the second opening.

[0024] Optionally, an angle between the second direction and the first direction ranges from 15 degrees to 75 degrees.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a plurality of bit lines are formed on the first surface, and a plurality of capacitors are formed on the second surface after the thinning process, the bit lines are parallel to the second direction, and each bit line is electrically connected to a group of a plurality of active areas, and each active area is electrically connected to two capacitors; or, a plurality of bit lines are formed on the second surface after the thinning process, and a plurality of capacitors are formed on the first surface, the bit lines are parallel to the second direction, and each bit line is electrically connected to a plurality of active areas, and each active area is electrically connected to two capacitors, and the plurality of capacitors and the plurality of bit lines do not require a special alignment process during the formation process, thereby simplifying the difficulty of the process. At the same time, from the perspective of the storage unit arrangement, the bit lines and the capacitors are respectively located on both sides of the active area, and the unit storage unit is 4F. 2 The structure occupies a smaller area and improves the level of chip integration.

[0027] In the semiconductor structure provided by the technical solution of the present invention, a plurality of bit lines located on the first surface and a plurality of capacitors located on the second surface, the bit lines are parallel to the second direction, and each bit line is electrically connected to a group of the active areas, and each active area is electrically connected to two capacitors; or, a bit line located on the second surface and a plurality of capacitors located on the first surface, the bit line is electrically connected to the active area, the bit line is parallel to the second direction and arranged along the first direction, and each active area is electrically connected to two capacitors. The bit line and the capacitor are located on both sides of the active area, and the unit memory cell is 4F. 2 The structure of the memory cell arrangement occupies a smaller area, which improves the integration level of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0029] Figures 2 to 15 is a schematic structural diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 16 to 21 It is a structural schematic diagram of each step in a method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0032] As described in the background art, the existing dynamic random access memory still needs to be improved. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0033] Figure 1 Schematic diagram of a semiconductor structure in one embodiment.

[0034] Please refer to Figure 1 , including: a substrate 100; a word line gate structure 101 located in the substrate 100; a source doping region 103 and a drain doping region 102 located in the substrate 100 on both sides of the word line gate structure 101; a bit line structure 105 electrically connected to the source doping region 103 through a source plug 104; and a capacitor structure 107 electrically connected to the drain doping region 102 through a capacitor plug 106.

[0035] The formation process of the semiconductor structure is as follows: first, a source doping region 103 and a drain doping region 102 are formed, then a word line gate structure 101 is formed in the substrate 100, then a source plug 104 and a bit line structure 105 are formed, then a capacitor plug 106 is formed, and finally a capacitor structure 107 is formed. The channel of the semiconductor structure is U-shaped, and the source doping region 103 and the drain doping region 102 are on both horizontal sides of the word line gate structure 101. The bit line structure 105 and the capacitor structure 107 are on the same side of the transistor, and are both located above the substrate in terms of processing technology. The capacitor plug 106 of the capacitor structure 107 needs to pass through the bit line structure 105, which makes the overall process complexity high, and has extremely high requirements for the photolithography process and alignment. At the same time, from the perspective of the memory cell array, the unit memory cell is 6F. 2 The structure occupies a large area and is not conducive to the integrated development of chips.

[0036] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, wherein a bit line is formed on the first surface or the second surface after the thinning process, the bit line extends along the second direction, and the bit line is electrically interconnected with the active area; a plurality of capacitors are formed on the second surface after the thinning process or the first surface, and the plurality of capacitors and the bit line are located on two opposite surfaces of the substrate, and the plurality of capacitors and the bit line do not require a special alignment process during the formation process, thereby simplifying the difficulty of the process. At the same time, from the perspective of the storage unit arrangement, the bit line and the capacitor are respectively located on both sides of the active area, and the unit storage unit is 4F.2 The structure occupies a smaller area and improves the level of chip integration.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 15 It is a structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3 A top view of the structure. Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along the DD1 direction is provided, wherein a substrate 201 is provided, wherein the substrate 201 has a first surface 201a and a second surface 201b opposite to each other, wherein the substrate 201 includes a plurality of active areas 202 and a first isolation layer 203 arranged along a first direction X and a second direction Y, wherein the first isolation layer 203 is located between adjacent active areas 202, wherein the second direction Y forms an acute angle with the first direction X, and the projection pattern of each active area 202 on the first surface 201a or the second surface 201b is a rectangle, and the long side direction of the rectangle is perpendicular to the first direction X.

[0040] An angle between the second direction Y and the first direction X is in a range of 15 to 75 degrees.

[0041] In this embodiment, the material of the substrate 201 is silicon. In other embodiments, the material of the substrate 201 includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0042] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 A top view of the structure. Figure 5 yes Figure 4Schematic diagram of the cross-sectional structure along the EE1 direction, a plurality of first grooves 204 are formed in the substrate 201, the first grooves 204 extend from the first surface 201a to the second surface 201b, and the plurality of first grooves 204 are arranged in parallel along a third direction Z, the third direction Z is perpendicular to the first direction X, each first groove 204 is located between two adjacent rows of active areas 202, and the first grooves 204 also penetrate a plurality of active areas 202 on both sides along the third direction Z, and the sidewalls and bottom of the first grooves 204 expose a portion of the surface of the active area 202.

[0043] The formation process of the first groove 204 includes one of a dry etching process and a wet etching process or a combination of the two. In this embodiment, the formation process of the first groove 204 is a dry etching process. The dry etching process is conducive to forming a better groove morphology.

[0044] Please refer to Figure 6 and Figure 7 , Figure 6 yes Figure 7 A top view of the structure. Figure 7 yes Figure 6 In the cross-sectional structural diagram along the EE1 direction, a word line gate structure 205 is formed in the first groove 204.

[0045] The method for forming the word line gate structure 205 includes: forming a gate dielectric material layer (not shown) on the side wall surface and bottom surface of the first groove 204 and the surface of the first surface 201a; forming a gate material layer (not shown) on the gate dielectric material layer; planarizing the gate material layer and the gate dielectric material layer until the surface of the first surface 201 is exposed to form an initial word line gate structure; etching back the initial word line gate structure until a portion of the side wall of the first groove 204 is exposed to form the word line gate structure 205.

[0046] The material of the gate material layer includes metal or silicon; the material of the gate dielectric material layer includes oxide. In this embodiment, the material of the gate material layer is tungsten; the material of the gate dielectric material layer is hafnium oxide.

[0047] The top surface of the word line gate structure 205 in the direction toward the first surface 201a of the substrate is lower than the surface of the first surface 201a of the active region 202 , providing physical space for subsequently forming a first source and drain region on the first surface 201a of the active region 202 .

[0048] In this embodiment, the top surface of the word line gate structure 205 in the direction toward the first surface 201a is lower than the surface of the substrate first surface 201a. In another embodiment, the top surface of the word line gate structure 205 in the direction toward the first surface 201a is higher than the surface of the substrate first surface 201a.

[0049] In this embodiment, the method for forming the word line gate structure 205 includes: forming a word line gate material layer in the first groove 204 and on the surface of the first surface 201a; planarizing the word line gate material layer until the first surface 201a is exposed; after the planarization process, etching back the word line gate material layer to form the word line gate structure 205.

[0050] In this embodiment, after the word line gate structure 205 is formed, an insulating layer 206 is further formed in the first groove 204 , and the surface of the insulating layer 206 is flush with the first surface 201 a .

[0051] In this embodiment, subsequently, a second isolation layer is formed in each active area 202, and the projection of the second isolation layer on the surface of the substrate 201 is located between the projections of the adjacent word line gate structures 205 on the surface of the substrate 201; the substrate 201 is thinned from the second surface 201b until the surface of the first isolation layer 203 is exposed; a plurality of bit lines are formed on the first surface 201a, and a plurality of capacitors are formed on the second surface 201b after the thinning process, the bit lines are parallel to the second direction Y, and each bit line is electrically connected to a plurality of active areas 202, and each active area 202 is electrically connected to two capacitors. For the method of forming the second isolation layer, the bit lines, and the plurality of capacitors, please refer to Figures 8 to 15 .

[0052] In another embodiment, subsequently, a second isolation layer is formed in each of the active areas, and the projection of the second isolation layer on the surface of the substrate is located between the projections of adjacent word line gate structures on the surface of the substrate; the substrate is thinned from the second surface until the surface of the first isolation layer is exposed; a plurality of bit lines are formed on the thinned second surface, and a plurality of capacitors are formed on the first surface, the bit lines are parallel to the second direction, and each bit line is electrically connected to a plurality of the active areas, and each of the active areas is electrically connected to two capacitors.

[0053] Please refer to Figure 8 and Fig. 9 , Figure 8 yes Fig. 9 A top view of the structure. Fig. 9 yes Figure 8In the cross-sectional structural diagram along the EE1 direction, a second isolation layer 207 is formed in each active area 202, and the projection of the second isolation layer 207 on the surface of the substrate 201 is located between the projections of the adjacent word line gate structures 205 on the surface of the substrate 200.

[0054] In this embodiment, the method for forming the second isolation layer 207 includes: forming a plurality of second grooves (not marked in the figure) in the substrate 201, the second grooves extending from the first surface 201a to the second surface 201b, the plurality of second grooves being arranged along a third direction Z, the third direction Z being perpendicular to the first direction X, and the plurality of second grooves penetrating the plurality of active regions 202 along the first direction X, the projection of the second groove on the surface of the substrate 201 being located between the projections of adjacent word line gate structures 205 on the surface of the substrate 201, the size of the second groove along the normal direction of the surface of the substrate 201 being smaller than the size of the first isolation layer 203 along the normal direction of the surface of the substrate 201; and forming the second isolation layer 207 in the second grooves.

[0055] After forming the second isolation layer 207 and before forming the plurality of capacitors, the method further includes: injecting first doping ions from the first surface 201 into the active region 202 to form a first source and drain region 208 in the active region 202 .

[0056] The first doping ions include N-type ions or P-type ions. In this embodiment, the first doping ions are N-type ions.

[0057] In this embodiment, after forming the first source and drain regions 208, the plurality of capacitors are formed. For a method of forming the plurality of capacitors, please refer to Fig.10 and Fig.11 .

[0058] Please refer to Fig.10 and Fig.11 , Fig.10 yes Fig.11 A top view of the structure. Fig.11 yes Fig.10 Schematic diagram of the cross-sectional structure along the EE1 direction, after the first source and drain regions 208 are formed, a first dielectric layer 209 is formed on the first surface 201a and the first source and drain regions 208; a plurality of third grooves (not marked in the figure) are formed in the first dielectric layer 209, and the third grooves expose the surfaces of the first source and drain regions 208; the capacitors 210 are formed in the third grooves, and one of the capacitors 210 is electrically connected to one of the first source and drain regions 208.

[0059] The capacitor 210 includes a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0060] The shape of the dielectric layer includes: a planar shape or a "U" shape.

[0061] When the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0062] When the dielectric layer is in a "U" shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0063] The material of the first electrode layer includes: metal or metal nitride; the material of the second electrode layer includes: metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes: a combination of one or more of tantalum nitride and titanium nitride.

[0064] In this embodiment, a capacitor plug 211 is provided between the capacitor 210 and the first source and drain region 208; a method for forming the capacitor plug 211 includes: a first opening (not shown) is provided in the third groove, the first opening exposes the surface of the first source and drain region 208; and the capacitor plug 211 is formed in the first opening. In other embodiments, the capacitor may be in direct contact with the first source and drain region without forming the capacitor plug.

[0065] The material of the capacitor plug 211 includes: metal or metal nitride; the metal includes: one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0066] Please refer to Fig.12 and Fig.13 , Fig.12 yes Fig.13 A top view of the structure. Fig.13 yes Fig.12 , the cross-sectional structure schematic diagram along the FF1 direction, the substrate 201 is thinned from the second surface 201b until the surface of the first isolation layer 203 is exposed.

[0067] Specifically, in this embodiment, after the capacitor 210 is formed, the substrate 201 is thinned from the second surface 201 b .

[0068] In this embodiment, the thinning method includes: providing a base 300; bonding the surface of the base 300 to the surface of the second dielectric layer 209; turning over the base 300 and the substrate 201, and thinning the second surface 201b of the substrate 201.

[0069] The thinning process includes a mechanical chemical grinding process.

[0070] Please refer to Fig.14 and Fig.15 , Fig.14 yes Fig.15 The top view of the second dielectric layer is omitted. Fig.15 yes Fig.14 The cross-sectional structure diagram along the FF1 direction in FIG. 1 shows that a plurality of bit lines 212 are formed on the thinned second surface 201 b.

[0071] The bit line 212 is located on the second surface 201b, and the method for forming the bit line 212 includes: forming a second dielectric layer 213 on the second surface 201b after the thinning process; forming a plurality of fourth grooves (not marked in the figure) in the second dielectric layer 213, wherein the fourth grooves extend along the second direction Y, and one of the fourth grooves exposes a portion of the surface of the active area 202; and forming the bit line 212 in the fourth groove.

[0072] The bit lines 212 extend along the second direction Y, and the word lines 205 extend along the first direction X, and there is a certain angle between the bit lines 212 and the word lines 205. Therefore, under the same chip unit area, the distance between adjacent bit lines 212 is increased, and the parasitic capacitance between the bit lines 212 is reduced, thereby improving the performance of the device.

[0073] The material of the bit line 212 includes metal. In this embodiment, the metal is copper. In other embodiments, the metal may be aluminum, tungsten, etc.

[0074] In this embodiment, after forming the word line 205 and before forming the bit line 212, the method further includes: injecting second doping ions into the active area 202 from the second surface 201b to form a second source and drain area 214 in the active area 202. Specifically, the second source and drain area 214 is formed after the thinning process.

[0075] The second doping ions include N-type ions or P-type ions. In this embodiment, the second doping ions are N-type ions.

[0076] A channel is formed between the first source / drain region 208 and the second source / drain region 214 . The channel is a vertical channel, which is beneficial to improving the density of the device and increasing the integration of the device.

[0077] In this embodiment, the bit line 212 is in direct contact with the second source and drain region 214. In other embodiments, a bit line plug is further provided between the bit line 212 and the active region 202. Specifically, a bit line plug is further provided between the bit line 212 and the second source and drain region 214, and the projection of the bit line plug on the surface of the substrate 201 is located between the projections of adjacent word line gate structures on the surface of the substrate 201.

[0078] Thus, the semiconductor structure formed, the capacitors 210 and the bit lines 212 do not require a special alignment process during the formation process, thus simplifying the process difficulty; at the same time, from the perspective of the memory cell arrangement, the unit memory cell is 4F 2 The structure occupies a smaller area and improves the level of chip integration.

[0079] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.14 and Fig.15 , comprising: a substrate 201, the substrate 201 having a first surface 201a and a second surface 201b opposite to each other, the substrate 201 comprising a plurality of active areas 202 and a first isolation layer 203 arranged in an array along a first direction X and a second direction Y, the first isolation layer 203 being located between adjacent active areas 202, the second direction Y being at an acute angle to the first direction X, the projection pattern of each active area 202 on the first surface 201a or the second surface 201b being a rectangle, and the long side direction of the rectangle being perpendicular to the first direction X; a plurality of first grooves (not shown in the figure) located in the substrate 201, the first grooves extending from the first surface 201a to the second surface 201b, the plurality of first grooves being arranged in parallel along a third direction Z, the third direction Z being perpendicular to the first direction X, and each first groove The groove is located between two adjacent rows of active areas 202, and the first groove also penetrates a plurality of active areas 202 on both sides along the third direction Z, and the sidewall and bottom of the first groove expose part of the surface of the active area 202; a word line gate structure 205 located in the first groove; a second isolation layer 207 located in each of the active areas 202, and the projection of the second isolation layer 207 on the surface of the substrate 201 is located between the projections of the adjacent word line gate structures 205 on the surface of the substrate 201; a bit line 212 located on the second surface 201b and a plurality of capacitors 210 located on the first surface 201a, the bit line 212 is electrically connected to the active area 202, the bit line 212 is parallel to the second direction Y and arranged along the first direction X, and each of the active areas 202 is electrically connected to two capacitors 210.

[0080] The semiconductor structure, from the perspective of the memory cell arrangement, the bit line 212 and the plurality of capacitors 210 are located on both sides of the active region, and the unit memory cell is 4F. 2 The structure occupies a smaller area and improves the level of chip integration.

[0081] The bit line 212 is located on the second surface 201b, and the plurality of capacitors 210 are located on the first surface 201a, and further include: a plurality of second grooves (not shown in the figure) located in the substrate 201, the second isolation layer 207 is located in the second grooves, the second grooves extend from the first surface 201a to the second surface 201b, the plurality of second grooves are arranged along a third direction Z, the third direction Z is perpendicular to the first direction X, and the second grooves pass through the plurality of active areas 202 along the first direction X, the projection of the second groove on the surface of the substrate 201 is located between the projections of adjacent word line gate structures 205 on the surface of the substrate 201, the size of the second groove along the normal direction of the surface of the substrate 201 is smaller than the size of the first isolation layer 203 along the normal direction of the surface of the substrate 201; first source and drain regions 208 located in the active area 202 on both sides of the second isolation layer 207, the first source and drain regions 208 extend from the first surface 201a to the second surface 201b, and one of the capacitors 210 is electrically connected to one of the first source and drain regions 208.

[0082] Figures 16 to 21 It is a structural schematic diagram of each step in a method for forming a semiconductor structure according to another embodiment of the present invention.

[0083] In this embodiment, the plurality of bit lines are located on the first surface, and the plurality of capacitors are located on the second surface. Figure 6 and Figure 7 Based on this, continue to refer to Fig.16 and Fig.17 .

[0084] Please refer to Fig.16 and Fig.17 , Fig.16 yes Fig.17 The top view of the second dielectric layer is omitted. Fig.17 yes Fig.16 Schematic diagram of the cross-sectional structure along the HH1 direction, a second dielectric layer 301 is formed on the first surface 201a; a plurality of fourth grooves (not marked in the figure) are formed in the second dielectric layer 301, the fourth grooves extend along the second direction Y, and one of the fourth grooves exposes a portion of the surface of the active area 202; the bit line 302 is formed in the fourth groove.

[0085] In this embodiment, specifically, after the insulating layer 206 is formed, the second dielectric layer 301 is formed.

[0086] The material of the bit line 302 includes metal. In this embodiment, the metal is copper. In other embodiments, the metal may be aluminum, tungsten, etc.

[0087] The bit lines 302 extend along the second direction Y, and the word lines 205 extend along the first direction X, and there is a certain angle between the bit lines 302 and the word lines 205. Therefore, under the same chip unit area, the distance between adjacent bit lines 302 is increased, and the parasitic capacitance between the bit lines 302 is reduced, thereby improving the performance of the device.

[0088] In this embodiment, after forming the word line gate structure and before forming the bit line, the method further includes: injecting second doping ions from the first surface 201 a into the active area 202 to form a second source and drain area 303 in the active area 202 .

[0089] The second doping ions include N-type ions or P-type ions. In this embodiment, the second doping ions are N-type ions.

[0090] In this embodiment, a bit line plug 304 is further provided between the bit line 302 and the active region 202, and the projection of the bit line plug 304 on the surface of the substrate 201 is located between the projections of the adjacent word line gate structures 205 on the surface of the substrate 201; the method for forming the bit line plug 304 comprises: the fourth groove further has a second opening, the second opening exposes the second source and drain region 303; and the bit line plug 304 is formed in the second opening. Specifically, the bit line plug 304 is located between the bit line 302 and the second source and drain region 303.

[0091] In other embodiments, the bit line 302 is in direct contact with the active region 202 , and the bit line plug may not be formed.

[0092] Please refer to Fig.18 and Fig.19 , Fig.18 yes Fig.19 A top view of the structure. Fig.19 yes Fig.18 A schematic cross-sectional structure diagram along the NN1 direction shows that the substrate 201 is thinned from the second surface 201 b until the surface of the first isolation layer 203 is exposed.

[0093] In this embodiment, specifically, after the bit lines 302 are formed, the substrate 201 is thinned from the second surface 201 b .

[0094] The thinning method comprises: providing a base 400; bonding the surface of the base 400 to the surface of the second dielectric layer 301; turning over the base 400 and the substrate 201, and thinning the second surface 201b of the substrate 201.

[0095] The thinning process includes a mechanical chemical grinding process.

[0096] Please continue to refer to Fig.18 and Fig.19 After the thinning process and before forming the plurality of capacitors, a plurality of second grooves (not shown in the figure) are formed in the substrate, the plurality of second grooves extend from the second surface 201b to the first surface 201a, the plurality of second grooves are arranged along a third direction Z, the third direction Z is perpendicular to the first direction X, and the second grooves penetrate the plurality of active areas 202 along the first direction X, the projection of the second groove on the surface of the substrate 201 is located between the projections of adjacent word line gate structures 205 on the surface of the substrate 201, and the size of the second groove along the normal direction of the surface of the substrate 201 is smaller than the size of the first isolation layer 203 along the normal direction of the surface of the substrate 201; a second isolation layer 305 is formed in the second groove.

[0097] refer to Fig. 20 and Fig.21 , Fig. 20 yes Fig.21 A top view of the structure. Fig.21 yes Fig. 20 The schematic cross-sectional structure diagram along the NN1 direction, after forming the second isolation layer 305 and before forming the plurality of capacitors, further includes: injecting first doping ions into the active area 202 from the second surface 201 b to form a first source and drain area 306 in the active area 202 .

[0098] The first doping ions include N-type ions or P-type ions. In this embodiment, the first doping ions are N-type ions.

[0099] A channel is formed between the first source / drain region 306 and the second source / drain region 303 . The channel is a vertical channel, which is beneficial to improving the density of the device and increasing the integration of the device.

[0100] Please continue to refer to Fig. 20 and Fig.21After forming the first source and drain regions 306, a first dielectric layer 307 is formed on the second surface 201b and the first source and drain regions 306; a plurality of third grooves (not shown in the figure) are formed in the first dielectric layer 307, and the third grooves expose the surfaces of the first source and drain regions 306; a plurality of capacitors 308 are formed in the third grooves, and one of the capacitors 308 is electrically connected to one of the first source and drain regions 306.

[0101] The capacitor 308 includes a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.

[0102] The shape of the dielectric layer includes: a planar shape or a "U" shape.

[0103] When the dielectric layer is planar, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0104] When the dielectric layer is in a "U" shape, the surface of the first electrode layer is an uneven surface, and the surface of the second electrode layer is an uneven surface; or, the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.

[0105] The material of the first electrode layer includes: metal or metal nitride; the material of the second electrode layer includes: metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes: a combination of one or more of tantalum nitride and titanium nitride.

[0106] In this embodiment, a capacitor plug 309 is provided between the capacitor 308 and the first source and drain region 306; a method for forming the capacitor plug 309 includes: a first opening (not shown) is provided in the third groove, the first opening exposes the surface of the first source and drain region 306; and the capacitor plug 309 is formed in the first opening. In other embodiments, the capacitor may be in direct contact with the first source and drain region without forming the capacitor plug.

[0107] The material of the capacitor plug 309 includes: metal or metal nitride; the metal includes: one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0108] Thus, the semiconductor structure formed, the capacitors 308 and the bit lines 302 do not require a special alignment process during the formation process, thus simplifying the process difficulty; at the same time, from the perspective of the storage unit arrangement, the bit lines and capacitors are located on both sides of the active area, and the unit storage unit is 4F. 2The structure occupies a smaller area and improves the level of chip integration.

[0109] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.21 , comprising: a substrate 201, the substrate 201 having a first surface 201a and a second surface 201b opposite to each other, the substrate 201 comprising a plurality of active areas 202 and a first isolation layer 203 arranged in an array along a first direction X and a second direction Y, the first isolation layer 203 being located between adjacent active areas 202, the second direction Y being at an acute angle to the first direction X, the projection pattern of each active area 202 on the first surface 201a or the second surface 201b being a rectangle, and the long side direction of the rectangle being perpendicular to the first direction X; a plurality of first grooves (not shown in the figure) located in the substrate 201, the first grooves extending from the first surface 201a to the second surface 201b, the plurality of first grooves being arranged in parallel along a third direction Z, the third direction Z being perpendicular to the first direction X, and the plurality of first grooves being arranged in parallel along a third direction Z. A groove is located between two adjacent rows of active areas 202, and the first groove also penetrates a plurality of active areas 202 on both sides along the third direction Z, and the sidewall and bottom of the first groove expose part of the surface of the active area 202; a word line gate structure 205 located in the first groove; a second isolation layer 305 located in each of the active areas 202, and the projection of the second isolation layer 305 on the surface of the substrate 201 is located between the projections of adjacent word line gate structures 205 on the surface of the substrate 201; a plurality of bit lines 302 located on the first surface 201a and a plurality of capacitors 308 located on the second surface 201b, the bit lines 302 are parallel to the second direction Y, and each bit line 302 is electrically connected to a group of the plurality of active areas 202, and each of the active areas 202 is electrically connected to two capacitors 308.

[0110] The semiconductor structure, from the perspective of the storage unit arrangement, the bit line and the capacitor are located on both sides of the active area, and the unit storage unit is 4F. 2 The structure occupies a smaller area and improves the level of chip integration.

[0111] The plurality of bit lines 302 are located on the first surface 201a, the plurality of capacitors 308 are located on the second surface 201b, and further include: a plurality of second grooves (not shown in the figure) located in the substrate 201, the second isolation layer 305 is located in the second grooves, the plurality of second grooves extend from the second surface to the first surface 201b, the plurality of second grooves are arranged along a third direction Z, the third direction Z is perpendicular to the first direction X, and the second grooves penetrate the plurality of active areas 202 along the first direction X, the projection of the second groove on the surface of the substrate 201 is located between the projections of adjacent word line gate structures 205 on the surface of the substrate 201, the size of the second groove along the normal direction of the surface of the substrate 201 is smaller than the size of the first isolation layer 203 along the normal direction of the surface of the substrate 201; the first source and drain regions 306 located in the active area 202 on both sides of the second isolation layer 305, and one of the capacitors 308 is electrically connected to one of the first source and drain regions 306.

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a first surface and a second surface opposite to each other, the substrate comprises a plurality of active areas and a first isolation layer arranged in an array along a first direction and a second direction, the first isolation layer is located between adjacent active areas, the second direction forms an acute angle with the first direction, the projection figure of each active area on the first surface or the second surface is a rectangle, and the long side direction of the rectangle is perpendicular to the first direction; A plurality of first grooves located in the substrate, the first grooves extending from the first surface to the second surface, the plurality of first grooves being arranged in parallel along a third direction, the third direction being perpendicular to the first direction, each first groove being located between two adjacent rows of active areas, and the first grooves also penetrate a plurality of active areas on both sides along the third direction, and the sidewalls and bottom of the first grooves exposing a portion of the surface of the active area; a word line gate structure located in the first groove; a plurality of second grooves located in the substrate, a second isolation layer located in the second grooves, the second grooves extending from the first surface to the second surface, the plurality of second grooves arranged along a third direction, the third direction being perpendicular to the first direction, and the second grooves passing through the plurality of active areas along the first direction, the projection of the second grooves on the surface of the substrate being located between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second grooves along the normal direction of the substrate surface being smaller than the size of the first isolation layer along the normal direction of the substrate surface; A bit line located on the second surface and a plurality of capacitors located on the first surface, the bit line being electrically connected to the active area, the bit line being parallel to the second direction and arranged along the first direction, and each of the active areas being electrically connected to two capacitors.

2. The semiconductor structure according to claim 1, wherein: Also includes: The first source and drain regions are located in the active region on both sides of the second isolation layer, the first source and drain regions extend from the first surface to the second surface, and one of the capacitors is electrically connected to one of the first source and drain regions.

3. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other, the substrate comprises a plurality of active regions and a first isolation layer arranged along a first direction and a second direction, the first isolation layer is located between adjacent active regions, the second direction forms an acute angle with the first direction, a projection pattern of each active region on the first surface or the second surface is a rectangle, and the long side direction of the rectangle is perpendicular to the first direction; A plurality of first grooves are formed in the substrate, the first grooves extend from the first surface to the second surface, the plurality of first grooves are arranged in parallel along a third direction, the third direction is perpendicular to the first direction, each first groove is located between two adjacent rows of active areas, and the first grooves also penetrate a plurality of active areas on both sides along the third direction, and the sidewalls and bottom of the first grooves expose a portion of the surface of the active area; forming a word line gate structure in the first groove; Performing a thinning process on the substrate from the second surface until a surface of the first isolation layer is exposed; A plurality of second grooves are formed in the substrate, the second grooves extend from the first surface to the second surface, the plurality of second grooves are arranged along a third direction, the third direction is perpendicular to the first direction, and the plurality of second grooves penetrate through the plurality of active areas along the first direction, the projection of the second groove on the surface of the substrate is located between the projections of adjacent word line gate structures on the surface of the substrate, and the size of the second groove along the normal direction of the substrate surface is smaller than the size of the first isolation layer along the normal direction of the substrate surface; forming a second isolation layer in the second groove; A plurality of bit lines are formed on the thinned second surface, and a plurality of capacitors are formed on the first surface. The bit lines are parallel to the second direction, and each bit line is electrically connected to a plurality of active areas, and each active area is electrically connected to two capacitors.

4. The method for forming a semiconductor structure according to claim 3, wherein: After forming the second isolation layer and before forming the plurality of capacitors, the method further includes: implanting first doping ions into the active region from the first surface to form a first source and drain region in the active region.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the plurality of capacitors comprises: after forming the first source and drain regions, forming a first dielectric layer on the first surface and the first source and drain regions; forming a plurality of third grooves in the first dielectric layer, wherein the third grooves expose the surfaces of the first source and drain regions; and forming the capacitors in the third grooves, wherein one of the capacitors is electrically connected to one of the first source and drain regions.

6. The method for forming a semiconductor structure according to claim 5, wherein: A capacitor plug is provided between the capacitor and the first source and drain region. The method for forming the capacitor plug comprises: a first opening is provided in the third groove, and the first opening exposes the surface of the first source and drain region; and the capacitor plug is formed in the first opening.

7. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the bit line comprises: forming a second dielectric layer on the second surface after the thinning process; forming a plurality of fourth grooves in the second dielectric layer, wherein the fourth grooves extend along the second direction, and one of the fourth grooves exposes a portion of the surface of a plurality of the active regions; and forming the bit line in the fourth grooves.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming the word line gate structure and before forming the bit line, the method further includes: implanting second doping ions into the active region from the second surface to form a second source and drain region in the active region.

9. The method for forming a semiconductor structure according to claim 8, wherein: A bit line plug is further provided between the bit line and the active area, and a projection of the bit line plug on the substrate surface is located between projections of adjacent word line gate structures on the substrate surface; The method for forming the bit line plug includes: the fourth groove further has a second opening, and the second opening exposes the second source and drain region; The bit line plug is formed in the second opening.

10. The method for forming a semiconductor structure according to claim 3, wherein: An angle between the second direction and the first direction is in a range of 15 to 75 degrees.

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