Variable Gain Amplifier and Its Application

Abstract

The present invention discloses a variable gain amplifier and its application, wherein the amplifier comprises a first differential pair, a second differential pair and / or a third differential pair, and a fourth differential pair, each differential pair comprises two groups of cross-coupled common source and common gate structures, each common source and common gate structure comprises an input transistor and an output transistor. The variable gain amplifier of the present invention breaks through the limitation that a conventional variable gain amplifier design requires multiple stages or additional passive devices to achieve extremely low phase error, and can achieve extremely low phase error in a larger gain variation range by only using a first-stage common source and common gate structure, and at the same time has a 180° inversion function, and has a wide range of applications.

Description

Technical Field

[0001] The invention belongs to the technical field of high-frequency chips, and in particular relates to a variable gain amplifier with low phase error and application thereof. Background Art

[0002] Applications in the millimeter wave band (wavelength 0.1 to 1 cm) often require amplitude modulation, but at the same time, it is necessary to ensure that the additional phase shift caused by amplitude modulation is extremely small.

[0003] In traditional designs, in order to maintain a small additional phase shift while modulating the amplitude, more than two amplifier stages are often required, and the phase responses of the two amplifier stages are in opposite directions, which results in a larger chip area and higher power consumption. Alternatively, a unipolar amplifier is used, but passive devices are required for phase compensation. In this way, due to the bandwidth of the passive devices themselves, phase compensation can only be achieved within a very small range, and it will also bring more losses.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a variable gain amplifier and application thereof. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a variable gain amplifier and application thereof.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A variable gain amplifier, the amplifier comprising a first differential pair, a second differential pair and / or a third differential pair, and a fourth differential pair, wherein:

[0008] The first differential pair includes a cross-coupled first cascode structure and a second cascode structure, the first cascode structure includes a first input transistor and a first output transistor, and the second cascode structure includes a second input transistor and a second output transistor;

[0009] The second differential pair includes a third cascode structure and a fourth cascode structure that are cross-coupled, the third cascode structure includes a third input transistor and a third output transistor, and the fourth cascode structure includes a fourth input transistor and a fourth output transistor;

[0010] The third differential pair includes a cross-coupled fifth cascode structure and a sixth cascode structure, the fifth cascode structure includes a fifth input transistor and a fifth output transistor, and the sixth cascode structure includes a sixth input transistor and a sixth output transistor;

[0011] The fourth differential pair includes a seventh cascode structure and an eighth cascode structure that are cross-coupled, the seventh cascode structure includes a seventh input transistor and a seventh output transistor, and the eighth cascode structure includes an eighth input transistor and an eighth output transistor;

[0012] The first input transistor, the third input transistor, the fifth input transistor, and the seventh input transistor are respectively connected to the first differential signal, and the second input transistor, the fourth input transistor, the sixth input transistor, and the eighth input transistor are respectively connected to the second differential signal;

[0013] The first output transistor, the third output transistor, the sixth output transistor, and the eighth output transistor are respectively connected to the first output terminal, and the second output transistor, the fourth output transistor, the fifth output transistor, and the seventh output transistor are respectively connected to the second output terminal;

[0014] The on and off of the first differential pair, the second differential pair, the third differential pair, and the fourth differential pair are controlled by a first control signal, a second control signal, a third control signal, and a fourth control signal, respectively, and the fourth control signal is an inverse signal of the first control signal, and the third control signal is an inverse signal of the second control signal.

[0015] In one embodiment, the amplifier includes a first differential pair, a second differential pair, a third differential pair, and a fourth differential pair, and the amplifier includes:

[0016] In the forward high gain state, the first control signal is a low level signal, the second control signal is a low level signal, the third control signal is a high level signal, and the second control signal is a high level signal;

[0017] In the forward low gain state, the first control signal is a high level signal, the second control signal is a low level signal, the third control signal is a high level signal, and the second control signal is a low level signal;

[0018] In the reverse high gain state, the first control signal is a high level signal, the second control signal is a high level signal, the third control signal is a low level signal, and the second control signal is a low level signal;

[0019] In the reverse low gain state, the first control signal is a low level signal, the second control signal is a high level signal, the third control signal is a low level signal, and the second control signal is a high level signal.

[0020] In one embodiment, the size ratio of the first input transistor to the first output transistor, the size ratio of the second input transistor to the second output transistor, the size ratio of the third input transistor to the third output transistor, the size ratio of the fourth input transistor to the fourth output transistor, the size ratio of the fifth input transistor to the fifth output transistor, the size ratio of the sixth input transistor to the sixth output transistor, the size ratio of the seventh input transistor to the seventh output transistor, and the size ratio of the eighth input transistor to the eighth output transistor are all equal;

[0021] The sizes of the first input transistor, the second input transistor, the seventh input transistor, and the eighth input transistor are equal, the sizes of the third input transistor, the fourth input transistor, the fifth input transistor, and the sixth input transistor are equal, and the sizes of the first input transistor, the second input transistor, the seventh input transistor, and the eighth input transistor are smaller than the sizes of the third input transistor, the fourth input transistor, the fifth input transistor, and the sixth input transistor;

[0022] The sizes of the first output transistor, the second output transistor, the seventh output transistor, and the eighth output transistor are equal, the sizes of the third output transistor, the fourth output transistor, the fifth output transistor, and the sixth output transistor are equal, and the sizes of the first output transistor, the second output transistor, the seventh output transistor, and the eighth output transistor are smaller than the sizes of the third output transistor, the fourth output transistor, the fifth output transistor, and the sixth output transistor.

[0023] In one embodiment, the gate of the first input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the first input transistor is connected to the source of the first output transistor, the gate of the first output transistor is connected to the first control signal, and the drain is connected to the first output terminal;

[0024] The gate of the second input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the second input transistor is connected to the source of the second output transistor, the gate of the second output transistor is connected to the first control signal, and the drain is connected to the second output terminal;

[0025] The gate of the third input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the third input transistor is connected to the source of the third output transistor, the gate of the third output transistor is connected to the second control signal, and the drain is connected to the first output terminal;

[0026] The gate of the fourth input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the fourth input transistor is connected to the source of the fourth output transistor, the gate of the fourth output transistor is connected to the second control signal, and the drain is connected to the second output terminal;

[0027] The gate of the fifth input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the fifth input transistor is connected to the source of the fifth output transistor, the gate of the fifth output transistor is connected to the third control signal, and the drain is connected to the second output terminal;

[0028] The gate of the sixth input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the sixth input transistor is connected to the source of the sixth output transistor, the gate of the sixth output transistor is connected to the third control signal, and the drain is connected to the first output terminal;

[0029] The gate of the seventh input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the seventh input transistor is connected to the source of the seventh output transistor, the gate of the seventh output transistor is connected to the fourth control signal, and the drain is connected to the second output terminal;

[0030] The gate of the eighth input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the eighth input transistor is connected to the source of the eighth output transistor, the gate of the eighth output transistor is connected to the fourth control signal, and the drain is connected to the first output terminal.

[0031] In one embodiment, a neutralization capacitor is electrically connected between the gate of the first input transistor and the drain of the second input transistor, between the gate of the second input transistor and the drain of the first input transistor, between the gate of the third input transistor and the drain of the fourth input transistor, between the gate of the fourth input transistor and the drain of the third input transistor, between the gate of the fifth input transistor and the drain of the sixth input transistor, between the gate of the sixth input transistor and the drain of the fifth input transistor, between the gate of the seventh input transistor and the drain of the eighth input transistor, and between the gate of the eighth input transistor and the drain of the third input transistor.

[0032] In one embodiment, the amplifier further includes a plurality of fifth differential pairs and a sixth differential pair, wherein:

[0033] The fifth differential pair includes a ninth cascode structure and a tenth cascode structure that are cross-coupled, the ninth cascode structure includes a ninth input transistor and a ninth output transistor, and the tenth cascode structure includes a tenth input transistor and a tenth output transistor;

[0034] The sixth differential pair includes an eleventh cascode structure and a twelfth cascode structure that are cross-coupled, the eleventh cascode structure includes an eleventh input transistor and an eleventh output transistor, and the twelfth cascode structure includes a twelfth input transistor and a twelfth output transistor.

[0035] In one embodiment, the size ratio of the ninth input transistor to the ninth output transistor, the size ratio of the tenth input transistor to the tenth output transistor, the size ratio of the eleventh input transistor to the eleventh output transistor, and the size ratio of the twelfth input transistor to the twelfth output transistor are equal, and are equal to the size ratio of the first input transistor to the first output transistor;

[0036] The sizes of the ninth input transistor, the tenth input transistor, the eleventh input transistor and the twelfth input transistor are equal, and are not equal to the sizes of the first input transistor and the third input transistor;

[0037] The sizes of the ninth output transistor, the tenth output transistor, the eleventh output transistor and the twelfth output transistor are equal, and are different from the sizes of the first output transistor and the third output transistor.

[0038] In one embodiment, the first to eighth input transistors and the first to eighth output transistors are NMOS transistors or PMOS transistors.

[0039] In one embodiment, the first output terminal and the second output terminal are respectively connected to the first input terminal and the second input terminal of an output load, and the output load is a combination of one or more of a transformer, a transmission line, a capacitor, an inductor, and a resistor.

[0040] Another embodiment of the present invention provides a technical solution as follows:

[0041] An application of a variable gain amplifier, wherein the variable gain amplifier is applied in a microwave band or a millimeter wave band.

[0042] The present invention has the following beneficial effects:

[0043] The variable gain amplifier of the present invention breaks through the limitation that conventional variable gain amplifier designs require multiple stages or additional passive devices to achieve extremely low phase errors. It can achieve extremely low phase errors in a larger gain variation range through only a single-stage common-source and common-gate structure. At the same time, it has a 180° inversion function and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 is a circuit diagram of a variable gain amplifier in a specific embodiment of the present invention;

[0046] Figure 2a , 2b They are small signal equivalent circuit diagrams of a variable gain amplifier in a specific embodiment of the present invention working in a high gain state and a low gain state respectively. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] Ginseng Figure 1 As shown, a specific embodiment of the present invention discloses a variable gain amplifier, which includes a first differential pair A, a second differential pair B, a third differential pair C, and a fourth differential pair D, wherein:

[0049] The first differential pair A includes a cross-coupled first cascode structure and a second cascode structure, the first cascode structure includes a first input transistor M1 and a first output transistor M11, and the second cascode structure includes a second input transistor M2 and a second output transistor M12;

[0050] The second differential pair B includes a third cascode structure and a fourth cascode structure that are cross-coupled, the third cascode structure includes a third input transistor M3 and a third output transistor M13, and the fourth cascode structure includes a fourth input transistor M4 and a fourth output transistor M14;

[0051] The third differential pair C includes a cross-coupled fifth cascode structure and a sixth cascode structure, the fifth cascode structure includes a fifth input transistor M5 and a fifth output transistor M15, and the sixth cascode structure includes a sixth input transistor M6 and a sixth output transistor M16;

[0052] The fourth differential pair D includes a cross-coupled seventh cascode structure and an eighth cascode structure. The seventh cascode structure includes a seventh input transistor M7 and a seventh output transistor M17. The eighth cascode structure includes an eighth input transistor M8 and an eighth output transistor M18.

[0053] In this embodiment, four differential pairs are taken as an example, and the output transistors (common gate transistors) of all the differential pairs are connected to the independent input transistors (common source transistors) of the branch, rather than sharing the input transistors with other output transistors.

[0054] The first input transistor M1, the third input transistor M3, the fifth input transistor M5, and the seventh input transistor M7 are respectively connected to the first differential signal Vi+, the second input transistor M2, the fourth input transistor M4, the sixth input transistor M6, and the eighth input transistor M8 are respectively connected to the second differential signal Vi-, and the first differential signal Vi+ and the second differential signal Vi- are the positive signal and the negative signal in the differential input signal;

[0055] The first output transistor M11, the third output transistor M13, the sixth output transistor M16, and the eighth output transistor M18 are respectively connected to the first output terminal outp (positive terminal), and the second output transistor M12, the fourth output transistor M14, the fifth output transistor M15, and the seventh output transistor M17 are respectively connected to the second output terminal outn (negative terminal).

[0056] Specifically:

[0057] The gate of the first input transistor M1 is connected to the first differential signal Vi+, the source is connected to the reference potential, the drain of the first input transistor M1 is connected to the source of the first output transistor M11, the gate of the first output transistor M11 is connected to the first control signal ctrl1, and the drain is connected to the first output terminal outp;

[0058] The gate of the second input transistor M2 is connected to the second differential signal Vi-, the source is connected to the reference potential, the drain of the second input transistor M2 is connected to the source of the second output transistor M12, the gate of the second output transistor M12 is connected to the first control signal ctrl1, and the drain is connected to the second output terminal outn;

[0059] The gate of the third input transistor M3 is connected to the first differential signal Vi+, the source is connected to the reference potential, the drain of the third input transistor M3 is connected to the source of the third output transistor M13, the gate of the third output transistor M13 is connected to the second control signal ctrl2, and the drain is connected to the first output terminal outp;

[0060] The gate of the fourth input transistor M4 is connected to the second differential signal Vi-, the source is connected to the reference potential, the drain of the fourth input transistor M4 is connected to the source of the fourth output transistor M14, the gate of the fourth output transistor M14 is connected to the second control signal ctrl2, and the drain is connected to the second output terminal outn;

[0061] The gate of the fifth input transistor M5 is connected to the first differential signal Vi+, the source is connected to the reference potential, the drain of the fifth input transistor M5 is connected to the source of the fifth output transistor M15, the gate of the fifth output transistor M15 is connected to the third control signal ctrl2_n, and the drain is connected to the second output terminal outn;

[0062] The gate of the sixth input transistor M6 is connected to the second differential signal Vi-, the source is connected to the reference potential, the drain of the sixth input transistor M6 is connected to the source of the sixth output transistor M16, the gate of the sixth output transistor M16 is connected to the third control signal ctrl2_n, and the drain is connected to the first output terminal outp;

[0063] The gate of the seventh input transistor M7 is connected to the first differential signal Vi+, the source is connected to the reference potential, the drain of the seventh input transistor M7 is connected to the source of the seventh output transistor M17, the gate of the seventh output transistor M17 is connected to the fourth control signal ctrl1_n, and the drain is connected to the second output terminal outn;

[0064] The gate of the eighth input transistor M8 is connected to the second differential signal Vi-, the source is connected to the reference potential, the drain of the eighth input transistor M8 is connected to the source of the eighth output transistor M18, the gate of the eighth output transistor M18 is connected to the fourth control signal ctrl1_n, and the drain is connected to the first output terminal outp.

[0065] Preferably, the first input transistor M1 to the eighth input transistor M8 and the first output transistor M11 to the eighth output transistor M18 in this embodiment are all NMOS transistors, and may also be PMOS transistors in other embodiments.

[0066] In this embodiment, the on and off of the first differential pair A, the second differential pair B, the third differential pair C, and the fourth differential pair D are controlled by the first control signal ctrl1, the second control signal ctrl2, the third control signal ctrl2_n, and the fourth control signal ctrl1_n, respectively, and the fourth control signal ctrl1_n is the reverse signal of the first control signal ctrl1, and the third control signal ctrl2_n is the reverse signal of the second control signal ctrl2.

[0067] like Figure 1 As shown, in this embodiment, the first control signal ctrl1 and the second control signal ctrl2 are the selection control signals for the amplifier differential pair to be turned on and off, and the fourth control signal ctrl1_n and the third control signal ctrl2_n are respectively the logic negation signals of the first control signal ctrl1 and the second control signal ctrl2 after the inverter, so when ctrl1 is logic 1, ctrl1_n is 0; when ctrl1 is logic 0, ctrl1_n is 1. Similarly, the relationship between the ctrl2 and ctrl2_n signals can be deduced.

[0068] The relationship between the amplifier control logic (ctrl1, ctrl2) and the circuit function (stage) is shown in Table 1 below, where the 1 signal and 0 signal of ctrl1 and ctrl2 refer to logical 1 and 0.

[0069] Table 1. Control logic and circuit function table

[0070]

[0071] The corresponding relationship between control logic and circuit function is as follows:

[0072] In the forward high gain state, the first control signal ctrl1 is a low level signal, the second control signal ctrl2 is a low level signal, the third control signal ctrl2_n is a high level signal, and the second control signal ctrl2 is a high level signal;

[0073] In the forward low gain state, the first control signal ctrl1 is a high level signal, the second control signal ctrl2 is a low level signal, the third control signal ctrl2_n is a high level signal, and the second control signal ctrl2 is a low level signal;

[0074] In the reverse high-gain state, the first control signal ctrl1 is a high-level signal, the second control signal ctrl2 is a high-level signal, the third control signal ctrl2_n is a low-level signal, and the second control signal ctrl2 is a low-level signal;

[0075] In the reverse low gain state, the first control signal ctrl1 is a low level signal, the second control signal ctrl2 is a high level signal, the third control signal ctrl2_n is a low level signal, and the second control signal ctrl2 is a high level signal.

[0076] When the amplifier needs to achieve forward conduction, the ctrl1 and ctrl2 control signals are both 0. At this time, only the third differential pair C and the fourth differential pair D are turned on, while the first differential pair A and the second differential pair B are turned off. The positive end signals of the third differential pair C and the fourth differential pair D flow into the first output terminal outp, and the negative end signals of the third differential pair C and the fourth differential pair D flow into the second output terminal outn. When the gain change function is realized without changing the phase, ctrl1 is 1 and ctrl2 is 0. At this time, the positive signal of the first differential pair A and the negative signal of the third differential pair C flow into the second output terminal outn. Since the size of the first differential pair A is small, the phase of the signal at the second output terminal outn is the same as the phase of the third differential pair C, and the energy of the signal is the energy of the third differential pair C minus the energy of the first differential pair A, which plays the role of reducing gain while keeping the phase unchanged; the same analysis method can be used to conclude that the signal at the first output terminal outp also has a reduced gain while keeping the phase unchanged;

[0077] When ctrl1 is 0 and ctrl2 is 1, the negative terminal signal of the fourth differential pair D and the positive terminal signal of the second differential pair B flow into the second output terminal outn. Since the size of the second differential pair B is larger than that of the fourth differential pair D, the phase of the second output terminal outn is reversed at this time, and the energy is the difference between the two, which belongs to reverse phase low gain;

[0078] When ctrl1 is 1 and ctrl2 is also 1, the positive end signals of the first differential pair A and the second differential pair B flow into the second output end outn. At this time, the signals are inverted and the two signals are added together, so they are in an inverted high gain state.

[0079] In the amplifier of this embodiment:

[0080] The size ratio of the first input transistor M1 to the first input transistor M11, the size ratio of the second input transistor M2 to the second input transistor M12, the size ratio of the third input transistor M3 to the third input transistor M13, the size ratio of the fourth input transistor M4 to the fourth input transistor M14, the size ratio of the fifth input transistor M5 to the fifth input transistor M15, the size ratio of the sixth input transistor M6 to the sixth input transistor M16, the size ratio of the seventh input transistor M7 to the seventh input transistor M17, and the size ratio of the eighth input transistor M8 to the eighth input transistor M18 are all equal;

[0081] The sizes of the first input transistor M1, the second input transistor M2, the seventh input transistor M7, and the eighth input transistor M8 are equal, and the sizes of the third input transistor M3, the fourth input transistor M4, the fifth input transistor M5, and the sixth input transistor M6 are equal, and the sizes of the first input transistor M1, the second input transistor M2, the seventh input transistor M7, and the eighth input transistor M8 are smaller than the sizes of the third input transistor M3, the fourth input transistor M4, the fifth input transistor M5, and the sixth input transistor M6;

[0082] The sizes of the first output transistor M11, the second output transistor M12, the seventh output transistor M17, and the eighth output transistor M18 are equal, the sizes of the third output transistor M13, the fourth output transistor M14, the fifth output transistor M15, and the sixth output transistor M16 are equal, and the sizes of the first output transistor M11, the second output transistor M12, the seventh output transistor M17, and the eighth output transistor M18 are smaller than the sizes of the third output transistor M13, the fourth output transistor M14, the fifth output transistor M15, and the sixth output transistor M16.

[0083] For the structure of 4 differential pairs, the sizes of the differential pairs are the same, and there are two groups of differential pairs with different sizes, one large and one small.

[0084] In other embodiments, one of the differential pairs with a larger size may be deleted (the second differential pair B or the third differential pair C) to remove the 180° reverse function and ensure a more compact layout. This is also applicable to a structure with more than four differential pairs.

[0085] Furthermore, in this embodiment, each differential pair is also provided with a neutralizing capacitor, and the purpose of the neutralizing capacitor is to improve the stability and gain of the amplifier, and to reduce the phase error caused by the gain change.

[0086] Specifically, a neutralization capacitor is electrically connected between the gate of the first input transistor M1 and the drain of the second input transistor M2, between the gate of the second input transistor M2 and the drain of the first input transistor M1, between the gate of the third input transistor M3 and the drain of the fourth input transistor M4, between the gate of the fourth input transistor M4 and the drain of the third input transistor M3, between the gate of the fifth input transistor M5 and the drain of the sixth input transistor M6, between the gate of the sixth input transistor M6 and the drain of the fifth input transistor M5, between the gate of the seventh input transistor M7 and the drain of the eighth input transistor M8, and between the gate of the eighth input transistor M8 and the drain of the seventh input transistor M8.

[0087] In this embodiment, the first output terminal outp and the second output terminal outn are connected to the first input terminal and the second input terminal of the output load respectively. The output load in this embodiment is described by taking the transformer XFMR1 as an example. In other embodiments, the output load may also be a combination of one or more devices such as a transmission line, a capacitor, an inductor, and a resistor. The output load does not affect the implementation of the variable gain amplifier.

[0088] The following analysis combines the small signal equivalent circuit to analyze the additional phase shift when the gain changes.

[0089] Ginseng Figure 2a , 2b FIG. 1 is a small signal equivalent circuit of the variable gain amplifier in this embodiment working in different gain states, wherein: Figure 2a In high gain state, Figure 2b In low gain state. To simplify the analysis, the influence of the neutralizing capacitor is not considered. Figure 2a , 2b The common gate transfer function in the two cases can be obtained as:

[0090] A v+ =Z load [jω(C ds11 +C ds10 )+g m11 +g m10 ];

[0091] Av- =Z load [jω(C ds11 -C ds15 )+g m11 -g m15 ].

[0092] The phase of the transfer function can be written as:

[0093]

[0094]

[0095] Among them A V+ is the transfer function in high gain state, A V- is the transfer function in the low gain state, Zload is the load impedance, j is a unit imaginary number, ω is the angular frequency, C ds is the parasitic capacitance between the drain and source, g m is the transconductance of the transistor, and the subscript number is the specific transistor number.

[0096] Since transistor M10 (with gm 10 corresponding transistor) and transistor M15 (with gm 15 If the size of the corresponding transistor) and the DC bias are consistent, then the phase of the transfer function of the two is consistent, and the phase error is 0.

[0097] At the same time, under different gain states, looking inward from the second output terminal outn toward the differential pair, since the sizes of the first differential pair A and the fourth differential pair D are exactly the same and the DC bias voltages are also the same; and the sizes of the second differential pair B and the third differential pair C are exactly the same and the DC bias voltages are also the same, then the parasitic parameters from the second output terminal outn to the ground remain the same under different gains, so its phase can also remain the same under different gain states.

[0098] From the above analysis, it can be seen that under the action of the above two mechanisms, the variable gain amplifier can maintain an extremely low phase shift while changing the gain.

[0099] In this embodiment, 4 differential pairs are taken as an example to implement the control bit number of a 1-bit variable gain amplifier. In other embodiments, the present invention can also be expanded to 8 differential pairs, 12 differentials, 16 differential pairs, etc., to implement 2-bit, 3-bit and 4-bit variable gain amplifiers.

[0100] For example, the amplifier further includes two fifth differential pairs and two sixth differential pairs, that is, a total of 8 differential pairs, where:

[0101] The fifth differential pair includes a ninth cascode structure and a tenth cascode structure that are cross-coupled, the ninth cascode structure includes a ninth input transistor and a ninth output transistor, and the tenth cascode structure includes a tenth input transistor and a tenth output transistor;

[0102] The sixth differential pair includes an eleventh cascode structure and a twelfth cascode structure that are cross-coupled, the eleventh cascode structure includes an eleventh input transistor and an eleventh output transistor, and the twelfth cascode structure includes a twelfth input transistor and a twelfth output transistor.

[0103] The connection method of the fifth differential pair and the sixth differential pair is exactly the same as that of the first differential pair A and the fourth differential pair D, and the second differential pair B and the third differential pair C, and will not be described again here.

[0104] The size ratio of the ninth input transistor to the ninth output transistor, the size ratio of the tenth input transistor to the tenth output transistor, the size ratio of the eleventh input transistor to the eleventh output transistor, and the size ratio of the twelfth input transistor to the twelfth output transistor are equal and equal to the size ratio of the first input transistor to the first output transistor;

[0105] The sizes of the ninth input transistor, the tenth input transistor, the eleventh input transistor and the twelfth input transistor are equal, and are not equal to the sizes of the first input transistor and the third input transistor;

[0106] The sizes of the ninth output transistor, the tenth output transistor, the eleventh output transistor, and the twelfth output transistor are equal, and are different from the sizes of the first output transistor and the third output transistor.

[0107] For a structure with 8 differential pairs, the sizes of the differential pairs are the same, and there are a total of four groups of differential pairs with different sizes. More pairs of differential pairs must also have the same sizes, and the sizes of each pair of differential pairs can be different, but there must be a pair with the largest size.

[0108] The variable gain amplifier of the present invention can be applied to microwave bands and millimeter wave bands, and can achieve extremely low phase error in a large gain variation range, and can also achieve a 180° phase shift function, and has ultra-low additional phase shift characteristics while gain changes. Of course, the present invention is not limited to microwave bands and millimeter wave bands, and can be applied to other frequency bands.

[0109] It can be seen from the above technical solutions that the present invention has the following advantages:

[0110] The variable gain amplifier of the present invention breaks through the limitation that conventional variable gain amplifier designs require multiple stages or additional passive devices to achieve extremely low phase errors. It can achieve extremely low phase errors in a larger gain variation range through only a single-stage common-source and common-gate structure. At the same time, it has a 180° inversion function and has a wide range of applications.

[0111] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0112] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A variable gain amplifier, characterized in that: The amplifier includes a first differential pair, a second differential pair and / or a third differential pair, and a fourth differential pair, wherein: The first differential pair includes a cross-coupled first cascode structure and a second cascode structure, the first cascode structure includes a first input transistor and a first output transistor, and the second cascode structure includes a second input transistor and a second output transistor; The second differential pair includes a third cascode structure and a fourth cascode structure that are cross-coupled, the third cascode structure includes a third input transistor and a third output transistor, and the fourth cascode structure includes a fourth input transistor and a fourth output transistor; The third differential pair includes a cross-coupled fifth cascode structure and a sixth cascode structure, the fifth cascode structure includes a fifth input transistor and a fifth output transistor, and the sixth cascode structure includes a sixth input transistor and a sixth output transistor; The fourth differential pair includes a seventh cascode structure and an eighth cascode structure that are cross-coupled, the seventh cascode structure includes a seventh input transistor and a seventh output transistor, and the eighth cascode structure includes an eighth input transistor and an eighth output transistor; The first input transistor, the third input transistor, the fifth input transistor, and the seventh input transistor are respectively connected to the first differential signal, and the second input transistor, the fourth input transistor, the sixth input transistor, and the eighth input transistor are respectively connected to the second differential signal; The first output transistor, the third output transistor, the sixth output transistor, and the eighth output transistor are respectively connected to the first output terminal, and the second output transistor, the fourth output transistor, the fifth output transistor, and the seventh output transistor are respectively connected to the second output terminal; The on and off of the first differential pair, the second differential pair, the third differential pair, and the fourth differential pair are controlled by a first control signal, a second control signal, a third control signal, and a fourth control signal, respectively, and the fourth control signal is an inverse signal of the first control signal, and the third control signal is an inverse signal of the second control signal.

2. The variable gain amplifier according to claim 1, characterized in that: The amplifier includes a first differential pair, a second differential pair, a third differential pair, and a fourth differential pair, and the amplifier includes: In the forward high gain state, the first control signal is a low level signal, the second control signal is a low level signal, the third control signal is a high level signal, and the second control signal is a high level signal; In the forward low gain state, the first control signal is a high level signal, the second control signal is a low level signal, the third control signal is a high level signal, and the second control signal is a low level signal; In the reverse high gain state, the first control signal is a high level signal, the second control signal is a high level signal, the third control signal is a low level signal, and the second control signal is a low level signal; In the reverse low gain state, the first control signal is a low level signal, the second control signal is a high level signal, the third control signal is a low level signal, and the second control signal is a high level signal.

3. The variable gain amplifier according to claim 2, characterized in that: The size ratio of the first input transistor to the first output transistor, the size ratio of the second input transistor to the second output transistor, the size ratio of the third input transistor to the third output transistor, the size ratio of the fourth input transistor to the fourth output transistor, the size ratio of the fifth input transistor to the fifth output transistor, the size ratio of the sixth input transistor to the sixth output transistor, the size ratio of the seventh input transistor to the seventh output transistor, and the size ratio of the eighth input transistor to the eighth output transistor are all equal; The sizes of the first input transistor, the second input transistor, the seventh input transistor, and the eighth input transistor are equal, the sizes of the third input transistor, the fourth input transistor, the fifth input transistor, and the sixth input transistor are equal, and the sizes of the first input transistor, the second input transistor, the seventh input transistor, and the eighth input transistor are smaller than the sizes of the third input transistor, the fourth input transistor, the fifth input transistor, and the sixth input transistor; The sizes of the first output transistor, the second output transistor, the seventh output transistor, and the eighth output transistor are equal, the sizes of the third output transistor, the fourth output transistor, the fifth output transistor, and the sixth output transistor are equal, and the sizes of the first output transistor, the second output transistor, the seventh output transistor, and the eighth output transistor are smaller than the sizes of the third output transistor, the fourth output transistor, the fifth output transistor, and the sixth output transistor.

4. The variable gain amplifier according to claim 2, characterized in that: The gate of the first input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the first input transistor is connected to the source of the first output transistor, the gate of the first output transistor is connected to the first control signal, and the drain is connected to the first output terminal; The gate of the second input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the second input transistor is connected to the source of the second output transistor, the gate of the second output transistor is connected to the first control signal, and the drain is connected to the second output terminal; The gate of the third input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the third input transistor is connected to the source of the third output transistor, the gate of the third output transistor is connected to the second control signal, and the drain is connected to the first output terminal; The gate of the fourth input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the fourth input transistor is connected to the source of the fourth output transistor, the gate of the fourth output transistor is connected to the second control signal, and the drain is connected to the second output terminal; The gate of the fifth input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the fifth input transistor is connected to the source of the fifth output transistor, the gate of the fifth output transistor is connected to the third control signal, and the drain is connected to the second output terminal; The gate of the sixth input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the sixth input transistor is connected to the source of the sixth output transistor, the gate of the sixth output transistor is connected to the third control signal, and the drain is connected to the first output terminal; The gate of the seventh input transistor is connected to the first differential signal, the source is connected to the reference potential, the drain of the seventh input transistor is connected to the source of the seventh output transistor, the gate of the seventh output transistor is connected to the fourth control signal, and the drain is connected to the second output terminal; The gate of the eighth input transistor is connected to the second differential signal, the source is connected to the reference potential, the drain of the eighth input transistor is connected to the source of the eighth output transistor, the gate of the eighth output transistor is connected to the fourth control signal, and the drain is connected to the first output terminal.

5. The variable gain amplifier according to claim 4, characterized in that: A neutralization capacitor is electrically connected between the gate of the first input transistor and the drain of the second input transistor, between the gate of the second input transistor and the drain of the first input transistor, between the gate of the third input transistor and the drain of the fourth input transistor, between the gate of the fourth input transistor and the drain of the third input transistor, between the gate of the fifth input transistor and the drain of the sixth input transistor, between the gate of the sixth input transistor and the drain of the fifth input transistor, between the gate of the seventh input transistor and the drain of the eighth input transistor, and between the gate of the eighth input transistor and the drain of the third input transistor.

6. The variable gain amplifier according to claim 3, characterized in that: The amplifier further includes a plurality of fifth differential pairs and a sixth differential pair, wherein: The fifth differential pair includes a ninth cascode structure and a tenth cascode structure that are cross-coupled, the ninth cascode structure includes a ninth input transistor and a ninth output transistor, and the tenth cascode structure includes a tenth input transistor and a tenth output transistor; The sixth differential pair includes an eleventh cascode structure and a twelfth cascode structure that are cross-coupled, the eleventh cascode structure includes an eleventh input transistor and an eleventh output transistor, and the twelfth cascode structure includes a twelfth input transistor and a twelfth output transistor.

7. The variable gain amplifier according to claim 6, characterized in that: The size ratio of the ninth input transistor to the ninth output transistor, the size ratio of the tenth input transistor to the tenth output transistor, the size ratio of the eleventh input transistor to the eleventh output transistor, and the size ratio of the twelfth input transistor to the twelfth output transistor are equal, and are equal to the size ratio of the first input transistor to the first output transistor; The sizes of the ninth input transistor, the tenth input transistor, the eleventh input transistor and the twelfth input transistor are equal, and are not equal to the sizes of the first input transistor and the third input transistor; The sizes of the ninth output transistor, the tenth output transistor, the eleventh output transistor and the twelfth output transistor are equal, and are different from the sizes of the first output transistor and the third output transistor.

8. The variable gain amplifier according to claim 4, characterized in that: The first to eighth input transistors and the first to eighth output transistors are NMOS transistors or PMOS transistors.

9. The variable gain amplifier according to claim 1, characterized in that: The first output terminal and the second output terminal are respectively connected to the first input terminal and the second input terminal of an output load, and the output load is a combination of one or more of a transformer, a transmission line, a capacitor, an inductor, and a resistor.

10. An application of a variable gain amplifier as claimed in any one of claims 1 to 9, characterized in that: The variable gain amplifier is applied to a microwave band or a millimeter wave band.

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