Mainframe hardware fault identification method, device, equipment and storage medium

Abstract

This specification relates to a large-scale mainframe hardware fault identification technology in the financial field or other fields, and provides a large-scale mainframe hardware fault identification method, device, equipment and storage medium, the method comprising: extracting keyword English entities from the hardware English alarm history information of the target host system; quantizing and encoding the keyword English entities according to the frequency of occurrence of each type of letters to obtain a fault feature sequence set; training a hidden Markov model according to the fault feature sequence set to obtain a hardware fault identification model; and using the hardware fault identification model to identify the hardware fault of the target host system. The embodiments of this specification can improve the timeliness of large-scale mainframe hardware fault identification.

Description

Technical Field

[0001] The present specification relates to a mainframe hardware fault identification technology in the financial field or other fields, and in particular to a mainframe hardware fault identification method, device, equipment and storage medium. Background Art

[0002] At present, data centers in the financial sector generally use large hosts imported from abroad. These large hosts have complex internal structures, and their technical documents are often written in English and number nearly a thousand pages. In many cases, the hardware alarms (described in English) of large hosts are not hardware fault alarms, so they need to be identified. At present, when the English description of hardware alarms is found, it is generally identified manually based on the English description of the fault alarm and the technical documents; this method is time-consuming and labor-intensive, and has low timeliness. Summary of the invention

[0003] The purpose of the embodiments of this specification is to provide a mainframe hardware fault identification method, device, equipment and storage medium to improve the timeliness of mainframe hardware fault identification.

[0004] To achieve the above objectives, on the one hand, an embodiment of this specification provides a method for identifying a hardware fault of a large mainframe, comprising:

[0005] Extract keyword English entities from the target host system's hardware English alarm history information;

[0006] The keyword English entities are quantized and encoded according to the frequency of occurrence of each type of letters to obtain a fault feature sequence set;

[0007] Training a hidden Markov model according to the fault feature sequence set to obtain a hardware fault identification model;

[0008] The hardware fault identification model is used to identify hardware faults of the target host system.

[0009] In an embodiment of this specification, the training of a hidden Markov model according to the fault feature sequence set includes:

[0010] According to the formula Iteratively update the hidden Markov model until the logarithmic difference of the probability values ​​of two adjacent iterations is less than a given threshold, and use the hidden Markov model at this time as a hardware fault identification model;

[0011] in, is the state transition probability matrix of the target host system from implicit state i to implicit state j; is the output probability matrix of the target host system when the fault feature sequence k appears in the hidden state j; l is the number variable of the observation sequence sample set; L is the total number of samples of l; t is the observation state time point variable; T is the total number of samples of t; M is the total number of hidden states; is the observation sequence (O1, O2, ..., O t ) probability of occurrence; a ij is the state transition probability of the target host system from implicit state i to implicit state j; is the observed value under the hidden state j Probability of occurrence; is the observation sequence (O i+2 ,O i+3 ,…,O T ) probability of occurrence; is the observation sequence (O t+1 ,O t+2 ,…,O T ) probability of occurrence; is the observation sequence (O1, O2, ..., O t+1 ) probability of occurrence; is the observation sequence (O1, O2, ..., O t ) probability of occurrence; is the observation sequence (O t+1 ,O t+2 ,…,O T ) occurs; O t =v k represents the observation value O at time t t The value of v k .

[0012] In the embodiments of this specification, the given threshold is determined in advance according to the following formula:

[0013]

[0014] Where thd(F) is the given threshold corresponding to fault F, γ is the proportional coefficient; K is the number of fault feature sequence groups; (i) is the i-th fault feature sequence; F is the hidden Markov model corresponding to fault F; P(O (i) |λ F ) is the value in the model λ F Next O (i) Probability of occurrence; len(O (i) ) is the fault feature sequence O (i) The dimension length is long.

[0015] In an embodiment of this specification, the step of using the hardware fault identification model to identify the hardware fault of the target host system includes:

[0016] Quantify and encode the hardware English alarm information to be identified of the target host system into a fault feature sequence to be identified;

[0017] Inputting the to-be-identified fault feature sequence into each model of the hardware fault identification model set, so as to find the maximum output probability logarithm value under all models of the hardware fault identification model set;

[0018] The maximum output probability logarithm value is compared with a given threshold of the corresponding model to determine the hardware fault type corresponding to the hardware English alarm information to be identified.

[0019] In an embodiment of this specification, comparing the maximum output probability logarithm value with a given threshold of the corresponding model includes:

[0020] When the comparison result satisfies When the hardware English alarm information is confirmed to be a hardware failure alarm information;

[0021] Where G is the fault indicator; O (i) is the fault feature sequence to be identified; G is the hidden Markov model corresponding to fault G; P(O (i) |λ G ) is the value in the model λ F Next O (i) Probability of occurrence; len(O (i) ) is the fault feature sequence to be identified O (i) The dimension length is long; thd() is the given threshold calculation formula.

[0022] In an embodiment of this specification, the method further includes:

[0023] The hardware fault identification model is updated.

[0024] In an embodiment of this specification, the updating of the hardware fault identification model includes:

[0025] According to the formula Updating the hardware fault identification model;

[0026] in, is the state transition probability matrix obtained by training the hardware fault recognition model based on the fault feature sequence set after adding the hth group of fault feature sequences; K is the number of fault feature sequence groups in the fault feature sequence set; I h is the number of learning updates based on the initial model; is the state transition probability matrix of the hardware fault identification model before adding the hth group of fault feature sequences; a ij ' is the state transition probability matrix obtained by training the hardware fault identification model using the hth group of fault feature sequences alone; is the output probability matrix obtained by training the hardware fault identification model based on the fault feature sequence set after adding the hth group of fault feature sequences; is the output probability matrix of the hardware fault identification model before adding the hth group of fault feature sequences, b jk ' is the output probability matrix obtained by training the hardware fault identification model using the hth group of fault feature sequences alone.

[0027] On the other hand, the embodiment of this specification also provides a large host hardware fault identification device, including:

[0028] An entity extraction module, used to extract keyword English entities from the hardware English alarm history information of the target host system;

[0029] A quantization encoding module, used for quantizing and encoding the keyword English entity according to the frequency of occurrence of each type of letters to obtain a fault feature sequence set;

[0030] A model training module, used for training a hidden Markov model according to the fault feature sequence set to obtain a hardware fault identification model;

[0031] The fault identification module is used to identify the hardware faults of the target host system using the hardware fault identification model.

[0032] On the other hand, an embodiment of the present specification further provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein when the computer program is executed by the processor, the instructions of the above method are executed.

[0033] On the other hand, an embodiment of the present specification further provides a computer storage medium on which a computer program is stored. When the computer program is executed by a processor of a computer device, the instructions of the above method are executed.

[0034] It can be seen from the technical solutions provided by the above embodiments of this specification that, in the embodiments of this specification, after extracting the keyword English entities from the hardware English alarm history information of the target host system, the keyword English entities can be quantized and encoded according to the frequency of each type of letters to obtain a fault feature sequence set; then the hidden Markov model is trained according to the fault feature sequence set to obtain a hardware fault identification model; on this basis, the hardware fault identification model can be used to identify the hardware faults of the target host system, thereby realizing the automatic location of the hardware faults of the large host, improving the timeliness of locating the hardware faults of the large host, and saving labor costs. Not only that, compared with conventional fixed keyword matching, in the embodiments of this specification, the quantization encoding of the keyword English entities according to the frequency of each type of letters has better flexibility, and also has better applicability for the diversity of keyword English entities for the same type of faults. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art description. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. In the drawings:

[0036] Figure 1 A schematic diagram showing an application scenario of a large host hardware fault identification device in some embodiments of this specification;

[0037] Figure 2 A flowchart of a method for identifying a mainframe hardware failure in some embodiments of this specification is shown;

[0038] Figure 3 It shows a structural block diagram of a large host hardware fault identification device in some embodiments of this specification;

[0039] Figure 4 The structure block diagram of the computer device in some embodiments of the present specification is shown.

[0040] [Description of Reference Numerals]

[0041] 31. Entity extraction module;

[0042] 32. Quantization coding module;

[0043] 33. Model training module;

[0044] 34. Fault identification module;

[0045] 402. Computer equipment;

[0046] 404, processor;

[0047] 406. Memory;

[0048] 408. Driving mechanism;

[0049] 410, input / output interface;

[0050] 412. Input devices;

[0051] 414. Output device;

[0052] 416. Presentation equipment;

[0053] 418. Graphical user interface;

[0054] 420, network interface;

[0055] 422. Communication link;

[0056] 424. Communication bus. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this specification.

[0058] The embodiments of this specification relate to mainframe hardware fault identification technology. Among them, mainframes are generally large computer systems that use dedicated processor instruction sets, operating systems, and application software, and usually have high reliability, high availability, high serviceability, and high security, and are often used in commercial fields such as banking and telecommunications. At present, data centers in the domestic financial field generally use mainframes imported from abroad. These mainframes have complex internal structures, and their technical documents are often written in English and number nearly a thousand pages. It is difficult for operation and maintenance personnel to identify their hardware fault alarms in a timely manner. Especially for non-professionals, when the English description of the fault alarm is found, it is necessary to manually locate the faulty component based on the English description of the fault alarm and the technical documents, which is time-consuming and laborious.

[0059] In view of this, in order to improve the efficiency of locating large-scale mainframe hardware failures and reduce labor costs, the embodiments of this specification provide a technical solution for automatically locating large-scale mainframe hardware failures based on fault alarm English information. Figure 1As shown, some embodiments provide a mainframe hardware fault identification device 10 to obtain hardware English alarm history information from a mainframe 20, train a Hidden Markov Model (HMM) based on the hardware English alarm history information to obtain a hardware fault identification model; and use the hardware fault identification model to identify hardware faults of a target host system, thereby achieving automatic location of mainframe hardware faults.

[0060] Those skilled in the art should understand that in the embodiments of this specification, the use of HMM in training the initial model is only an exemplary description; in other embodiments, any other suitable machine learning model may be used as the initial training model, and this specification does not limit this, and the specific selection can be made as needed.

[0061] refer to Figure 2 As shown, the embodiment of this specification provides a mainframe hardware fault identification method applicable to the mainframe hardware fault identification device mentioned above, which may include the following steps:

[0062] S201. Extract keyword English entities from the hardware English alarm history information of the target host system.

[0063] S202 , quantize and encode the keyword English entities according to the frequency of occurrence of each type of letters to obtain a fault feature sequence set.

[0064] S203: training a hidden Markov model according to the fault feature sequence set to obtain a hardware fault identification model.

[0065] S204: Use the hardware fault identification model to identify hardware faults of the target host system.

[0066] In the embodiments of this specification, after extracting the keyword English entity from the hardware English alarm history information of the target host system, the keyword English entity can be quantized and encoded according to the frequency of each type of letters to obtain a fault feature sequence set; then the hidden Markov model is trained according to the fault feature sequence set to obtain a hardware fault identification model; on this basis, the hardware fault identification model can be used to identify the hardware fault of the target host system, thereby realizing the automatic location of the hardware fault of the large host, improving the timeliness of locating the hardware fault of the large host, and saving labor costs. Not only that, compared with conventional fixed keyword matching, in the embodiments of this specification, the quantization encoding of the keyword English entity according to the frequency of each type of letters has better flexibility, and also has better applicability for the diversity of keyword English entities for the same type of faults.

[0067] The target host system is a large host that needs to be monitored for hardware faults; since a large host may have multiple hardware faults, a corresponding hardware fault identification model can be constructed for each hardware fault. Therefore, in some embodiments, extracting keyword English entities from the hardware English alarm history information of the target host system may include the following steps:

[0068] 1) From the alarm database of the target host system, for each type of hardware failure, select the hardware English alarm history information within the specified range, thereby obtaining the corresponding hardware alarm data set. The specified range may be a specified time range (e.g., within one year, within three years, within five years, etc.) and / or a specified space range (e.g., a mainframe in a single data center, a mainframe in all domestic data centers, etc.). For example, in an exemplary embodiment, the types of hardware failures in the data center of Bank A can be divided into four types, C1 to C4, and the specified range may be the hardware failures of all domestic data centers of Bank A within three years. For example, for the four types of hardware failures C1 to C4, four hardware alarm data sets D1 to D4 can be selected from the alarm database of the target host system. D1 corresponds to hardware failure C1, D2 corresponds to hardware failure C2, D3 corresponds to hardware failure C3, and D4 corresponds to hardware failure C4. Each hardware alarm data set may include multiple hardware alarm information of the same type of hardware failure.

[0069] 2) Preprocess the hardware alarm data set corresponding to each type of hardware fault. Since the structural formats of the alarm data of different large hosts may be different (for example, the alarm data of some large hosts may be structured text, while the alarm data of other large hosts may be unstructured text, etc.), in order to facilitate subsequent processing, standardization and other preprocessing can be performed first. Of course, in order to facilitate the subsequent quantitative encoding of the keyword English entity according to the frequency of occurrence of each type of letter, the preprocessing can also include the step of uniformly changing the uppercase letters in the hardware English alarm history information to lowercase letters.

[0070] 3) For each preprocessed hardware alarm data set, extract the keyword English entity of each hardware alarm information, so as to obtain the keyword English entity set corresponding to each type of hardware failure. In some embodiments, the keyword English entity can be extracted based on rules and statistics, combined with English text context information. Among them, the keyword English entity can be used to characterize the core information content or main information content of the hardware alarm information; each keyword English entity can be an English text of a specified length containing one or more English keywords.

[0071] The keyword English entity cannot be directly used as the input for training the initial model (i.e., the initial HMM model), so the keyword English entity needs to be quantized and encoded. In other words, after obtaining the keyword English entity, the characteristic value of the keyword English entity can be represented by the digital code after discrete quantization. For example, in some embodiments, the keyword English entity can be quantized and encoded according to the frequency of occurrence of each type of letters, so as to obtain a fault feature sequence set, which can specifically include: for the keyword English entity set corresponding to each type of hardware fault, the keyword English entity can be quantized and encoded according to the frequency of occurrence of 26 English letters, so as to obtain a fault feature sequence set for each type of hardware fault.

[0072] Assuming that the fault feature sequence set of each type of hardware fault has K fault feature sequences (the fault feature sequence is the observation sequence), then for any type of hardware fault, its fault feature sequence set can be expressed as The i-th observation sequence in the fault feature sequence set can be expressed as Wherein, T is the sample dimension (in the embodiment of this specification, the value of T is 26). For example, in one embodiment, the fault feature sequence set of a certain type of hardware fault can be expressed as:

[0073]

[0074] For example, in an exemplary embodiment, assuming that a keyword English entity of a type of hardware failure is "mirrorhard disk drive failure", based on the above-mentioned quantization encoding method, the occurrence frequencies of 26 English letters a to z can be first counted: a: 2, b: 0, c: 0, d: 3, e: 2, f: 1, g: 0, h: 1, i: 4, j: 0, k: 0, l: 0, m: 1, n: 0, o: 1, p: 0, q: 0, r: 6, s: 1, t: 0, u: 1, v: 1, w: 0, x: 0, y: 0, z: 0; accordingly, the keyword English entity can be quantized and encoded as:

[0075] o={2,0,0,3,2,1,0,1,4,0,1,0,1,0,1,0,0,6,1,0,1,1,0,0,0,0}

[0076] Recursively in this way, a fault feature sequence set can be generated for each type of hardware fault to serve as a data set for training the hardware fault model of this type.

[0077] In some embodiments, when training an HMM model based on a fault feature sequence set, the HMM model can be iteratively updated according to the following formula until the logarithmic difference of the probability values ​​of two adjacent iterations is less than a given threshold, and the HMM model at this time is used as a hardware fault identification model.

[0078]

[0079] in, is the state transition probability matrix of the target host system from implicit state i to implicit state j; is the output probability matrix of the target host system when the fault feature sequence k appears in the hidden state j; l is the number variable of the observation sequence sample set; L is the total number of samples of l; t is the observation state time point variable; T is the total number of samples of t; M is the total number of hidden states; is the observation sequence (O1, O2, ..., O t ) probability of occurrence; a ij is the state transition probability of the target host system from implicit state i to implicit state j; is the observed value under the hidden state j Probability of occurrence; is the observation sequence (O i+2 ,O i+3 ,…,O T ) probability of occurrence; is the observation sequence (O t+1 ,O t+2 ,…,O T ) probability of occurrence; is the observation sequence (O1, O2, ..., O t+1 ) probability of occurrence; is the observation sequence (O1, O2, ..., O t ) probability of occurrence; is the observation sequence (O t+1 ,O t+2 ,…,O T ) occurs; O t =v k represents the observation value O at time t t The value of v k .

[0080] The above formula modifies the state transition probability matrix by adding a proportional factor And the output probability matrix A re-estimation calculation is performed to solve the underflow problem that occurs during the training of the traditional HMM model. In the embodiment of this specification, if there are N types of hardware fault categories, N training sets are required (each training set corresponds to a type of hardware fault); thus, N initial HMM models are trained based on the N training sets, and N hardware fault recognition models can be obtained.

[0081] When constructing a hardware fault identification model for each type of hardware fault, a corresponding given threshold may be pre-set. For example, in some embodiments, the given threshold for each type of hardware fault may be pre-determined according to the following formula:

[0082]

[0083] Where thd(F) is the given threshold corresponding to fault F, γ is the proportional coefficient; K is the number of fault feature sequence groups; (i) is the i-th fault feature sequence; F is the hidden Markov model corresponding to fault F; P(O (i) |λ F ) is the value in the model λ F Next O (i) Probability of occurrence; len(O (i) ) is the fault feature sequence O (i) The dimension length is long.

[0084] In the embodiment of this specification, the use of the hardware fault identification model to identify the hardware fault of the target host system may include the following steps:

[0085] 1) Quantify and encode the hardware English alarm information to be identified of the target host system into a fault feature sequence to be identified. This step can be a real-time step, and the hardware English alarm information to be identified can be the hardware English alarm information discovered in real time, and it can be quantified and encoded in real time into a fault feature sequence to be identified, so that it can be directly input into the hardware fault identification model; this can facilitate timely hardware fault location.

[0086] 2) Inputting the to-be-identified fault feature sequence into each model of the hardware fault identification model set, so as to find the maximum output probability logarithm value under all models of the hardware fault identification model set.

[0087] 3) Compare the maximum output probability logarithm value with a given threshold of the corresponding model to determine the hardware fault type corresponding to the hardware English alarm information to be identified.

[0088] In some embodiments, comparing the maximum output probability logarithm value with a given threshold of the corresponding model may include: when the comparison result satisfies , confirming that the hardware English alarm information is a hardware fault alarm information; wherein G is a fault identifier; O (i) is the fault feature sequence to be identified; G is the hidden Markov model corresponding to fault G; P(O (i) |λ G ) is the value in the model λ F Next O (i)Probability of occurrence; len(O (i) ) is the fault feature sequence to be identified O (i) The dimension length is long; thd() is the given threshold calculation formula.

[0089] In some embodiments, when the hardware English alarm information is identified as hardware fault alarm information, the hardware fault alarm information can also be sent to a designated person (eg, an operation and maintenance person) so that the designated person can respond and handle it in a timely manner.

[0090] In other embodiments, in order to improve the accuracy of the hardware fault identification, the hardware fault identification model can also be updated in a timely manner. For example, in some embodiments, updating the hardware fault identification model may include: according to the formula Updating the hardware fault identification model can not only improve the fault identification rate, but also expand the identification scope of similar hardware faults and have better applicability.

[0091] in, is the state transition probability matrix obtained by training the hardware fault recognition model based on the fault feature sequence set after adding the hth group of fault feature sequences; K is the number of fault feature sequence groups in the fault feature sequence set; I h is the number of learning updates based on the initial model; is the state transition probability matrix of the hardware fault identification model before adding the hth group of fault feature sequences; a ij ' is the state transition probability matrix obtained by training the hardware fault identification model using the hth group of fault feature sequences alone; is the output probability matrix obtained by training the hardware fault identification model based on the fault feature sequence set after adding the hth group of fault feature sequences; is the output probability matrix of the hardware fault identification model before adding the hth group of fault feature sequences, b jk ' is the output probability matrix obtained by training the hardware fault identification model using the hth group of fault feature sequences alone.

[0092] It should be noted that the update timing of updating the hardware fault identification model using the above formula can be: after each hardware fault is successfully identified using the hardware fault identification model set, the corresponding fault data (i.e., the corresponding fault feature sequence) is added to the corresponding training set, and the corresponding model in the hardware fault identification model set is updated. For example, taking the newly discovered h-th group of fault feature sequences as input, when a hardware fault is successfully identified using model A in the hardware fault identification model set, the h-th group of fault feature sequences can be added to the training set X of model A, and then model A is optimized and updated according to the training set X.

[0093] Although the process flows described above include multiple operations that occur in a particular order, it should be clearly understood that the processes may include more or fewer operations, which may be performed sequentially or in parallel (eg, using parallel processors or a multi-threaded environment).

[0094] refer to Figure 3 As shown, in some embodiments of this specification, a mainframe hardware fault identification device may include:

[0095] The entity extraction module 31 can be used to extract keyword English entities from the hardware English alarm history information of the target host system;

[0096] The quantization encoding module 32 may be used to quantize and encode the keyword English entity according to the frequency of occurrence of each type of letters to obtain a fault feature sequence set;

[0097] The model training module 33 can be used to train a hidden Markov model according to the fault feature sequence set to obtain a hardware fault identification model;

[0098] The fault identification module 34 may be used to identify hardware faults of the target host system using the hardware fault identification model.

[0099] In the embodiment of the present specification, on the basis of the entity extraction module 31 extracting the keyword English entity from the hardware English alarm history information of the target host system, the quantization coding module 32 can quantize and code the keyword English entity according to the frequency of each type of letters to obtain a fault feature sequence set; so that the model training module 33 can train the hidden Markov model according to the fault feature sequence set, thereby obtaining a hardware fault identification model; on this basis, the fault identification module 34 can use the hardware fault identification model to identify the hardware fault of the target host system, thereby realizing the automatic location of the hardware fault of the large host, improving the timeliness of locating the hardware fault of the large host, and saving labor costs. Not only that, compared with conventional fixed keyword matching, in the embodiment of the present specification, quantizing and coding the keyword English entity according to the frequency of each type of letters has better flexibility, and also has better applicability for the diversity of keyword English entities for the same type of faults.

[0100] In some device embodiments, training a hidden Markov model according to the fault feature sequence set may include:

[0101] According to the formula The hidden Markov model is iteratively updated until the logarithmic difference of the probability values ​​of two adjacent iterations is less than a given threshold, and the hidden Markov model at this time is used as a hardware fault identification model.

[0102] In some device embodiments, a given threshold for each type of hardware failure may be determined in advance according to the following formula;

[0103]

[0104] In some device embodiments, the using the hardware fault identification model to identify the hardware fault of the target host system may include:

[0105] Quantify and encode the hardware English alarm information to be identified of the target host system into a fault feature sequence to be identified;

[0106] Inputting the to-be-identified fault feature sequence into each model of the hardware fault identification model set, so as to find the maximum output probability logarithm value under all models of the hardware fault identification model set;

[0107] The maximum output probability logarithm value is compared with a given threshold of the corresponding model to determine the hardware fault type corresponding to the hardware English alarm information to be identified.

[0108] In some device embodiments, comparing the maximum output probability logarithm value with a given threshold of the corresponding model may include:

[0109] When the comparison result satisfies , confirm that the hardware English alarm information is a hardware failure alarm information.

[0110] In some embodiments, the mainframe hardware fault identification apparatus may further include a model optimization module, which may be used to update the hardware fault identification model.

[0111] In some device embodiments, updating the hardware fault identification model may include:

[0112] According to the formula The hardware fault identification model is updated.

[0113] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0114] The embodiments of this specification also provide a computer device. Figure 4As shown, in some embodiments of the present specification, the computer device 402 may include one or more processors 404, such as one or more central processing units (CPUs) or graphics processing units (GPUs), and each processing unit may implement one or more hardware threads. The computer device 402 may also include any memory 406, which is used to store any kind of information such as code, settings, data, etc. In a specific embodiment, the computer program on the memory 406 and can be run on the processor 404, when the computer program is run by the processor 404, the instructions of the mainframe hardware fault identification method described in any of the above embodiments may be executed. Non-limitingly, for example, the memory 406 may include any one or more combinations of the following: any type of RAM, any type of ROM, flash memory device, hard disk, optical disk, etc. More generally, any memory may use any technology to store information. Further, any memory may provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of the computer device 402. In one case, when the processor 404 executes an associated instruction stored in any memory or a combination of memories, the computer device 402 may perform any operation of the associated instruction. The computer device 402 also includes one or more drive mechanisms 408 for interacting with any storage, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0115] The computer device 402 may also include an input / output interface 410 (I / O) for receiving various inputs (via input device 412) and for providing various outputs (via output device 414). A specific output mechanism may include a presentation device 416 and an associated graphical user interface 418 (GUI). In other embodiments, the input / output interface 410 (I / O), input device 412, and output device 414 may not be included, and the computer device 402 may be used as a computer device in a network. The computer device 402 may also include one or more network interfaces 420 for exchanging data with other devices via one or more communication links 422. One or more communication buses 424 couple the components described above together.

[0116] The communication link 422 may be implemented in any manner, for example, through a local area network, a wide area network (e.g., the Internet), a point-to-point connection, etc., or any combination thereof. The communication link 422 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0117] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products of some embodiments of the present specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processor to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processor generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0118] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processor to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0119] These computer program instructions can also be loaded onto a computer or other programmable data processor so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0120] In a typical configuration, a computer device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0121] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0122] Computer-readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computer device. As defined in this specification, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0123] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, the embodiments of this specification may take the form of complete hardware embodiments, complete software embodiments or embodiments combining software and hardware. Moreover, the embodiments of this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0124] The present specification embodiments may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present specification embodiments may also be practiced in distributed computing environments where tasks are performed by remote processors connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0125] It should also be understood that in the embodiments of this specification, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0126] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. In the description of this specification, the description of the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of this specification. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, in the absence of contradiction, a person skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0127] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for identifying a hardware failure of a large mainframe, characterized in that: include: Extract keyword English entities from the target host system's hardware English alarm history information; For the keyword English entity set corresponding to each type of hardware fault, the occurrence frequency of 26 English letters in it is counted respectively, and the occurrence frequency of each English letter is sorted according to the order of the 26 English letters to obtain the fault feature sequence set; Training a hidden Markov model according to the fault feature sequence set to obtain a hardware fault identification model; The hardware fault identification model is used to identify hardware faults of the target host system.

2. The mainframe hardware fault identification method according to claim 1, characterized in that: The step of training a hidden Markov model according to the fault feature sequence set comprises: According to the formula Iteratively update the hidden Markov model until the logarithmic difference of the probability values ​​of two adjacent iterations is less than a given threshold, and use the hidden Markov model at this time as a hardware fault identification model; in, is the state transition probability matrix of the target host system from implicit state i to implicit state j; is the output probability matrix of the target host system when the fault feature sequence k appears in the hidden state j; l is the number variable of the observation sequence sample set; L is the total number of samples of l; t is the observation state time point variable; T is the total number of samples of t; M is the total number of hidden states; is the observation sequence (O1, O2, ..., O t ) probability of occurrence; a ij is the state transition probability of the target host system from implicit state i to implicit state j; is the observed value under the hidden state j Probability of occurrence; is the observation sequence (O i+2 ,O i+3 ,…,O T ) probability of occurrence; is the observation sequence (O t+1 ,O t+2 ,…,O T ) probability of occurrence; is the observation sequence (O1, O2, ..., O t+1 ) probability of occurrence; is the observation sequence (O1, O2, ..., O t ) probability of occurrence; is the observation sequence (O t+1 ,O t+2 ,…,O T ) occurs; t =v k represents the observation value O at time t t The value of v k .

3. The mainframe hardware fault identification method according to claim 2, characterized in that: The given threshold is predetermined according to the formula Sure; Where thd(F) is the given threshold corresponding to fault F, γ is the proportional coefficient; K is the number of fault feature sequence groups; (i) is the i-th fault feature sequence; F is the hidden Markov model corresponding to fault F; P(O (i) |λ F ) is the value in the model λ F Next O (i) Probability of occurrence; len(O (i) ) is the fault feature sequence O (i) The dimension length of .

4. The mainframe hardware fault identification method according to claim 1, characterized in that: The using the hardware fault identification model to identify the hardware fault of the target host system includes: Quantify and encode the hardware English alarm information to be identified of the target host system into a fault feature sequence to be identified; Inputting the to-be-identified fault feature sequence into each model of the hardware fault identification model set, so as to find the maximum output probability logarithm value under all models of the hardware fault identification model set; The maximum output probability logarithm value is compared with a given threshold of the corresponding model to determine the hardware fault type corresponding to the hardware English alarm information to be identified.

5. The mainframe hardware fault identification method according to claim 4, characterized in that: The step of comparing the maximum output probability logarithm value with a given threshold of the corresponding model comprises: When the comparison result satisfies When the hardware English alarm information is confirmed to be a hardware failure alarm information; Among them, G is the fault indicator; O (i) is the fault feature sequence to be identified; G is the hidden Markov model corresponding to fault G; P(O (i) |λ G ) is the value in the model λ G Next O (i) Probability of occurrence; len(O (i) ) is the fault feature sequence to be identified O (i) Dimension length; thd() is the given threshold calculation formula.

6. The mainframe hardware fault identification method according to claim 1, characterized in that: Also includes: The hardware fault identification model is updated.

7. The mainframe hardware fault identification method according to claim 6, characterized in that: The updating of the hardware fault identification model includes: According to the formula Updating the hardware fault identification model; in, is the state transition probability matrix obtained by training the hardware fault recognition model based on the fault feature sequence set after adding the hth group of fault feature sequences; K is the number of fault feature sequence groups in the fault feature sequence set; I h is the number of learning updates based on the initial model; is the state transition probability matrix of the hardware fault identification model before adding the hth group of fault feature sequences; a ij ' is the state transition probability matrix obtained by training the hardware fault identification model using the hth group of fault feature sequences alone; is the output probability matrix obtained by training the hardware fault identification model based on the fault feature sequence set after adding the hth group of fault feature sequences; is the output probability matrix of the hardware fault identification model before adding the hth group of fault feature sequences, b jk ' is the output probability matrix obtained by training the hardware fault identification model using the hth group of fault feature sequences alone.

8. A large mainframe hardware fault identification device, characterized in that: include: An entity extraction module, used to extract keyword English entities from the hardware English alarm history information of the target host system; A quantitative coding module is used to count the occurrence frequencies of 26 English letters in the keyword English entity set corresponding to each type of hardware fault, and sort the occurrence frequencies of each English letter in the order of the 26 English letters to obtain a fault feature sequence set; A model training module, used for training a hidden Markov model according to the fault feature sequence set to obtain a hardware fault identification model; The fault identification module is used to identify the hardware faults of the target host system using the hardware fault identification model.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: When the computer program is executed by the processor, the computer program executes the instructions of the method according to any one of claims 1 to 7.

10. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor of a computer device, the computer program executes instructions of the method according to any one of claims 1 to 7.

Images