Multilayer capacitor and plate for mounting the multilayer capacitor

Abstract

This invention provides a multilayer capacitor and a plate for mounting the multilayer capacitor. The multilayer capacitor includes: a body comprising an effective region, an upper cover region disposed above the effective region, and a lower cover region disposed below the effective region; the effective region comprising alternately stacked first and second inner electrodes and a dielectric layer disposed between the first and second inner electrodes, the first and second inner electrodes being alternately exposed through two end surfaces of the body; and a first and second outer electrode disposed at both ends of the body and respectively connected to the first and second inner electrodes. The body further includes a buffer layer disposed on the lower surface of the lower cover region, the buffer layer comprising a first and second dummy electrode spaced apart from each other along the length of the body, and a groove recessed in the lower surface of the buffer layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0047201, filed on April 20, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a multilayer capacitor and a plate for mounting the multilayer capacitor. Background Technology

[0003] The demand for passive components is increasing due to the high performance of IT and mobile devices such as electronic products and computers.

[0004] Furthermore, because modern electronic devices require passive components to be placed in a limited board area, the component mounting density increases as the number of mounted components increases.

[0005] Such high-density passive components generate heat and vibration due to their interaction with each other. In this regard, improvements in functionality are required in addition to the characteristics required in existing passive components.

[0006] Multilayer ceramic capacitors (MLCCs) (a type of multilayer chip electronic component) are used in a variety of electronic devices due to their advantages such as small size, high capacitance and ease of installation.

[0007] Multilayer ceramic capacitors can have a structure in which internal electrodes of different polarities are alternately stacked while dielectric layers are interspersed between them.

[0008] In this case, due to the piezoelectric properties of the dielectric layer, when a DC or AC voltage is applied to the multilayer ceramic capacitor, a piezoelectric phenomenon can be generated between the inner electrodes, causing the volume of the ceramic body to expand and contract according to the frequency, thereby generating periodic vibration.

[0009] When mounted on a multilayer capacitor, such vibrations are transmitted to the board through the external electrodes and solder, making the entire board a sound-reflecting surface to produce vibrating sound as noise.

[0010] Vibrating sounds can occur in the audible frequency range of 20 Hz to 20,000 Hz, which can cause discomfort to listeners, and such vibrating sounds that cause discomfort to listeners are referred to as acoustic noise.

[0011] Due to recent reductions in component noise in electronic devices, acoustic noise generated in multilayer capacitors may become more pronounced. Particularly in the case of mobile devices, reducing such acoustic noise can significantly improve acoustic performance and durability. Therefore, there is a need to research techniques that can effectively reduce acoustic noise generated in multilayer capacitors. Summary of the Invention

[0012] One aspect of this disclosure is to provide a multilayer capacitor capable of effectively reducing acoustic noise and a plate for mounting the multilayer capacitor.

[0013] According to one aspect of this disclosure, a multilayer capacitor includes: a body comprising an effective region, an upper cover region disposed above the effective region, and a lower cover region disposed below the effective region, the effective region comprising alternately stacked first and second inner electrodes and a dielectric layer disposed between the first and second inner electrodes, the first and second inner electrodes being alternately exposed through two end surfaces of the body; and a first and second outer electrode disposed at both ends of the body and respectively connected to the first and second inner electrodes. The body further includes a buffer layer disposed on the lower surface of the lower cover region, the buffer layer comprising a first and second dummy electrode spaced apart from each other in the length direction of the body, and grooves recessed in the lower surface of the buffer layer.

[0014] In an example embodiment, the groove may extend from one side surface of the body to the other side surface of the body in the width direction of the body.

[0015] In an example embodiment, the first dummy electrode and the second dummy electrode may be configured on a single dielectric layer to face each other in the length direction.

[0016] In an example embodiment, the first dummy electrode and the second dummy electrode may be exposed through the two end surfaces of the body and connected to the first external electrode and the second external electrode, respectively.

[0017] In an example embodiment, the groove may be disposed between the first dummy electrode and the second dummy electrode.

[0018] In an example embodiment, the thickness of the lower coverage area may be greater than the distance between the first inner electrode and the second inner electrode in the effective area.

[0019] In an example embodiment, a plurality of the grooves may be provided on the lower surface of the buffer layer.

[0020] In an example embodiment, each of the plurality of grooves may extend from one side surface of the body to the other side surface of the body in the width direction of the body.

[0021] In an example embodiment, the buffer layer may further include a third dummy electrode disposed between the first dummy electrode and the second dummy electrode.

[0022] In an example embodiment, the first dummy electrode, the second dummy electrode, and the third dummy electrode are spaced apart from each other on a single dielectric layer along the length of the body.

[0023] In an example embodiment, the first dummy electrode and the second dummy electrode may be exposed through the two end surfaces of the body and may be connected to the first external electrode and the second external electrode, respectively.

[0024] In an example embodiment, one of the plurality of grooves may be disposed between the first dummy electrode and the third dummy electrode, and another of the plurality of grooves may be disposed between the second dummy electrode and the third dummy electrode.

[0025] In an example embodiment, the groove may intersect with the line connecting the first dummy electrode and the second dummy electrode.

[0026] According to another aspect, a board for mounting a multilayer capacitor includes: a board having a first electrode pad and a second electrode pad on one surface thereon; and the multilayer capacitor. The first external electrode and the second external electrode of the multilayer capacitor are mounted to be connected to the first electrode pad and the second electrode pad, respectively. Attached Figure Description

[0027] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 This is a perspective view schematically illustrating a multilayer capacitor according to an exemplary embodiment of the present disclosure;

[0029] Figure 2 yes Figure 1 An inverted perspective view;

[0030] Figures 3A to 3C This shows the application to Figure 1 A perspective view of the first internal electrode and the second internal electrode, as well as the first dummy electrode and the second dummy electrode, of a multilayer capacitor.

[0031] Figure 4 It is along Figure 1 A cross-sectional view taken from line I-I' in the diagram;

[0032] Figure 5 and Figure 6 This is a side cross-sectional view illustrating a method for forming a groove on the mounting surface of a body when manufacturing a multilayer capacitor according to an example embodiment;

[0033] Figure 7 This is a schematic cross-sectional view of a multilayer capacitor according to another example embodiment;

[0034] Figure 8 This shows the application to Figure 7 A plan view of the first to third dummy electrodes of a multilayer capacitor; and

[0035] Figure 9 It is shown schematically. Figure 4 A cross-sectional view of a multilayer capacitor mounted on a plate. Detailed Implementation

[0036] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0037] However, this disclosure may be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein.

[0038] Specifically, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0039] For clarity of description, the shape and size of the elements in the drawings may be exaggerated, and the elements indicated by the same reference numerals in the drawings are the same elements.

[0040] Furthermore, throughout the specification it will be understood that, unless otherwise stated, when a part “includes” an element, it may also include another element, without excluding the other element.

[0041] Multilayer capacitors

[0042] Figure 1 This is a perspective view schematically illustrating a multilayer capacitor according to an exemplary embodiment of the present disclosure. Figure 2 yes Figure 1 The inverted perspective view, and Figures 3A to 3C This shows the application to Figure 1 A perspective view of the first internal electrode and the second internal electrode, as well as the first dummy electrode and the second dummy electrode, of a multilayer capacitor. Figure 4 It is along Figure 1 The cross-sectional view taken from line I-I' in the diagram.

[0043] Reference Figures 1 to 4 According to an example embodiment, the multilayer capacitor 100 may include a body 110 in which a plurality of dielectric layers, a plurality of first inner electrodes 121 and a plurality of second inner electrodes 122 are stacked, and a first outer electrode 131 and a second outer electrode 132 are electrically connected to the first inner electrodes 121 and the second inner electrodes 122, respectively.

[0044] In the following description, for the purpose of illustrating exemplary embodiments in this disclosure, the orientation of the capacitor body 110 is defined as follows: that is, X, Y, and Z shown in the figures represent the length direction, width direction, and thickness direction of the capacitor body 110, respectively.

[0045] The body 110 is formed by alternately stacking and sintering multiple dielectric layers 111 in the Z direction. Adjacent dielectric layers 111 can be integrated, making the boundaries between them potentially difficult to discern without the use of a scanning electron microscope (SEM).

[0046] The main body 110 may have a hexahedral shape, but is not limited to this.

[0047] The shape and size of the body 110 and the number of layers of the dielectric layer 111 are not limited to the shape, size and number of layers shown in the accompanying drawings.

[0048] In the example embodiment, for ease of description, the two surfaces of the body 110 that are opposite to each other in the Z direction are defined as first surface 1 and second surface 2; the two surfaces connected to first surface 1 and second surface 2 and opposite to each other in the X direction are defined as third surface 3 and fourth surface 4; and the two surfaces connected to both first surface 1 and second surface 2, as well as third surface 3 and fourth surface 4 and opposite to each other in the Y direction are defined as fifth surface 5 and sixth surface 6. In this case, first surface 1 may be a mounting surface.

[0049] The dielectric layer 111 may include, but is not limited to, a ceramic material with a high dielectric constant (e.g., BaTiO3-based ceramic powder, etc.), as long as sufficient capacitance can be obtained.

[0050] In addition, ceramic additives, organic solvents, plasticizers, binders, dispersants, etc., can be added to the dielectric layer 111 together with the ceramic powder.

[0051] For example, transition metal oxides or transition metal carbides, rare earth elements, magnesium (Mg), aluminum (Al), etc., can be used as ceramic additives.

[0052] The main body 110 may include: an effective region, which is a portion that contributes to the capacitance of the capacitor; and an upper covering region 112 and a lower covering region 113, which are formed above and below the effective region, respectively, as upper and lower edge portions in the Z direction.

[0053] Except that the upper cover region 112 and the lower cover region 113 do not include internal electrodes, the upper cover region 112 and the lower cover region 113 may have the same material and structure as the dielectric layer 111.

[0054] The upper cover region 112 and the lower cover region 113 can be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the effective region in the Z direction, respectively, and can prevent damage to the inner electrode due to physical or chemical stress.

[0055] The main body 110 includes a first internal electrode 121 and a second internal electrode 122 in the effective area.

[0056] The first inner electrode 121 and the second inner electrode 122 are electrodes with different polarities and are formed on one surface of the dielectric layer 111. One end of the first inner electrode 121 is exposed through the third surface 3 to connect to the first outer electrode 131, and one end of the second inner electrode 122 is exposed through the fourth surface 4 to connect to the second outer electrode 132.

[0057] The first inner electrode 121 and the second inner electrode 122 are electrically insulated from each other by a dielectric layer 111 between them.

[0058] According to the above structure, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge accumulates between the first internal electrode and the second internal electrode.

[0059] The capacitance of the multilayer capacitor 100 is proportional to the area of ​​the first inner electrode 121 and the second inner electrode 122 stacked in the Z direction in the effective region.

[0060] Furthermore, the materials used to form the first internal electrode 121 and the second internal electrode 122 are not specifically limited, but may be conductive pastes formed, for example, using noble metals (such as platinum (Pt), palladium (Pd), palladium-silver (Pd-Ag) alloys, etc.) and at least one of nickel (Ni) and copper (Cu).

[0061] Methods for printing conductive paste include screen printing, gravure printing, etc., but are not limited to these.

[0062] In an example embodiment, the thickness of the lower coverage region 113 may be greater than the distance between the first inner electrode 121 and the second inner electrode 122 in the effective region.

[0063] In this respect, compared with a multilayer capacitor having a structure in which the buffer layer is directly disposed on the lower surface of the effective area without a lower covering area, when the effective area is spaced further away from the mounting surface and the multilayer capacitor 100 is mounted on a plate, the transmission of vibrations generated in the multilayer capacitor 100 can be reduced, thereby further reducing acoustic noise.

[0064] The first external electrode 131 and the second external electrode 132 are provided with voltages of different polarities and are formed at both ends of the body 110 in the X direction.

[0065] The first external electrode 131 and the second external electrode 132 are formed using conductive metals such as silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), copper (Cu), or alloys thereof, but are not limited thereto.

[0066] If necessary, a first plating layer and a second plating layer (not shown) may be formed on the first external electrode 131 and the second external electrode 132.

[0067] The first and second plating layers may include a Ni plating layer formed on the first external electrode 131 and the second external electrode 132, and a tin (Sn) plating layer formed on the Ni plating layer.

[0068] When the multilayer capacitor 100 is mounted on a board, such first and second plating layers act as solder to enhance the adhesion between the multilayer capacitor 100 and the board. The plating process can be performed using known methods.

[0069] The first external electrode 131 may include a first connecting portion 131a and a first strip portion 131b.

[0070] The first connecting portion 131a is formed on the third surface 3 of the body 110 and is connected to the exposed portion of the first internal electrode 121.

[0071] The first strip 131b extends from the first connection 131a to a portion of the first surface 1 of the capacitor body 110.

[0072] The first strip portion 131b may extend further from the first connecting portion 131a to a portion of the second surface 2, the fifth surface 5, and the sixth surface 6 of the capacitor body 110 for enhancing adhesion, etc.

[0073] The second external electrode 132 may include a second connecting portion 132a and a second strip portion 132b.

[0074] The second connection portion 132a is formed on the fourth surface 4 of the main body 110 and is connected to the exposed portion of the second inner electrode 122.

[0075] The second strip 132b extends from the second connecting portion 132a to a portion of the second surface 2 of the capacitor body 110.

[0076] The second strip 132b may extend further from the second connecting portion 132a to a portion of the second surface 2, the fifth surface 5, and the sixth surface 6 of the capacitor body 110 for enhancing adhesion, etc.

[0077] The main body 110 may also include a buffer layer 114 formed on the lower surface of the lower coverage area 113.

[0078] The groove 170 is recessed inward on the lower surface of the buffer layer 114.

[0079] The groove 170 extends linearly from the fifth surface 5 of the body 110 to the sixth surface 6 of the body 110.

[0080] In addition, the plurality of first dummy electrodes 123 and the plurality of second dummy electrodes 124 may be configured to face each other while being spaced apart by a predetermined gap in the X direction relative to the groove 170.

[0081] like Figure 5 and Figure 6 As shown, the gap between the first dummy electrode 123 and the second dummy electrode 124 is an element used to form a groove 170 on the lower surface of the buffer layer 114 during the process of stacking and pressing the cover area, effective area, upper cover area and buffer layer.

[0082] In other words, during pressing, the density of the region without the first dummy electrode and the second dummy electrode is lower than the density of the region with the first dummy electrode and the second dummy electrode, thereby causing a portion of the lower surface of the buffer layer 114 to be recessed and create a step. This is used to form an upwardly recessed groove 170 on the lower surface of the buffer layer 114.

[0083] Therefore, the groove 170 can be disposed in the X direction between the first dummy electrode 123 and the second dummy electrode 124.

[0084] The groove 170 serves as an air layer and is constructed to further reduce the transmission of vibrations generated in the body 110, based on the principle that vibration transmissibility is lower in gases (mediums with lower density) than in solids (mediums with higher density, such as sound barriers or air layer insulators on roads). The groove 170 may intersect with the line 34 connecting the first dummy electrode 123 and the second dummy electrode 124. For example, the groove 170 may intersect with the line 34 connecting the first dummy electrode 123 and the second dummy electrode 124 on at least one dielectric layer 114a.

[0085] In this configuration, the first dummy electrode 123 and the second dummy electrode 124 may be configured on a single dielectric layer 114a to face each other in the X direction of the body 110. Figure 4 The diagram shows a three-layer dielectric layer 114a on which a first dummy electrode 123 and a second dummy electrode 124 are formed, but the number of dielectric layers 114a is not limited to this.

[0086] The first dummy electrode 123 can be exposed through the third surface 3 of the main body to be electrically connected to the first connection portion 131a of the first external electrode 131, and the second dummy electrode 124 can be exposed through the fourth surface 4 of the main body to be electrically connected to the second connection portion 132a of the second external electrode 132.

[0087] Therefore, the equivalent series resistance (ESR) and equivalent series inductance (ESL) of multilayer capacitors can be reduced.

[0088] Typically, as the electrode paths within a multilayer capacitor lengthen, the ESR and ESL values ​​of the multilayer capacitor decrease.

[0089] As mentioned above, reducing the ESL and ESR of multilayer capacitors reduces the noise of electrical signals in IT devices, thereby enhancing the performance of electronic devices.

[0090] Furthermore, the first dummy electrode 123 and the second dummy electrode 124 prevent the lower part of the body 110 from shrinking, thereby reducing delamination or cracking, and even when delamination occurs, prevent delamination from being transmitted to the inner electrode, thereby improving the reliability of the product.

[0091] According to the example embodiment, a buffer layer 114 is further prepared, and a general laminator is used to laminate the upper cover region (or lower cover region), the effective region, and the lower cover region (or upper cover region) to prepare a part of the body. The pre-prepared buffer layer 114 is then temporarily attached to the lower surface of the lower cover region and the buffer layer 114 is pressed to prepare the body 110.

[0092] Therefore, the body is formed with a groove formed on its lower surface and has dummy electrodes. Since the orientation of the stack does not have to be restricted to bottom-to-top or top-to-bottom, the advantages are: improved process freedom during body manufacturing and simplified manufacturing facilities to reduce process difficulty.

[0093] Furthermore, the groove is formed to be recessed inward on the mounting surface of the buffer layer of the multilayer capacitor, and a margin is ensured between the effective area and the buffer layer on which the groove is formed, so that when the multilayer capacitor is mounted on the board, the piezoelectric stress generated in the multilayer capacitor is dispersed and suppressed, thereby reducing the vibration transmitted to the board through the solder and reducing acoustic noise.

[0094] Furthermore, reducing the vibration generated in the multilayer capacitor enhances the adhesion between the multilayer capacitor and the plate and prevents the durability of the multilayer capacitor from deteriorating, thereby improving its reliability.

[0095] Modify Example

[0096] Figure 7 This is a schematic cross-sectional view of a multilayer capacitor 100' according to another example embodiment. Figure 8 This shows the application to Figure 7 A plan view of the first to third dummy electrodes of a multilayer capacitor.

[0097] Since the structures of the effective region, upper and lower covering regions, the first and second inner electrodes, and the first and second outer electrodes are similar to those previously described, their detailed descriptions will be omitted to avoid repetition. A buffer layer with a structure different from the aforementioned structures will be shown and described based on the differences.

[0098] Reference Figure 7 and Figure 8 Multiple grooves 171 and 172 may be formed to be recessed inward on the lower surface of the buffer layer 114'.

[0099] Each of the grooves 171 and 172 can be formed in a linear form, extending from the fifth surface 5 of the body 110' to the sixth surface 6.

[0100] The buffer layer 114' may also include a third dummy electrode 127 located between the first dummy electrode 125 and the second dummy electrode 126. Grooves 171 and 172 may intersect with lines 34' connecting the first dummy electrode 125 to the third dummy electrode 127. For example, grooves 171 and 172 may intersect with lines 34' on at least one dielectric layer 114a' connecting the first dummy electrode 125 to the third dummy electrode 127.

[0101] In this case, compared with the first dummy electrode 123 and the second dummy electrode 124 described in the foregoing embodiments, the first dummy electrode 125 and the second dummy electrode 126 may be formed to be shorter in the X direction.

[0102] The first dummy electrode 125 to the third dummy electrode 127 may be spaced apart from each other along the X direction of the body on a single dielectric layer 114a'.

[0103] Furthermore, the first dummy electrode 125 is exposed through the third surface 3 of the main body to be electrically connected to the first connection portion 131a of the first external electrode 131, and the second dummy electrode 126 is exposed through the fourth surface 4 of the main body to be electrically connected to the second connection portion 132a of the second external electrode 132.

[0104] In this case, the gap between the first dummy electrode 125 and the third dummy electrode 127, and the gap between the second dummy electrode 126 and the third dummy electrode 127, are elements used to form grooves 171 and 172 on the lower surface of the buffer layer 114' during the process of stacking the lower cover area, the effective area, the upper cover area, and the buffer layer and then pressing them.

[0105] Therefore, groove 171 is located between the first dummy electrode 125 and the third dummy electrode 127 in the X direction, and groove 172 is located between the second dummy electrode 126 and the third dummy electrode 127 in the X direction.

[0106] In the example embodiment, two grooves 171 and 172 are shown, but this disclosure is not limited thereto.

[0107] For example, the three grooves can be formed to be spaced apart from each other in the X direction, and the number of dummy electrodes disposed on a single dielectric layer can be increased proportionally to the number of grooves.

[0108] Based on the above structure, the main body can be formed by appropriately adjusting the number of grooves according to the size of the multilayer capacitor. When the main body is formed with two or more grooves instead of one groove, the stress dispersion effect is enhanced due to the multiple grooves.

[0109] In this respect, the effect of reducing acoustic noise can be further improved. In addition, when forming a greater number of smaller grooves, the size of the grooves can be more easily controlled compared to forming a large groove.

[0110] Plate for mounting multilayer capacitors

[0111] Figure 9 It is shown schematically. Figure 4 A cross-sectional view of a multilayer capacitor mounted on a plate.

[0112] Reference Figure 9 According to an example embodiment, a board for mounting a multilayer capacitor includes a board 210 on which a multilayer capacitor 100 is mounted, and a first electrode pad 221 and a second electrode pad 222 spaced apart on the board 210.

[0113] The multilayer capacitor 100 can be electrically connected to the board 210 via solder 231 and 232, while the first external electrode 131 contacts the first electrode pad 221 and the second external electrode 132 contacts the second electrode pad 222.

[0114] Furthermore, the example embodiments illustrate Figure 4 The mounting configuration of multilayer capacitors; however, this disclosure is not limited thereto. As an example, Figure 7 The multilayer capacitor shown is mounted on a plate with a similar construction, thus forming a mounting plate.

[0115] According to the foregoing example embodiments, there is an effect of reducing the acoustic noise of multilayer capacitors.

[0116] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A multilayer capacitor, comprising: The body includes an effective region, an upper covering region disposed above the effective region, and a lower covering region disposed below the effective region. The effective region includes alternately stacked first and second inner electrodes and a dielectric layer disposed between the first and second inner electrodes. The first and second inner electrodes are alternately exposed through two end surfaces of the body. The first and second external electrodes are disposed at both ends of the main body and are respectively connected to the first and second internal electrodes. The main body further includes a buffer layer disposed on the lower surface of the lower coverage area, and a first dummy electrode and a second dummy electrode are disposed within the buffer layer and spaced apart from each other in the length direction of the main body. The groove is recessed in the lower surface of the buffer layer, and the groove overlaps with at least one of the first dummy electrode and the second dummy electrode in the length direction of the body.

2. The multilayer capacitor according to claim 1, in, The groove extends from one side surface of the body to the other side surface of the body in the width direction of the body.

3. The multilayer capacitor according to claim 1, wherein, The first dummy electrode and the second dummy electrode are configured to face each other in the length direction on a single dielectric layer.

4. The multilayer capacitor according to claim 3, wherein, The first dummy electrode and the second dummy electrode are exposed through the two end surfaces of the body and are respectively connected to the first external electrode and the second external electrode.

5. The multilayer capacitor according to any one of claims 1 to 4, wherein, The groove is disposed between the first dummy electrode and the second dummy electrode.

6. The multilayer capacitor according to claim 1, wherein, The thickness of the lower coverage area is greater than the distance between the first inner electrode and the second inner electrode in the effective area.

7. The multilayer capacitor according to claim 1, wherein, Multiple grooves are provided on the lower surface of the buffer layer.

8. The multilayer capacitor according to claim 7, wherein, Each of the plurality of grooves extends from one side surface of the body to the other side surface of the body in the width direction of the body.

9. The multilayer capacitor according to claim 7, wherein, The buffer layer also includes a third dummy electrode disposed between the first dummy electrode and the second dummy electrode.

10. The multilayer capacitor according to claim 9, wherein, The first dummy electrode, the second dummy electrode, and the third dummy electrode are spaced apart from each other on a single dielectric layer along the length of the body.

11. The multilayer capacitor according to claim 9, wherein, The first dummy electrode and the second dummy electrode are exposed through the two end surfaces of the body and are respectively connected to the first external electrode and the second external electrode.

12. The multilayer capacitor according to any one of claims 9 to 11, wherein, One of the plurality of grooves is disposed between the first dummy electrode and the third dummy electrode, and another of the plurality of grooves is disposed between the second dummy electrode and the third dummy electrode.

13. The multilayer capacitor according to claim 1, wherein, The groove intersects with the line connecting the first dummy electrode and the second dummy electrode.

14. A multilayer capacitor, comprising: The body includes an effective region, an upper covering region disposed above the effective region, and a lower covering region disposed below the effective region. The effective region includes alternately stacked first and second inner electrodes and a dielectric layer disposed between the first and second inner electrodes. The first and second inner electrodes are alternately exposed through two end surfaces of the body. The first and second external electrodes are disposed at both ends of the main body and are respectively connected to the first and second internal electrodes. The main body further includes a buffer layer disposed on the lower surface of the lower coverage area, and a first dummy electrode and a second dummy electrode are disposed within the buffer layer and spaced apart from each other in the length direction of the main body. The groove is recessed in the lower surface of the buffer layer, and The lower coverage area does not contain inner electrodes or dummy electrodes, and the thickness of the lower coverage area is greater than the distance between the first inner electrode and the second inner electrode in the effective area.

15. A plate for mounting multilayer capacitors, comprising: A board, comprising a first electrode pad and a second electrode pad on one surface; and The multilayer capacitor according to any one of claims 1 to 14, The first external electrode and the second external electrode of the multilayer capacitor are mounted to be connected to the first electrode pad and the second electrode pad, respectively.

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