Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. A semiconductor device can be manufactured on a multi-layer redistribution structure using heterogeneous devices and asymmetric double-sided molding packaging technology. The semiconductor device can be formed into a heterogeneous three-dimensional fan-out die packaging structure with a small profile, and a single carrier substrate can be used to form the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area, thereby obtaining more functions. Integrated circuits with high functionality require many input / output pads. However, for applications where miniaturization is more important, a smaller package may be required.

[0003] Integrated Fan Out (InFO) packaging technology is becoming more and more popular, especially when used in conjunction with Wafer Level Packaging (WLP) technology. Wafer-level packaging technology packages integrated circuits in a package that typically includes a redistribution layer (RDL) or post passivation interconnect that serves as a fan-out wiring as a package contact pad, so that the electrical contacts can have a larger pitch than the contact pads of the integrated circuit. This packaging structure has a high functional density and has a relatively low cost and high-performance package. With the increasing demand for shrinking electronic devices, there is a demand for smaller and more creative semiconductor die packaging technology. An example of such a packaging system is System-in-Package (SiP) technology. In a system-level packaging device, multiple heterogeneous semiconductor dies can be integrated into a single chip carrier package that can perform most or all of the functions of this device. Therefore, complete functional units can be built into a multi-chip package using system-in-package technology to provide a high level of integration and component density, thereby producing a semiconductor device with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0004] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including depositing a first dielectric layer above a carrier substrate, adhering a first device to the first dielectric layer, sealing the first device in a first molding compound, forming an interconnect structure above the first device, wherein a first interface between the interconnect structure and the first device has a first shape, placing a second device above the interconnect structure, wherein the interconnect structure electrically couples the second device to the first device, wherein a second interface between the interconnect structure and the second device has a second shape, wherein the first shape is different from the second shape, and after placing the second device above the interconnect structure, sealing the second device in a second molding compound.

[0005] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including depositing a first dielectric layer above a system-on-chip device, forming a first opening through the first dielectric layer, a first grain connection element of the system-on-chip device exposed from the first opening, depositing a first metallization pattern above the first dielectric layer and in the first opening, the first opening leading to the first grain connection element, a first flat contact area interface formed between the first metallization pattern and the first grain connection element, forming a second dielectric layer above the first metallization pattern, forming a second opening through the second dielectric layer, forming a second metallization pattern above the second dielectric layer and in the second opening, placing an integrated circuit device above the second metallization pattern, and attaching a contact area of ​​the integrated circuit device to a surface of the second metallization pattern, wherein the surface of the second metallization pattern is recessed.

[0006] Some embodiments of the present disclosure provide a semiconductor device, including a system-on-chip device, an integrated circuit device, and a redistribution structure, wherein the redistribution structure is physically separated from and electrically connected to the integrated circuit device and the system-on-chip device, and the redistribution structure includes a first metal line and a second metal line, the first metal line and the integrated circuit device have a concave interface, and the second metal line and the system-on-chip device have a flat interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration purposes. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0008] Figure 1 A process of forming an integrated fan-out via on a carrier substrate in an intermediate step of forming a system-in-package device according to some embodiments is shown.

[0009] Figure 2 A process of placing an integrated circuit die on a carrier substrate in an intermediate step of forming a system-in-package device according to some embodiments is shown.

[0010] Figure 3 A process of packaging an integrated circuit die on a carrier substrate in an intermediate step of forming a system-in-package device according to some embodiments is shown.

[0011] Figure 4A In an intermediate step of forming a system-in-package device according to some embodiments, Figure 3 The process of forming the front-side distribution structure and the conductive connection elements above the structure.

[0012] Figure 4B and Figure 4C According to some embodiments Figure 4A Magnified view of the region of the intermediate structure.

[0013] Figure 5 In an intermediate step of forming a system-in-package device according to some embodiments, Figure 4A The front side focuses on the placement and sealing process of the integrated device on the distribution structure.

[0014] Fig. 6A and Figure 6B The present invention shows the Figure 5 The present invention relates to a process for peeling off a carrier substrate of a structure in a system, and a process for forming external contacts above an integrated fan-out via in an intermediate step of forming a system-level package device.

[0015] Fig. 7A and Figure 7B The following are shown according to two embodiments. Figure 5 The present invention relates to a process for peeling off a carrier substrate of a structure in a system, and a process for forming external contacts above an integrated fan-out via in an intermediate step of forming a system-level package device.

[0016] Fig. 8A and Figure 8B The present invention shows the Figure 5 The present invention relates to a process for peeling off a carrier substrate of a structure in a system, and a process for forming external contacts above an integrated fan-out via in an intermediate step of forming a system-level package device.

[0017] The reference numerals are described as follows:

[0018] 101: Carrier substrate

[0019] 103: Release layer

[0020] 105: Front dielectric layer

[0021] 107: Integrated fan-out vias

[0022] 109: First Part

[0023] 111: Second Part

[0024] 113: Bonding components

[0025] 114: Integrated circuit chips

[0026] 115: Dam element

[0027] 126: Die connection element

[0028] 301: First sealing element

[0029] 401: Front focus distribution structure

[0030] 403: Bump area

[0031] 404: Flat surface contact area

[0032] 405: First dielectric layer

[0033] 407: First metallization pattern

[0034] 409: Second dielectric layer

[0035] 411: Second metallization pattern

[0036] 413: The third dielectric layer

[0037] 415: Third metallization pattern

[0038] 417: Fourth dielectric layer

[0039] 419: Fourth metallization pattern

[0040] 421: First bump area

[0041] 423: Second bump area

[0042] 425: First Area

[0043] 427: Conductive connecting element

[0044] 429: First Pad Interface

[0045] 435: Second Area

[0046] 437: Second pad interface

[0047] 445: Bonding pad shape

[0048] 500: First intermediate system-level packaging structure

[0049] 501: Multilayer ceramic capacitor

[0050] 503: Surface Mount Devices

[0051] 505: Integrated device

[0052] 507: Second sealing element

[0053] 600: First system-level package device

[0054] 601: Tape

[0055] 603: External connection components

[0056] 610: Second system-in-package device

[0057] 700: Third system-level package device

[0058] 710: Fourth system-level package device

[0059] 800: Fifth system-level package device

[0060] 801: Integrated redistribution layer

[0061] 810: Sixth system-level package device

[0062] 813: Metallized pattern

[0063] 817: Dielectric layer

[0064] 821: Passivation film

[0065] 823: Micro bump

[0066] D1: First distance

[0067] D2: Second distance

[0068] D3: The third distance

[0069] D4: The fourth distance

[0070] D5: The fifth distance

[0071] D6: Sixth Distance

[0072] H1: First height

[0073] H2: Second height

[0074] H3: The third height

[0075] H4: The fourth height

[0076] H7: Seventh Height

[0077] H8: The eighth height

[0078] H9: The ninth height

[0079] Th2: Second thickness

[0080] Th3: Third thickness

[0081] Th4: Fourth thickness

[0082] Lvl1: First level

[0083] P1: First spacing

[0084] W1: First width

[0085] W2: Second width

[0086] W3: Third width

[0087] W4: fourth width DETAILED DESCRIPTION

[0088] Many different implementation methods or examples are disclosed below to implement the different features of the provided subject matter. The following describes specific embodiments of the components and their arrangements to illustrate the present disclosure. Of course, these embodiments are only for illustration and do not limit the scope of the present disclosure. For example, it is mentioned in the specification that the first characteristic component is formed on the second characteristic component, which includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which there are other features between the first characteristic component and the second characteristic component, that is, the first characteristic component and the second characteristic component are not in direct contact. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present disclosure and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0089] Additionally, spatially relative terms such as "below", "below", "below", "above", and "above" may be used to facilitate description of the relationship between one (some) elements or features and another (some) elements or features in the diagrams, and these spatially relative terms are intended to encompass different orientations of the device including the features. The device may be turned (rotated 90 degrees or to other orientations), and the spatially relative terms used herein may be interpreted in a similar manner.

[0090] In the present disclosure, various aspects of device packages and their formation processes are described. This device package can be, for example, a system-in-Package (SiP) device. In some embodiments, the system-in-package device can integrate heterogeneous die on both sides of a redistribution structure in a face-to-face arrangement. According to some embodiments, a single carrier substrate can be used to form the system-in-package device in a chip-first process flow. According to some embodiments, a first group of heterogeneous die can be bonded to a first side of the redistribution structure and embedded in a first molding compound, and a second group of heterogeneous die can be bonded to a second side of the redistribution structure and embedded in a second molding compound. According to some embodiments, the redistribution structure can include multiple redistribution layers, and the first and second molding compounds can be formed by different molding compounds and have different heights. Therefore, an asymmetric dual-sided molded package system-in-package device can be formed on a multi-layer redistribution structure. In some embodiments, an integrated redistribution layer (e.g., a fan-out structure) is formed on a system-on-chip (SoC) component and integrated in the system-in-package device. This method of integrating heterogeneous die in a system-in-package device can achieve high levels of integration and component density and provide a low-cost system-in-package process, thereby producing semiconductor devices with higher functionality and smaller footprint on a printed circuit board (PCB).

[0091] According to some embodiments, Figures 1 to 8B A cross-sectional view showing intermediate steps in forming a heterogeneous three-dimensional (3D) Fan-Out die package (e.g., a system-level package). Specifically, Figure 1 A carrier substrate 101 , a release layer 103 formed on the carrier substrate 101 , and a front-side dielectric layer 105 formed on the release layer 103 are shown.

[0092] The carrier substrate 101 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 101 may be a wafer so that a plurality of packages can be formed simultaneously on the carrier substrate 101. The release layer 103 may be formed of a polymer-based material, and in a subsequent step, the release layer 103 may be removed from the structure to be formed thereon together with the carrier substrate 101. In some embodiments, the release layer 103 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In some embodiments, the release layer 103 may be a glue, such as an ultraviolet (UV) glue that loses its adhesive properties when exposed to ultraviolet light. The release layer 103 may be dispensed and cured in the form of a liquid, and may be a laminate film laminated to the carrier substrate 101, etc. The top surface of the release layer 103 may be horizontal and may have a high degree of coplanarity.

[0093] The front dielectric layer 105 is formed on the release layer 103. The bottom surface of the front dielectric layer 105 may be in direct contact with the top surface of the release layer 103. In some embodiments, the front dielectric layer 105 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In some embodiments, the front dielectric layer 105 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The front dielectric layer 105 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, combinations thereof, etc.

[0094] exist Figure 1107 (Through Integrated Fan-Out Vias, TIVs) is further shown in the figure. For example, a seed layer (not shown) is formed on the front dielectric layer 105 to form the integrated fan-out vias 107. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. For example, the seed layer may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, and the like. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using methods such as physical vapor deposition (PVD). A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed for patterning. The pattern of the photoresist corresponds to the integrated fan-out vias 107. The patterning process forms an opening through the photoresist, thereby exposing the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. The portion of the photoresist and the seed layer where the conductive material is not formed is removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. After the photoresist is removed, the exposed portion of the seed layer is then removed by an acceptable etching process, such as wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms an integrated fan-out via 107. According to some embodiments, the integrated fan-out via 107 is formed to have a first height H1 between about 100 μm and about 250 μm (such as about 120 μm), and a first pitch P1 between about 80 μm and about 250 μm (such as about 100 μm). However, any suitable height and pitch may be used.

[0095] Figure 2An integrated circuit die 114 is shown attached to the top surface of the front dielectric layer 105. According to some embodiments, the integrated circuit die 114 may include a group of heterogeneous dies, such as a system on a chip and one or more integrated passive devices (IPD) dies. However, the integrated circuit die 114 may be other types of dies, such as logic dies (e.g., central processing units, microcontrollers, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), etc. or a combination thereof. Furthermore, in some embodiments, the integrated circuit dies 114 may have different sizes (eg, different heights and / or surface areas), and in other embodiments, the integrated circuit dies 114 may have the same size (eg, the same height and / or surface area).

[0096] Before the integrated circuit die 114 is attached to the front-side dielectric layer 105, the integrated circuit die 114 may be processed according to a suitable process to form an integrated circuit and embed the integrated circuit into the die. The integrated circuit die 114 may initially be formed in a wafer, which may include different device regions. The aforementioned device regions are tested and separated in subsequent steps to form a plurality of known-good-dies (KGDs). For example, each integrated circuit die 114 includes internal components, including a semiconductor substrate, an integrated circuit, an active device, a passive device, a dielectric layer, a conductive redistribution feature, an interconnect structure, a passivation layer, and / or packaging materials for embedding internal components, such as an encapsulant or a molding compound. Each integrated circuit die 114 also includes a die connection element 126 for external connection of the integrated circuit die 114. The die connection element 126 is, for example, a conductive pillar, and includes a metal (e.g., copper), and is mechanically and electrically connected to the internal components of the integrated circuit die 114. Once the integrated circuit die 114 is formed, the integrated circuit die 114 can be tested and identified as a known good die.

[0097] According to some embodiments, the integrated circuit die 114 may be a set of heterogeneous dies, which include, for example, a first component 109 (e.g., a system on a chip) having a second height H2 and one or more second components 111 (e.g., an integrated passive device) having a third height H3. According to some embodiments, the second height H2 of the first component 109 is between about 70 μm and about 150 μm (e.g., about 100 μm), and the third height H3 of the one or more second components 111 is between about 50 μm and about 100 μm (e.g., about 80 μm).

[0098] Furthermore, in embodiments where the third height H3 (e.g., the height of the one or more second components 111) is less than the second height H2 (e.g., the height of the first component 109), a dam element 115 may be added to the back side of the one or more second components 111 to reduce the height difference between the one or more second components 111 and the first component 109. By reducing the height difference, damage caused by stress in subsequent processes may be reduced or eliminated.

[0099] In certain embodiments, the dam element 115 may be formed of a solid material such as a semiconductor material (e.g., silicon). In addition, the dam element 115 may be formed to have a fourth height H4 to reduce the height difference between the one or more second components 111 and the first component 109. The fourth height H4 is, for example, between about 20 μm and about 50 μm (e.g., about 20 μm). However, any suitable material and any suitable height may be used.

[0100] Adhesive element 113 adheres each integrated circuit die 114 to front dielectric layer 105, for example to Figure 2 The integrated fan-out vias 107 shown are between the integrated fan-out vias 107. The adhesive element 113 may be any suitable adhesive, epoxy, die attach film (DAF), etc. According to some embodiments, the integrated circuit die 114 is attached to the front side dielectric layer 105 using a die attach film. The die attach film may be an epoxy resin, a phenol resin, an acrylic rubber, a silica filler, or a combination thereof, and a lamination technique is used to apply the die attach film. However, any other suitable material and any suitable method may also be used to adhere the integrated circuit die 114 to the front side dielectric layer 105. In some embodiments, the adhesive element 113 may be applied to the back side of the integrated circuit die 114, or the adhesive element 113 may be applied to the surface of the front side dielectric layer 105. The integrated circuit dies 114 may be singulated from the wafer, for example, by sawing or dicing, and attached to the front side dielectric layer 105 by bonding elements 113 using, for example, a pick-and-place tool.

[0101] According to some embodiments, one or more integrated circuit dies 114 are attached to the front side dielectric layer 105 via an adhesive element 113 in the form of a die attach film, and a leveling process may be performed to align the top of the die attach element 126 to a first level Lvl1. For example, a leveling film (e.g., a leveling foil, etc.) may be placed in contact with the die attach element 126 and the upper surface of the integrated circuit die 114. After the leveling film is placed, a flattening tool may be used to apply downward pressure to the integrated circuit die 114 while raising the process temperature to a melting point of the die attach film or higher. The die attach film is thus compressed, thereby allowing the die attach element 126 of the integrated circuit die 114 to be aligned to the first level Lvl1, which is a first distance D1 from the front side dielectric layer 105. According to some embodiments, the process temperature is between about 50° C. and about 200° C. (eg, about 110° C.), and the first distance D1 is between about 105 μm and about 195 μm (eg, about 135 μm). However, any suitable temperature and distance may be used.

[0102] exist Figure 3In the embodiment, the first sealing element 301 is placed at a first level Lvl1 or higher above the front side dielectric layer 105 and seals the integrated fan-out via 107 and the integrated circuit size 114. The first sealing element 301 may be a molding compound, an epoxy resin, etc., and the first sealing element 301 may be applied by compression molding, transfer molding, etc. According to some embodiments, the first sealing element 301 has a first thermal expansion coefficient CTE1 at a temperature below the glass transition temperature of the first sealing element 301, and has a second thermal expansion coefficient CTE2 at a temperature greater than or equal to the glass transition temperature of the first sealing element 301. According to some embodiments, the first thermal expansion coefficient CTE1 of the first sealing element 301 is between about 6 ppm / K and about 20 ppm / K, for example, a first thermal expansion coefficient CTE1 of about 10 ppm / K at a glass transition temperature between about 147° C. and about 153° C. (e.g., about 150° C.) According to some embodiments, the first sealing element 301 has a second coefficient of thermal expansion CTE2 between about 30 ppm / K and about 50 ppm / K, for example, a second coefficient of thermal expansion CTE2 of about 41 ppm / K at a glass transition temperature between about 147° C. and about 153° C. (e.g., about 150° C.). However, other suitable coefficients of thermal expansion may be used. After curing the first sealing element 301, the first sealing element 301 may be subjected to a grinding process to expose the integrated fan-out vias 107 and the die connection elements 126. After the grinding process, the top surfaces of the integrated fan-out vias 107, the die connection elements 126, and the first sealing element 301 are coplanar and have a second distance D2 with the front side dielectric layer 105. According to some embodiments, the second distance D2 is between about 105 μm and about 195 μm, for example, about 135 μm. However, any suitable distance may be used. In some embodiments, for example, if the first sealing element 301 is placed at the first level Lvl1 and the integrated fan-out vias 107 and the die connecting elements 126 are already exposed, the grinding process may be omitted.

[0103] Figure 4AThe formation process of the front side redistribution structure 401 and the conductive connection element 427 is shown. The front side redistribution structure 401 includes a dielectric layer and a metallization pattern. The metallization pattern and the dielectric layer may also be referred to as a redistribution layer or a redistribution line. For example, a front side redistribution structure 401 including four dielectric layers (e.g., 405, 409, 413, and 417) and four metallization patterns (e.g., 407, 411, 415, and 419) is depicted. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 401. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed subsequently may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed subsequently may be repeated. The front side redistribution structure 401 may also be referred to herein as an integrated fan-out (InFO) structure.

[0104] According to some embodiments, the front side redistribution structure 401 can be formed by first forming a first dielectric layer 405 on the coplanar surface of the first sealing element 301, the integrated fan-out via 107 and the die connection element 126. In some embodiments, the first dielectric layer 405 is formed of a polymer, which can be a photosensitive material that can be patterned using a lithography mask, such as polybenzoxazole, polyimide, benzocyclobutene, etc. In some embodiments, the first dielectric layer 405 is formed of a nitride such as silicon nitride, or an oxide such as silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, etc., the like, or a combination thereof. The first dielectric layer 405 can be formed by spin coating, chemical vapor deposition, lamination, a combination thereof, etc. According to some embodiments, the first dielectric layer 405 is deposited to have a second thickness Th2 between about 4 μm and about 12 μm, such as about 7 μm. However, any suitable thickness can be used. After the first dielectric layer 405 is deposited, the first dielectric layer 405 is patterned. The patterning process forms an opening that exposes the die connection element 126 of the integrated circuit die 114 and a portion of the integrated fan-out via 107. The patterning can be performed by an acceptable process, such as when the first dielectric layer 405 is a photosensitive material, by exposing and developing the first dielectric layer 405. In an embodiment where the first dielectric layer 405 is a nitride, the patterning can be performed using any suitable process to form the opening. For example, an etching process such as anisotropic etching can be used.

[0105] Then, a first metallization pattern 407 is formed on and extends along the main surface of the first dielectric layer 405 and conforms to the sidewalls of the opening extending through the first dielectric layer 405. Therefore, the first metallization pattern 407 includes a plurality of flat surface contact areas 404 that are physically and electrically coupled to the die connection elements 126 of the integrated circuit die 114. For example, to form the first metallization pattern 407, a seed layer (not shown) may be formed above the first dielectric layer 405 and in the opening extending through the first dielectric layer 405. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer including a plurality of sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, physical vapor deposition. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating, etc., and the photoresist may be exposed for patterning. The pattern of the photoresist corresponds to the first metallization pattern 407. Patterning forms an opening through the photoresist to expose the seed layer. Then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by a plating process such as electroplating or electroless plating. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the seed layer below the conductive material forms a first metallization pattern 407. According to some embodiments, the first metallization pattern 407 may be deposited to have a third thickness Th3 between about 2 μm and about 8 μm, for example, about 4 μm. However, any suitable thickness may be used. The portion on the photoresist and the seed layer where the conductive material is not formed is removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma. After the photoresist is removed, the exposed portion of the seed layer is removed, for example, by an acceptable etching process, such as wet etching or dry etching.

[0106] After depositing the first metallization pattern 407, a second dielectric layer 409 is deposited on the first metallization pattern 407 and the first dielectric layer 405. Therefore, the uppermost portion of the first metallization pattern 407 is buried in the second dielectric layer 409. The second dielectric layer 409 can be formed in a similar manner to the first dielectric layer 405, and can have a similar material and a similar thickness (e.g., a second thickness Th2) as the first dielectric layer 405. However, any suitable material and thickness can be used. After depositing the second dielectric layer 409, an opening is formed in the second dielectric layer 409 to expose some areas of the first metallization pattern 407. The opening in the second dielectric layer 409 can be formed using any patterning process suitable for forming an opening in the first dielectric layer 405 (e.g., exposing and developing a photosensitive material, etching a nitride material, etc.).

[0107] After the opening is formed in the second dielectric layer 409, the second metallization pattern 411 is then formed. The second metallization pattern 411 is deposited on the main surface of the second dielectric layer 409 and extends along the main surface of the second dielectric layer 409, and conforms to the opening in the second dielectric layer 409, and the opening extends through the second dielectric layer 409 to be physically and electrically coupled to the first metallization pattern 407. The second metallization pattern 411 can be formed in a manner similar to the first metallization pattern 407, and can be formed to have similar materials and similar thicknesses (e.g., third thickness Th3) as the first metallization pattern 407. However, any suitable material and thickness can be used. In some embodiments, the second metallization pattern 411 has a different size from the first metallization pattern 407. For example, the second metallization pattern 411 can be wider or thicker than the first metallization pattern 407. In addition, the portion of the second metallization pattern 411 that conforms to the opening in the second dielectric layer 409 can have a different spacing from the portion of the first metallization pattern 407 that conforms to the opening in the first dielectric layer 405. However, any material may be used to form the second metallization pattern 411. As described above, any process suitable for forming the first metallization pattern 407 and the second metallization pattern 411 may be used to form the first metallization pattern 407 of any width and / or thickness.

[0108] After the second metallization pattern 411 is deposited, the third dielectric layer 413 is deposited on the second metallization pattern 411 and the second dielectric layer 409. The third dielectric layer 413 can be formed in a manner similar to the first dielectric layer 405, and can have a similar material and a similar thickness (e.g., a second thickness Th2) as the first dielectric layer 405. After the third dielectric layer 413 is formed, an opening is formed in the third dielectric layer 413 to expose the area of ​​the second metallization pattern 411, and the opening can be formed in the first dielectric layer 405 using any patterning process suitable for forming an opening.

[0109] Next, a third metallization pattern 415 is formed on the main surface of the second dielectric layer 409, extending along the main surface of the second dielectric layer 409 and conforming to the opening in the third dielectric layer 413 to be physically and electrically coupled to the second metallization pattern 411. The third metallization pattern 415 can be formed using any material and any process suitable for forming the first metallization pattern 407. The third metallization pattern 415 can be formed to have a similar thickness (e.g., a third thickness Th3) as the first metallization pattern 407. However, any suitable material and thickness can be used. In some embodiments, the third metallization pattern 415 has a different size from the second metallization pattern 411. For example, the third metallization pattern 415 can be wider or thicker than the second metallization pattern 411. In some embodiments, the third metallization pattern 415 has a different size from the first metallization pattern 407 and / or the second metallization pattern 411. Furthermore, according to some embodiments, a portion of the third metallization pattern 415 conforming to the opening of the third dielectric layer 413 may have a different pitch than a portion of the second metallization pattern 411 conforming to the opening of the second dielectric layer 409 .

[0110] After the third metallization pattern 415 is deposited, a fourth dielectric layer 417 is deposited on the third metallization pattern 415 and the third dielectric layer 413. The fourth dielectric layer 417 may be formed in a manner similar to the first dielectric layer 405, may be formed using similar processes and materials, and may be formed to have a similar thickness (e.g., second thickness Th2) as the first dielectric layer 405. After the fourth dielectric layer 417 is formed, an opening may be formed in the fourth dielectric layer 417 to expose an area of ​​the third metallization pattern 415, and any patterning process suitable for forming an opening in the first dielectric layer 405 may be used to form the opening.

[0111] According to some embodiments, the fourth metallization pattern 419 is formed on and extends along the main surface of the fourth dielectric layer 417, and conforms to the opening in the fourth dielectric layer 417 to be physically and electrically coupled to the third metallization pattern 415. The fourth metallization pattern 419 can be formed using any material and process suitable for forming the first metallization pattern 407. In addition, the fourth metallization pattern 419 can have any appropriate thickness (e.g., a fourth thickness Th4) between about 10 μm and about 40 μm (e.g., about 30 μm). In some embodiments, the fourth metallization pattern 419 has a different size from any of the first metallization pattern 407, the second metallization pattern 411, and / or the third metallization pattern 415. In addition, the portion of the fourth metallization pattern 419 that conforms to the opening of the fourth dielectric layer 417 can have a different spacing from the portion of the third metallization pattern 415 that conforms to the opening of the third dielectric layer 413. In some embodiments, the fourth metallization pattern 419 is a desired uppermost metal layer of the front-side redistribution structure 401 .

[0112] Figure 4A It is also shown that the uppermost metal layer of the front side redistribution structure 401 includes a plurality of bump regions 403. The plurality of bump regions 403 may have the same width or may have different widths. According to some embodiments, the plurality of bump regions 403 include a first bump region 421 having a first width W1. The first bump region 421 may be disposed in a first region 425 on a first component 109 (e.g., a system on a chip) of an integrated circuit die 114. In some embodiments, the first width W1 is between about 300 μm and about 550 μm, for example about 300 μm. However, any suitable width may be used.

[0113] According to some embodiments, the plurality of bump regions 403 include a second bump region 423 having a second width W2. The second bump region 423 may be disposed on one of the second portions 111 of the integrated circuit die 114 in the second region 435, such as one of the integrated passive devices. In some embodiments, the second width W2 is between about 150 μm and about 300 μm, such as about 200 μm. However, any suitable width may be used.

[0114] In some embodiments, the top metal layer of the front side redistribution structure 401 may be covered by a plurality of under bump metallizations (UBM) (not shown separately), or may be replaced by a plurality of under bump metallizations. In some embodiments, the under bump metallization includes a metal seed layer, which may be a single layer, or a composite layer including a plurality of sublayers formed of different materials (e.g., a titanium layer and a copper layer above the titanium layer). A conductive material is formed on the metal seed layer using a method such as a physical vapor deposition process. After forming the seed layer, a photoresist may be deposited by spin coating or a similar method, and then patterned (e.g., by exposure) so that the opening in the photoresist corresponds to the desired position of the under bump metallization layer. After patterning the photoresist, a conductive material is formed in the opening of the photoresist corresponding to the under bump metallization layer. The conductive material includes a metal (e.g., copper, titanium, tungsten, aluminum, alloys thereof, combinations thereof, etc.), and may be formed by plating (e.g., electroplating or electroless plating, etc.). The photoresist is then removed (e.g., by ashing or a stripping process, such as using oxygen plasma, etc.), and the exposed portion of the seed layer (if any) not covered by the conductive material is removed, such as by an acceptable etching process (e.g., wet etching or dry etching). Thus, an under bump metallization layer is formed above and through the patterned opening in the uppermost dielectric layer (e.g., the fourth dielectric layer 417) and in contact with the underlying metallization pattern (e.g., the third metallization pattern 415).

[0115] Figure 4A Further shown is a conductive connection element 427 formed on the bump region 403 of the uppermost metallization pattern (e.g., the fourth metallization pattern 419) of the front side redistribution structure 401. After the uppermost metal layer is formed, a pre-solder printing process can be performed on the bump region 403 of the uppermost metallization pattern. According to some embodiments, the conductive connection element 427 is formed above and fills the bonding pad shape 445 of the bump region 403.

[0116] The conductive connection element 427 may be a ball grid array (BGA) connection element, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connection element 427 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, a solder layer is first formed by evaporation, electroplating, printing, solder transfer, placing solder balls, etc. to form the conductive connection element 427. After the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In some embodiments, the conductive connection element 427 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, etc. The metal column may be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and the metal capping layer may be formed by a plating process.

[0117] Figure 4B Show Figure 4A FIG. 4 is an enlarged view of the first region 425 of the third metallization pattern 415. According to some embodiments, the first bump region 421 has a first width W1, thereby reducing the mechanical stress applied to the third metallization pattern 415. Therefore, the various thicknesses and widths of the bump region 403 of the fourth metallization pattern 419 can increase the mechanical reliability of the front-side redistribution structure 401. In addition, the first bump region 421 has a concave contact area facing the conductive connection element 427 and a flat surface contact area 404 facing away from the conductive connection element 427. In addition, there is a first pad interface 429 between the first metallization pattern 407 and the contact area of ​​the die connection element 126 of the first component 109 (e.g., system on chip) of the integrated circuit die 114. The first pad interface 429 of the fourth metallization pattern 419 includes a flat surface contact area 404 facing the die connection element 126 (e.g., system on chip) of the first component 109 and a concave contact area facing away from the die connection element 126. According to some embodiments, the first pad interface 429 has a third width W3 between about 10 μm and about 30 μm (eg, about 20 μm). According to some embodiments, the front-side redistribution structure 401 includes a first bonding pad ratio R1, which can be defined by the following formula: 10 <R1=W1 / W3<55。

[0118] Figure 4C Show Figure 4A FIG. 4 is an enlarged view of the second region 435 of FIG. According to some embodiments, the second bump region 423 has a second width W2 to reduce the mechanical stress applied to the third metallization pattern 415. Therefore, various thicknesses and widths of the bump region 403 of the fourth metallization pattern 419 can increase the mechanical reliability of the front-side redistribution structure 401. According to some embodiments, the second width W2 can be between about 150 μm and about 300 μm, for example, about 200 μm.

[0119] In addition, there is a second pad interface 437 between the first metallization pattern 407 and the contact area of ​​the die connection element 126 of the second component 111 (e.g., an integrated passive device) of one of the integrated circuit dies 114. The second pad interface 437 of the first metallization pattern 407 includes a flat surface contact area 404 facing the die connection element 126 and a joint shape facing away from the die connection element 126. According to some embodiments, the second pad interface 437 has a fourth width W4 between about 10 μm and about 30 μm, for example, about 20 μm. In some embodiments, the front-side redistribution structure 401 includes a second bonding pad ratio R2, and the second bonding pad ratio R2 can be defined by the following formula: <R2=W2 / W4<30。

[0120] Figure 5 An integrated device 505 is shown attached to the top metal layer (e.g., fourth metallization pattern 419) of the front redistribution structure 401 to electrically connect one or more integrated circuit dies 114 and / or one or more integrated fan-out vias 107 on both sides of the front redistribution structure 401. The integrated device 505 can be, for example, a semiconductor device or other device including one or more passive devices, such as capacitors (e.g., multi-layer ceramic capacitors (MLCC) 501), resistors, inductors, etc. The integrated device 505 can be, for example, an integrated passive device, a surface-mount device (SMD) 503, etc. The integrated device 505 attached to the front redistribution structure 401 can be similar or different types of devices. Figure 5 Further shown are the placement states of three integrated devices 505, although more or fewer integrated devices 505 may be attached. The integrated devices 505 may be attached by, for example, sequentially dipping connection elements (e.g., conductive bumps or conductive pads) of the integrated devices 505, such as solder balls (not shown), into solder and then using a pick-and-place tool to physically align the connection elements of the integrated devices 505 with corresponding areas of the front-side redistribution structure 401. In some cases, a reflow process may be performed to bond the connection elements of the integrated devices 505 to the conductive connection elements 427.

[0121] In some embodiments, an optional bottom fill layer (not shown) is formed between each integrated device 505 and the front side redistribution structure 401, and around the connection elements of the integrated device 505. The optional bottom fill layer can reduce stress and prevent the contacts from being damaged by the reflow process. The optional bottom fill layer can be formed by a capillary flow process after the integrated device 505 is attached, or the optional bottom fill layer can be formed by an appropriate deposition method before the integrated device 505 is attached. In some embodiments where flux is used to attach the integrated device 505, the flux can be used as an optional bottom fill layer.

[0122] Figure 5 Further shown is a second sealing element 507 formed on the front side redistribution structure 401 to encapsulate the integrated device 505. The second sealing element 507 may be a molding compound, a molding underfill material, an epoxy resin, etc., and the second sealing element 507 may be applied by compression molding, transfer molding, etc. According to some embodiments, the second sealing element 507 has a first coefficient of thermal expansion CTE1 at a temperature below a glass transition temperature of the second sealing element 507, and has a second coefficient of thermal expansion CTE2 at a temperature greater than or equal to the glass transition temperature of the second sealing element 507. According to some embodiments, the first coefficient of thermal expansion CTE1 of the second sealing element 507 is between about 8 ppm / K and about 30 ppm / K, for example, having a first coefficient of thermal expansion CTE1 of about 9 ppm / K below a glass transition temperature between about 157° C. and about 163° C. (e.g., about 160° C.). According to some embodiments, the second thermal expansion coefficient CTE2 of the second sealing element 507 is between about 15 ppm / K and about 40 ppm / K, for example, having a second thermal expansion coefficient CTE2 of about 25 ppm / K at a glass transition temperature between about 157° C. and about 163° C. (e.g., about 160° C.). However, other suitable thermal expansion coefficients may be used.

[0123] According to some embodiments, the first coefficient of thermal expansion CTE1 of the second sealing element 507 may be different from the first coefficient of thermal expansion CTE1 of the first sealing element 301. Figure 5The intermediate structure may be referred to as a first intermediate system-level package structure 500 in the present disclosure, and the first intermediate system-level package structure 500 includes a plurality of system-level package components, and the system-level package components include asymmetric dual-sided moldings of a multi-layer redistribution layer structure. In some embodiments, a first ratio (CTE-R1) of a first coefficient of thermal expansion CTE1 of the second sealing element 507 to a first coefficient of thermal expansion CTE1 of the first sealing element 301 may be between about 0.8≤CTE-R1≤0.99. In addition, according to some embodiments, a second ratio (CTE-R2) of a second coefficient of thermal expansion CTE2 of the second sealing element 507 to a second coefficient of thermal expansion CTE2 of the first sealing element 301 may be between about 0.1≤CTE-R2≤0.7.

[0124] After curing the second sealing element 507, the second sealing element 507 may be subjected to a grinding process to reduce the height of the second sealing element 507 to a third distance D3 from the uppermost dielectric layer (e.g., the fourth dielectric layer 417). According to some embodiments, the third distance D3 is between about 200 μm and about 700 μm, for example, about 550 μm. However, any suitable distance may be used. In some embodiments, for example, if the first sealing element 301 is formed to have a desired third distance D3, the grinding process may be omitted. According to some embodiments, the ratio of the height of the second sealing element 507 to the height of the first sealing element 301 (e.g., D3 / D2) may be between about 0≤D3 / D2≤6.

[0125] Fig. 6A The first system-in-package device 600 formed from the first intermediate system-in-package structure 500 is shown. First, the first intermediate system-in-package structure 500 is flipped over and placed on the tape 601 for further processing. After the first intermediate system-in-package structure 500 is placed on the tape 601, a peeling process can be performed to detach or de-bond the carrier substrate 101 from the front dielectric layer 105. In some embodiments, the peeling process includes applying light such as laser or ultraviolet light to the release layer 103, so that the release layer 103 is decomposed by the heat of the light, so that the carrier substrate 101 can be removed.

[0126] like Fig. 6AAs shown, an external connection element 603 may be formed to connect the first system-level package device 600 to the outside. Initially, an opening may be formed in the front dielectric layer 105 to expose the contact area of ​​the integrated fan-out via 107. The opening may be formed using, for example, laser drilling, etching, etc. In such an embodiment, the integrated fan-out via 107 may be formed to have a sixth height H6, which is the same as the second distance D2. However, any suitable height may be used.

[0127] Once the contact area of ​​the integrated fan-out via 107 is exposed, an external connection element 603 may be formed over the integrated fan-out via 107 to electrically connect to the front-side redistribution structure 401. In some embodiments, an optional solderability treatment, such as a pre-soldering treatment, may be performed on the exposed contact area of ​​the integrated fan-out via 107 before forming the external connection element 603. The external connection element 603 may be deposited over the integrated redistribution layer 801 using a process and materials similar to those used to form the conductive connection element 427. According to some embodiments, the external connection element 603 is formed by initially forming a layer of pre-solder paste or solder on the exposed contact area of ​​the integrated fan-out via 107. However, any suitable process (e.g., evaporation, electroplating, printing, solder transfer, placement of solder balls, etc.) may be used to form the pre-solder paste or solder on the exposed contact area of ​​the integrated fan-out via 107. In some embodiments, the external connection element 603 may be a microbump. However, the external connection element 603 may also be a ball grid array connection element, a solder ball, a metal column, a controlled collapse chip connection bump, a bump formed by chemical nickel palladium immersion gold plating technology, or the like. The external connection element 603 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof.

[0128] After the first intermediate SLP structure 500 is peeled off from the carrier substrate, the first intermediate SLP structure 500 may be singulated (eg, by sawing, laser drilling, etching, or a combination thereof) into a plurality of first SLP devices 600 . Fig. 6A It is also shown that the first system-in-package device 600 can be manufactured as, for example, a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) device including external connection elements (e.g., external connection elements 603). The first pitch P1 of the aforementioned external connection elements is between about 80 μm and about 250 μm, for example, about 100 μm.

[0129] Figure 6B A second system-in-package device 610 is shown according to some embodiments. Fig. 6A The first system-in-package device 600 is different in that the front dielectric layer 105 is also removed before forming external contacts on the integrated fan-out vias 107. According to some embodiments, after the carrier substrate 101 is removed, the front dielectric layer 105 is removed by a grinding process (e.g., a chemical mechanical planarization (CMP) process). The grinding process can be performed to remove the bonding element 113 and planarize the back side of the integrated fan-out vias 107, the first sealing element 301, the dam element 115, and the first component 109 of the one or more second components 111 to a fourth distance D4 from the front redistribution structure 401. According to some embodiments, the fourth distance D4 is between about 85μm and about 175μm, for example, about 115μm. The integrated fan-out vias 107 are thus lowered to have a seventh height H7 equal to the fourth distance D4. After the grinding process, a cleaning process (e.g., a die attach film cleaning process) can be performed. Therefore, the backside of the integrated fan-out via 107 and the first component 109 is coplanar with the surface of the first sealing element 301 and is exposed on the surface of the first sealing element 301 for subsequent processes.

[0130] After the contact area of ​​the integrated fan-out via 107 is exposed, an external connection element 603 may be formed above the integrated fan-out via 107 to electrically connect to the front redistribution structure 401. Fig. 6A Any of the materials and methods described herein may be used to form the external connection element 603 above the integrated fan-out via 107. However, in some embodiments, after an optional contact pad (not shown) is formed on the exposed integrated fan-out via 107, the external connection element 603 is directly bonded above the integrated fan-out via 107. In some embodiments, after the integrated fan-out via 107 is exposed from the first sealing element 301, the contact pad is directly formed on the exposed integrated fan-out via 107 and physically connected to the integrated fan-out via 107, so that the external connection element 603 can be placed above the contact pad. By directly bonding the external connection element 603 to the integrated fan-out via 107, the height and resistance of the integrated fan-out via 107 can be reduced, and the back side of the first component 109 (e.g., system-on-chip) can be exposed, thereby allowing heat from the first component 109 to dissipate from the second package internal system device 610. Figure 6B It is further shown that the second system-in-package device 610 may be, for example, a heterogeneous 3D fan-out system-in-package device including external connection elements (eg, external connection elements 603 ), wherein the external connection elements have a first pitch P1 .

[0131] Fig. 7A and Figure 7B 1 and 2 respectively illustrate a third system-in-package device 700 and a fourth system-in-package device 710 according to some embodiments. Fig. 6A The first system-in-package device 600 is different from the fourth system-in-package device 710 Figure 6B The second system-in-package device 610 is different in that one or more second components 111 are omitted in the third system-in-package device 700 and the fourth system-in-package device 710 .

[0132] Fig. 8A and Figure 8B 1 and 10 respectively illustrate a fifth system-in-package device 800 and a sixth system-in-package device 810 according to some embodiments. Fig. 7A The third system-in-package device 700 and Figure 7B The fourth system-in-package device 710 is different in that an integrated redistribution layer 801 and micro bumps 823 are used to couple the first component 109 to the front-side redistribution structure 401 .

[0133] Initially, a first part 109 (e.g., a system-on-chip) may be formed in a wafer, depending on the applicable process, and the wafer may include different device regions that are tested and singulated in subsequent steps to form multiple known good dies. An integrated redistribution layer 801 and microbumps 823 may be formed over the first component 109 to allow the first component 109 to be connected to the outside. For example, the integrated redistribution layer 801 may be electrically coupled to a die pad (not shown) of the first component 109, and microbumps 823 may be formed over the contact area of ​​the integrated redistribution layer 801.

[0134] For example, the integrated redistribution layer 801 can be formed as a metallization pattern 813 in a dielectric layer 817. The metallization pattern 813 includes metal lines and vias formed in and / or over one or more dielectric layers 817 (e.g., low-k dielectric layers). As described above, any material and process suitable for forming the metallization pattern and dielectric layer of the front-side redistribution structure 401 can be used to form the metallization pattern 813 and the dielectric layer 817 with any suitable thickness.

[0135] In some embodiments, a passivation film 821 may be formed on the uppermost metallization pattern of the integrated redistribution layer 801, and an opening may be formed in the passivation film 821 to expose the contact region of the integrated redistribution layer 801. The passivation film 821 may be a polymer such as polybenzoxazole, polyimide, benzocyclobutene, etc., a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, etc., or a combination thereof. The passivation film 821 may be formed by, for example, spin coating, lamination, chemical vapor deposition, etc.

[0136] After the contact area is exposed, microbumps 823 may be formed over the contact area of ​​the integrated redistribution layer 801. In some embodiments, the microbumps 823 may be formed using solder (e.g., solder balls, solder bumps, etc.) formed over the contact area of ​​the integrated redistribution layer 801. The microbumps 823 allow the first component 109 to be connected to the outside world. In some embodiments, the microbumps 823 are formed as conductive pillars (e.g., using a metal such as copper), which extend through the openings in the passivation film 821 and are physically and electrically coupled to the respective contact areas of the integrated redistribution layer 801. The microbumps 823 may be formed, for example, by electroplating.

[0137] therefore, Fig. 8A The fifth system-in-package device 800 and Figure 8B The sixth system-in-package device 810 shown may have some different dimensions from the third system-in-package device 700 and the fourth system-in-package device 710. For example, in the fifth system-in-package device 800, after the grinding process is performed to planarize the top surface of the first sealing element 301 and the integrated fan-out via 107 and the micro-bump 823 (previously Figure 3 ), the first sealing element 301, the integrated fan-out via 107, and the microbump 823 are coplanar at a fifth distance D5 from the front dielectric layer 105. In addition, the integrated fan-out via 107 of the fifth system-in-package device 800 has an eighth height H8 substantially equal to the fifth distance D5. According to some embodiments, the fifth distance D5 is between about 110 μm and about 210 μm, for example, about 145 μm. However, any suitable distance may be used.

[0138] In the sixth embodiment of the system-in-package device 810, after performing a grinding process to planarize the top surface of the first sealing element 301 and the integrated fan-out via 107 and the micro-bump 823 (previously Figure 3) and removing the adhesive element 113, the first sealing element 301, the integrated fan-out via 107, and the microbump 823 are coplanar at a sixth distance D6 from the front dielectric layer 105. In addition, the integrated fan-out via 107 of the sixth system-in-package device 810 has a ninth height H9 substantially equal to the sixth distance D6. According to some embodiments, the sixth distance D6 is between about 90 μm and about 200 μm, for example about 135 μm. However, any suitable distance may be used.

[0139] According to some embodiments of the present disclosure, various anisotropic devices and asymmetric double-sided molding packages can be used to manufacture system-level package devices on a multi-layer redistribution layer structure with a small profile formed using a single carrier substrate. Therefore, the system-level package device can be manufactured more efficiently and is less prone to defects.

[0140] Embodiments of the present disclosure may also include other features and processes. For example, a test structure may be included to assist in verification testing of a three-dimensional package or a three-dimensional integrated circuit device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate to allow the use of probes and / or probe cards to test the three-dimensional package or the three-dimensional integrated circuit. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods of the present disclosure may be used together with a test method for verification of a known good die intermediate step to increase yield and reduce cost.

[0141] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including depositing a first dielectric layer over a carrier substrate, adhering a first device to the first dielectric layer, sealing the first device in a first molding compound, forming an interconnect structure over the first device, a first interface between the interconnect structure and the first device having a first shape, placing a second device over the interconnect structure, the interconnect structure electrically coupling the second device to the first device, a second interface between the interconnect structure and the second device having a second shape, the first shape being different from the second shape, and sealing the second device in a second molding compound after placing the second device over the interconnect structure. In some embodiments, the thermal expansion coefficient of the second molding compound is different from the thermal expansion coefficient of the first molding compound. In some embodiments, the coefficient of thermal expansion of the first molding compound is a first coefficient of thermal expansion of the first molding compound, the first coefficient of thermal expansion of the first molding compound is lower than a glass transition temperature of the first molding compound, the coefficient of thermal expansion of the second molding compound is a first coefficient of thermal expansion of the second molding compound, the first coefficient of thermal expansion of the second molding compound is lower than the glass transition temperature of the second molding compound, and the ratio of the first coefficient of thermal expansion of the second molding compound to the first coefficient of thermal expansion of the first molding compound is between 0.8 and 0.99, including 0.8 and 0.99. In some embodiments, the coefficient of thermal expansion of the first molding compound is a second coefficient of thermal expansion of the first molding compound, the second coefficient of thermal expansion of the first molding compound is higher than the glass transition temperature of the first molding compound, the coefficient of thermal expansion of the second molding compound is a second coefficient of thermal expansion of the second molding compound, the second coefficient of thermal expansion of the second molding compound is higher than the glass transition temperature of the second molding compound, and the ratio of the second coefficient of thermal expansion of the second molding compound to the second coefficient of thermal expansion of the first molding compound is between 0.1 and 0.7, including 0.1 and 0.7. In some embodiments, the semiconductor device manufacturing method further includes placing an integrated passive device above the carrier substrate, attaching the integrated passive device to the silicon dam element, and making the integrated passive device flush with the first device. In some embodiments, the first shape is a flat surface, and the second shape is a concave shape. In some embodiments, the concave shape has a first width, the flat surface has a second width, and the ratio of the first width to the second width is between 3 and 7, including 3 and 7.

[0142] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including depositing a first dielectric layer over a system-on-chip device, forming a first opening through the first dielectric layer, a first die connection element of the system-on-chip device exposed from the first opening, depositing a first metallization pattern over the first dielectric layer and in the first opening, the first opening leading to the first die connection element, a first planar contact region interface formed between the first metallization pattern and the first die connection element, forming a second dielectric layer over the first metallization pattern, forming a second opening through the second dielectric layer, forming a second metallization pattern over the second dielectric layer and in the second opening, placing an integrated circuit device over the second metallization pattern, and attaching a contact region of the integrated circuit device to a surface of the second metallization pattern, wherein the surface of the second metallization pattern is recessed. In some embodiments, the method for manufacturing a semiconductor device also includes sealing the system-on-chip device in a first molding compound before depositing the first dielectric layer, and sealing the integrated circuit device in a second molding compound after placing the integrated circuit device over the second metallization pattern. In some embodiments, a ratio of a second height of the second molding compound to a first height of the first molding compound is at most 6. In some embodiments, the semiconductor device manufacturing method further includes forming a via before depositing a first dielectric layer over the system-on-chip device, and after the operation of forming the via, the system-on-chip device is adjacent to the via. In some embodiments, the semiconductor device manufacturing method further includes forming a third opening, the first interconnect via is exposed from the third opening, and the operation of depositing a first metallization pattern over the first dielectric layer further includes depositing the first metallization pattern to the first interconnect via in the third opening. In some embodiments, the semiconductor device manufacturing method further includes forming a first external connection element to the first interconnect via, the first interconnect via being opposite to the first metallization pattern, and forming a second external connection element adjacent to the first external connection element, and the distance between the first external connection element and the second external connection element is between 80 μm and 250 μm, including 80 μm and 250 μm. In some embodiments, the surface of the second metallization pattern has a first width, the first flat contact area interface has a second width, and the ratio of the first width to the second width is between 3 and 7, including 3 and 7.

[0143] Some embodiments of the present disclosure provide a semiconductor device, including a system-on-chip device, an integrated circuit device, and a redistribution structure, wherein the redistribution structure is physically separated from the integrated circuit device and the system-on-chip device and electrically connected, and the redistribution structure includes a first metal line and a second metal line, wherein the first metal line has a concave interface with the integrated circuit device, and the second metal line has a flat interface with the system-on-chip device. In some embodiments, the concave interface has a first width, and the flat interface has a second width, and the second width is smaller than the first width. In some embodiments, the ratio of the first width to the second width is between 3 and 7, including 3 and 7. In some embodiments, the semiconductor device further includes a first internal connection via, wherein the redistribution structure further includes a third metal line, which has a second flat interface with the first internal connection via. In some embodiments, the semiconductor device further includes an integrated passive device adjacent to the system-on-chip device, wherein the integrated passive device is electrically connected to the redistribution structure and physically contacts a dam element, and the dam element and the integrated passive device are located on both sides of the redistribution structure. In some embodiments, the semiconductor device also includes a first molding compound and a second molding compound, the first molding compound seals the system on chip, the first molding compound has a first height, the second molding compound seals the integrated circuit device, the second molding compound has a second height, and the ratio of the second height to the first height is between 0 and 6, including 0 and 6.

[0144] The above content summarizes the features of many embodiments, so anyone with ordinary knowledge in the art can better understand the various aspects of the present disclosure. Anyone with ordinary knowledge in the art may have no difficulty in designing or modifying other processes and structures based on the present disclosure to achieve the same purpose and / or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the art should also understand that different changes, substitutions and modifications are made without departing from the spirit and scope of the present disclosure, and such equivalent creations do not exceed the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: Depositing a first dielectric layer over a carrier substrate; adhering a first device to the first dielectric layer; sealing the first device in a first molding compound; forming an interconnect structure above the first device, wherein a first interface between the interconnect structure and the first device has a first shape; placing a second device over the interconnect structure, the interconnect structure electrically coupling the second device to the first device, wherein a second interface between the interconnect structure and the second device has a second shape, the first shape is different from the second shape, wherein the first shape is a flat surface, and the second shape is a concave shape, the concave shape has a first width, the flat surface has a second width, and a ratio of the first width to the second width is between 3 and 7, inclusive; and After placing the second device over the interconnect structure, the second device is encapsulated in a second molding compound.

2. The method for manufacturing a semiconductor device according to claim 1, wherein The second molding compound has a coefficient of thermal expansion that is different from a coefficient of thermal expansion of the first molding compound.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The thermal expansion coefficient of the first molding compound is a first thermal expansion coefficient of the first molding compound, the first thermal expansion coefficient of the first molding compound is lower than a glass transition temperature of the first molding compound, and the thermal expansion coefficient of the second molding compound is a first thermal expansion coefficient of the second molding compound, the first thermal expansion coefficient of the second molding compound is lower than a glass transition temperature of the second molding compound; as well as A ratio of the first coefficient of thermal expansion of the second molding compound to the first coefficient of thermal expansion of the first molding compound is between 0.8 and 0.99, inclusive.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The coefficient of thermal expansion of the first molding compound is a second coefficient of thermal expansion of the first molding compound, the second coefficient of thermal expansion of the first molding compound is higher than the glass transition temperature of the first molding compound, and the coefficient of thermal expansion of the second molding compound is a second coefficient of thermal expansion of the second molding compound, the second coefficient of thermal expansion of the second molding compound is higher than the glass transition temperature of the second molding compound; as well as A ratio between the second coefficient of thermal expansion of the second molding compound and the second coefficient of thermal expansion of the first molding compound is between 0.1 and 0.7, inclusive.

5. The method for manufacturing a semiconductor device according to claim 1, further comprising: placing an integrated passive device on the carrier substrate, the integrated passive device being attached to a silicon dam element; as well as The integrated passive device is made flush with the first device.

6. A method for manufacturing a semiconductor device, comprising: depositing a first dielectric layer over a system-on-chip device; forming a first opening through the first dielectric layer, a first die connection element of the system-on-chip device being exposed from the first opening; Depositing a first metallization pattern over the first dielectric layer and in the first opening, the first opening leading to the first die connection element, a first planar contact region interface formed between the first metallization pattern and the first die connection element; depositing a second dielectric layer over the first metallization pattern; forming a second opening through the second dielectric layer; forming a second metallization pattern above the second dielectric layer and in the second opening, wherein a surface of the second metallization pattern has a first width, the first flat contact region interface has a second width, and a ratio of the first width to the second width is between 3 and 7, inclusive; placing an integrated circuit device on top of the second metallization pattern; as well as A contact area of ​​the integrated circuit device is attached to the surface of the second metallization pattern, and the surface of the second metallization pattern is recessed.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising: prior to the operation of depositing the first dielectric layer, encapsulating the system-on-chip device in a first molding compound; as well as After placing the integrated circuit device over the second metallization pattern, the integrated circuit device is sealed in a second molding compound.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: A ratio of a second height of the second molding compound to a first height of the first molding compound is at most 6.

9. The method for manufacturing a semiconductor device according to claim 6, further comprising: A via is formed before depositing the first dielectric layer over the system-on-chip device, wherein after forming the via, the system-on-chip device is adjacent to the via.

10. The method for manufacturing a semiconductor device according to claim 6, further comprising: A third opening is formed, and a first interconnect via is exposed from the third opening, wherein the operation of depositing the first metallization pattern on the first dielectric layer further includes depositing the first metallization pattern in the third opening, and the third opening leads to the first interconnect via.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising: forming a first external connection element to the first internal connection via, the first internal connection via being opposite to the first metallization pattern; as well as A second external connection element is formed adjacent to the first external connection element, and a distance between the first external connection element and the second external connection element is between 80 μm and 250 μm, inclusive.

12. A semiconductor device comprising: a system-on-chip device; an integrated circuit device; as well as A redistribution structure is physically separated from and electrically coupled to the integrated circuit device and the system-on-chip device, wherein the redistribution structure includes a first metal line and a second metal line, the first metal line and the integrated circuit device have a concave interface, and the second metal line and the system-on-chip device have a flat interface, wherein the concave interface has a first width, and the flat interface has a second width, and the second width is smaller than the first width, wherein the ratio of the first width to the second width is between 3 and 7, including 3 and 7. 13 . The semiconductor device as claimed in claim 12 , further comprising a first interconnect via, wherein the redistribution structure further comprises a third metal line, and the third metal line and the first interconnect via have a second flat interface.

14. The semiconductor device as claimed in claim 13, further comprising an integrated passive device adjacent to the system on chip device, the integrated passive device being electrically connected to the redistribution structure and physically contacting a dam element, and the dam element and the integrated passive device being located on both sides of the redistribution structure.

15. The semiconductor device according to claim 12, further comprising: a first molding compound, sealing the system on chip, the first molding compound having a first height; as well as A second molding compound seals the integrated circuit device, the second molding compound having a second height, and a ratio of the second height to the first height is between 0 and 6, inclusive.

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