Wafer support, semiconductor processing system and method thereof

Abstract

A wafer support, a semiconductor processing system and a method thereof, wherein the semiconductor processing system includes a wafer support and a control system. The wafer support includes a plurality of heating elements and a plurality of temperature sensors. The heating elements heat a semiconductor wafer supported by the support system. The temperature sensors generate sensor signals indicating the temperature. The control system selectively controls the heating elements in response to the sensor signals.

Description

Technical Field

[0001] The present disclosure relates to a wafer support, a semiconductor processing system and a method thereof, and more particularly to a wafer support, a semiconductor processing system and a method thereof for heating a semiconductor wafer. Background Art

[0002] The ongoing demand for computing power has been increasing for electronic devices including smartphones, tablet computers, desktop computers, laptop computers, and many other types of electronic devices. Integrated circuits provide the computing power for these electronic devices. One way to increase computing power in an integrated circuit is to increase the number of transistors and other integrated circuit features that can be included in a given area of ​​a semiconductor substrate.

[0003] In order to continue to reduce the size of features in integrated circuits, various thin film deposition techniques have been implemented. These techniques can form very thin films. However, thin film deposition techniques also face serious difficulties in ensuring that the film is formed correctly. Summary of the invention

[0004] In one embodiment of the present disclosure, a wafer support is provided. The wafer support includes a top surface, an array of multiple heating elements, an array of multiple temperature sensors, multiple first electrical connectors, and multiple second electrical connectors. The top surface is configured to support a semiconductor wafer. The array of multiple heating elements is positioned below the top surface and is configured to output heat. The array of multiple temperature sensors includes a corresponding first temperature sensor relative to each heating element, and the corresponding first temperature sensor is configured to generate multiple first sensor signals. Multiple first electrical connectors are coupled to these heating elements and are configured to be able to selectively control each heating element. Multiple second electrical connectors are coupled to the corresponding first temperature sensors.

[0005] In another embodiment of the present disclosure, a semiconductor processing system includes a semiconductor processing chamber, a wafer support, and a control system. The wafer support is positioned in the semiconductor processing chamber and is configured to support a semiconductor wafer, and the wafer support includes an array of multiple heating elements and an array of multiple temperature sensors. Each heating element is configured to heat the semiconductor wafer when the semiconductor wafer is positioned on the wafer support. The array of multiple temperature sensors includes a corresponding first temperature sensor relative to each heating element, and the corresponding first temperature sensor is configured to generate a plurality of first sensor signals. The control system is communicatively coupled to the heating elements and the corresponding first temperature sensors, and is configured to selectively operate each heating element at least partially in response to the first sensor signals.

[0006] In one embodiment of the present disclosure, a semiconductor processing method includes supporting a semiconductor wafer with a wafer support positioned in a semiconductor processing chamber. Performing semiconductor processing on the wafer in the semiconductor processing chamber. Heating the semiconductor wafer with a plurality of heating elements positioned in the wafer support during the semiconductor processing. Generating a plurality of first sensor signals for each heating element using a corresponding first temperature sensor positioned in the wafer support. In response to the first sensor signals, selectively controlling the heating elements using a control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, the various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with the practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity, the size of the various features can be arbitrarily increased or reduced.

[0008] Figure 1 is a diagram of a semiconductor processing system according to one embodiment;

[0009] Figure 2A is a cross-sectional view of a wafer support according to one embodiment;

[0010] Figure 2B is a top view of a wafer support according to one embodiment;

[0011] Figure 2C is a cross-sectional view of a wafer support according to one embodiment;

[0012] Figure 3A is a cross-sectional view of a heating element according to one embodiment;

[0013] Figure 3B is a top view of a heating element according to one embodiment;

[0014] Figure 4A is a top view of a wafer according to one embodiment;

[0015] Figure 4B is a cross-sectional view of a wafer according to one embodiment;

[0016] Figure 4C is a top view of a wafer support according to one embodiment;

[0017] Figure 5A is a cross-sectional view of a wafer after a first thin film deposition process according to one embodiment;

[0018] Figure 5B is a cross-sectional view of a wafer support according to one embodiment, illustrating selective activation of a heating element during a second deposition process;

[0019] Figure 5C is a cross-sectional view of a wafer after a second thin film deposition process according to one embodiment;

[0020] Fig. 6A is a cross-sectional view of a wafer support according to one embodiment;

[0021] Figure 6B is a cross-sectional view of a wafer support according to one embodiment;

[0022] Figure 7 is a flow chart of a method 700 for performing semiconductor processing.

[0023]

Explanation of symbols

[0024] 100:Semiconductor processing systems

[0025] 102: Semiconductor processing chamber

[0026] 104: Wafer

[0027] 106:Semiconductor processing equipment

[0028] 108: Wafer support

[0029] 110: Control System

[0030] 112: Heating element

[0031] 114: Temperature sensor

[0032] 114a: Top temperature sensor

[0033] 114b: Bottom temperature sensor

[0034] 116: Electrical connection

[0035] 118:Electrical connector

[0036] 120:Electrical connector

[0037] 122: Top surface

[0038] 124: Top surface

[0039] 125: Bottom surface

[0040] 127a: Top thermocouple

[0041] 127b: Bottom thermocouple

[0042] 129: Top surface

[0043] 130: Heating coil

[0044] 131: Ceramic materials

[0045] 133: Copper pad

[0046] 134: pad part

[0047] 135: Aluminum layer

[0048] 136: Group

[0049] 137: Barrier layer

[0050] 139: Passivation layer

[0051] 140: First Film

[0052] 141: Groove / hole

[0053] 142: Group 1

[0054] 143: Extrudate

[0055] 144: Second Group

[0056] 146: The third group

[0057] 148: Second film

[0058] 149: Top surface

[0059] 150: Fixture

[0060] 700: Method

[0061] 702: Steps

[0062] 704: Steps

[0063] 706: Steps

[0064] 708: Steps

[0065] 710: Steps DETAILED DESCRIPTION

[0066] In the following description, a number of thicknesses and materials are described for various layers and structures within an integrated circuit die. For various embodiments, specific dimensions and materials are given by way of example. Based on the present disclosure, those skilled in the art will recognize that in many cases, other dimensions and materials can be used without departing from the scope of the present disclosure.

[0067] The following disclosure provides many different embodiments or examples for implementing the different features of the described subject matter. Specific examples of components and arrangements are described below to simplify this description. Of course, these examples are only examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0068] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to simplify descriptions to describe the relationship of one element or feature to another element or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0069] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be practiced without these specific details. In other cases, well-known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0070] Unless the context requires otherwise, throughout the following specification and claims, the word "comprise" and variations such as "include" and "comprising" are to be interpreted in an open, inclusive sense, ie, to mean "including, but not limited to."

[0071] The use of ordinal numbers such as first, second, and third does not necessarily imply an ordinal sense of ranking, but rather merely serves to distinguish between multiple instances of an action or structure.

[0072] Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification do not necessarily all refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0073] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in a sense including "and / or" unless the content clearly dictates otherwise.

[0074] Embodiments of the present disclosure provide many benefits over conventional semiconductor processing systems. Embodiments of the present disclosure provide a wafer support having an array of selectively operable heating elements. These heating elements can be operated to provide a uniform temperature distribution on the surface of a wafer supported by the wafer support. The uniform temperature distribution can correspond to all areas of the surface having substantially the same temperature. Alternatively, the heating elements can be operated to heat selected areas of the wafer more than other areas. As a result, semiconductor processing can be performed more reliably and with better results. The film can have a uniform thickness. In addition, the pad portion of the wafer can be selectively degassed to prevent damage to the wafer. Selectively operable heating elements can also produce many other benefits.

[0075] Figure 1 is a block diagram of a semiconductor processing system 100 according to one embodiment. The semiconductor processing system 100 includes a semiconductor processing chamber 102 for performing one or more semiconductor processes on a wafer 104. The semiconductor processing system 100 includes semiconductor processing equipment 106, a wafer support 108, and a control system 110. The components of the semiconductor processing system 100 cooperate to perform a semiconductor process on the wafer 104 and ensure that the semiconductor process is successful.

[0076] In one embodiment, the wafer 104 is a semiconductor wafer. Typically, semiconductor wafers undergo a large number of processes during manufacturing. These processes may include thin film deposition, photoresist patterning, etching processes, dopant implantation processes, annealing processes, and other types of processes. After all processing steps are completed, the wafer 104 is cut into a plurality of individual integrated circuits.

[0077] In addition, it is beneficial to heat the wafer 104 during many semiconductor processes. For example, many thin film deposition processes benefit from increasing the temperature of the wafer during thin film deposition. The increased temperature of the wafer can promote deposition. For many thin film deposition processes, the deposition rate is faster when the wafer 104 is at a higher temperature rather than a lower temperature. In other words, during deposition, when the wafer 104 is heated to a higher temperature, the film accumulates faster. In some cases, this is done because the deposited material is more likely to combine or react with the exposed deposition surface of the wafer 104. In addition, the material already deposited on the wafer 104 can more easily react or combine with the additional deposited material.

[0078] Wafer support 108 is configured to support wafer 104. For example, wafer support 108 may include a flat and circular top surface so that circular wafer 104 can be positioned and supported on the top surface. As will be described in more detail below, wafer support 108 may also include one or more mechanisms for firmly holding wafer 104 in place.

[0079] The wafer support 108 includes a plurality of heating elements 112. The heating elements 112 generate heat. The heat generated by the heating elements 112 may heat the top surface of the wafer support 108. The wafer 104 positioned on the wafer support 108 receives the heat from the wafer support 108. Thus, during semiconductor processing, the heating elements 112 apply heat to the wafer 104. For example, the heating elements 112 may heat the wafer 104 during a thin film deposition process. Alternatively, the heating elements 112 may heat the wafer 104 during other semiconductor processing.

[0080] In one embodiment, the array of heating elements 112 is distributed to promote uniform heating of the wafer 104. The heating elements 112 are distributed so that when the wafer 104 is positioned on the wafer support 108, each area of ​​the bottom surface of the wafer 104 is directly positioned above one of the heating elements 112. The distribution of a large number of heating elements 112 throughout the wafer support 108 can help ensure that all areas of the wafer 104 are heated uniformly. This can help ensure that the temperature of the wafer 104 is uniform in all areas of the wafer 104 during semiconductor processing. If the temperature of the wafer 104 is substantially uniform across the top surface of the wafer 104, then in many cases, it will be more likely that the semiconductor processing will be completed properly.

[0081] One possible way to heat a wafer during semiconductor processing is to have a wafer support with a single large heater coil wrapped underneath the top surface of the wafer support. However, one problem with this approach is that it typically results in non-uniform temperatures across the surface of the wafer. This is because the center portion of the wafer support is typically heated to a higher temperature than the peripheral portions of the wafer support. This in turn results in the center region of the top surface of the wafer having a higher temperature than the peripheral regions of the wafer. The non-uniform temperature distribution on the wafer surface leads to failures in semiconductor processing. For example, if the center portion of the top surface of the wafer is hotter than the peripheral portions of the wafer during a thin film deposition process, the film may be thicker at the center region than at the peripheral regions. This can result in integrated circuits with mismatched features and performance, or even integrated circuits that do not function at all.

[0082] The semiconductor processing system 100 overcomes this problem by providing an array of heating elements 112. Because the wafer support 108 includes a large number of heating elements 112 evenly distributed below the top surface of the wafer support 108, the heating elements 112 can evenly heat the wafer 104. As a result, the top surface of the wafer 104 can have a substantially uniform temperature at the central region and the peripheral region. In the example of a thin film deposition process, this results in a thin film having uniform thickness and other physical properties.

[0083] In one embodiment, the heating element 112 is connected to the control system 110 via one or more electrical connections 116. The control system 110 controls the function of the heating element 112. Specifically, the control system 110 can enable or disable the heating element 112. Enabling the heating element 112 will cause the heating element 112 to generate heat. Deactivating the heating element 112 will stop the heating element from generating heat. In addition, the control system 110 can control how much heat the heating element 112 generates. Thus, the control system 110 can increase or decrease the temperature of the wafer 104 by causing the heating element 112 to increase or decrease the heat output.

[0084] Although not in Figure 1 1 , but in one embodiment, the control system 110 may include one or more power supplies. The power supply may supply power to the heating element 112 so that the heating element 112 can generate heat. Alternatively, the control system 110 is connected to a power supply, which is connected to the heating element 112. In this case, the control system 110 controls the heating element 112 by controlling the output of the power supply to the heating element 112.

[0085] In one embodiment, the heating element 112 is an electric heating element. The electric heating element 112 may include an electric conductor or a resistor. The heating element 112 generates heat by passing an electric current through the electric conductor or the resistor. The heating elements 112 may each include a corresponding conductive coil. The heating element generates heat by passing an electric current through the conductive coil. Other types of heating elements 112 may be utilized without departing from the scope of the present disclosure.

[0086] In one embodiment, the control system 110 is configured to selectively control each heating element 112. In this case, the control system 110 can selectively enable each individual heating element 112. Thus, the control system 110 can enable some heating elements 112 and not enable other heating elements 112. In some cases, it is beneficial to heat some areas of the wafer 104 more than other areas. The wafer support 108 and the control system 110 enable different areas of the wafer 104 to be selectively heated.

[0087] In one embodiment, the control system 110 is configured to selectively control how much heat each heating element 112 generates. The control system 110 selectively causes some heating elements 112 to generate more heat than other heating elements 112. In one embodiment, the peripheral regions of the wafer 104 may tend to dissipate more heat than the central region of the wafer 104. Therefore, to ensure a uniform temperature of the wafer 104, the control system 110 may control the peripheral heating elements 112 to generate more heat than the central heating element 112 to account for the greater heat dissipation at the peripheral regions of the wafer 104. The electrical connectors 116 may include a plurality of electrical connectors capable of selectively heating the individual heating elements 112.

[0088] In one embodiment, the temperature sensor 114 is configured to sense the temperature of the heating element 112. The temperature sensor 114 may be disposed in thermal contact with the heating element 112. The thermal contact enables the temperature sensor 114 to sense the temperature of the heating element 112. Alternatively, the temperature sensor 114 may be disposed adjacent to the heating element 112 but not in thermal contact with the heating element 112.

[0089] In one embodiment, the temperature sensors 114 are electrically connected to the control system 110 via a plurality of electrical connectors 118. The temperature sensors 114 may generate sensor signals indicative of the temperature of the heating element 112, the wafer support 108, and / or the wafer 104. The temperature sensors 114 may transmit the sensor signals to the control system 110. Each temperature sensor 114 may provide an individual sensor signal to the control system 110. The sensor signal from an individual temperature sensor 114 indicates the temperature at or near the location of the temperature sensor 114.

[0090] In one embodiment, the control system 110 may control the heating elements 112 in response to the sensor signals from the temperature sensors 114. The control system 110 may selectively enable or disable each heating element 112 in response to the sensor signals from the temperature sensors 114. The control system 110 may adjust the heat output of each heating element 112 in response to the sensor signals from the temperature sensors 114.

[0091] In one embodiment, the wafer support 108 includes a respective temperature sensor 114 for each heating element 112. Thus, for each heating element 112, the respective temperature sensor 114 generates a sensor signal indicative of the temperature of the heating element 112 or the temperature in an area adjacent to the heating element 112. In this case, the control system 110 receives the sensor signal for each individual heating element 112. The control system 110 can then adjust the heat output of each heating element 112 in response to the respective sensor signal so as to produce or maintain selected thermal characteristics of the wafer 104.

[0092] In one embodiment, the corresponding temperature sensor 114 of each heating element 112 senses the temperature of the wafer 104 at the area above the heating element 112. Therefore, for each heating element 112, the corresponding temperature sensor 114 generates a sensor signal indicative of the temperature of the wafer 104 at the area above the heating element 112. The control system 110 receives the sensor signal for each individual heating element 112. The control system 110 can then adjust the heat output of each heating element 112 in response to the corresponding sensor signal to produce or maintain selected thermal characteristics of the wafer 104.

[0093] In one embodiment, the wafer support 112 includes two corresponding temperature sensors 114 for each heating element 112 of the pin. A first temperature sensor of the corresponding temperature sensors 114 senses the temperature of the heating element 112. A second temperature sensor of the corresponding temperature sensors 114 senses the temperature of the wafer 104 at an area above the heating element 112.

[0094] The semiconductor processing system 100 includes semiconductor processing equipment 106. The semiconductor processing equipment 106 assists in performing semiconductor processing. The semiconductor processing equipment 106 may include equipment that assists thin film deposition processes, etching processes, ion implantation processes, annealing processes, photolithography processes, and other types of processes. The semiconductor processing equipment 106 may include components for generating plasma within the semiconductor processing chamber 102. Some of the semiconductor processing equipment 106 may be completely located within the semiconductor processing chamber 102. Some of the semiconductor processing equipment 106 may be partially located within the semiconductor processing chamber 102 and partially located outside the semiconductor processing chamber 102. Some of the semiconductor processing equipment 106 may be completely located outside the semiconductor processing chamber 102.

[0095] The semiconductor processing equipment 106 may include equipment for managing gases or flows within the semiconductor processing chamber 102. The processing equipment may include components for introducing gases or fluids into the semiconductor processing chamber 102, for removing gases or fluids from the semiconductor processing chamber, and for monitoring and controlling the flow, presence, or composition of gases within the semiconductor processing chamber 102. The semiconductor processing equipment 106 may include equipment for maintaining a selected pressure within the semiconductor processing chamber 102.

[0096] The semiconductor processing equipment 106 may include electrical components for generating electric fields, voltages, magnetic fields, electrical signals, or other types of electrical effects. Thus, the semiconductor processing equipment 106 may include electrodes, wires, radio frequency power supplies, transmitters, receivers, or other types of electrical devices that may be utilized in semiconductor processing.

[0097] In one embodiment, the control system 110 is communicatively coupled to the semiconductor processing equipment 106 via one or more electrical connectors 120. The control system 110 can control semiconductor processing by controlling the semiconductor processing equipment 106. The control system 110 can adjust the operation of the semiconductor processing equipment 106 in response to the sensor signal from the temperature sensor 114. For example, in some cases, it may be beneficial to adjust the flow of deposition material or other fluids entering the deposition chamber based on the temperature of the wafer 104. In other cases, it may be beneficial to adjust the parameters of plasma generation within the semiconductor processing chamber 102 based on the temperature in the wafer 104. The control system 110 can make these adjustments in response to the sensor signal from the temperature sensor 114.

[0098] In one embodiment, the control system 110 may cause the semiconductor processing equipment 106 to completely stop semiconductor processing in response to the sensor signal provided by the temperature sensor 114. In order to avoid serious damage to the semiconductor wafer 104, in some cases, the control system 110 may determine that the best course of action is to completely stop semiconductor processing until other adjustments or repairs can be made.

[0099] In one embodiment, the control system 110 may include a portion external to the semiconductor processing chamber 102, a portion internal to the semiconductor processing chamber 102, and / or a portion executed in the cloud. Thus, the control system 110 may have various processing, memory, and data transmission resources distributed in multiple locations. The control system 110 may also include virtual memory, processing, and data transmission resources in the cloud.

[0100] In one embodiment, the control system 110 may include a machine learning based analysis model. The machine learning based analysis model may be trained to selectively operate each heating element 112 in response to a sensor signal from the temperature sensor 114. The machine learning based analysis model may be trained to control or adjust semiconductor processing parameters based on the sensor signal.

[0101] Figure 2A 1 is a cross-sectional view of a wafer support 108 according to one embodiment. The wafer support 108 includes a top surface 122. During semiconductor processing, the wafer 104 (in Figure 2A The wafer support 108 includes an array of heating elements 112. Each heating element 112 generates heat. The heating elements 112 may be substantially as follows: Figure 1 The described aspects generate heat. Figure 1 As described, the heating element 112 can be connected to the electrical connector 116 (at Figure 2A (not shown) is connected to the control system 110.

[0102] During semiconductor processing, the heating element 112 generates heat. The heat generated by the heating element 112 heats the wafer 104 via the top surface 122 of the wafer support 108. The heating element 112 can be operated to establish or maintain a uniform temperature across the deposition surface of the wafer 104. The heating element 112 can be operated to establish a selected temperature distribution across the surface of the wafer 104.

[0103] In one embodiment, each heating element 112 includes a top temperature sensor 114a and a bottom temperature sensor 114b. The top temperature sensor 114a in each heating element 112 senses the temperature of the wafer 104. The bottom temperature sensor 114b in each heating element 112 senses the temperature of the heating element 112.

[0104] In one embodiment, the top temperature sensor 114a is located at the top surface 122 of the wafer support 108. In this case, the top temperature sensor 114a senses the temperature of the bottom surface of the wafer 104. When the wafer 104 is placed on the wafer support 108, the bottom surface of the wafer 104 contacts the top surface 122 of the wafer support 108. This portion of the top temperature sensor 114a may be in direct contact with the bottom surface of the wafer 104.

[0105] In one embodiment, the top temperature sensor 114a generates a sensor signal indicating a temperature at the bottom surface of the wafer 104 directly above the top temperature sensor 114a. The temperature of the top surface of the wafer can be inferred from the temperature of the bottom surface of the wafer. In practice, there will be a temperature gradient between the bottom surface of the wafer 104 and the top surface of the wafer 104. Because the bottom surface of the wafer 104 is closer to the heating element 112, the bottom surface may have a slightly higher temperature than the top surface of the wafer. The control system 110 can estimate the temperature of the top surface of the wafer 104 based on the temperature of the bottom surface of the wafer 104.

[0106] In one embodiment, the top temperature sensor 114a of each heating element 112 is positioned slightly below the top surface 112 of the wafer support 108. In this case, the wafer support 108 may include a material layer on top of the heating elements 112. The material layer may include a thermally conductive material to distribute heat from the heating elements 112 to the wafer 104.

[0107] In one embodiment, the heating element 112 has a thickness T. In one example, the thickness T is between 3 cm and 8 cm. The heating element 112 may have other thicknesses T without departing from the scope of the present disclosure.

[0108] Figure 2B According to one embodiment Figure 2A FIG. 1 is a top view of the wafer support 108 . Figure 2BThe view of FIG. 1 illustrates the top temperature sensor 114a exposed at the top surface 122. However, in some embodiments, the top temperature sensor 114a is not exposed at the top surface 122. Instead, the top temperature sensor 114a may be disposed slightly below the top surface 122 of the wafer support 108. In this case, the top temperature sensor 114a would not be visible at the top surface 122 of the wafer support 108.

[0109] In one embodiment, the top surface 122 of the wafer support 108 is circular. The top surface 122 of the wafer support 108 is a diameter D. The diameter D is selected to support a circular wafer 104 of a selected size. In one embodiment, the diameter D is selected to be the same diameter as the wafer 104 to be supported by the wafer support 108. In one example, the wafer support 108 is configured to support a wafer having a diameter of 300 mm. In this case, the wafer support 108 has a diameter of 300 mm. Alternatively, the diameter D can be slightly larger than the diameter of the largest wafer 104 expected to be supported on the wafer support 108.

[0110] Figure 2B The diagram shows a distribution of heating elements 112 having a rounded top surface. Figure 2A 1 , the heating elements 112 have a cylindrical shape. However, in alternative embodiments, the heating elements 112 may have a top surface other than circular and an overall shape other than cylindrical without departing from the scope of the present disclosure. Furthermore, the wafer support 108 includes material disposed between the heating elements 112 such that the wafer support 108 is substantially solid and has no air gaps. However, in other embodiments, the wafer support 108 may include gaps or voids.

[0111] Figure 2C 1 is a cross-sectional view of a wafer support 108 according to one embodiment, wherein a wafer 104 is positioned on the wafer support. The wafer 104 includes a top surface 124 and a bottom surface 125. The bottom surface of the wafer 104 is in direct contact with the top surface 122 of the wafer support 108. The top surface 124 of the wafer 104 may also be referred to as a deposition surface. This is because the thin film deposition process will deposit a thin film on the top surface 124 of the wafer 104. Although the top surface 124 is Figure 2C 1. As shown in FIG. 1, top surface 124 is substantially flat, but in practice, top surface 124 may include surface features such as protrusions and depressions according to the pattern of the thin film of wafer 104.

[0112] Figure 3A is a cross-sectional view of a heating element 112 according to one embodiment. Figure 3A The heating element 112 can be Figures 1 to 2C1. The heating element 112 is one example of a type of heating element utilized in the wafer support 108. The heating element 112 generates heat to heat the wafer 104 during semiconductor processing.

[0113] In one embodiment, the heating element 112 includes a heating coil 130. When current passes through the heating coil 130, the heating element 112 generates heat. The heating coil 130 may include a conductive material such as copper, tungsten, or other conductive material that can generate heat when current passes through the heating coil 130. The heating coil 130 may also include a resistor. The heating coil 130 may be coated with an insulating material. Based on the present disclosure, those skilled in the art will recognize that many configurations and materials can be used for the heating coil 130 without departing from the scope of the present disclosure.

[0114] In one embodiment, the heating coil 130 is connected to two electrical connectors 116. The two electrical connectors 116 can be coupled to the control system 110 (see Figure 1 ) or coupled to a power source controlled by the control system 110. The control system 110 can selectively deliver current to the heating coil 130 via the two electrical connectors 116. In particular, a voltage can be applied between the electrical connectors 116 to deliver current to the heating coil 130.

[0115] In one embodiment, each heating coil 130 can be selectively controlled by the control system 110, as previously described with respect to Figure 1 Thus, each heating element 112 may include two or more electrical connectors 116 coupled to the control system 110 . The control system 110 may then selectively enable, disable, or adjust the current through the heating coil 130 via the electrical connectors 116 .

[0116] In one embodiment, the heating element 112 includes a top thermocouple 127a and a bottom thermocouple 127b. The top thermocouple 127a and the bottom thermocouple 127b are Figure 1 The heating element 114 or Figures 1 to 2C 1. Thus, the top thermocouple 127a and the bottom thermocouple 127b are temperature sensors.

[0117] In one embodiment, the top thermocouple 127a is configured to generate a sensor signal indicative of the temperature of the wafer 104 in the region directly above the heating element 112. The top thermocouple 127a can function in a standard thermocouple manner by generating a voltage between two leads. According to a well-known relationship, the voltage represents the temperature near the two leads. The two leads of the top thermocouple 127a can be positioned at the top surface 129 of the heating element 112. Depending on the specific structure of the wafer support 108 in various embodiments, the top surface 129 of the heating element 112 may or may not correspond to the top surface 122 of the wafer support 108. Alternatively, the two leads of the top thermocouple 127a can be disposed slightly below the top surface 129 of the heating element 112.

[0118] In one embodiment, the bottom thermocouple 127b is positioned to sense the temperature near the heating coil 130. The bottom thermocouple 127b functions in the same manner as the top thermocouple 127a. The bottom thermocouple 127b generates a voltage between two leads. The voltage represents the temperature near the two leads. The two leads of the bottom thermocouple 127b may be disposed within the heating coil 130 but not in contact with the heating coil 130. The bottom thermocouple 127b generates a sensor signal indicating the temperature of the heating coil 130.

[0119] In one embodiment, the top and bottom thermocouples 127b are connected to the control system 110 via electrical connectors 118. Although only a single electrical connector 118 is illustrated connecting each of the top thermocouple 127a and the bottom thermocouple 127b, in practice, there may be two electrical connectors 118 for each of the top thermocouple 127a and the bottom thermocouple 127b. The control system 110 may adjust the function of the heating coil 130 in response to the sensor signals from the top thermocouple 127a and the bottom thermocouple 127b.

[0120] In one embodiment, the heating element 112 includes a ceramic material 131 covering the heater coil 130, the top thermocouple 127a, and the bottom thermocouple 127b. The ceramic material 131 is selected to conduct heat from the heater coil 130 to the wafer 104. The ceramic material 131 may constitute a majority of the volume of the heating element 112. The ceramic material 131 may be positioned to prevent electrical shorts between different areas of the heater coil 130. The ceramic material 131 may also be positioned to prevent electrical shorts between the thermocouples 127a, 127b and the heater coil 131.

[0121] Figure 3B According to one embodiment Figure 3A A top view of the heating element 112 is shown. Figure 3B In the embodiment of the present invention, the heating element 112 has a substantially circular top surface 129. Therefore, Figure 3A , Figure 3B The heating element 112 may have a substantially cylindrical shape. However, other shapes may be used without departing from the scope of the present disclosure. Figure 3A , Figure 3B A heating element 112 is provided.

[0122] exist Figure 3B In the view of FIG. 1 , the top thermocouple 127a is visible at the top surface 129 of the heating element 112. However, in practice, the top thermocouple 127a may not be visible because it may be positioned below the top surface 129. Figure 3B In the view of FIG. 1 , the heating coil 130 and the electrical connector 116 are illustrated in phantom, indicating that they are positioned below the top surface 129 of the heating element 112. The bottom thermocouple 127b is not visible because Figure 3A , Figure 3B In the example of , it is positioned directly below the top thermocouple 127a. Other shapes and configurations of the heating element 112 may be utilized without departing from the scope of the present disclosure.

[0123] Figure 4A 1 is a top view of wafer 104 according to one embodiment. Wafer 104 has a plurality of pad locations 134. Pad locations 134 may correspond to connection pads of integrated circuits to be cut from wafer 104. When packaging the integrated circuit, wire bonds may be coupled between the pads and the leads on the lead frame. During the wire bonding process, the pad locations may be heated due to welding or other bonding processes. If moisture is present in any of the layers of wafer 104 at pad location 134, the moisture may evaporate. Steam may eject from the layer and damage the pad location or wire bonds.

[0124] Figure 4B is a cross-sectional view of a pad site 134 of a wafer 104 according to one embodiment. The pad site 134 includes a copper pad 133 and a passivation layer 139. A tantalum or tantalum nitride barrier layer 137 is positioned on the copper pad 133 and on the passivation layer 139. An aluminum layer 135 is positioned on the barrier layer 137. The passivation layer 139 has been etched over the copper pad 133 to form a trench or hole 141. As described above, if moisture is present during the wire bonding process at the pad site 134, the moisture may become vapor and eject in a process known as degassing. The ejection of vapor may produce an extrusion 143 in the layer 135. The extrusion 143 is undesirable and may cause the wire bonding process to fail. About Figure 4B The materials and structures shown are given by way of non-limiting examples. Other materials may be used for the pad area 134 without departing from the scope of the present disclosure.

[0125] Figure 4CFIG. 1 is a top view of a wafer support 108 according to one embodiment. The wafer support 108 can reduce or prevent degassing problems and avoid the following problems: Figure 4A , Figure 4B The extrusion 143 is generally produced as described. In particular, during the formation of the pad location 134, the group 136 of heating elements 112 can be selectively operated at a higher temperature than the other heating elements 112. The group 136 of heating elements 112 corresponds to the group 136 of heating elements 112 positioned at Figure 4A 134. The pad site 134 is shown with a heating element 112 directly below it. In particular, the control circuit 110 can selectively control the group 136 of heating elements 112 at selected locations to heat to a relatively high temperature. The elevated temperature causes any moisture present to evaporate during the deposition process so that no moisture remains after the deposition process. This effectively degasses the pad site 134. When wire bonding is performed at the next stage after dicing, the pad site 134 has been degassed. The result is that gas will not be ejected and damage the pad site, for example by forming extrusions 143.

[0126] Figure 5A 1 is a cross-sectional view of a wafer 104 after a first thin film deposition process according to one embodiment. A first thin film 140 has been deposited on the wafer 104. Due to errors in the deposition process of the thin film 140, or due to design, the thin film 140 may have a non-uniform thickness. In particular, the thin film is thicker near the central area of ​​the wafer 104 and thinner near the peripheral area.

[0127] Figure 5B is a top view of a wafer support 108 according to one embodiment, the wafer support including a plurality of selectively operable heating elements 112. A control system 110 (see Figure 1 ) receives data indicating the uneven thickness of the thin film 140. Subsequently, the control system 110 selectively controls the respective groups of the heating elements 112 during the deposition process of the second thin film. In particular, during the deposition of the second thin film, the control system 110 selectively controls the first group 142 of the heating elements 112, the second group 144 of the heating elements 112, and the third group 146 of the heating elements 112.

[0128] In one embodiment, the control system 112 controls the first group 142 of the heating elements 112 to heat to a first temperature. The control system 112 controls the second group 144 of the heating elements 112 to heat to a second temperature greater than the first temperature. The control system 112 controls the third group 146 of the heating elements 112 to heat to a third temperature greater than the second temperature. In other words, the control system 110 controls the heating elements during the deposition process of the second film 112 to generate less heat at those areas where the first film 140 is thickest and more heat at those areas where the first film 142 is thinnest. The second film is deposited faster at those areas of the wafer 104 where it is hottest. The result is that the second film has a substantially flat top surface despite the uneven surface of the first film.

[0129] Figure 5C After the second film 148 is deposited on the first film 140, Figure 5A FIG. 1 is a cross-sectional view of a wafer 104 of FIG. 1. Although the thickness of the first film 140 is non-uniform, the second film 148 has a substantially flat top surface 149. This can be achieved without a separate planarization process by selectively controlling the heat output of a group of heating elements 112 or individual heating elements 112 during the second deposition process.

[0130] Fig. 6A A wafer support 108 is shown supporting the wafer 104 according to one embodiment. Fig. 6A Not shown, but the wafer support 108 may include Figures 1 to 5C The plurality of heating elements 112 are shown and described. The wafer support 108 is configured to hold the wafer 104 by electrostatic attraction. In particular, a voltage is applied between a top surface 122 of the wafer support 108 and a bottom surface 125 of the wafer 104. Fig. 6A In the example of FIG. 1 , positive charge accumulates at the top surface 122 of the wafer support 108. Negative charge accumulates at the bottom surface 125 of the wafer 104. As a result, the bottom surface 125 of the wafer 104 is attracted to the top surface 122 of the wafer support 108. The electrostatic attraction force holds the wafer 104 firmly in place on the top surface 122 of the wafer support 108. In alternative embodiments, negative charge may accumulate at the top surface 122 of the wafer support 108, while positive charge may accumulate at the bottom surface 125 of the wafer 104.

[0131] Despite Fig. 6A1 , but the wafer support 108 may include a layer of conductive material at or near the top of the wafer support 108. One or more electrical connectors may be coupled to the layer of conductive material so that a voltage may be applied to the layer of conductive material to generate an electrostatic charge on the top surface 122 of the wafer support 108. The wafer support 108 may also include a thin layer of dielectric material on top of the layer of conductive material.

[0132] The electrostatic forces holding the wafer 104 may also inhibit or prevent warping of the wafer 104 during semiconductor processing. In some cases, it may be that the edge of the wafer 104 tends to warp upward. However, the electrostatic forces prevent the edge of the wafer 104 from warping or otherwise deforming.

[0133] Figure 6B A wafer support 108 is illustrated supporting a wafer 104 according to one embodiment. The wafer support 108 includes clamps 150 that are selectively operable to clamp the wafer 104 to the wafer support 108 during semiconductor processing. The clamps 150 can be selectively placed in position to hold the wafer 104 and can be selectively removed to release the wafer 104. As described above, clamping the wafer 104 during semiconductor processing can help inhibit or prevent warping of the wafer 104. Although in Figure 6B Although not shown, the wafer support 108 may include Figures 1 to 5B A plurality of selectively operable heating elements 112 are shown and described.

[0134] Embodiments of the present disclosure provide many benefits over conventional semiconductor processing systems. Embodiments of the present disclosure provide a wafer support having an array of selectively operable heating elements. These heating elements can be operated to provide a uniform temperature distribution over the surface of a wafer supported by the wafer support. The heating elements can be operated to heat selected areas of the wafer more than other areas. As a result, semiconductor processing can be performed more reliably and with better results. Films can have uniform thickness. Pad locations can be selectively degassed to prevent damage to the wafer. Selectively operable heating elements can also produce many other benefits.

[0135] Figure 7 is a flow chart of a method 700 for performing semiconductor processing. At 702, method 700 includes supporting a semiconductor wafer with a wafer support positioned within a semiconductor processing chamber. An example of a semiconductor wafer is Figure 1 A semiconductor wafer 104 is provided. An example of a wafer support is Figure 1 An example of a semiconductor processing chamber is Figure 1At 704, the method 700 includes performing semiconductor processing on a semiconductor wafer in the semiconductor processing chamber. At 706, the method includes heating the semiconductor wafer with a plurality of heating elements positioned within a wafer support during semiconductor processing. An example of a heating element is Figure 1 At 708, method 700 includes generating a first sensor signal for each heating element using a corresponding first temperature sensor positioned within the wafer support. An example of a temperature sensor is Figure 1 At 710, method 700 includes selectively controlling each heating element using a control system in response to the first sensor signal. An example of a control system is Figure 1 A control system 110 is provided.

[0136] In one embodiment, a wafer support includes a top surface configured to support a semiconductor wafer, and an array of heating elements positioned below the top surface and configured to output heat. The wafer support includes a temperature sensor array including a respective first temperature sensor for each heating element, the respective first temperature sensor configured to generate a first sensor signal. The wafer support includes a plurality of first electrical connectors coupled to the heating elements and configured to enable selective control of the respective heating elements. The wafer support includes a plurality of second electrical connectors coupled to the first temperature sensors.

[0137] In one embodiment, a semiconductor processing system includes a semiconductor processing chamber and a wafer support positioned in the semiconductor processing chamber and configured to support a semiconductor wafer. The wafer support includes an array of heating elements, each of the heating elements being configured to heat the semiconductor wafer when the semiconductor wafer is positioned on the wafer support. The wafer support includes an array of temperature sensors, the array of temperature sensors including a respective first temperature sensor for each heating element, the respective first temperature sensor being configured to generate a first sensor signal. The semiconductor processing system includes a control system communicatively coupled to the heating elements and the first temperature sensors, and configured to selectively operate the respective heating elements at least partially in response to the first sensor signals.

[0138] In one embodiment, a method includes supporting a semiconductor wafer with a wafer support positioned within a semiconductor processing chamber; performing semiconductor processing on the semiconductor wafer within the semiconductor processing chamber; and heating the semiconductor wafer with a plurality of heating elements positioned within the wafer support during semiconductor processing. The method includes generating a first sensor signal for each heating element with a corresponding first temperature sensor positioned within the wafer support; and selectively controlling the respective heating elements with a control system in response to the first sensor signals.

[0139] Embodiments of the present disclosure provide many benefits over conventional semiconductor processing systems. Embodiments of the present disclosure provide a wafer support having an array of selectively operable heating elements. These heating elements can be operated to provide a uniform temperature distribution over the surface of a wafer supported by the wafer support. The heating elements can be operated to heat selected areas of the wafer more than other areas. As a result, semiconductor processing can be performed more reliably and with better results. Films can have uniform thickness. The pad portion of the wafer can be selectively degassed to prevent damage to the wafer. Selectively operable heating elements can also produce many other benefits.

[0140] The various embodiments described above can be combined to provide other embodiments. If necessary, the various aspects of the embodiments can be modified to adopt the concepts of various patents, applications and publications to provide other embodiments.

[0141] These and other changes may be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents granted by such claims. Therefore, the claims are not limited by the present disclosure.

[0142] In one embodiment of the present disclosure, a semiconductor processing system includes a wafer support. The wafer support includes a top surface, an array of multiple heating elements, an array of multiple temperature sensors, multiple first electrical connectors, and multiple second electrical connectors. The top surface is configured to support a semiconductor wafer. The array of multiple heating elements is positioned below the top surface and is configured to output heat. The array of multiple temperature sensors includes a corresponding first temperature sensor relative to each heating element, and the corresponding first temperature sensor is configured to generate multiple first sensor signals. Multiple first electrical connectors are coupled to these heating elements and are configured to be able to selectively control each heating element. Multiple second electrical connectors are coupled to the corresponding first temperature sensors. In one or more of the above and following embodiments, each heating element includes a corresponding heating coil. In one or more of the above and following embodiments, the array of these temperature sensors includes a corresponding second temperature sensor relative to each heating element, and the corresponding second temperature sensor is configured to generate multiple second sensor signals. In one or more of the above and following embodiments, for each heating element, the corresponding first temperature sensor is positioned below the corresponding second temperature sensor. In one or more of the above and following embodiments, for each heating element, the first sensor signals indicate the temperature of the heating coil. In one or more of the above and following embodiments, for each heating element, the second sensor signals indicate the temperature of the area of ​​the semiconductor wafer above the heating element. In one or more of the above and following embodiments, each heating element includes a ceramic material that covers the heating coil. In one or more of the above and following embodiments, the ceramic material covers the corresponding first temperature sensor and the corresponding second temperature sensor. In one or more of the above and following embodiments, the semiconductor processing system further includes a conductive material that is configured to hold the semiconductor wafer in place via electrostatic force. In one or more of the above and following embodiments, the semiconductor processing system further includes a fixture that is configured to hold the semiconductor wafer in place. In one or more of the above and following embodiments, the corresponding first temperature sensor includes a thermocouple.

[0143] In another embodiment of the present disclosure, a semiconductor processing system includes a semiconductor processing chamber, a wafer support, and a control system. The wafer support is positioned in the semiconductor processing chamber and is configured to support a semiconductor wafer, and the wafer support includes an array of multiple heating elements and an array of multiple temperature sensors. Each heating element is configured to heat the semiconductor wafer when the semiconductor wafer is positioned on the wafer support. The array of multiple temperature sensors includes a corresponding first temperature sensor relative to each heating element, and the corresponding first temperature sensor is configured to generate a plurality of first sensor signals. The control system is communicatively coupled to the heating elements and the corresponding first temperature sensors, and is configured to selectively operate each heating element in response to at least partially the first sensor signals. In one or more of the above and following embodiments, the control system is configured to operate the heating elements to generate a uniform temperature distribution on the surface of the semiconductor wafer. In one or more of the above and following embodiments, the control system is configured to operate the heating elements to selectively heat some areas of the semiconductor wafer more than other areas. In one or more of the above and following embodiments, the semiconductor processing system further includes a semiconductor processing device that is communicatively coupled to a control system and is configured to perform semiconductor processing on a semiconductor wafer in a semiconductor processing chamber, wherein the control system is configured to adjust the semiconductor processing device in response to the first sensor signals. In one or more of the above and following embodiments, the array of temperature sensors includes a corresponding second temperature sensor relative to each heating element, and the corresponding second temperature sensor is configured to generate a plurality of second sensor signals. In one or more of the above and following embodiments, for each heating element, the first sensor signals indicate a temperature of the heating elements, wherein the second sensor signals indicate a temperature of a semiconductor wafer region above the heating elements.

[0144] In one embodiment of the present disclosure, a semiconductor processing method includes supporting a semiconductor wafer with a wafer support positioned in a semiconductor processing chamber. Performing semiconductor processing on the wafer in the semiconductor processing chamber. Heating the semiconductor wafer with multiple heating elements positioned in the wafer support during semiconductor processing. Using corresponding first temperature sensors positioned in the wafer support to generate multiple first sensor signals for each heating element. In response to these first sensor signals, the heating elements are selectively controlled using a control system. In one or more of the above and following embodiments, the semiconductor processing method also includes using corresponding second temperature sensors positioned in the wafer support to generate multiple second sensor signals for each heating element. And, in response to these second sensor signals, each heating element is selectively controlled using a control system. In one or more of the above and following embodiments, the semiconductor processing method also includes using a control system to adjust the semiconductor processing in response to these first sensor signals.

Claims

1. A wafer support, characterized in that: include: a top surface configured to support a semiconductor wafer; an array of a plurality of heating elements positioned below the top surface and configured to output heat, each heating element comprising a respective heating coil; an array of a plurality of temperature sensors, including a respective first temperature sensor and a respective second temperature sensor relative to each of the heating elements, the respective first temperature sensor being configured to generate a plurality of first sensor signals indicating a temperature of the respective heating coil, the respective second temperature sensor being disposed above the respective heating coil, the respective second temperature sensor being configured to generate a plurality of second sensor signals indicating a temperature of a region of the semiconductor wafer above the respective heating coil; a plurality of first electrical connectors coupled to the plurality of heating elements and configured to selectively control each of the heating elements; as well as A plurality of second electrical connectors are coupled to the corresponding first temperature sensors.

2. The wafer support according to claim 1, characterized in that: The respective second temperature sensor comprises a thermocouple.

3. The wafer support as claimed in claim 1, characterized in that: When the semiconductor wafer is placed on the wafer support, a bottom surface of the semiconductor wafer contacts the top surface of the wafer support, and the corresponding second temperature sensor directly contacts the bottom surface of the semiconductor wafer.

4. The wafer support according to claim 1, wherein: For each of the heating elements, the corresponding first temperature sensor is positioned below the corresponding second temperature sensor.

5. The wafer support as claimed in claim 1, characterized in that: The respective second temperature sensor is positioned below the top surface of the wafer support.

6. The wafer support according to claim 5, characterized in that: Also included is a layer of thermally conductive material disposed on top of the array of the plurality of heating elements.

7. The wafer support according to claim 6, characterized in that: Each of the heating elements comprises a ceramic material, and the ceramic material covers the heating coil.

8. The wafer support according to claim 7, characterized in that: The ceramic material covers the corresponding first temperature sensor and the corresponding second temperature sensor.

9. The wafer support according to claim 1, wherein: Also included is a conductive material configured to hold the semiconductor wafer in place via electrostatic forces.

10. The wafer support according to claim 1, wherein: Also included is a clamp configured to hold the semiconductor wafer in place.

11. The wafer support according to claim 1, wherein: The respective first temperature sensor comprises a thermocouple.

12. A semiconductor processing system, characterized in that: include: a semiconductor processing chamber; A wafer support positioned in the semiconductor processing chamber and configured to support a semiconductor wafer, the wafer support comprising: an array of a plurality of heating elements, each heating element configured to heat the semiconductor wafer when the semiconductor wafer is positioned on the wafer support, each heating element comprising a respective heating coil; and an array of a plurality of temperature sensors, including a respective first temperature sensor and a respective second temperature sensor relative to each of the heating elements, the respective first temperature sensor being configured to generate a plurality of first sensor signals indicating a temperature of the respective heating coil, the respective second temperature sensor being disposed above the respective heating coil, the respective second temperature sensor being configured to generate a plurality of second sensor signals indicating a temperature of a region of the semiconductor wafer above the respective heating coil; and A control system is communicatively coupled to the plurality of heating elements and the respective first temperature sensors and is configured to selectively operate each of the heating elements at least in part in response to the plurality of first sensor signals.

13. The semiconductor processing system of claim 12, wherein: The control system is configured to operate the plurality of heating elements to generate a uniform temperature distribution on a surface of the semiconductor wafer.

14. The semiconductor processing system of claim 12, wherein: The control system is configured to operate the plurality of heating elements to selectively heat some regions of the semiconductor wafer more than other regions.

15. The semiconductor processing system of claim 12, wherein: Further included is a semiconductor processing device communicatively coupled to the control system and configured to perform a semiconductor process on the semiconductor wafer within the semiconductor processing chamber, wherein the control system is configured to adjust the semiconductor processing device in response to the plurality of first sensor signals.

16. The semiconductor processing system of claim 12, wherein: When the semiconductor wafer is placed on the wafer support, a bottom surface of the semiconductor wafer contacts the top surface of the wafer support, and the corresponding second temperature sensor directly contacts the bottom surface of the semiconductor wafer.

17. The semiconductor processing system of claim 16, wherein: The respective second temperature sensor is positioned below the top surface of the wafer support.

18. A semiconductor processing method, characterized in that: The following steps are involved: Supporting a semiconductor wafer with a wafer support positioned within a semiconductor processing chamber; performing a semiconductor process on the wafer in the semiconductor processing chamber; heating the semiconductor wafer during the semiconductor processing with a plurality of heating elements positioned within the wafer support, each of the heating elements comprising a respective heating coil; generating a plurality of first sensor signals for each of the heating elements using a respective first temperature sensor positioned within the wafer support and generating a plurality of second sensor signals indicative of a temperature of a region of the wafer above the respective heating coil using a respective second temperature sensor positioned within the wafer support and located at the respective heating coil; as well as In response to the first sensor signals, a control system is used to selectively control the heating elements.

19. The semiconductor processing method according to claim 18, wherein: The following steps are also included: In response to the plurality of second sensor signals, the control system is used to selectively control each of the heating elements.

20. The semiconductor processing method according to claim 18, wherein: Also included is regulating the semiconductor process using the control system in response to the plurality of first sensor signals.

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