Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate; forming an amorphous silicon material layer on the substrate at a first preset deposition temperature, the amorphous silicon material layer being used to form a pseudo gate structure or a core layer, the first preset deposition temperature being lower than the crystallization temperature of amorphous silicon; etching the amorphous silicon material layer to form an amorphous silicon layer, the amorphous silicon layer being used as a pseudo gate structure or a core layer. The present invention reduces the probability of amorphous silicon crystallizing during the formation of the amorphous silicon material layer by making the first preset deposition temperature lower than the crystallization temperature of amorphous silicon, and is not easy to convert amorphous silicon into polycrystalline silicon. Accordingly, when the amorphous silicon material layer is subsequently etched, it is beneficial to improve the etching rate and the uniformity of the etching effect, thereby reducing the line edge roughness of the amorphous silicon layer, wherein the amorphous silicon layer is used as a pseudo gate structure or a core layer. Therefore, improving the line edge roughness of the amorphous silicon layer is beneficial to improving the performance of the semiconductor structure accordingly.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the semiconductor integrated circuit manufacturing process, a series of processes are used, such as deposition, photolithography, etching and planarization, to form a semiconductor structure. Among them, photolithography and etching are the main graphic methods in the semiconductor manufacturing process.

[0003] The photolithography process usually forms a photosensitive material layer (for example, a photoresist layer) on a substrate, and then transfers the pattern on the mask to the photosensitive material layer through exposure, thereby forming a pattern in the photosensitive material layer to form a patterned mask layer to define the area to be etched; and the etching process usually uses the mask layer as a mask to etch the area to be etched in the layer to be etched, thereby transferring the pattern in the mask layer to the layer to be etched, and then forming the desired structure in the layer to be etched.

[0004] With the continuous development of ultra-large integrated circuits, the critical dimension (CD) of semiconductor devices continues to decrease. As the critical dimension becomes smaller and smaller, how to improve the accuracy and stability of pattern transfer has become a research hotspot in the industry. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an amorphous silicon material layer on the substrate at a first preset deposition temperature, wherein the amorphous silicon material layer is used to form a pseudo gate structure or a core layer, and the first preset deposition temperature is lower than the crystallization temperature of amorphous silicon; etching the amorphous silicon material layer to form an amorphous silicon layer, wherein the amorphous silicon layer is used as a pseudo gate structure or a core layer.

[0007] Optionally, the amorphous silicon material layer is used to form a core layer; in the step of etching the amorphous silicon material layer to form an amorphous silicon layer, the amorphous silicon layer is used as the core layer; after forming the core layer, the formation method further includes: forming a mask side wall on the side wall of the core layer; after forming the mask side wall, removing the core layer; after removing the core layer, etching the substrate using the mask side wall as a mask, transferring the pattern of the mask side wall to the substrate, forming a substrate and a fin protruding from the substrate.

[0008] Optionally, the step of forming a mask sidewall on the sidewall of the core layer includes: forming a mask material layer conformally covering the core layer and the substrate at a second preset deposition temperature, wherein the second preset deposition temperature is lower than the crystallization temperature of amorphous silicon; removing the mask material layer located on the top of the core layer and on the substrate, and retaining the remaining mask material layer located on the sidewall of the core layer as a mask sidewall.

[0009] Optionally, the amorphous silicon material layer is used to form a pseudo gate structure; after forming the amorphous silicon material layer on the substrate at a first preset deposition temperature and before etching the amorphous silicon material layer, the formation method also includes: forming a discrete core layer on the amorphous silicon material layer; forming mask side walls on the side walls of the core layer; after forming the mask side walls, removing the core layer; the step of etching the amorphous silicon material layer includes: after removing the core layer, etching the amorphous silicon material layer using the mask side walls as a mask to form an amorphous silicon layer, and the amorphous silicon layer is used as a pseudo gate structure.

[0010] Optionally, the step of forming a mask sidewall on the sidewall of the core layer includes: forming a mask material layer that conformally covers the core layer and the amorphous silicon material layer at a second preset deposition temperature, wherein the second preset deposition temperature is lower than the crystallization temperature of amorphous silicon; removing the mask material layer located on the top of the core layer and the amorphous silicon material layer, and retaining the remaining mask material layer located on the sidewall of the core layer as a mask sidewall.

[0011] Optionally, the step of forming a discrete core layer on the amorphous silicon material layer includes: forming a core material layer on the amorphous silicon material layer at a third preset deposition temperature, wherein the third preset deposition temperature is lower than the crystallization temperature of amorphous silicon; and etching the core material layer to form a discrete core layer.

[0012] Optionally, a furnace tube process is used to form an amorphous silicon material layer on the substrate.

[0013] Optionally, the mask material layer is formed by an atomic layer deposition process.

[0014] Optionally, a furnace tube process is adopted to form the core material layer.

[0015] Optionally, the first preset deposition temperature is less than or equal to 510 degrees Celsius.

[0016] Optionally, the first preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius.

[0017] Optionally, the second preset deposition temperature is less than or equal to 510 degrees Celsius.

[0018] Optionally, the second preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius.

[0019] Optionally, the third preset deposition temperature is less than or equal to 510 degrees Celsius.

[0020] Optionally, the third preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius.

[0021] Optionally, the material of the mask sidewalls includes silicon nitride, silicon oxynitride, silicon carbide or silicon carbon oxynitride.

[0022] Optionally, the material of the core layer includes amorphous silicon.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] In the technical solution of the method for forming a semiconductor structure provided by an embodiment of the present invention, an amorphous silicon material layer is formed on a substrate at a first preset deposition temperature, and the amorphous silicon material layer is used to form a pseudo gate structure or a core layer, and the first preset deposition temperature is lower than the crystallization temperature of amorphous silicon; by making the first preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of amorphous silicon in the process of forming the amorphous silicon material layer can be reduced, and it is not easy to convert amorphous silicon into polycrystalline silicon, that is, it is beneficial to keep the material state of the amorphous silicon material layer in an amorphous state, and accordingly, when the amorphous silicon material layer is subsequently etched, it is beneficial to improve the uniformity of the etching rate and the uniformity of the etching effect, thereby reducing the line edge roughness (LER) of the amorphous silicon layer, wherein the amorphous silicon layer is used as a pseudo gate structure or a core layer, therefore, improving the line edge roughness of the amorphous silicon layer is correspondingly beneficial to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 6 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0026] Figures 7 to 16 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0027] As the characteristic size of MOSFET continues to decrease, high-k metal gate (HKMG) technology is widely used in semiconductor manufacturing processes, and HKMG technology usually adopts a gate last process. In the gate last process, a dummy gate structure is usually formed first to occupy the position of the metal gate structure, and then the dummy gate structure is replaced by the metal gate structure. Among them, the material of the dummy gate structure is usually polysilicon, and the process of forming the dummy gate structure usually includes the steps of forming a polysilicon material layer and etching the polysilicon material layer.

[0028] However, in the polysilicon material layer, the polysilicon material has a variety of crystal orientations, including <100> Crystal direction, <110> Crystal orientation and <111> Crystal orientation. Polysilicon with different crystal orientations has different etching rates. <100> The etching rate of polysilicon in the crystal direction is the highest. <111> The etching rate of polysilicon in the crystal direction is the lowest.

[0029] Therefore, in the step of etching the polysilicon material layer, the uniformity of the etching rate and the uniformity of the etching effect of the polysilicon material layer are both poor, resulting in poor line edge roughness of the pseudo-gate structure, which in turn affects the line edge roughness of the metal gate structure, and correspondingly leads to a decrease in the performance of the semiconductor structure. Moreover, the increase in the line edge roughness of the metal gate structure is also likely to increase the probability of short circuit between the conductive plug connected to the source and drain doping regions and the metal gate structure, which will correspondingly lead to a decrease in the yield of the semiconductor structure. Among them, as the characteristic size of MOSFET continues to decrease, the impact of the line edge roughness problem on the performance of the semiconductor structure becomes more obvious.

[0030] In order to improve the above problems, a current solution is to use amorphous silicon material to form a pseudo gate structure. Compared with polycrystalline silicon material with multiple crystal orientations, amorphous silicon material has no crystal orientation. Therefore, the etching rate uniformity and etching effect uniformity of amorphous silicon material are better.

[0031] However, after adopting amorphous silicon material, the line edge roughness of the dummy gate structure is still poor. According to research, in the process of forming the amorphous silicon material layer, when the temperature reaches its crystallization temperature, amorphous silicon is easy to crystallize and thus transform into polycrystalline silicon. Therefore, even if the dummy gate structure adopts amorphous silicon material, it is still difficult to improve the problem of poor line edge roughness of the dummy gate structure.

[0032] Adjusting the process parameters of the etching process is another optimization method. However, adjusting the process parameters of the etching process will affect the overall morphology of the pseudo gate structure and cannot achieve local correction, which can easily lead to undercut problems in the pseudo gate structure. Therefore, it is also difficult to improve the problem of poor line edge roughness by optimizing the etching process.

[0033] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming an amorphous silicon material layer on the substrate at a first preset deposition temperature, the amorphous silicon material layer being used to form a pseudo gate structure or a core layer, the first preset deposition temperature being lower than the crystallization temperature of amorphous silicon; etching the amorphous silicon material layer to form an amorphous silicon layer, the amorphous silicon layer being used as a pseudo gate structure or a core layer.

[0034] In an embodiment of the present invention, an amorphous silicon material layer is formed on a substrate at a first preset deposition temperature, and the amorphous silicon material layer is used to form a pseudo gate structure or a core layer. The first preset deposition temperature is lower than the crystallization temperature of amorphous silicon. By making the first preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of amorphous silicon in the process of forming the amorphous silicon material layer can be reduced, and it is not easy to convert amorphous silicon into polycrystalline silicon, that is, it is beneficial to keep the material state of the amorphous silicon material layer in an amorphous state. Accordingly, when the amorphous silicon material layer is subsequently etched, it is beneficial to improve the uniformity of the etching rate and the uniformity of the etching effect, thereby improving the line edge roughness of the amorphous silicon layer, wherein the amorphous silicon layer is used as a pseudo gate structure or a core layer. Therefore, improving the line edge roughness of the amorphous silicon layer is correspondingly beneficial to improving the performance of the semiconductor structure.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0037] refer to Figure 1 , providing a substrate 100.

[0038] The substrate 100 is used as a layer to be etched. In this embodiment, the substrate 100 is used to form a substrate and a fin located on the substrate.

[0039] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate.

[0040] In some further embodiments, the substrate may further include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, wherein the first semiconductor layer is used to provide a process basis for subsequent formation of a substrate, and the second semiconductor layer is used to provide a process basis for subsequent formation of a fin.

[0041] It should be noted that the forming method further includes: forming a hard mask material layer 110 on the substrate 100 ; and forming an etch stop layer 115 on the hard mask material layer 110 .

[0042] The hard mask material layer 110 is used to form a hard mask layer through a subsequent etching process, and the hard mask layer is used as a mask for etching the substrate 100. Moreover, in a subsequent grinding process for forming an isolation structure (STI), the top of the hard mask layer is used to define a stop position of the grinding process.

[0043] In this embodiment, the material of the hard mask material layer 110 is silicon nitride.

[0044] The subsequent process also includes forming a core layer on the etch stop layer 115. The process of forming the core layer generally includes a deposition step and an etching step. During the etching process, the top surface of the etch stop layer 115 is used to define the stop position of the etching process, thereby protecting the hard mask material layer 110, thereby reducing the probability of the top surface height inconsistency of the hard mask material layer 110, so that the height and morphology of the target pattern formed subsequently can meet the process requirements. In addition, the mask sidewalls formed on the sidewalls of the core layer are also formed by a process combining deposition and etching. During the process of forming the mask sidewalls, the top surface of the etch stop layer 115 can also define the stop position of the etching process.

[0045] In this embodiment, the material of the etch stop layer 115 is silicon oxide.

[0046] In this embodiment, a chemical vapor deposition process is used to form the hard mask material layer 110 and the etch stop layer 115. The process temperature of the chemical vapor deposition process is relatively low, for example, 100 degrees Celsius to 200 degrees Celsius.

[0047] Continue to refer Figure 1 An amorphous silicon material layer 200 is formed on the substrate 100 at a first preset deposition temperature, wherein the amorphous silicon material layer 200 is used to form a core layer. The first preset deposition temperature is lower than the crystallization temperature of amorphous silicon.

[0048] The amorphous silicon material layer 200 is used to form a core layer after a subsequent etching process.

[0049] By making the first preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of amorphous silicon in the process of forming the amorphous silicon material layer 200 can be reduced, and it is not easy to convert amorphous silicon into polycrystalline silicon, that is, it is beneficial to keep the material state of the amorphous silicon material layer 200 in an amorphous state. The amorphous silicon material does not have a crystal orientation. Accordingly, when the amorphous silicon material layer 200 is subsequently etched to form a core layer, it is beneficial to improve the uniformity of the etching rate and the uniformity of the etching effect, thereby reducing the line edge roughness of the core layer, thereby improving the quality of subsequent graphic transfer, and correspondingly improving the performance of the semiconductor structure.

[0050] In this embodiment, a furnace tube process is adopted to form the amorphous silicon material layer 200 on the substrate 100 .

[0051] The process temperature of the furnace tube process is relatively high, which is beneficial to increasing the deposition rate of the amorphous silicon material layer 200 , thereby improving the manufacturing efficiency. Moreover, the process time of the furnace tube process is also relatively long.

[0052] Increasing the first preset deposition temperature is conducive to increasing the deposition rate of amorphous silicon. When the temperature is higher than 550 degrees Celsius, the probability of amorphous silicon crystallizing becomes higher. Therefore, the first preset deposition temperature is less than or equal to 510 degrees Celsius to significantly reduce the probability of amorphous silicon crystallizing.

[0053] However, when the first preset deposition temperature is too low, it is easy to cause the amorphous silicon material layer 200 to fail to form, thereby reducing the film quality of the amorphous silicon material layer 200, or, when other process parameters are constant, it is easy to cause the thickness of the amorphous silicon material layer 200 to be difficult to reach the preset value. In order to make the thickness of the amorphous silicon material layer 200 reach the preset value, the process time needs to be increased accordingly. At the same temperature, the longer the process time, the higher the probability of crystallization of amorphous silicon.

[0054] To this end, in this embodiment, the first preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius, so that the film quality and thickness of the amorphous silicon material layer 200 can meet the process requirements and reduce the probability of crystallization of amorphous silicon.

[0055] Combined with reference Figure 1 and Figure 2 , etching the amorphous silicon material layer 200 (such as Figure 1 As shown), an amorphous silicon layer 210 is formed, and the amorphous silicon layer 210 is used as a core layer.

[0056] In this embodiment, the fin is formed by a self-aligned double patterning (SADP) process, and the core layer is used to provide a process basis for the subsequent formation of a mask sidewall, and the core layer is used to define the interval between adjacent fins. The mask sidewall is used to define the shape, position and size of the fin.

[0057] Specifically, the steps of forming the amorphous silicon layer 210 include: Figure 1 As shown, a mask stack (not shown) is formed on the amorphous silicon material layer 200, and the mask stack includes a bottom anti-reflective coating (BARC) layer 300 covering the amorphous silicon material layer 200, and a photoresist layer 310 located on the bottom anti-reflective coating 300; Figure 2 As shown, using the photoresist layer 310 as a mask, the bottom anti-reflective coating 300 and the amorphous silicon material layer 200 are sequentially etched to pattern the amorphous silicon material layer 200 into an amorphous silicon layer 210; after forming the amorphous silicon layer 210, the remaining mask stack is removed.

[0058] The bottom anti-reflection coating 300 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern.

[0059] In this embodiment, the core layer is formed by etching the amorphous silicon material layer 200 , which is beneficial to improving the verticality of the sidewall of the core layer.

[0060] It should be noted that the forming method is used to form a fin portion, so after forming the core layer, the forming method further includes:

[0061] Combined with reference Figure 3 and Figure 4 , a mask sidewall 230 (such as Figure 4 shown).

[0062] The mask spacer 230 is used as a mask for etching the substrate 100 .

[0063] The core layer needs to be removed later, so there is a high etching selectivity ratio between the core layer and the mask sidewall 230 , thereby reducing the probability of damage to the mask sidewall 230 during the process of removing the core layer.

[0064] Therefore, the material of the mask sidewall 230 is selected such that in the step of removing the core layer, the etching selectivity ratio between the core layer and the mask sidewall 230 is greater than or equal to 3:1. Specifically, the etching selectivity ratio between the core layer and the mask sidewall 230 is greater than or equal to 5:1.

[0065] In this embodiment, the material of the mask sidewall 230 is silicon nitride. Amorphous silicon and silicon nitride have relatively high etching selectivity, and silicon and silicon nitride have relatively high etching selectivity, so that the pattern of the mask sidewall 230 can be better transferred to the substrate 100.

[0066] In other embodiments, the material of the mask sidewalls may also be other suitable materials such as silicon oxynitride, silicon carbide, or carbon oxynitride silicon.

[0067] Specifically, the steps of forming the mask sidewall 230 include: Figure 3 As shown, a mask material layer 220 conformally covering the core layer (ie, amorphous silicon layer 210) and the hard mask material layer 110 is formed at a second preset deposition temperature, wherein the second preset deposition temperature is lower than the crystallization temperature of amorphous silicon; Figure 4 As shown, the mask material layer 220 located on the top of the core layer and the hard mask material layer 110 is removed, and the remaining mask material layer 220 located on the sidewall of the core layer is retained as a mask spacer 230 .

[0068] In this embodiment, the mask material layer 220 is formed by using an atomic layer deposition process.

[0069] The atomic layer deposition process is usually used for atomic-scale controllable thin film growth. This process forms a thin film by depositing a single atomic layer layer by layer, which is beneficial to improving the control accuracy of the thickness of the mask material layer 220 and the thickness uniformity of the mask material layer 220. In addition, this process has strong gap filling ability and step coverage ability, which is beneficial to improving the coverage effect of the mask material layer 220 on the core layer and the hard mask material layer 110.

[0070] Among them, since the atomic layer deposition process forms a thin film by depositing a single atomic layer layer by layer, the atomic layer deposition process includes multiple cycle processes, and therefore, the process time of the atomic layer deposition process is usually relatively long.

[0071] The mask material layer 220 is deposited on the amorphous silicon layer 210. During the process of forming the mask material layer 220, the amorphous silicon layer 210 is also located in the deposition chamber. Under the action of heat conduction, the second preset deposition temperature will also affect the amorphous silicon layer 210. Since the process time of the atomic layer deposition process is usually long, at the same temperature, the longer the process time, the higher the probability of crystallization of amorphous silicon. When the second preset deposition temperature is too high, it is also easy to cause crystallization of amorphous silicon. Therefore, by making the second preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of amorphous silicon can be further reduced.

[0072] Similarly, increasing the second preset deposition temperature is beneficial to increasing the deposition rate of the mask material layer 220. When the temperature is higher than 550 degrees Celsius, the probability of amorphous silicon crystallizing becomes higher. Therefore, the second preset deposition temperature is less than or equal to 510 degrees Celsius to reduce the probability of amorphous silicon crystallizing.

[0073] However, when the second preset deposition temperature is too low, the mask material layer 220 may fail to be formed, thereby reducing the film quality of the mask material layer 220 and causing the thickness of the mask material layer 220 to be difficult to reach the preset value, thereby affecting the morphology and size of the subsequently formed fins. Alternatively, in order to make the thickness of the mask material layer 220 reach the preset value, the process time needs to be increased accordingly. At the same temperature, the longer the process time, the higher the probability of crystallization of amorphous silicon.

[0074] In this embodiment, the second preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius, so that the film quality and thickness of the mask material layer 220 can meet the process requirements and reduce the probability of crystallization of amorphous silicon.

[0075] In this embodiment, an anisotropic maskless etching process is used to form the mask sidewall 230, so that the mask material layer 220 on the top of the core layer and the hard mask material layer 110 can be removed, and the mask material layer 220 on the sidewall of the core layer is retained.

[0076] Specifically, the anisotropic maskless etching process is a dry etching process.

[0077] refer to Figure 5 After forming the mask sidewall 230, the core layer (ie, the amorphous silicon layer 210) is removed (eg Figure 4 shown).

[0078] By removing the core layer, preparation is made for etching the substrate 100 using the mask sidewall 230 as a mask.

[0079] In this embodiment, a dry etching process (such as an anisotropic dry etching process) is used to etch and remove the core layer. During the dry etching process, a polymer is formed on the sidewall of the mask sidewall 230, and the polymer can protect the mask sidewall 230, thereby reducing damage to the mask sidewall 230, and further helping to reduce the line edge roughness of the mask sidewall 230.

[0080] refer to Figure 6 , remove the core layer (ie, the amorphous silicon layer 210) (eg Figure 4 After that, the substrate 100 is etched using the mask sidewall 230 as a mask (as shown in FIG. Figure 5 As shown), a substrate 130 and a fin 140 protruding from the substrate 130 are formed.

[0081] Specifically, the steps of forming a substrate 130 and a fin 140 protruding from the substrate 130 include: using the mask sidewall 230 as a mask, etching the etch stop layer 115 and the hard mask material layer 110, and transferring the pattern of the mask sidewall 230 to the hard mask material layer 110 to form a hard mask layer 120; after forming the hard mask layer 120, using the hard mask layer 120 as a mask, continuing to etch the base 100, and the remaining base 100 after etching serves as the substrate 130, and the protrusion located on the substrate 130 serves as the fin 140.

[0082] It should be noted that the mask sidewalls 230 will be consumed during the etching of the hard mask material layer 110. After the hard mask layer 120 is formed, when there are still remaining mask sidewalls 230 on the hard mask layer 120, the remaining mask sidewalls 230 are retained, so that during the etching of the substrate 100, the remaining mask sidewalls 230 can continue to serve as etching masks, and the step of removing the mask sidewalls 230 separately is omitted.

[0083] In the process of etching the hard mask material layer 110 , the patterned etch stop layer 115 can still serve as an etching mask.

[0084] As an example, after the hard mask layer 120 is formed, the mask spacer 230 is removed.

[0085] In this embodiment, a dry etching process (for example, an anisotropic dry etching process) is used to etch the hard mask material layer 110 and the substrate 100. The dry etching process has an anisotropic etching characteristic, which is beneficial to improving the morphology quality of the fin 140. Moreover, during the dry etching process, by adjusting the etching gas and etching parameters, the etching stop layer 115, the hard mask material layer 110 and the substrate 100 can be sequentially etched in the same etching equipment, and the process is simple and does not require the conversion of the machine.

[0086] In this embodiment, after etching a portion of the thickness of the base 100 , the fin 140 and the substrate 130 are an integrated structure.

[0087] In other embodiments, when the substrate includes a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, in the step of etching the substrate, only the second semiconductor layer is etched, the first semiconductor layer is used as a substrate, and the remaining second semiconductor layer protruding from the first semiconductor layer is used as a fin. Accordingly, the material of the fin may also be different from that of the substrate.

[0088] Figures 7 to 16 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

[0089] The similarities between this embodiment and the above-mentioned embodiment are not repeated here. The difference between this embodiment and the above-mentioned embodiment is that: Figure 8 As shown, in the step of forming an amorphous silicon material layer 500 on a substrate (not shown), the amorphous silicon material layer 500 is used to form a dummy gate structure.

[0090] refer to Figure 7 , providing a substrate 400 (not shown).

[0091] In this embodiment, the formed semiconductor structure is a fin field effect transistor, so the base 400 includes a substrate 410 and a plurality of discrete fins 420 located on the substrate 410 .

[0092] In this embodiment, the substrate 410 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0093] In this embodiment, the fin 420 is an integral structure with the substrate 410. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of accurately controlling the height of the fin.

[0094] Therefore, in this embodiment, the material of the fin 420 is the same as the material of the substrate 410, and the material of the fin 420 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from the material of the substrate.

[0095] In some other embodiments, the method can also be used to form a gate-all-around (GAA) transistor or a planar transistor.

[0096] It should be noted that an isolation layer 401 is further formed on the substrate 410 where the fin 420 is exposed. The isolation layer 401 covers a portion of the sidewall of the fin 420 , and the top of the isolation layer 401 is lower than the top of the fin 420 .

[0097] The isolation layer 401 is used as a shallow trench isolation (STI) structure, and the isolation layer 401 is used to isolate adjacent transistors. In this embodiment, the material of the isolation layer 401 is silicon oxide. In other embodiments, the material of the isolation layer can also be other insulating materials such as silicon nitride or silicon oxynitride.

[0098] refer to Figure 8 An amorphous silicon material layer 500 is formed on the substrate 400 at a first preset deposition temperature, wherein the amorphous silicon material layer 500 is used to form a dummy gate structure. The first preset deposition temperature is lower than the crystallization temperature of amorphous silicon.

[0099] The amorphous silicon material layer 500 is used to form a dummy gate structure after a subsequent etching process, wherein the dummy gate structure is used to occupy a space position for the formation of a metal gate structure.

[0100] The material of the amorphous silicon material layer 500 is amorphous silicon. Since amorphous silicon has no crystal orientation, this correspondingly improves the uniformity of the etching rate and the uniformity of the etching effect; moreover, it also improves the subsequent etching rate of the amorphous silicon material layer 500, and correspondingly improves the manufacturing efficiency.

[0101] Among them, by making the first preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of amorphous silicon in the process of forming the amorphous silicon material layer 500 can be reduced, and it is not easy to convert amorphous silicon into polycrystalline silicon, that is, it is beneficial to keep the material state of the amorphous silicon material layer 500 in an amorphous state. Accordingly, when the amorphous silicon material layer 500 is subsequently etched to form a pseudo-gate structure, it is beneficial to improve the uniformity of the etching rate and the uniformity of the etching effect, thereby reducing the line edge roughness of the pseudo-gate structure, and correspondingly can reduce the line edge roughness of the metal gate structure, thereby improving the performance of the semiconductor structure.

[0102] Moreover, after the dummy gate structure is subsequently formed, the step of removing the dummy gate structure is also included, thereby forming a metal gate structure at the position of the dummy gate structure. Therefore, by maintaining the material state of the amorphous silicon material layer 500 in an amorphous state, the uniformity of the etching rate and the uniformity of the etching effect are improved, which is correspondingly beneficial to ensuring the removal effect and removal rate of the dummy gate structure, thereby reducing the problem of residual dummy gate structure, and further improving the performance of the semiconductor structure.

[0103] In this embodiment, a furnace tube process is adopted to form the amorphous silicon material layer 500 on the substrate 400 .

[0104] The process temperature of the furnace tube process is relatively high, which is beneficial to increasing the deposition rate of the amorphous silicon material layer 500 , thereby improving the manufacturing efficiency. Moreover, the process time of the furnace tube process is also relatively long.

[0105] Increasing the first preset deposition temperature is beneficial to increasing the deposition rate of amorphous silicon. When the temperature is higher than 550 degrees Celsius, the probability of amorphous silicon crystallizing becomes higher. Therefore, the first preset deposition temperature is less than or equal to 510 degrees Celsius to significantly reduce the probability of amorphous silicon crystallizing.

[0106] However, when the first preset deposition temperature is too low, it is easy to cause the amorphous silicon material layer 500 to fail to form, thereby reducing the film quality of the amorphous silicon material layer 500. Moreover, when other parameters such as process time are constant, it is easy to cause the thickness of the amorphous silicon material layer 500 to be difficult to reach the preset value. In order to make the thickness of the amorphous silicon material layer 500 reach the preset value, the process time needs to be increased accordingly. At the same temperature, the longer the process time, the higher the probability of crystallization of amorphous silicon.

[0107] To this end, in this embodiment, the first preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius, so that the film quality and thickness of the amorphous silicon material layer 500 can meet the process requirements and at the same time reduce the probability of crystallization of amorphous silicon.

[0108] Specifically, the amorphous silicon material layer 500 covers the fin 420 and the isolation layer 401 .

[0109] It should be noted that after forming the amorphous silicon material layer 500 , the forming method further includes: forming a hard mask material layer 510 on the amorphous silicon material layer 500 and an etch stop layer 520 located on the hard mask material layer 510 .

[0110] The hard mask material layer 510 is used to form a hard mask layer through a subsequent etching process. The hard mask layer is used as a mask for etching the amorphous silicon material layer 500 and is also used to protect the top of the dummy gate structure.

[0111] In this embodiment, the material of the hard mask material layer 510 is silicon nitride.

[0112] Subsequently, a separate core layer will be formed on the etch stop layer 520. The process of forming the core layer generally includes the steps of forming a core material layer and etching the core material layer. In the process of etching the core material layer, the top surface of the etch stop layer 520 is used to define the stop position of the etching process to avoid over-etching, thereby reducing the probability of inconsistent top surface height of the film layer to be etched below (for example, the hard mask material layer 510), so that the height and morphology of the target pattern formed subsequently can meet the process requirements. In addition, the mask sidewalls subsequently formed on the sidewalls of the core layer are formed by a process combining deposition and etching. In the process of forming the mask sidewalls, the top surface of the etch stop layer 520 can also define the stop position of the etching process. Among them, in the SADP process, the material selected for the mask sidewalls is generally silicon nitride.

[0113] Therefore, in this embodiment, the material of the etch stop layer 520 is silicon oxide.

[0114] The etching selectivity of amorphous silicon and silicon oxide is relatively high, and the etching selectivity of silicon nitride and silicon oxide is also relatively high, thereby reducing the damage to the etch stop layer 520 caused by the etching process used when forming the core layer and the mask sidewall. Moreover, the material of the hard mask material layer 510 is silicon nitride, and the etch stop layer 520 is also used to protect the hard mask material layer 510, so as to prevent the process of forming the core layer and the mask sidewall from damaging the hard mask material layer 510. In addition, in the subsequent process of transferring the pattern of the mask sidewall to the hard mask material layer 510, the pattern of the mask sidewall is first transferred to the etch stop layer 520, so that the patterned etch stop layer 520 can also play a role as a mask when etching the hard mask material layer 510.

[0115] In other embodiments, according to the materials of the core layer and the mask sidewalls, the material of the etch stop layer may also be silicon nitride or silicon nitride oxide.

[0116] Combined with reference Figures 9 to 11 The forming method further comprises: forming a separate core layer 640 (such as Fig.11 shown).

[0117] Specifically, the core layer 640 is formed on the etch stop layer 520 .

[0118] In this embodiment, the SADP process is used to form the dummy gate structure, and the core layer 640 is used to provide a process basis for the subsequent formation of the mask sidewalls, and the core layer 640 is used to define the interval between adjacent dummy gate structures. The mask sidewalls are used to define the shape, position and size of the dummy gate structure.

[0119] The core layer 640 will be removed later, so the material of the core layer 640 is a material that is easy to remove, and the process of removing the core layer 640 causes less damage to other film layers. In this embodiment, the material of the core layer 640 is amorphous silicon. Amorphous silicon is helpful to improve the verticality of the side wall of the core layer 640.

[0120] Specifically, the steps of forming the core layer 640 include: Fig. 9 As shown, a core material layer 600 is formed on the amorphous silicon material layer 500 at a third preset deposition temperature, and the third preset deposition temperature is lower than the crystallization temperature of amorphous silicon; Fig.11 As shown, the core material layer 600 is etched to form a separate core layer 640 .

[0121] In this embodiment, a furnace tube process is used to form the core material layer 600 on the amorphous silicon material layer 500. The furnace tube process has a higher process temperature, which is beneficial to increase the deposition rate of the core material layer 600, thereby improving manufacturing efficiency. In addition, the furnace tube process also has a longer process time.

[0122] Among them, the core material layer 600 is deposited on the amorphous silicon material layer 500. In the process of forming the core material layer 600, the amorphous silicon material layer 500 is also located in the deposition chamber. Under the action of heat conduction, the third preset deposition temperature will also affect the amorphous silicon material layer 500. When the third preset deposition temperature is too high, it is also easy to cause the amorphous silicon material layer 500 to crystallize. Therefore, by making the third preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of the amorphous silicon material layer 500 is further reduced, thereby reducing the line edge roughness of the subsequently formed pseudo gate structure.

[0123] Moreover, in the present embodiment, the material of the core layer 640 is also amorphous silicon. Therefore, by making the third preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of the material of the core material layer 600 (i.e., amorphous silicon) can be reduced during the formation of the core material layer 600. Accordingly, when etching the core material layer 600 to form the core layer 640, it is beneficial to improve the uniformity of the etching rate and the uniformity of the etching effect, thereby reducing the line edge roughness of the core layer 640.

[0124] Subsequently, a mask sidewall is formed on the sidewall of the core layer 640, and the pattern is transferred to the amorphous silicon material layer 500 through the mask sidewall, thereby reducing the line edge roughness of the core layer 640, which is also beneficial to reducing the line edge roughness of the mask sidewall, thereby reducing the line edge roughness of the pseudo gate structure formed subsequently.

[0125] Increasing the third preset deposition temperature is beneficial to increasing the deposition rate of amorphous silicon. When the temperature is higher than 550 degrees Celsius, the probability of amorphous silicon crystallizing becomes higher. Therefore, in order to reduce the probability of amorphous silicon crystallizing, the third preset deposition temperature is less than or equal to 510 degrees Celsius.

[0126] However, when the third preset deposition temperature is too low, it is easy to cause the core material layer 600 to fail to form, thereby reducing the film quality of the core material layer 600. Moreover, when other parameters such as process time are constant, it is easy to cause the thickness of the core material layer 600 to be difficult to reach the preset value. In order to make the thickness of the core material layer 600 reach the preset value, the process time needs to be increased accordingly. At the same temperature, the longer the process time, the higher the probability of crystallization of amorphous silicon will become.

[0127] To this end, in this embodiment, the third preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius, so that the film quality and thickness of the core material layer 600 can meet the process requirements and at the same time reduce the probability of crystallization of amorphous silicon.

[0128] It should be noted that after forming the core material layer 600 , the method further includes: forming a protective layer 610 on the core material layer 600 .

[0129] The protective layer 610 is used to protect the core material layer 600, so as to prevent the subsequently formed organic material layer from contaminating the core material layer 600. In addition, the protective layer 610 is also helpful to improve the adhesion between the core material layer 600 and the organic material layer.

[0130] In this embodiment, the material of the protective layer 610 is silicon oxide, and the protective layer 610 is formed by a chemical vapor deposition process. The process temperature of the chemical vapor deposition process is relatively low, for example, 100 degrees Celsius to 200 degrees Celsius, so the process of forming the protective layer 610 leads to a low probability of crystallization of the amorphous silicon material layer 500.

[0131] Combined with reference Fig.10 and Fig.11 The step of etching the core material layer 600 includes: forming a mask stack (not shown) on the protective layer 610, the mask stack including a bottom anti-reflective coating 620 covering the protective layer 610, and a photoresist layer 630 located on the bottom anti-reflective coating 620; using the photoresist layer 630 as a mask, sequentially etching the bottom anti-reflective coating 620, the protective layer 610 and the core material layer 600 to pattern the core material layer 600 into a core layer 640; after forming the core layer 640, removing the remaining mask stack.

[0132] The bottom anti-reflection coating 620 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern.

[0133] In this embodiment, a dry etching process (for example, an anisotropic dry etching process) is used to etch the core material layer 600. The dry etching process has an anisotropic etching characteristic, which is beneficial to improving the morphology quality of the core layer 640. Moreover, during the dry etching process, by adjusting the etching gas and etching parameters, the bottom anti-reflective coating 620, the protective layer 610 and the core material layer 600 can be etched in sequence in the same etching equipment, and the process is simple and does not require the conversion of the machine.

[0134] Among them, in the process of etching the bottom anti-reflective coating 620, the top surface of the protective layer 610 is used to define the stop position of the etching process. There is a higher etching selectivity ratio between silicon oxide and amorphous silicon. By first transferring the pattern to the protective layer 610 and then continuing to transfer it to the core material layer 600, it is beneficial to improve the verticality of the side wall of the core layer 640 and reduce the line edge roughness of the core layer 640.

[0135] Combined with reference Figure 12 to Figure 13 , a mask sidewall 660 (such as Fig.13 shown).

[0136] The mask sidewall spacer 660 is used as a mask for etching the amorphous silicon material layer 500 .

[0137] The core layer 640 needs to be removed later, so there is a high etching selectivity ratio between the core layer 640 and the mask sidewall 660 , thereby reducing the probability of damage to the mask sidewall 660 during the process of removing the core layer 640 .

[0138] Therefore, the material of the mask sidewall 660 is selected such that in the step of removing the core layer 640, the etching selectivity ratio of the core layer 640 to the mask sidewall 660 is greater than or equal to 3:1. Specifically, the etching selectivity ratio of the core layer 640 to the mask sidewall 660 is greater than or equal to 5:1.

[0139] In this embodiment, the material of the mask sidewall 660 is silicon nitride. Amorphous silicon and silicon nitride have relatively high etching selectivity, so the pattern of the mask sidewall 660 can be well transferred to the amorphous silicon material layer 500.

[0140] In other embodiments, the material of the mask sidewalls may also be other suitable materials such as silicon oxynitride, silicon carbide, or carbon oxynitride silicon.

[0141] Specifically, the steps of forming the mask sidewall 660 include: Fig.12As shown, a mask material layer 650 conformally covering the core layer 640 and the amorphous silicon material layer 500 is formed at a second preset deposition temperature, wherein the second preset deposition temperature is lower than the crystallization temperature of amorphous silicon; Fig.13 As shown, the mask material layer 650 located on the top of the core layer 640 and the amorphous silicon material layer 500 is removed, and the remaining mask material layer 650 located on the sidewall of the core layer 640 is retained as a mask sidewall 660 .

[0142] In this embodiment, the mask material layer 650 is formed by using an atomic layer deposition process.

[0143] The atomic layer deposition process is usually used for atomic-scale controllable thin film growth. The process forms a thin film by depositing a single atomic layer layer by layer, which is beneficial to improving the control accuracy of the thickness of the mask material layer 650 and the thickness uniformity of the mask material layer 650. In addition, the process has a strong gap filling ability and step coverage ability. Among them, since the atomic layer deposition process forms a thin film by depositing a single atomic layer layer by layer, the atomic layer deposition process includes multiple cycles, and therefore, the process time of the atomic layer deposition process is usually relatively long.

[0144] The mask material layer 650 is deposited on the amorphous silicon material layer 500. During the process of forming the mask material layer 650, the amorphous silicon material layer 500 is also located in the deposition chamber. Under the action of heat conduction, the second preset deposition temperature will also affect the amorphous silicon material layer 500. Since the process time of the atomic layer deposition process is usually long, at the same temperature, the longer the process time, the higher the probability of crystallization of amorphous silicon. When the second preset deposition temperature is too high, it is also easy to cause crystallization of amorphous silicon. Therefore, by making the second preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of the amorphous silicon material layer 500 can be further reduced.

[0145] Moreover, in the present embodiment, the material of the core layer 640 is also amorphous silicon. Therefore, by making the second preset deposition temperature lower than the crystallization temperature of amorphous silicon, the probability of crystallization of the core layer 640 can also be reduced, thereby improving the uniformity of the etching rate of the core layer 640 in the subsequent process of removing the core layer 640.

[0146] Similarly, increasing the second preset deposition temperature is beneficial to increasing the deposition rate of the mask material layer 650. When the temperature is higher than 550 degrees Celsius, the probability of amorphous silicon crystallizing becomes higher. Therefore, the second preset deposition temperature is less than or equal to 510 degrees Celsius to reduce the probability of amorphous silicon crystallizing.

[0147] However, when the second preset deposition temperature is too low, the mask material layer 650 may fail to be formed, thereby reducing the film quality of the mask material layer 650 and causing the thickness of the mask material layer 650 to be difficult to reach the preset value, thereby affecting the morphology and size of the subsequently formed pseudo-gate structure. Alternatively, in order to make the thickness of the mask material layer 650 reach the preset value, the process time needs to be increased accordingly. At the same temperature, the longer the process time, the higher the probability of crystallization of amorphous silicon.

[0148] In this embodiment, the second preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius, so that the film quality and thickness of the mask material layer 650 can meet the process requirements and reduce the probability of crystallization of amorphous silicon.

[0149] In this embodiment, an anisotropic maskless etching process is used to form the mask sidewall 660, so that the mask material layer 650 on the top of the core layer 640 and the amorphous silicon material layer 500 can be removed, and the mask material layer 650 on the side wall of the core layer 640 is retained.

[0150] Specifically, the anisotropic maskless etching process is a dry etching process.

[0151] refer to Fig.14 After forming the mask sidewall 660, the core layer 640 (such as Fig.13 shown).

[0152] By removing the core layer 640 , preparation is made for etching the amorphous silicon material layer 500 using the mask sidewalls 660 as a mask.

[0153] In this embodiment, a dry etching process (such as an anisotropic dry etching process) is used to etch and remove the core layer 640. During the dry etching process, a polymer is formed on the sidewall of the mask sidewall 660, and the polymer can protect the mask sidewall 660, thereby reducing damage to the mask sidewall 660, and further helping to reduce the line edge roughness of the mask sidewall 660.

[0154] Combined with reference Fig.15 and Fig.16 , etching the amorphous silicon material layer 500 (such as Fig.15 As shown), an amorphous silicon layer 550 is formed (as shown Fig.16 As shown), the amorphous silicon layer 550 is used as a dummy gate structure.

[0155] The dummy gate structure is used to occupy a space position for the subsequent formation of a metal gate structure.

[0156] Specifically, the step of etching the amorphous silicon material layer 500 includes: removing the core layer 640 (such as Fig.13 As shown), the amorphous silicon material layer 500 is etched using the mask sidewall 660 as a mask to form an amorphous silicon layer 550.

[0157] Specifically, Fig.15 As shown, the mask sidewall 660 is used as a mask to sequentially etch the etch stop layer 520 and the hard mask material layer 510 (as shown in FIG. Fig.14 As shown), the pattern of the mask sidewall 660 is transferred to the hard mask material layer 510 to form a hard mask layer 530; as shown Fig.16 As shown, after the hard mask layer 530 is formed, the amorphous silicon material layer 500 is continuously etched using the hard mask layer 530 as a mask to form an amorphous silicon layer 550 .

[0158] In the process of etching the hard mask material layer 510 , the patterned etch stop layer 520 can still serve as an etching mask.

[0159] It should be noted that the material of the hard mask material layer 510 and the mask sidewall 660 is the same, and the material of the etch stop layer 520 is silicon oxide. Therefore, during the process of etching the hard mask material layer 510 and the amorphous silicon material layer 500, the mask sidewall 660 and the etch stop layer 520 are easily consumed.

[0160] As an example, after forming the hard mask layer 530, the mask sidewall 660 has been removed, and only a partial thickness of the etch stop layer 520 is retained; after forming the amorphous silicon layer 550, the etch stop layer 520 is removed. In other embodiments, after forming the hard mask layer, the etch stop layer can also be completely removed.

[0161] In this embodiment, a dry etching process (for example, an anisotropic dry etching process) is used to sequentially etch the etching stop layer 520 , the hard mask material layer 510 , and the amorphous silicon material layer 500 .

[0162] The dry etching process has anisotropic etching characteristics, which is beneficial to improving the morphology quality of the pseudo gate structure. Moreover, during the dry etching process, by adjusting the etching gas and etching parameters, the etching stop layer 520, the hard mask material layer 510 and the amorphous silicon material layer 500 can be etched sequentially in the same etching equipment. The process is simple and there is no need to change the machine.

[0163] In this embodiment, the side wall roughness of the core layer 640 is relatively small, thereby reducing the side wall roughness of the mask side wall 660. Moreover, the material of the amorphous silicon material layer 500 still remains in an amorphous state. Therefore, when etching the amorphous silicon material layer 500, the uniformity of the etching rate and the uniformity of the etching effect are better, thereby reducing the side wall roughness of the pseudo gate structure, which in turn is beneficial to improving the side wall roughness of the subsequent metal gate structure, thereby improving the performance of the semiconductor structure.

[0164] It should be noted that source and drain doped regions are formed on both sides of the metal gate structure. Therefore, improving the sidewall roughness of the metal gate structure is beneficial to reducing the probability of short circuit between the conductive plug connected to the source and drain doped regions and the metal gate structure, thereby improving the yield of the semiconductor structure.

[0165] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an amorphous silicon material layer on the substrate at a first preset deposition temperature, wherein the amorphous silicon material layer is used to form a dummy gate structure, and the first preset deposition temperature is lower than a crystallization temperature of amorphous silicon; Etching the amorphous silicon material layer to form an amorphous silicon layer, wherein the amorphous silicon layer is used as a dummy gate structure; Before etching the amorphous silicon material layer, the formation method further includes: forming a discrete core layer on the amorphous silicon material layer at a third preset deposition temperature, wherein the third preset deposition temperature is lower than the crystallization temperature of amorphous silicon; forming a mask sidewall on the sidewall of the core layer at a second preset deposition temperature, wherein the second preset deposition temperature is lower than the crystallization temperature of amorphous silicon; after forming the mask sidewall, removing the core layer; In the step of etching the amorphous silicon material layer, the mask sidewall is used as a mask.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of etching the amorphous silicon material layer includes: after removing the core layer, etching the amorphous silicon material layer using the mask sidewall as a mask to form an amorphous silicon layer, wherein the amorphous silicon layer is used as a dummy gate structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of forming a mask sidewall on the sidewall of the core layer comprises: forming a mask material layer conformally covering the core layer and the amorphous silicon material layer at a second preset deposition temperature, wherein the second preset deposition temperature is lower than a crystallization temperature of amorphous silicon; The mask material layer located on the top of the core layer and on the amorphous silicon material layer is removed, and the remaining mask material layer located on the side wall of the core layer is retained as a mask sidewall.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a discrete core layer on the amorphous silicon material layer comprises: forming a core material layer on the amorphous silicon material layer at a third preset deposition temperature, wherein the third preset deposition temperature is lower than a crystallization temperature of amorphous silicon; The core material layer is etched to form a discrete core layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: An amorphous silicon material layer is formed on the substrate by adopting a furnace tube process.

6. The method for forming a semiconductor structure according to claim 3, wherein: The mask material layer is formed by an atomic layer deposition process.

7. The method for forming a semiconductor structure according to claim 4, wherein: The core material layer is formed by adopting a furnace tube process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The first preset deposition temperature is less than or equal to 510 degrees Celsius.

9. The method for forming a semiconductor structure according to claim 8, wherein: The first preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius.

10. The method for forming a semiconductor structure according to claim 1, wherein: The second preset deposition temperature is less than or equal to 510 degrees Celsius.

11. The method for forming a semiconductor structure according to claim 10, wherein: The second preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius.

12. The method for forming a semiconductor structure according to claim 1, wherein: The third preset deposition temperature is less than or equal to 510 degrees Celsius.

13. The method for forming a semiconductor structure according to claim 12, wherein: The third preset deposition temperature is 400 degrees Celsius to 510 degrees Celsius.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the mask sidewalls includes silicon nitride, silicon oxynitride, silicon carbide or silicon carbon oxynitride.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the core layer includes amorphous silicon.

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