Semiconductor device and method of forming the same

Abstract

Provided is a semiconductor device and a method of forming the same. The semiconductor device includes semiconductor fins. The semiconductor device includes a gate spacer over the semiconductor fins, a lower portion of the gate spacer surrounding a first region, and an upper portion of the gate spacer surrounding a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer in contact with the gate dielectric, the dielectric protection layer including a first portion within the second region and a second portion lining a top surface of the metal gate.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, and particularly to a method of manufacturing non-planar transistors. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, such improvement in integration density comes from the repeated reduction of the minimum feature size, which allows more components to be integrated in a given area.

[0003] Fin Field-Effect Transistor (FinFET) devices have become increasingly popular in integrated circuits. A FinFET device has a three-dimensional structure that includes fins protruding from a substrate and a gate structure that wraps around the fins. The gate structure is configured to control the flow of charge carriers in the conductive channel of the FinFET device. For example, in a triple-gate FinFET device, the gate structure wraps around three sides of the fin, thereby forming a conductive channel on three sides of the fin. Summary of the Invention

[0004] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor fin, a gate spacer, a gate dielectric, a metal gate, and a dielectric protection layer. The gate spacer is above the semiconductor fin, wherein a lower portion of the gate spacer surrounds a first region, and an upper portion of the gate spacer surrounds a second region. The gate dielectric is within the first region, the metal gate is within the first region, and the dielectric protection layer contacts the gate dielectric. The dielectric protection layer includes a first portion within the second region and a second portion that lines a top surface of the metal gate.

[0005] According to other embodiments, a method of forming a semiconductor device is provided. The method includes: removing a dummy gate structure straddling a semiconductor fin to form a gate trench; forming a gate structure within a lower portion of the gate trench, the gate structure including a gate dielectric and a metal gate above the gate dielectric; and forming a dielectric protection layer above the gate structure; wherein the dielectric protection layer includes a first portion within an upper portion of the gate trench and a second portion that lines a top surface of the metal gate.

[0006] According to some other embodiments, a method of forming a semiconductor device is provided. The method includes: forming a dummy gate structure across a portion of a semiconductor fin; forming gate spacers along sidewalls of the dummy gate structure; forming source / drain regions on both sides of the semiconductor fin, the source / drain regions being separated from the dummy gate structure by the gate spacers; removing the dummy gate structure to form a gate trench surrounded by the gate spacers; forming a gate structure in a lower portion of the gate trench, the gate structure including a gate dielectric and a metal gate over the gate dielectric; forming a dielectric protection layer over the gate structure, wherein the dielectric protection layer includes a first portion in an upper portion of the gate trench and a second portion over a top surface of the metal gate; forming a pair of source / drain contacts electrically connected to the source / drain regions; and forming a gate contact extending through the second portion of the dielectric protection layer to be electrically connected to the metal gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are merely for illustrative purposes. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present disclosure.

[0008] Figure 1 A perspective view showing a fin field-effect transistor (FinFET) device according to some embodiments.

[0009] Figure 2 A flowchart showing an exemplary manufacturing method of a non-planar transistor device according to some embodiments.

[0010] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 and Figure 17 show cross-sectional views of an exemplary fin field-effect transistor device at various process stages manufactured by the method of Figure 2 at various process stages.

[0011] Wherein, the reference numerals are described as follows:

[0012] 100: fin field-effect transistor device

[0013] 102: Substrate

[0014] 104: Fin

[0015] 106: Isolation region

[0016] 108: Gate dielectric

[0017] 110: Gate

[0018] 112S: Source region

[0019] 112D: Drain region

[0020] 200: Method

[0021] 202, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230: Operations

[0022] 300: Fin field-effect transistor device

[0023] 302: Substrate

[0024] 404: Fin

[0025] 406: Pad oxide layer

[0026] 408: Pad nitride layer

[0027] 410: Mask

[0028] 411: Trench

[0029] 500: Isolation region

[0030] 600, 600A, 600B: dummy gate structure

[0031] 602: dummy gate dielectric

[0032] 604: dummy gate

[0033] 606: Mask

[0034] 700: lightly doped drain region

[0035] 702: Gate spacer

[0036] 800: Source / drain region

[0037] 900: Interlayer dielectric

[0038] 902: Contact etch stop layer

[0039] 904: Dielectric layer

[0040] 1000A, 1000B: Gate trenches

[0041] 1000A_1, 1000B_1: First region

[0042] 1000_2, 1000A_2, 1000B_2: Second region

[0043] 1100, 1100A, 1100B: Active gate structure

[0044] 1102: Gate dielectric layer (gate dielectric)

[0045] 1104: Metal layer (metal gate)

[0046] 1200: Blanket dielectric

[0047] 1300: Sacrificial layer

[0048] 1401: Etching process

[0049] 1501: Etching process

[0050] 1600: Dielectric protection layer

[0051] 1600A: First part

[0052] 1600B: Second part

[0053] 1702: Contact

[0054] 1704: Contact

[0055] 1708: Dielectric

[0056] A - A: Cross-section

[0057] B - B: Cross-section

[0058] H1: Depth

[0059] M1: Depth Detailed implementation mode

[0060] Numerous embodiments or examples are provided below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, when it is described that a first element is formed on a second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. In addition, the embodiments of the present disclosure may repeat element symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent the relationship between different embodiments and / or configurations being discussed.

[0061] Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "above", "higher", etc., for the purpose of facilitating the description of the relationship between one (or some) component(s) or feature(s) and another (or some) component(s) or feature(s) in the drawings. Spatially relative terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

[0062] The terms "about" and "substantially" may indicate a range in which a given quantity of a numerical value varies within, for example, 5% of that numerical value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the numerical value).

[0063] The embodiments of the present disclosure are discussed in the context of forming a fin field-effect transistor device, and particularly in the context of forming a contact for a fin field-effect transistor device. In some embodiments, a dummy gate structure is formed over a fin, and after forming gate spacers around the dummy gate structure, source / drain regions are formed on respective sides of the gate spacers. Then, an interlayer dielectric (ILD) layer is formed over the source / drain regions, and the dummy gate structure is removed to form a gate trench in the interlayer dielectric layer. Then, an active gate structure is formed in the lower portion of the gate trench. Then, a dielectric protection layer is formed over the gate trench to overlay the top surface of the active gate structure and extend at least partially along the inner sidewalls of the upper portion of the gate trench. Then, a (gate) contact is formed to penetrate the portion of the dielectric protection layer on the top surface of the active gate structure, thereby electrically connecting to the active gate structure.

[0064] The gate contacts formed by the above method for fin field effect transistor devices can be less affected by short circuit (or bridging) problems. As the size of the technology node continues to shrink, the distance between adjacent device features in an integrated circuit may be significantly reduced. As such, forming corresponding contacts (e.g., via structures) to couple the device features may become challenging. For example, the contacts of adjacent device features that should be electrically insulated from each other may inadvertently be bridged, which may be caused by the decreasing distance between adjacent device features, resulting in the interlayer dielectric (ILD) layer formed between the contacts corresponding to the device features becoming thinner or more easily penetrable. As disclosed herein, by forming a dielectric protection layer, the contacts can be better insulated from adjacent contacts. Thus, even if the interlayer dielectric layer between two adjacent contacts becomes thinner or is inadvertently penetrated (by a conductive material), the disclosed dielectric protection layer can ensure that two adjacent contacts that should be electrically isolated remain electrically isolated from each other.

[0065] Figure 1 A perspective view showing a fin field effect transistor device 100 exemplary in accordance with some embodiments is shown. The fin field effect transistor device 100 includes a substrate 102 and fins 104 protruding above the substrate 102. Isolation regions 106 are formed on opposite sides of the fins 104, and the fins 104 protrude above the isolation regions 106. A gate dielectric 108 extends along the sidewalls and above the top surface of the fins 104, and a gate 110 is above the gate dielectric 108. Source regions / drain regions 112S and 112D are in (or extend from) the fins 104 and on opposite sides of the gate dielectric 108 and the gate 110. Figure 1 Is provided as a reference for a plurality of cross-sections in the subsequent figures. For example, cross-section B-B extends along the longitudinal axis of the gate 110 of the fin field effect transistor device 100, cross-section A-A is perpendicular to cross-section B-B and along the longitudinal axis of the fins 104, and, for example, in the direction of the current between the source regions / drain regions 112S and 112D. For clarity of illustration, the subsequent figures refer to these reference cross-sections.

[0066] Figure 2 A flowchart showing a method 200 for forming a non-planar transistor device in accordance with one or more embodiments of the present disclosure is shown. For example, at least some of the operations in method 200 can be used to form a fin field effect transistor device (e.g., fin field effect transistor device 100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor, etc. It should be noted that method 200 is only an example and is not intended to limit the embodiments of the present disclosure. Thus, it should be understood that it can be in Figure 2Before, during, and after the method 200, additional operations are provided, and some other operations are only briefly described herein. In some embodiments, the operations of the method 200 can be respectively associated with the cross-sectional views of the exemplary fin field effect transistor devices shown in Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 at various process stages, which will be discussed in further detail below.

[0067] Briefly overviewing, the method 200 starts with operation 202 to provide a substrate. The method 200 then proceeds to operation 204 to form one or more fins. The method 200 then proceeds to operation 206 to form isolation regions. The method 200 then proceeds to operation 208 to form dummy gate structures. The method 200 then proceeds to operation 210 to form lightly doped drain (LDD) regions and one or more gate spacers. The method 200 then proceeds to operation 212 to grow source / drain regions. The method 200 then proceeds to operation 214 to form an interlayer dielectric (ILD). The method 200 then proceeds to operation 216 to remove the dummy gate structures, and after removing the dummy gate structures, gate trenches are formed. The method 200 then proceeds to operation 218 to form active gate structures, which can be disposed in the lower portions of the gate trenches. The method 200 then proceeds to operation 220 to deposit a blanket dielectric. The method 200 then proceeds to operation 222 to deposit a sacrificial layer on the blanket dielectric. The method 200 then proceeds to operation 224 to remove a portion of the sacrificial layer. The method 200 then proceeds to operation 226 to remove a portion of the blanket dielectric. The method 200 then proceeds to operation 228 to remove the remaining portion of the sacrificial layer. The method 200 then proceeds to operation 230 to form at least one contact for each of the active gate structures and the source / drain regions.

[0068] As described above, Figures 3 to 17 respectively show cross-sectional views of a portion of the fin field effect transistor device 300 at various process stages of the Figure 2 method. The fin field effect transistor device 300 is substantially similar to Figure 1The fin field-effect transistor device 100 shown, but the fin field-effect transistor device 300 has a plurality of gate structures and a plurality of fins. For example, Figures 3 to 6 shows a cross-sectional view of the fin field-effect transistor device 300 along section line B-B (as Figure 1 shown); Figures 7 to 17 shows a cross-sectional view of the fin field-effect transistor device 300 along section line A-A (as Figure 1 shown). Although Figures 3 to 17 the fin field-effect transistor device 300 is illustrated, it should be understood that the fin field-effect transistor device 300 may include many other devices, such as an inductor, a fuse, a capacitor, a coil, etc., but for clarity of illustration, they are not shown in Figures 3 to 17 .

[0069] Corresponding to Figure 2 operation 202, Figure 3 is a cross-sectional view of the fin field-effect transistor device 300 in one of a plurality of process stages, wherein the fin field-effect transistor device 300 includes a semiconductor substrate 302. The substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 302 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulating layer, and the insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, and the substrate is typically a silicon or glass substrate, and other substrates may also be used, such as a multi-layer or gradient substrate. In some embodiments, the semiconductor material of the substrate 302 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing.

[0070] Corresponding to Figure 2 operation 204, Figure 4A cross-sectional view of a fin field-effect transistor device 300 in one of multiple process stages, where the fin field-effect transistor device 300 includes a (semiconductor) fin 404. Although Figure 4 the embodiments (and subsequent figures) only show one fin, it should be understood that the fin field-effect transistor device 300 can include any number of fins as long as it can be maintained within the scope of the present disclosure. In some embodiments, techniques such as photolithography and etching can be used to pattern the substrate 302 to form the fins 404. For example, a mask layer is formed above the substrate 302, such as a pad oxide layer 406 and a pad nitride layer 408 covering it. The pad oxide layer 406 can be a thin film containing silicon oxide, which is formed, for example, using a thermal oxidation process. The pad oxide layer 406 can act as an adhesion layer between the substrate 302 and the pad nitride layer 408 covering it. In some embodiments, the pad nitride layer 408 is formed of silicon nitride, silicon oxynitride, carbonitride, etc. or a combination of the foregoing. For example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) can be used to form the pad nitride layer 408.

[0071] The mask layer is patterned using photolithography techniques. Generally, photolithography techniques utilize the deposition of a photoresist material (not shown), irradiation (exposure), and development to remove a portion of the photoresist material, and the remaining photoresist material can protect the underlying material (such as the mask layer in this example) from subsequent process steps such as etching. For example, a photoresist material can be used to pattern the pad oxide layer 406 and the pad nitride layer 408 to form a patterned mask 410, as Figure 4 shown.

[0072] The patterned mask 410 can then be used to pattern the exposed portion of the substrate 302 to form trenches (or openings) 411, thereby defining the fins 404, with each fin 404 located between two adjacent trenches 411, as Figure 4As shown. In some embodiments, trenches are etched in the substrate 302 using, for example, reactive ion etch (RIE), neutral beam etch (NBE), etc., or a combination of the foregoing to form fins 404. The etching can be anisotropic. In some embodiments, the trenches 411 can be strips (viewed from the top) that are parallel to each other and closely spaced relative to each other. In some embodiments, the trenches 411 can be continuous and surround a corresponding one of the fins 404. The plurality of fins 404 may sometimes be referred to hereinafter as the fin 404.

[0073] The fins 404 can be patterned by any suitable method. For example, the fins 404 can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, thereby allowing the generation of patterns having, for example, a pitch smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned by a photolithography process, spacers are formed alongside the patterned sacrificial layer using a self-aligned process, and then the sacrificial layer is removed. The remaining spacers or mandrels can then be used to pattern the fins.

[0074] Corresponding to Figure 2 operation 206 Figure 5A cross-sectional view of a fin field-effect transistor device 300 in one of multiple process stages, where the fin field-effect transistor device 300 includes an isolation region 500. The isolation region 500 formed of an insulating material can electrically insulate adjacent fins from each other. The insulating material can be an oxide such as silicon oxide, a nitride, etc. or a combination of the foregoing, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post curing to transform it into another material (e.g., an oxide)), etc. or a combination of the foregoing. Other insulating materials and / or other forming processes can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a flowable chemical vapor deposition (FCVD) process. Once the insulating material is formed, an annealing process can be performed. A planarization process such as chemical mechanical polish (CMP) can remove any excess insulating material and form a coplanar (not shown) top surface of the isolation region 500 and the top surface of the fin 404. The patterned mask 410 ( Figure 4 ) can also be removed by the planarization process.

[0075] In some embodiments, the isolation region 500 includes a liner, such as a liner oxide (not shown), which is located at the interface between each isolation region 500 and the substrate 302 (fin 404). In some embodiments, the liner oxide is formed to reduce crystalline defects at the interface between the substrate 302 and the isolation region 500. Similarly, the liner oxide can also be used to reduce crystalline defects at the interface between the fin 404 and the isolation region. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 302. However, other suitable methods can also be used to form the liner oxide.

[0076] Next, the isolation region 500 is recessed to form a shallow trench isolation (STI) region 500, as Figure 5As shown, the isolation region 500 is recessed such that the upper portion of the fin 404 protrudes from between adjacent shallow trench isolation regions 500. Each top surface of the shallow trench isolation region 500 may have a flat surface (as shown in the figure), a convex surface, a concave surface (such as a dish shape), or a combination of the foregoing. The top surface of the shallow trench isolation region 500 can be formed to be flat, convex, and / or concave by appropriate etching. The isolation region 500 can be recessed using an acceptable etching process, for example, an etching process selective to the material of the isolation region 500. For example, dry etching or wet etching using dilute hydrofluoric (DHF) acid can be performed to recess the isolation region 500.

[0077] Figures 3 to 5 Embodiments showing the formation of one or more fins (such as 404) are shown, however, fins can also be formed in a variety of different processes. For example, the top of the substrate 302 can be replaced with a suitable material, such as an epitaxial material suitable for the intended type of semiconductor device to be formed (e.g., N-type or P-type). Thereafter, the substrate 302 having the epitaxial material on top is patterned to form fins 404 comprising the epitaxial material.

[0078] As another example, a dielectric layer can be formed over the top surface of the substrate; trenches can be etched through the dielectric layer; a homoepitaxial structure can be grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form one or more fins.

[0079] In yet another example, a dielectric layer can be formed over the top surface of the substrate; trenches can be etched through the dielectric layer; a heteroepitaxial structure can be grown epitaxially in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form one or more fins.

[0080] In embodiments where an epitaxial material or structure is grown (e.g., a heteroepitaxial structure or a homoepitaxial structure), the grown material or structure can be doped in situ during growth, which can be free from prior and subsequent implantation, however, in situ and implantation doping can also be used together. Further, it can be beneficial to grow different materials in the NMOS region and in the PMOS region. In different embodiments, the fin 404 can comprise silicon germanium (Si x Ge 1-x, where x can range between 0 and 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc., but are not limited thereto.

[0081] corresponding to Figure 2 operation 208 of Figure 6 is a cross-sectional view of a fin field-effect transistor device 300 in one of a plurality of process stages, where the fin field-effect transistor device 300 includes a dummy gate structure 600. In some embodiments, the dummy gate structure 600 includes a dummy gate dielectric 602 and a dummy gate 604, and a mask 606 can be formed above the dummy gate structure 600. To form the dummy gate structure 600, a dielectric layer is formed on the fin 404. The dielectric layer can be, for example, silicon oxide, silicon nitride, the aforementioned multi-layer structure, etc., and can be formed by deposition or thermal growth.

[0082] A gate layer is formed above the dielectric layer, and a mask layer is formed above the gate layer. The gate layer can be deposited on the dielectric layer and then planarized, for example, by chemical mechanical polishing. The mask layer can be deposited above the gate layer. The gate layer can be formed of, for example, polysilicon, although other materials can also be used. The mask layer can be formed of, for example, silicon nitride, etc.

[0083] After forming the layers (e.g., the dielectric layer, the gate layer, and the mask layer), the mask layer can be patterned using acceptable photolithography and etching techniques to form the mask 606. Then, the pattern of the mask 606 can be transferred to the gate layer and the dielectric layer by acceptable etching techniques to form the dummy gate 604 and the underlying dummy gate dielectric 602, respectively. The dummy gate 604 and the dummy gate dielectric 602 cover a portion (e.g., the channel region) of the fin 404. The dummy gate 604 can also have a lengthwise direction (e.g., Figure 1 direction B-B of Figure 1 ), which is substantially perpendicular to the lengthwise direction of the fin 404 (e.g.,

[0084] In Figure 6In the example, it is shown that the dummy gate dielectric 602 is formed over the fin 404 (e.g., over the top surface and sidewalls of the fin 404) and over the shallow trench isolation region 500. In other embodiments, the dummy gate dielectric 602 can be formed by thermal oxidation of, for example, the material of the fin 404, so that the dummy gate dielectric 602 can be formed above the fin 404 but not above the shallow trench isolation region 500. It should be understood that these and other variations are still included within the scope of the present disclosure.

[0085] Figures 7 to 17 FIG. shows a fin field effect transistor device 300 in a further process (or fabrication) cross-section along section A-A (along the longitudinal axis of the fin) as Figure 1 shown. Briefly summarized, in the Figures 7 to 17 example, two dummy gate structures 600A and 600B are depicted above the fin 404. For simplicity, the dummy gate structures 600A and 600B can sometimes be collectively referred to as the dummy gate structure 600. It should be understood that more or fewer than three dummy gate structures can be formed above the fin 404 while still remaining within the scope of the present disclosure.

[0086] Corresponding to Figure 2 operation 210, Figure 7 FIG. is a cross-section of a fin field effect transistor device 300 in one of a plurality of process stages, wherein the fin field effect transistor device 300 includes a plurality of lightly doped drain (LDD) regions 700 formed in the fin 404. The lightly doped drain regions 700 can be formed by a plasma doping process. The plasma doping process can include forming and patterning a mask, such as a photoresist, to cover regions of the fin field effect transistor device 300 that are to be protected from the plasma doping process. The plasma doping process can implant N-type or P-type impurities in the fin 404 to form the lightly doped drain regions 700. For example, P-type impurities (such as boron) can be implanted in the fin 404 to form the lightly doped drain regions 700 for P-type devices. In another example, N-type impurities (such as phosphorus) can be implanted in the fin 404 to form the lightly doped drain regions 700 for N-type devices. In some embodiments, the lightly doped drain regions 700 abut one of the channel regions of the fin field effect transistor device 300 (e.g., the portion of the fin 404 covered by one of the dummy gate structures 600), and a portion of the lightly doped drain regions 700 can extend under the dummy gate structures 600 and into the channel region of the fin field effect transistor device 300. Figure 7Illustrates a non-limiting example of the lightly doped drain region 700. Other configurations, shapes, and formation methods of the lightly doped drain region 700 are also possible and are fully intended to be included within the scope of the present disclosure. For example, the lightly doped drain region 700 can be formed after forming the gate spacers 702 (to be discussed below). In some embodiments, the lightly doped drain region 700 can be omitted.

[0087] Continuing to refer Figure 7 , after forming the lightly doped drain region 700, in some embodiments, gate spacers 702 are formed around the dummy gate structure 600 (e.g., along its sidewalls and in contact therewith). For example, the gate spacers 702 can be formed on opposite sidewalls of the dummy gate structure 600. It should be understood that any number of gate spacers can be formed around the dummy gate structure 600 as long as it can be maintained within the scope of the present disclosure.

[0088] The gate spacers 702 can be low-k (low dielectric constant) spacers and can be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, silicon carbonitride, etc. or a combination of the foregoing. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition (CVD), etc., can be used to form the gate spacers 702.

[0089] Figure 7 (and the subsequent figures) The shape and formation method of the gate spacers 702 illustrated are only non-limiting examples. Other shapes and formation methods are also possible, and these and other variations are fully intended to be included within the scope of the present disclosure.

[0090] Corresponding to Figure 2 operation 212, Figure 8 is a cross-sectional view of the fin field-effect transistor device 300 in one of a plurality of process stages, where the fin field-effect transistor device 300 includes a plurality of source / drain regions 800. The source / drain regions 800 are formed in the recesses of the fins 404 adjacent to the dummy gate structure 600, such as between adjacent dummy gate structures 600 and / or beside the dummy gate structure 600. In some embodiments, for example, an anisotropic etching process is used with the dummy gate structure 600 as an etching mask to form the recesses, although any other suitable etching process can also be used.

[0091] The source / drain region 800 can be formed by epitaxially growing a semiconductor material in the recess using any suitable method, such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc. or a combination of the foregoing. As Figure 8 shown, the epitaxial source / drain region 800 can have a surface that raises from each surface of the fin 404 (e.g., raises above the non-recessed portion of the fin 404) and can have facets. In some embodiments, the source / drain regions 800 of adjacent fins can merge to form a continuous epitaxial source / drain region (not shown). In some embodiments, the source / drain regions 800 of adjacent fins can not merge together and remain separate source / drain regions 800 (not shown). In some embodiments, when the resulting fin field effect transistor device is an n-type fin field effect transistor, the source / drain region 800 can include silicon carbide (SiC), silicon phosphide (SiP), phosphorous-doped silicon carbon (SiCP), etc. In some embodiments, when the resulting fin field effect transistor device is a p-type fin field effect transistor, the source / drain region 800 includes silicon germanium (SiGe) and p-type impurities such as boron or indium.

[0092] The epitaxial source / drain region 800 can be implanted with dopants to form the source / drain region 800, and then an annealing process can be performed. The implantation process can include forming and patterning a mask such as photoresist to cover the regions of the fin field effect transistor device 300 that are to be protected from the implantation process. The source / drain region 800 can have an impurity (e.g., dopant) concentration in the range of about 1×10 19 cm -3 to about 1×10 21 cm -3 . P-type impurities (such as boron or indium) can be implanted into the source / drain region 800 of a p-type transistor, and N-type impurities (such as phosphorus or arsenic) can be implanted into the source / drain region 800 of an n-type transistor. In some embodiments, the epitaxial source / drain regions 800 can be doped in situ during their growth.

[0093] corresponding to Figure 2 operation 214, Figure 9 is a cross-sectional view of a fin field-effect transistor device 300 in one of a plurality of process stages, wherein the fin field-effect transistor device 300 includes an interlayer dielectric (ILD) 900. In some embodiments, before forming the interlayer dielectric 900, a contact etch stop layer (CESL) 902 is formed over the structure shown in Figure 9 The contact etch stop layer 902 can serve as an etch stop layer in subsequent etching processes and can include suitable materials such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing, and can be formed by suitable methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of the foregoing.

[0094] Next, the interlayer dielectric 900 is formed over the contact etch stop layer 902 and over the dummy gate structures 600 (e.g., 600A and 600B). In some embodiments, the interlayer dielectric 900 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and can be deposited by any suitable method such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD). After forming the interlayer dielectric 900, a dielectric layer 904 is formed over the interlayer dielectric 900. The dielectric layer 904 can serve as a protective layer to prevent or reduce loss of the interlayer dielectric 900 during subsequent etching processes. The dielectric layer 904 can be formed of a suitable material such as silicon nitride, silicon carbonitride, etc., and is formed using a suitable method such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD). After forming the dielectric layer 904, a planarization process such as chemical mechanical polishing (CMP) can be performed to achieve a level top surface of the dielectric layer 904. Chemical mechanical polishing can also remove the mask 606 ( Figure 8 ) disposed over the dummy gate 604 and a portion of the contact etch stop layer 902. In some embodiments, after the planarization process, the top surface of the dielectric layer 904 is flush with the top surface of the dummy gate 604.

[0095] A gate-last process (sometimes referred to as a gate replacement process) is then performed to replace the dummy gate 604 and the dummy gate dielectric 602 of each dummy gate structure 600 with an active gate structure (which can also be referred to as a replacement gate structure or a metal gate structure).

[0096] Corresponding to Figure 2 operation 216, Figure 10 is a cross-sectional view of the fin field-effect transistor device 300 in one of multiple process stages, where the dummy gate structures 600A and 600C ( Figure 9 ) are removed to form gate trenches 1000A and 1000B, respectively. For simplicity, the gate trenches 1000A and 1000B can sometimes be collectively referred to as the gate trench 1000.

[0097] In some embodiments, to remove the dummy gate structure 600, one or more etching steps are performed to remove the dummy gate 604 and the dummy gate dielectric 602 directly under the dummy gate 604, causing the gate trench 1000 (which can also be referred to as a recess) to be formed between the respective gate spacers 702. In other words, each gate trench 1000 is surrounded by its respective gate spacer 702, and each gate trench 1000 exposes the channel region of the fin 404. During the removal of the dummy gate, when the dummy gate 604 is etched, the dummy gate dielectric 602 can act as an etch stop layer. After the removal of the dummy gate 604, the dummy gate dielectric 602 can then be removed. In some embodiments, the gate spacers 702 can remain intact during the removal of the dummy gate 604 and / or the dummy gate dielectric 602.

[0098] Corresponding to Figure 2 operation 218, Figure 11A cross-sectional view of a fin field-effect transistor device 300 in one of multiple process stages, where the fin field-effect transistor device 300 includes active gate structures 1100A and 1100B. According to different embodiments, each of the active gate structures 1100A and 1100B is formed in a lower portion of a corresponding one of the gate trenches 1000. As shown, the active gate structure 1100A is formed in the lower portion of the gate trench 1000A; and the active gate structure 1100B is formed in the lower portion of the gate trench 1000B. In this way, a first region (1000A_1) of the gate trench 1000A surrounded by a lower portion (on the left-hand side) of the gate spacer 702 is filled with the active gate structure 1100A, and a second region (1000A_2) of the gate trench 1000A surrounded by an upper portion (on the left-hand side) of the gate spacer 702 can remain exposed; and a first region (1000B_1) of the gate trench 1000B surrounded by a lower portion (on the right-hand side) of the gate spacer 702 is filled with the active gate structure 1100B, and a second region (1000B_2) of the gate trench 1000B surrounded by an upper portion (on the right-hand side) of the gate spacer 702 can remain exposed. For simplicity, the first regions 1000A_1 and 1000B_1 of the gate trenches can sometimes be collectively referred to as the first region 1000_1, the second regions 1000A_2 and 1000B_2 of the gate trenches can sometimes be collectively referred to as the second region 1000_2, and the active gate structures 1100A and 1100B can sometimes be collectively referred to as the active gate structure 1100. In some embodiments, each active gate structure 1100 includes one or more gate dielectric layers (or gate dielectrics) 1102, one or more metal layers (or metal gates) 1104, an optional capping layer (not shown), and an adhesive layer (not shown).

[0099] For example, the gate dielectric layer 1102 is conformally deposited in the gate trench 1000, such as on the top surface and sidewalls of the fin 404, on the top surface and sidewalls of the gate spacer 702, and on the top surface of the dielectric layer 904. According to some embodiments, the gate dielectric layer 1102 includes silicon oxide, silicon nitride, or a multi-layer structure of the foregoing. In an exemplary embodiment, the gate dielectric layer 1102 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 1102 may have a dielectric constant value (k value) greater than about 7.0, and may include metal oxides or silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), and combinations of the foregoing. The method for forming the gate dielectric layer 1102 may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), etc. For example, the thickness of the gate dielectric layer 1102 may be between about 8 angstroms and about 20 angstroms.

[0100] The metal layer 1104 is formed on (e.g., conformally formed on) the gate dielectric layer 1102. In some embodiments, the metal layer 1104 may include a P-type work function layer, an N-type work function layer, a multi-layer of the foregoing, or a combination of the foregoing. In the discussion herein, the work function layer may also be referred to as a work function metal. Exemplary P-type work function metals that may be included in the gate structure of a P-type device include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), other suitable P-type work function materials, or combinations of the foregoing. Exemplary N-type work function metals that may be included in the gate structure of an N-type device include titanium (Ti), silver (Ag), tantalum aluminide (TaAl), tantalum aluminide carbide (TaAlC), titanium aluminide nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), other suitable N-type work function materials, or combinations of the foregoing. The work function value is associated with the material composition of the work function layer. Therefore, the material of the work function layer is selected to adjust its work function value such that the target threshold voltage V tis achieved in the formed device. The work function layer can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable processes. For example, the thickness of the P-type work function layer can be between about and about , while the thickness of the N-type work function layer can be between about and about .

[0101] An optional capping layer is formed on (e.g., conformally formed on) the metal layer 1104. If the capping layer is formed, it protects the underlying metal layer 1104 from oxidation. In some embodiments, the capping layer is a silicon-containing layer, such as a silicon layer, a silicon oxide layer, or a silicon nitride layer, which is formed by a suitable method, such as atomic layer deposition (ALD), molecular beam deposition (MBD), chemical vapor deposition (CVD), etc. The thickness of the capping layer can be between about and about .

[0102] The glue layer is formed on (e.g., conformally formed on) the capping layer, or on the metal layer 1104 (if the capping layer is omitted). The glue layer can serve as an adhesion layer between the underlying layer and the gate electrode material formed subsequently above the glue layer. The glue layer can be formed of a suitable material, such as titanium nitride, and can be formed using a suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0103] Corresponding to Figure 2 operation 220, Figure 12 is a cross-sectional view of the fin field-effect transistor device 300 in one of multiple process stages, where the fin field-effect transistor device 300 includes a blanket dielectric 1200. In some embodiments, the blanket dielectric 1200 is conformally formed above the fin field-effect transistor device 300. As shown, the blanket dielectric 1200 covers the top surface of the dielectric layer 904, extends along the inner sidewalls of the gate spacers 702 (the gate spacers 702 not filled by the active gate structure 1100), and covers the top surface of the active gate structure 1100. In other words, by forming the blanket dielectric 1200 as a conformal layer with a substantially thin thickness (e.g., about 1 to 20 nanometers (nm)), such a conformal layer in the second region 1000_2 of the gate trench can extend along the upper portions of the inner sidewalls of the gate spacers 702 and cover the top surface of the active gate structure 1100.

[0104] The blanket dielectric 1200 may include a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof. In some embodiments, the blanket dielectric 1200 and the gate spacer 702 may have different materials to provide etch selectivity in subsequent processes. The blanket dielectric 1200 may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition and postcuring in a remote plasma system to convert it to another material, such as an oxide), or combinations thereof. In other embodiments, the blanket dielectric 1200 may include a high-k dielectric material. Thus, the blanket dielectric 1200 may have a dielectric constant value greater than about 4.0 or even greater than about 7.0, and may include metal oxides or silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), and combinations thereof. A method for forming such a high-k blanket dielectric 1200 may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0105] corresponding to Figure 2 operation 222, Figure 13 is a cross-sectional view of a fin field effect transistor device 300 in one of a plurality of process stages, where the fin field effect transistor device 300 includes a sacrificial layer 1300. As shown, the sacrificial layer 1300 may be deposited over the fin field effect transistor device 300 to fill the remaining gate trenches 1000 (e.g., the second region 1000_2). The sacrificial layer 1300 may be used to define or control the height of a dielectric protection layer formed subsequently from the blanket dielectric 1200 and then removed, which will be discussed below.

[0106] In some embodiments, the sacrificial layer 1300 comprises a polymer-based dielectric and is deposited by spin coating to fill the second region 1000_2 of the gate trench. The polymer-based dielectric can be an inorganic polymer, such as a silicon-based polymer like spin-on glass (SOG). The polymer-based dielectric can be an organic polymer, such as a silicon-based polymer with a higher organic content, an aromatic hydrocarbon, a poly(arylene ether) (PAE) film, a benzocyclobutene (BCB)-based film, a polyimide or a fluorinated polyimide, an amorphous fluorinated carbon film, a polytetrafluoroethylene (PTFE) film, or a parylene. For example, one of the organic polymer-based dielectrics is FLARE( TM ), which is synthesized from perfluorobiphenyl and an aromatic bisphenol to produce a fluorine-doped polymer. After deposition (e.g., by spin coating), the sacrificial layer 1300 is immediately followed by curing at a temperature between about 350 °C and 420 °C for about 20 to 60 minutes.

[0107] Corresponding to Figure 2 operation 224, Figure 14 is a cross-sectional view of the fin field-effect transistor device 300 in one of the multiple process stages, in which a portion of the sacrificial layer 1300 is removed. In some embodiments, the portion of the sacrificial layer 1300 includes a portion above the dielectric layer 904 and recessed in the second region 1000_2 of the gate trench. The portion of the sacrificial layer 1300 can be removed by one or more etching processes 1401, thereby exposing a portion of the blanket dielectric 1200.

[0108] As Figure 14As shown in the example of , the exposed portion of the blanket dielectric 1200 may include the covering dielectric layer 904 and the portion of the blanket dielectric 1200 extending to a depth H1 in the second region 1000_2 of the gate trench. Thus, the etching process 1401 can recess the remaining portion of the sacrificial layer 1300 to a depth H1 in the second region 1000_2 of the gate trench while keeping the exposed portion of the blanket dielectric 1200 intact. Such a recessed sacrificial layer 1300 can be used to control the height of the dielectric protection layer (formed by the blanket dielectric 1200), which will be discussed in further detail below.

[0109] The etching process 1401 can be anisotropic. For example, the etching process 1401 can perform anisotropic plasma etching in a high-density plasma (HDP) etcher, and the etching gas may include carbon tetrafluoride (CF4), trifluoromethane (CHF3), methylfluoride (CH3F), and nitrogen (N2). The operating conditions of the etching process 1401 can be selected such that the etching rate of the material of the sacrificial layer 1300 is higher than that of the material of the blanket dielectric 1200.

[0110] Corresponding to Figure 2 operation 226 Figure 15A cross-sectional view of a fin field-effect transistor device 300 in one of multiple process stages, where the exposed portion of the blanket dielectric 1200 is removed. In some embodiments, the exposed portion of the blanket dielectric 1200 defined by the recessed sacrificial layer 1300 is removed by performing one or more etching processes 1501. The etching process 1501 can be isotropic. For example, the etching process 1501 can be performed by applying a wet etchant on the fin field-effect transistor device 300, and the wet etchant can include dilute hydrofluoric acid (DHF) and / or amine derivative etchants (e.g., NH4OH, NH3(CH3)OH, TetraMethyl Ammonium Hydroxide (TMAH), etc.). In some embodiments, the etchant can be placed in a solvent (e.g., ethylene glycol (EG), diethylene glycol (DEG), 1-(2-hydroxyethyl)-2-pyrrolidinone (HEP), dimethyl sulfoxide (DMSO), sulfolane, combinations of the foregoing, etc.) to a concentration of about 1 volume % to about 10 volume %. During the etching process, the wet etchant 1501 can be maintained at a temperature between about 30°C and about 65°C, such as about 50°C, for a time between about 30 seconds and about 300 seconds, such as about 150 seconds.

[0111] Corresponding to Figure 2 operation 228, Figure 16 A cross-sectional view of a fin field-effect transistor device 300 in one of multiple process stages, where the remaining portion of the sacrificial layer 1300 is removed. After removing the remaining portion of the sacrificial layer 1300, a dielectric protection layer (sometimes referred to as a dielectric helmet layer) 1600 can be formed. As shown, each dielectric protection layer 1600 formed in the second region 1000_2 of the gate trench has a U-shaped cross-section. For example, the dielectric protection layer 1600 has a first portion 1600A that lines or covers (e.g., makes physical contact with) the top surface of the active gate structure 1000 and a second portion 1600B that is connected to both ends of the first portion 1600A and extends along the sidewall of the second region 1000_2 (or the upper portion of the inner sidewall of the gate spacer 702).

[0112] In Figure 16In the example of, the second part 1600B of the dielectric protection layer is recessed by a depth M1 relative to the top surface of the gate spacer 702, which may be beneficial for subsequent processes for performing a planarization process. For example, one or more chemical mechanical polishing processes may be performed during the formation of the contacts, such that the recessed second part 1600B (relative to the gate spacer 702) can serve as a stop layer to end the chemical mechanical polishing process. However, it should be understood that the second part 1600B of the dielectric protection layer may be flush with the top surface of the gate spacer 702 and still remain within the scope of the present disclosure.

[0113] Corresponds to Figure 2 operation 230 of Figure 17 is a cross-sectional view of a fin field-effect transistor device 300 in one of a plurality of process stages, where the fin field-effect transistor device 300 includes contacts 1702 and 1704. Each of the contacts 1702 and 1704 may include a via structure that penetrates one or more dielectrics to electrically connect to a device structure, region, or feature. For example, the contact 1702 penetrates the dielectric 1708 and the dielectric protection layer 1600 to electrically connect to the active gate structure 1100 (specifically, the metal gate 1104); and the contact 1704 penetrates the interlayer dielectric 900 and the contact etch stop layer (ESL) 902 to electrically connect to the source / drain region 800. Accordingly, the contacts 1702 and 1704 may sometimes be referred to as the gate contact and the source / drain contact, respectively.

[0114] By forming the dielectric protection layer 1600 around the gate contact 1702, the gate contact 1702 can be better insulated from adjacent contacts such as the source / drain contact 1704. Thus, even if the interlayer dielectric 900 between the gate contact 1702 and each adjacent source / drain contact 1704 becomes thinner or is inadvertently penetrated (by a conductive material, such as when forming the contacts 1702 and / or 1704), the dielectric protection layer 1600 can ensure that the gate contact 1702 and each adjacent source / drain contact 1704 that should be electrically isolated remain electrically isolated from each other.

[0115] In some embodiments, the dielectric 1708 comprises a material similar to that of the interlayer dielectric 900. For example, the dielectric 1708 comprises a material selected from silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Thus, the dielectric 1708 is sometimes also referred to as an interlayer dielectric (ILD). The above materials can be deposited by using any suitable method such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD) to fill the gate trench 1000 (specifically, the second region 1000_2) to form the dielectric 1708. After filling the gate trench 1100 with the dielectric 1708, one or more chemical mechanical polishing processes can be performed to planarize the interlayer dielectric 900 and the dielectric 1708. During the chemical mechanical polishing process, the dielectric layer 904 can be removed. Then, one or more patterning processes can be performed to form respective openings extending through the interlayer dielectric 900 / dielectric 1708 to expose the metal gate 1104 and the source / drain regions 800. Then the openings are filled with a conductive material (e.g., copper, tungsten, etc.) to form the contacts 1702 and 1704. In some embodiments, each of the contacts 1702 and 1704 can be surrounded by a (diffusion) barrier layer, and the barrier layer is not shown for the clarity of the figure. The barrier layer can comprise a material selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and titanium (Ti).

[0116] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device comprises semiconductor fins. The semiconductor device comprises gate spacers above the semiconductor fins. The lower part of the gate spacers surrounds a first region, and the upper part of the gate spacers surrounds a second region. The semiconductor device comprises a gate dielectric within the first region. The semiconductor device comprises a metal gate within the first region. The semiconductor device comprises a dielectric protection layer in contact with the gate dielectric. The dielectric protection layer comprises a first part within the second region and a second part lining the top surface of the metal gate.

[0117] In one embodiment, the foregoing gate dielectric comprises at least one high-k dielectric material, and the dielectric protection layer comprises the same high-k dielectric material as the gate dielectric.

[0118] In one embodiment, the foregoing dielectric protection layer comprises a material selected from the group consisting of metal oxides or silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), and combinations thereof.

[0119] In one embodiment, the dielectric protection layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof as described above.

[0120] In one embodiment, the semiconductor device further comprises a pair of source / drain contact members and a gate contact member. The source / drain contact members are electrically connected to source / drain regions disposed on two sides of the semiconductor fin, and the gate contact member extends through a second portion of the dielectric protection layer to be electrically connected to the metal gate.

[0121] In one embodiment, the gate contact member is electrically insulated from any one of the source / drain contact members at least through a first portion of the dielectric protection layer.

[0122] In another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. The method includes removing a dummy gate structure straddling a semiconductor fin to form a gate trench. The method includes forming a gate structure in a lower portion of the gate trench, the gate structure including a gate dielectric and a metal gate above the gate dielectric. The method includes forming a dielectric protection layer above the gate structure, the dielectric protection layer including a first portion in an upper portion of the gate trench and a second portion lining a top surface of the metal gate.

[0123] In one embodiment, the step of forming the dielectric protection layer above the gate structure further includes: depositing a blanket dielectric along an inner sidewall of an upper portion of the gate trench and above a top surface of the metal gate, the blanket dielectric being connected to the gate dielectric; filling the upper portion of the gate trench with a sacrificial layer; removing a portion of the sacrificial layer to a depth in the gate trench while keeping the blanket dielectric intact; removing a portion of the blanket dielectric to the same depth in the gate trench while keeping the sacrificial layer intact, and a remaining portion of the blanket dielectric forms the dielectric protection layer; and removing a remaining portion of the sacrificial layer from the gate trench.

[0124] In one embodiment, the step of removing a portion of the sacrificial layer to a depth in the gate trench includes performing an anisotropic etching process on the sacrificial layer.

[0125] In one embodiment, the step of removing the remaining portion of the sacrificial layer includes performing an ashing process on the sacrificial layer.

[0126] In one embodiment, ends of the first portion of the dielectric protection layer are respectively recessed to the same depth in the gate trench.

[0127] In one embodiment, the gate dielectric includes at least one high-k dielectric material, and the dielectric protection layer includes the same high-k dielectric material as the gate dielectric.

[0128] In one embodiment, the dielectric protection layer comprises a material selected from the group consisting of metal oxides or silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), and combinations thereof.

[0129] In one embodiment, the dielectric protection layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof.

[0130] In one embodiment, the method for forming the semiconductor device further comprises: forming a pair of source / drain contact members electrically connected to the source regions / drain regions disposed on both sides of the semiconductor fin; and forming a gate contact member extending through a second portion of the dielectric protection layer to be electrically connected to the metal gate.

[0131] In one embodiment, the gate contact member is electrically insulated from any one of the source / drain contact members at least through a first portion of the dielectric protection layer.

[0132] In one embodiment, the gate dielectric and the dielectric protection layer have the same thickness.

[0133] In another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. The method comprises forming a dummy gate structure across a portion of the semiconductor fin. The method comprises forming gate spacers along sidewalls of the dummy gate structure. The method comprises forming source regions / drain regions on both sides of the semiconductor fin, the source regions / drain regions being separated from the dummy gate structure by the gate spacers. The method comprises removing the dummy gate structure to form a gate trench surrounded by the gate spacers. The method comprises forming a gate structure in a lower portion of the gate trench, the gate structure comprising a gate dielectric and a metal gate above the gate dielectric. The method comprises forming a dielectric protection layer above the gate structure, wherein the dielectric protection layer comprises a first portion in an upper portion of the gate trench and a second portion above a top surface of the metal gate. The method comprises forming a pair of source / drain contact members electrically connected to the source regions / drain regions. The method comprises forming a gate contact member extending through the second portion of the dielectric protection layer to be electrically connected to the metal gate.

[0134] In one embodiment, the gate contact member is electrically insulated from any one of the source / drain contact members at least through a first portion of the dielectric protection layer.

[0135] The foregoing outlines the features of several embodiments so that those of ordinary skill in the art to which this disclosure pertains can more readily understand aspects of the embodiments of this disclosure. Those of ordinary skill in the art to which this disclosure pertains should be able to understand that they can, based on the embodiments of this disclosure, design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those of ordinary skill in the art to which this disclosure pertains should also be able to understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A semiconductor fin; A gate spacer above the semiconductor fin, wherein a lower portion of the gate spacer surrounds a first region, and an upper portion of the gate spacer surrounds a second region; Source / drain regions disposed on two sides of the semiconductor fin; An etch stop layer disposed above the source / drain regions, a part of the etch stop layer contacting a sidewall of the gate spacer and a sidewall of the source / drain regions; A gate dielectric within the first region; A metal gate within the first region; and A dielectric protection layer contacting the gate dielectric, the dielectric protection layer including a first part within the second region and a second part lining a top surface of the metal gate.

2. The semiconductor device according to claim 1, wherein, The gate dielectric includes at least one high-k dielectric material, and the dielectric protection layer includes the same high-k dielectric material as the gate dielectric.

3. The semiconductor device according to claim 1, wherein, The dielectric protection layer includes a material selected from the group consisting of metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, and combinations of the foregoing metal oxides or silicates.

4. The semiconductor device according to claim 1, wherein, The dielectric protection layer includes a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations of the foregoing silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride.

5. The semiconductor device according to claim 1, further comprising: A pair of source / drain contacts electrically connected to the source / drain regions disposed on two sides of the semiconductor fin; And A gate contact extending through the second part of the dielectric protection layer to be electrically connected to the metal gate.

6. The semiconductor device according to claim 5, wherein, The gate contact is electrically insulated from any one of the pair of source / drain contacts at least through the first part of the dielectric protection layer.

7. A method for forming a semiconductor device, comprising: Removing a dummy gate structure across a semiconductor fin to form a gate trench; Forming a gate structure within a lower portion of the gate trench, the gate structure including a gate dielectric and a metal gate above the gate dielectric; Depositing a blanket dielectric along an inner sidewall of an upper portion of the gate trench and above a top surface of the metal gate, the blanket dielectric being connected to the gate dielectric; Filling the upper portion of the gate trench with a sacrificial layer; Removing a part of the sacrificial layer to a depth within the gate trench while keeping the blanket dielectric intact; Removing a part of the blanket dielectric to the same depth within the gate trench while keeping the sacrificial layer intact, a remaining part of the blanket dielectric forming a dielectric protection layer; and Removing a remaining part of the sacrificial layer from the gate trench.

8. The method for forming a semiconductor device according to claim 7, wherein, The step of removing a part of the sacrificial layer to a depth within the gate trench includes: performing an anisotropic etching process on the sacrificial layer.

9. The method for forming a semiconductor device according to claim 7, wherein, The step of removing a part of the blanket dielectric to the same depth within the gate trench includes: performing an isotropic etching process on the blanket dielectric.

10. The method for forming a semiconductor device according to claim 7, wherein, The step of removing the remaining part of the sacrificial layer includes: performing an ashing process on the sacrificial layer.

11. The method for forming a semiconductor device according to claim 7, wherein, Ends of a first part of the dielectric protection layer are respectively recessed to the same depth within the gate trench.

12. The method for forming a semiconductor device according to claim 7, wherein, The gate dielectric includes at least one high-k dielectric material, and the dielectric protection layer includes the same high-k dielectric material as the gate dielectric.

13. The method for forming a semiconductor device according to claim 7, wherein, The dielectric protection layer comprises a material selected from the group consisting of metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, and combinations of the foregoing metal oxides or silicates.

14. The method for forming a semiconductor device according to claim 7, wherein, The dielectric protection layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations of the foregoing silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride.

15. The method for forming a semiconductor device according to claim 7, further comprising: Form a pair of source / drain contact members, the pair of source / drain contact members being electrically connected to source regions / drain regions disposed on two sides of the semiconductor fin; and Form a gate contact member, the gate contact member extending through a second portion of the dielectric protection layer to be electrically connected to the metal gate.

16. The method for forming a semiconductor device according to claim 15, wherein, The gate contact member is electrically insulated from any one of the pair of source / drain contact members at least through a first portion of the dielectric protection layer.

17. The method for forming a semiconductor device according to claim 7, wherein, The gate dielectric and the dielectric protection layer have the same thickness.

18. A method for forming a semiconductor device, comprising: Form a dummy gate structure to span a portion of a semiconductor fin; Form a gate spacer along a sidewall of the dummy gate structure; Form source regions / drain regions on two sides of the semiconductor fin, the source regions / drain regions being separated from the dummy gate structure by the gate spacer; Remove the dummy gate structure to form a gate trench surrounded by the gate spacer; Form a gate structure in a lower portion of the gate trench, the gate structure comprising a gate dielectric and a metal gate above the gate dielectric; Deposit a blanket dielectric along an inner sidewall of an upper portion of the gate trench and above a top surface of the metal gate, the blanket dielectric being connected to the gate dielectric; Fill the upper portion of the gate trench with a sacrificial layer; Remove a portion of the sacrificial layer to a depth in the gate trench while keeping the blanket dielectric intact; Remove a portion of the blanket dielectric to the same depth in the gate trench while keeping the sacrificial layer intact, and a remaining portion of the blanket dielectric forms a dielectric protection layer; Remove a remaining portion of the sacrificial layer from the gate trench; Form a pair of source / drain contact members, the pair of source / drain contact members being electrically connected to the source regions / drain regions; and Form a gate contact member, the gate contact member extending through a portion of the dielectric protection layer to be electrically connected to the metal gate.

19. The method for forming a semiconductor device according to claim 18, wherein, The gate contact member is electrically insulated from any one of the pair of source / drain contact members at least through a first portion of the dielectric protection layer.

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