Memory device, semiconductor device and operation method thereof

Abstract

A memory device is provided, which may include a first electrode, a memory layer stack including at least one semiconductor metal oxide layer and at least one hydrogen-containing metal layer, and a second electrode. A semiconductor device is provided, which may include a semiconductor metal oxide layer including a source region, a drain region, and a channel region, a hydrogen-containing metal layer located on the surface of the channel region, and a gate electrode located on the channel region. Hydrogen-containing metal layer. Each hydrogen-containing metal layer may include at least 90% atomic percentage of at least one metal selected from platinum, iridium, osmium, and ruthenium, and may include 0.001% to 10% atomic percentage of hydrogen atoms. Hydrogen atoms may be reversibly immersed in the corresponding semiconductor metal oxide layer to change the resistivity and encode storage bits. Embodiments of the present invention also relate to semiconductor devices and methods of operating the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device, a semiconductor device, and an operating method thereof. Background Art

[0002] As semiconductor devices shrink to smaller sizes, new semiconductor memory cells are needed that provide high endurance and require low operating power. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a memory device is provided, comprising: a first electrode; a memory layer stack, located on the first electrode and comprising at least one semiconductor metal oxide layer and at least one hydrogen-containing metal layer, the hydrogen-containing metal layer comprising at least 90 atomic % of at least one metal selected from platinum, iridium, osmium and ruthenium and comprising hydrogen atoms; and a second electrode, located above the memory layer stack.

[0004] According to another aspect of an embodiment of the present invention, there is provided a semiconductor device, comprising: a semiconductor metal oxide layer, located on a dielectric material layer, and comprising a source region, a drain region, and a channel region located between the source region and the drain region; a hydrogen-containing metal layer, located on a surface of the channel region, and comprising at least 90 atomic percent of at least one metal selected from platinum, iridium, osmium, and ruthenium and including hydrogen atoms; and

[0005] The gate electrode is located on the hydrogen-containing metal layer.

[0006] According to another aspect of an embodiment of the present invention, a method for operating a semiconductor device is provided, comprising: providing a semiconductor device comprising a layer stack located between a first electrode and a second electrode, wherein the layer stack comprises at least one semiconductor metal oxide layer and at least one hydrogen-containing metal layer located above a dielectric material layer, wherein each of the at least one hydrogen-containing metal layer comprises at least 90 atomic percent of at least one metal selected from platinum, iridium, osmium and ruthenium and comprises hydrogen atoms; programming the semiconductor device to a hydrogenated state or a dehydrogenated state by applying a programming pulse across the first electrode and the second electrode or across a gate electrode located on at least one hydrogen-containing metal layer and one of the first electrode and the second electrode, wherein the hydrogenated state is a state in which at least one semiconductor metal oxide layer is impregnated with hydrogen atoms, and wherein the dehydrogenated state is a state in which at least one semiconductor metal oxide layer is hydrogen-deficient; and determining the memory state of the semiconductor device by measuring the conductance of a measurement current path between the first electrode and the second electrode under measurement bias conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a vertical cross-sectional view of the first exemplary structure after forming a complementary metal oxide semiconductor (CMOS) transistor, a metal interconnect structure embedded in a dielectric material layer, and a connecting via level dielectric layer according to the first embodiment of the present disclosure.

[0009] Figure 2 is a vertical cross-sectional view of the first exemplary structure after forming a connecting via structure array according to the first embodiment of the present disclosure.

[0010] Figure 3 is a vertical cross-sectional view of the first exemplary structure after forming a first electrode material layer, a memory material layer stack, and a second electrode material layer according to the first embodiment of the present disclosure.

[0011] Figure 4 is a vertical cross-sectional view of the first exemplary structure after patterning a pillar structure including a first electrode, a memory layer stack, and a second electrode according to the first embodiment of the present disclosure.

[0012] Figure 5 is a vertical cross-sectional view of the first exemplary structure after forming a dielectric diffusion barrier spacer according to the first embodiment of the present disclosure.

[0013] Figure 6 is a vertical cross-sectional view of the first exemplary structure after forming a memory level dielectric layer and a memory level metal interconnect structure and planarizing the top electrode according to the first embodiment of the present disclosure.

[0014] Figure 7 is a vertical cross-sectional view of a first alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0015] Figure 8 is a vertical cross-sectional view of a second alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0016] Fig. 9 is a vertical cross-sectional view of a third alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0017] Fig.10 is a vertical cross-sectional view of a fourth alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0018] Fig.11is a vertical cross-sectional view of a fifth alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0019] Fig. 12A is a vertical cross-sectional view of the second exemplary structure after forming a semiconductor metal oxide layer over the dielectric material layer according to the second embodiment of the present disclosure.

[0020] Fig. 12B yes Fig. 12A A top view of the second exemplary structure. The vertical plane A-A' is Fig. 12A A vertical cross-sectional view of a plane.

[0021] Fig.13A is a vertical cross-sectional view of a second exemplary structure after a hydrogen-containing metal layer and a gate electrode are formed over the semiconductor metal oxide layer according to the second embodiment of the present disclosure.

[0022] Fig. 13B yes Fig.13A A top view of the second exemplary structure. The vertical plane A-A' is Fig.13A A vertical cross-sectional view of a plane.

[0023] Fig.14A is a vertical cross-sectional view of a second exemplary structure after forming dielectric diffusion barrier spacers, source regions, and drain regions according to the second embodiment of the present disclosure.

[0024] Fig. 14B yes Fig.14A A top view of the second exemplary structure. The vertical plane A-A' is Fig.14A A vertical cross-sectional view of a plane.

[0025] Fig.15A is a vertical cross-sectional view of the second exemplary structure after forming a source contact via structure, a drain contact via structure, and a gate contact via structure according to the second embodiment of the present disclosure.

[0026] Fig. 15B yes Fig.15A A top view of the second exemplary structure. The vertical plane A-A' is Fig.15A A vertical cross-sectional view of a plane.

[0027] Fig.16A is a vertical cross-sectional view of a first alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0028] Fig. 16B yes Fig.16A A top view of a first alternative configuration of a second exemplary structure. Vertical plane AA' is Fig.16A A vertical cross-sectional view of a plane.

[0029] Fig.17Ais a vertical cross-sectional view of a second alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0030] Fig. 17B yes Fig.17A A top view of a second alternative configuration of a second exemplary structure. Vertical plane AA' is Fig.17A A vertical cross-sectional view of a plane.

[0031] Fig.18A is a vertical cross-sectional view of a third alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0032] Fig.18B yes Fig.18A A top view of a third alternative configuration of the second exemplary structure. The vertical plane AA' is Fig.18A A vertical cross-sectional view of a plane.

[0033] Fig.19A is a vertical cross-sectional view of a fourth alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0034] Fig.19B yes Fig.19A A top view of a fourth alternative configuration of the second exemplary structure. The vertical plane AA' is Fig.19A A vertical cross-sectional view of a plane.

[0035] Fig. 20 is a flowchart showing general processing steps of a method of manufacturing a memory device according to the first embodiment of the present disclosure.

[0036] Fig.21 is a flowchart showing general processing steps of a method of manufacturing a semiconductor device according to a second embodiment of the present disclosure.

[0037] Fig. 22 is a flow chart illustrating the general steps for operating the semiconductor device of the present disclosure. DETAILED DESCRIPTION

[0038] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0039] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0040] Hydrides of all transition metals, except those of the four platinum metals and tungsten, have been successfully synthesized, as described in V. Antonov et al., "The Solubility of Hydrogen in the Platinum Metals under High Pressure", Platinum Metals Edition, 1984, 28, (4), 158. "Platinum metals" refers to platinum, iridium, osmium and ruthenium. As far as the platinum group metals are concerned, there has been no shortage of attempts to synthesize hydrides of platinum, iridium, osmium and ruthenium, but the failure to synthesize platinum group metals is due to the low acceptability of hydrogen in their crystal lattices. This inertness or resistance to hydrogen absorption is characterized by the fact that, although the chemical potential of hydrogen dissolved in the metal may be very high, the hydrogen solubility corresponding to the equivalent high external pressure of hydrogen gas is generally very low.

[0041] Therefore, hydrogen atoms can be present in platinum metal (i.e., platinum, iridium, osmium and ruthenium) without forming hydrides. Embodiments of the present disclosure recognize that hydrogen can be stored in a hydrogen-containing metal layer including platinum, iridium, osmium and / or ruthenium adjacent to the semiconductor metal oxide layer at a relatively high atomic concentration. Hydrogen can be reversibly inserted and / or extracted from the semiconductor metal oxide layer. Hydrogen atoms can be incorporated into the interstitial positions of the semiconductor metal oxide material. Hydrogen atoms can act as shallow donors, thereby reducing the threshold voltage of the semiconductor metal oxide material.

[0042] The stack of the hydrogen-containing metal layer and the semiconductor metal oxide layer can be arranged between two electrodes, or can be arranged in a transistor configuration. The current can flow perpendicular to the interface between the hydrogen-containing metal layer and the semiconductor metal oxide layer. The current can have a variable conductivity, which depends on the amount of hydrogen incorporated into the semiconductor metal oxide layer. Alternatively, the current can flow along an in-plane direction within the semiconductor metal oxide layer with different threshold voltages, and the threshold voltage is determined by the amount of hydrogen incorporated into the semiconductor oxide layer when a gate voltage is applied to the hydrogen-containing metal layer. Various aspects of the present disclosure are now described in detail with reference to the accompanying drawings.

[0043] refer to Figure 1, showing a first exemplary structure according to the first embodiment of the present disclosure. The first exemplary structure includes a complementary metal oxide semiconductor (CMOS) transistor formed on a semiconductor substrate such as a single crystal silicon substrate, and a metal interconnect structure formed in a dielectric material layer. Specifically, the first exemplary structure includes a substrate 9, which can be a semiconductor substrate such as a commercially available silicon wafer. A shallow trench isolation structure 720 including a dielectric material such as silicon oxide can be formed on the upper portion of the substrate 9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, can be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Field effect transistors can be formed above the top surface of the substrate 9. For example, each field effect transistor can include a source region 732, a drain region 738, a semiconductor channel 735 (including a surface portion of the substrate 9 extending between the source region 732 and the drain region 738) and a gate structure 750. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source region 732 , and a drain-side metal-semiconductor alloy region 748 may be formed on each drain region 738 .

[0044] Typically, field effect transistors may be formed on a semiconductor substrate, and electrodes of a memory device to be subsequently formed may be electrically connected to corresponding field effect transistors through a metal interconnect structure formed above the semiconductor substrate within an interconnect level dielectric material layer. For example, a first exemplary structure may include a memory array region 100, in which a memory element array is subsequently formed, and a peripheral region 200, in which a logic device supporting the operation of the memory element array is formed. In one embodiment, the device (e.g., field effect transistor) in the memory array region 100 may include a bottom electrode access transistor, which provides access to the bottom electrode of a subsequently formed memory cell. At this processing step, a top electrode access transistor may be formed in the peripheral region 200, which provides access to the top electrode of a subsequently formed memory cell. The device (e.g., field effect transistor) in the peripheral region 200 may provide the functions required to operate the subsequently formed memory cell array. Specifically, the device in the peripheral region may be configured to control programming operations, erase operations, and sensing (reading) operations of the memory cell array. For example, the devices in the peripheral region may include sensing circuits and / or top electrode bias circuits. The devices formed on the top surface of the substrate 9 may include complementary metal oxide semiconductor (CMOS) transistors and optional additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuits 700.

[0045] Various metal interconnect structures embedded in the dielectric material layer may then be formed over the substrate 9 and the device (e.g., field effect transistor). The dielectric material layer may include, for example, a contact level dielectric material layer 601, a first metal line level dielectric material layer 610, a second line and via level dielectric material layer 620, a third line and via level dielectric material layer 630, and a fourth line and via level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in the contact level dielectric material layer 601 and contacting a component of the corresponding CMOS circuit 700, a first metal line structure 618 formed in the first metal line level dielectric material layer 610, a first metal via structure 622 formed in a lower portion of the second line and via level dielectric material layer 620, a second metal line structure 628 formed in an upper portion of the second line via level dielectric material layer 620, a second metal line structure 632 formed in a lower portion of the third line via level dielectric material layer 630, a third metal line structure 638 formed in an upper portion of the third line and via level dielectric material layer 630, a third metal via structure 642 formed in a lower portion of the fourth line and via level dielectric material layer 640, and a fourth metal line structure 648 formed in an upper portion of the fourth line and via level dielectric material layer 640. In one embodiment, the second metal line structure 628 may include a source line connecting a source side power supply of the memory element array. A voltage provided by the source line may be applied to the bottom electrode through an access transistor provided in the memory array region 100 .

[0046] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the intended scope of the disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line and via structure by a dual damascene process, the second metal via structure 632 and the third metal line structure 638 may be formed as an integrated line and via structure, and / or the third metal via structure 642 and the fourth metal line structure 648 may be formed as an integrated line and via structure. Although the present disclosure is described using an embodiment in which a memory cell array is formed above the fourth line and via level dielectric material layer 640, embodiments in which a memory cell array may be formed at a different metal interconnect level are expressly contemplated herein.

[0047] The dielectric material layer (601, 610, 620, 630, 640) is located at a lower level relative to the memory cell array to be formed subsequently. As such, the dielectric material layer (601, 610, 620, 630, 640) is referred to herein as a low-level dielectric layer, i.e., the dielectric material layer is located at a lower level relative to the memory cell array to be formed subsequently. The metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) is referred to herein as a low-level metal interconnect structure. A subset of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) includes a low-level metal line (e.g., a fourth metal line structure 648) embedded in the low-level dielectric layer and has a top surface within a horizontal plane including the topmost surface of the low-level dielectric layer. Typically, the total number of metal line layers within the lower-level dielectric layer ( 601 , 610 , 620 , 630 , 640 ) may be in the range of 1 to 10.

[0048] The dielectric cap layer 108 and the connecting via level dielectric layer 110 may be sequentially formed over the metal interconnect structure and the dielectric material layer. For example, the dielectric cap layer 108 may be formed on the top surface of the fourth metal line structure 648 and on the top surface of the fourth line and via level dielectric material layer 640. The dielectric cap layer 108 includes a dielectric cap material that can protect the underlying metal interconnect structure (such as the fourth metal line structure 648). In one embodiment, the dielectric cap layer 108 may include a material that can provide high etching resistance, i.e., a dielectric material, and may also be used as an etching stop material during an anisotropic etching process for etching the connecting via level dielectric layer 110 in a subsequent process. For example, the dielectric cap layer 108 may include silicon carbide or silicon nitride and may have a thickness in the range of from 5 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0049] The connecting via level dielectric layer 110 may include any material that may be used for the dielectric material layers (601, 610, 620, 630, 640). For example, the connecting via level dielectric layer 110 may include undoped silicate glass or doped silicate glass deposited by decomposition of tetraethyl orthosilicate (TEOS). The thickness of the connecting via level dielectric layer 110 may range from 50 nm to 200 nm, although lesser and greater thicknesses may also be used. The dielectric cap layer 108 and the connecting via level dielectric layer 110 may be formed as flat blanket (unpatterned) layers having respective flat top surfaces and respective flat bottom surfaces extending through the memory array region 100 and the peripheral region 200.

[0050] refer to Figure 2 , a through-hole cavity can be formed through the connection through-hole level dielectric layer 110 and the dielectric cover layer 108. For example, a photoresist layer (not shown) can be applied above the connection through-hole level dielectric layer 110 and can be patterned to form an opening in the area of ​​the memory array area 100 covering a corresponding one of the fourth metal line structures 648. Anisotropic etching can be performed to transfer the pattern in the photoresist layer through the connection through-hole level dielectric layer 110 and the dielectric cover layer 108. The through-hole cavity formed by the anisotropic etching process is referred to as the lower electrode contact through-hole cavity in this article because the bottom electrode connection through-hole structure is subsequently formed in the lower electrode contact through-hole cavity. The lower electrode contact through-hole cavity can have a tapered sidewall, and the taper angle of the tapered sidewall (in the direction relative to the vertical) is in the range of from 1 degree to 10 degrees. The top surface of the fourth metal line structure 648 can be physically exposed at the bottom of each lower electrode contact through-hole cavity. The photoresist layer can then be removed, for example, by ashing.

[0051] The metal barrier layer can be formed as a material layer. The metal barrier layer can cover the top surface of the physically exposed fourth metal line structure 648, the tapered sidewall of the lower electrode contact via cavity, and the top surface of the connecting via level dielectric layer 110 without any holes passing through. The metal barrier layer may include conductive metal nitrides such as TiN, TaN and / or WN. Other suitable materials within the disclosed expected range may also be used. The thickness of the metal barrier layer may be in the range from 3nm to 20nm, but smaller and larger thicknesses may also be used.

[0052] A metal fill material such as tungsten or copper may be deposited in the remaining volume of the lower electrode contact via cavity. Other suitable metal fill materials are within the intended scope of the present disclosure. Portions of the metal fill material and the metal barrier layer located above a horizontal plane including the topmost surface of the connecting via level dielectric layer 110 may be removed by a planarization process such as chemical mechanical planarization. Each remaining portion of the metal fill material located in a corresponding via cavity includes a metal via fill material portion 124. Each remaining portion of the metal barrier layer in a corresponding via cavity includes a metal barrier layer 122. Each combination of the metal barrier layer 122 and the metal via fill material portion 124 that fills the via cavity constitutes a connecting via structure (122, 124). An array of connecting via structures (122, 124) may be formed in the connecting via level dielectric layer 110, which is located on the metal interconnect structure below. The array of connecting via structures (122, 124) may contact the top surface of a subset of the fourth metal line structure 648. Typically, the array of connecting via structures (122, 124) contacts the top surfaces of a subset of the low-level metal lines located at the topmost level of the low-level dielectric layers (601, 610, 620, 630, 640). In one embodiment, the array of connecting via structures (122, 124) can be used as a first metal interconnect structure, providing electrical connection to the first electrode of each subsequently formed memory cell.

[0053] Optionally, the formation of the dielectric cap layer 108, the connecting via level dielectric layer 110, and the array of connecting via structures (122, 124) can be omitted, and a subset of the metal line structures embedded in the line and via level dielectric layer or in the line level dielectric layer can be used as a first metal interconnect structure to provide electrical connection to the first electrode of each memory cell to be formed subsequently. For example, a subset of the fourth metal line structure 648 embedded in the fourth line and via level dielectric material layer 640 and located in the memory array area 100 can be used as a first metal interconnect structure to provide electrical connection to the first electrode of each memory cell to be formed subsequently. Typically, the first metal interconnect structure is configured to provide electrical connection to the first electrode (e.g., the bottom electrode) of each memory cell to be formed subsequently. The first metal interconnect structure can be provided as a metal line (such as a one-dimensional periodic array of metal lines extending along a common level direction), or can be provided as a metal via structure, such as a two-dimensional array of connecting via structures (122, 124). Typically, each first metal interconnect structure may be embedded within a first dielectric material layer, such as connecting via level dielectric layer 110 (in embodiments using a two-dimensional array of connecting via structures (122, 124)), a dielectric material layer that embeds metal lines, such as fourth line and via level dielectric material layer 640. Each bottom surface of the first electrode may then be formed on a top surface of a corresponding one of the first metal interconnect structures.

[0054] Although the present disclosure is described using an embodiment in which a connecting via level dielectric layer 110 is used as the first dielectric material layer and an array of connecting via structures (122, 124) is used as the first metal interconnect structure, embodiments in which an array of via structures or an array of metal lines at a different level is used as the first metal interconnect structure are expressly contemplated herein.

[0055] refer to Figure 3 , a first electrode material layer 126L, a memory material layer stack (130L, 140L) and a second electrode material layer 158L can be sequentially deposited on a top surface of a first dielectric material layer (such as a connecting via level dielectric layer 110), and the first dielectric material layer is embedded in an array of connecting via structures (122, 124).

[0056] The first electrode material layer 126L may include and / or may be substantially composed of a conductive metal nitride material and / or an elemental metal and / or an intermetallic alloy. The conductive metal nitride material may include a metal diffusion barrier material that can prevent hydrogen diffusion. For example, conductive metal nitride materials that can be used for the first electrode material layer 126L include TiN, TaN, or WN. Elemental metals that can be used for the first electrode material layer 126L include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co, and Ni. Typically, elemental metals that prevent hydrogen diffusion can be used for the first electrode material layer 126L. In one embodiment, a refractory metal having a melting point greater than 2,000 degrees Celsius can be used for the first electrode material layer 126L. Typically, elemental metals with a high melting point tend to provide a low bulk diffusion coefficient for gases due to relatively tight bonding between atoms.

[0057] The first electrode material layer 126L may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the first electrode material layer 126L may be in the range of 1 nm to 100 nm, for example, from 2 nm to 50 nm and / or from 4 nm to 20 nm, but smaller and larger thicknesses may also be used. A stack of multiple metal layers may be used as the first electrode material layer 126L.

[0058] The memory material layer stack (130L, 140L) includes at least one semiconductor metal oxide material layer 130L and at least one hydrogen-containing metal layer 140L. In general, the at least one semiconductor metal oxide material layer 130L may be a single semiconductor metal oxide material layer 130L or a plurality of semiconductor metal oxide material layers 130L that may be vertically separated by the at least one hydrogen-containing metal layer 140L. The at least one hydrogen-containing metal layer 140L may be a single hydrogen-containing metal layer 140L or a plurality of hydrogen-containing metal layers 140L that may be vertically separated by the at least one semiconductor metal oxide material layer 130L. In one embodiment, a single semiconductor metal oxide material layer 130L and a single hydrogen-containing metal layer 140L may be present in the memory material layer stack (130L, 140L). In this embodiment, the single hydrogen-containing metal layer 140L may be located above or below the single semiconductor metal oxide material layer 130L. In another embodiment, a single semiconductor metal oxide material layer 130L and two hydrogen-containing metal layers 140L may be present in the memory material layer stack (130L, 140L). In this embodiment, a single semiconductor metal oxide material layer 130L may be located between two hydrogen-containing metal layers 140L. In yet another embodiment, two semiconductor metal oxide material layers 130L and a hydrogen-containing metal layer 140L may be present in the memory material layer stack (130L, 140L). In this embodiment, a single hydrogen-containing metal layer 140L may be located between two semiconductor metal oxide material layers 130L. In yet another embodiment, at least two semiconductor metal oxide material layers 130L and at least two hydrogen-containing metal layers 140L may be present in the memory material layer stack (130L, 140L). In this embodiment, at least two semiconductor metal oxide material layers 130L and at least two hydrogen-containing metal layers 140L may be vertically alternately arranged, wherein each pair of vertically adjacent layers includes a corresponding semiconductor metal oxide material layer 130L and a corresponding hydrogen-containing metal layer 140L.

[0059] Each semiconductor metal oxide material layer 130L includes a semiconductor metal oxide material, that is, a semiconductor metal oxide material that can provide 1.0 S / m to 1.0 x 10 5 In the intrinsic state or low-level electrical doping conditions, semiconductor metal oxide materials can be semiconducting or insulating, and their conductivity is generally in the range of 1.0x 10 -10S / m to 1.0 x 10 S / m. Exemplary semiconductor metal oxide materials that can be used for the at least one semiconductor metal oxide material layer 130L include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doping variants derived therefrom. In one embodiment, the semiconductor metal oxide material layer 130L may include indium gallium zinc oxide.

[0060] The semiconductor metal oxide material of each semiconductor metal oxide material layer 130L can be deposited, for example, by physical vapor deposition (i.e., sputtering). The semiconductor metal oxide material of each semiconductor metal oxide material layer 130L can be deposited as a polycrystalline material, or the semiconductor metal oxide material can be deposited as an amorphous material and then annealed at an elevated temperature to a polycrystalline material to increase the average grain size. The thickness of each semiconductor metal oxide material layer 130L can be in the range of from 2 nm to 100 nm, such as from 4 nm to 50 nm and / or from 6 nm to 25 nm, but smaller and larger thicknesses can also be used.

[0061] Each hydrogen-containing metal layer 140L may include and / or may be substantially composed of at least one of platinum metal (i.e., platinum, iridium, osmium, ruthenium or a combination thereof) and hydrogen atoms. Platinum metal refers to platinum, iridium, osmium and ruthenium, which do not form metal hydrides under normal hydride formation conditions, such as when the hydrogen partial pressure is in the range of 1 kbar to 50 kbar. The metal component of the hydrogen-containing metal layer 140L may be substantially composed of at least one metal selected from platinum, iridium, osmium and ruthenium. In one embodiment, the metal component of the hydrogen-containing metal layer 140L may be mainly composed of platinum.

[0062] Each hydrogen-containing metal layer 140L may be formed by physical vapor deposition in a vacuum or in an environment including hydrogen. The hydrogen partial pressure during the deposition process may be maintained at a level that does not hinder the deposition process such as the physical vapor deposition process. In one embodiment, the hydrogen partial pressure during the deposition of each hydrogen-containing metal layer 140L may be in the range of 1.0×10 -10 Support to 1.0×10 -3 Torr. Alternatively, the hydrogen-containing metal layer 140L may be deposited in a hydrogen-free environment or a low hydrogen pressure environment, and may be annealed at an elevated temperature in the hydrogen-containing environment. In the present embodiment, the annealing temperature may be in the range of 200 degrees Celsius to 500 degrees Celsius, for example, from 300 degrees Celsius to 400 degrees Celsius, and the hydrogen partial pressure during the annealing process may be in the range of 100 mTorr to 760 Torr. Alternatively or additionally, after depositing at least one of platinum, iridium, osmium, and ruthenium in a hydrogen-free environment or a low hydrogen pressure environment, hydrogen atoms may be implanted into each hydrogen-containing metal layer 140L.

[0063] Various process parameters that affect the incorporation of hydrogen into each hydrogen-containing metal layer 140L may be selected so that the atomic percentage of hydrogen atoms in each hydrogen-containing metal layer 140L is in a range of 0.001% to 10%, such as from 0.01% to 5% and / or from 0.1% to 3%. Various process parameters that affect the atomic percentage of hydrogen atoms in each hydrogen-containing metal layer 140L include, but are not limited to, the dose of hydrogen atoms during the hydrogen implantation process, the partial pressure of hydrogen during the annealing process in the hydrogen-containing environment, and the temperature and duration of the annealing process. In one embodiment, hydrogen implantation may be used to provide a high atomic percentage of hydrogen in each hydrogen-containing metal layer 140L. In this embodiment, each hydrogen-containing metal layer 140L may include an atomic percentage of hydrogen atoms greater than 1.0%, such as a percentage in the range of from 1.0% to 10%.

[0064] Each hydrogen-containing metal layer 140L may include at least 90% atomic percentage of at least one metal selected from platinum, iridium, osmium and ruthenium, and include an atomic percentage of hydrogen atoms in the range of 0.001% to 10% after the addition of hydrogen. In one embodiment, each hydrogen-containing metal layer 140L may include an atomic percentage of hydrogen atoms in the range of 0.001% to 10% after the incorporation of hydrogen, and the remainder of the atomic percentage may be at least one metal selected from platinum, iridium, osmium and ruthenium. In one embodiment, at least one metal selected from platinum, iridium, osmium and ruthenium may be platinum. In the present embodiment, each hydrogen-containing metal layer 140L may include an atomic percentage of hydrogen atoms in the range of 0.001% to 10% after the incorporation of hydrogen, and the atomic percentage of platinum may be the remainder of the atomic percentage of hydrogen atoms.

[0065] The thickness of each hydrogen-containing metal layer 140L can be in the range of from 2 nm to 100 nm, for example from 4 nm to 50 nm and / or from 6 nm to 25 nm, although smaller and larger thicknesses can also be used. Each hydrogen-containing metal layer 140L does not include any metal hydride, i.e., an MH compound in which M is a metal and hydrogen atoms occupy substitutional positions of the lattice structure. Therefore, a major portion or all of the hydrogen atoms present in each hydrogen-containing metal layer 140L are located in interstitial positions.

[0066] The second electrode material layer 158L may include and / or may be substantially composed of a conductive metal nitride material and / or an elemental metal and / or an intermetallic alloy. The conductive metal nitride material may include a metal diffusion barrier material that can prevent hydrogen diffusion. For example, the conductive metal nitride material that can be used for the second electrode material layer 158L includes TiN, TaN or WN. The elemental metals that can be used for the second electrode material layer 158L include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co and Ni. Typically, elemental metals that prevent hydrogen diffusion can be used for the second electrode material layer 158L. In one embodiment, a refractory metal having a melting point greater than 2000 degrees Celsius can be used for the second electrode material layer 158L. Typically, due to the relatively tight bonding between atoms, elemental metals with a high melting point tend to provide a low bulk diffusion coefficient for gases.

[0067] The second electrode material layer 158L may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the second electrode material layer 158L may be in a range from 1 nm to 100 nm, for example, from 2 nm to 50 nm and / or from 4 nm to 20 nm, but smaller and larger thicknesses may also be used. A stack of multiple metal layers may be used as the second electrode material layer 158L. The metal material of the second electrode material layer 158L may be the same as or different from the metal material of the first electrode material layer 126L.

[0068] refer to Figure 4 , a photoresist layer 177 may be applied on the second electrode material layer 158L and may be photolithographically patterned into array discrete photoresist material portions in the memory array region 100. Each patterned portion of the photoresist layer 177 may cover a corresponding one of the connecting via structures (122, 124). The sidewalls of each patterned portion of the photoresist layer 177 may coincide with the periphery of the top surface of the underlying connecting via structure (122, 124), may be laterally offset outward, or may be laterally offset inward. The sidewalls of each patterned portion of the photoresist layer 177 may have a hierarchical cross-sectional shape that is circular, elliptical, rectangular, rounded rectangular, or any substantially curved closed two-dimensional shape.

[0069] An anisotropic etching process may be performed to etch the unmasked portions of the second electrode material layer 158L, the memory material layer stack (130L, 140L), and the first electrode material layer 126L. Each patterned portion of the second electrode material layer 158L includes a second electrode 158. Each patterned portion of the memory material layer stack (130L, 140L) includes a memory layer stack (130, 140). Each patterned portion of the first electrode material layer 126L includes a first electrode 126. A subset of the remaining material portions originates from the material layer stack, including the second electrode material layer 158L, the memory material layer stack (130L, 140L), and the first electrode material layer. The electrode material layer 126L constitutes a memory cell 150. Each memory cell 150 may be a pillar structure having a flat top surface, a flat bottom surface, and at least one straight sidewall extending between the flat top surface and the flat bottom surface. At least one straight sidewall can be a single sidewall (such as a cylindrical sidewall) or a plurality of straight sidewalls (such as four planar sidewalls of a rectangular column structure, or a combination of four planar sidewalls of a column structure having a horizontal cross-sectional shape of a rounded rectangle and four convex cylindrical sidewalls).

[0070] Typically, each combination of the first electrode 126, the memory layer stack (130, 140) and the second electrode 158 can include a pillar structure having a top surface (which is the top surface of the second electrode 158), a bottom surface (which is the bottom surface of the first electrode 126), and a sidewall extending straight between the periphery of the top surface of the second electrode 158 and the periphery of the bottom surface of the first electrode 126.

[0071] Each memory layer stack (130, 140) includes at least one semiconductor metal oxide layer 130 and at least one hydrogen-containing metal layer 140. Each semiconductor metal oxide layer 130 is formed in Figure 3 The patterned portion of the corresponding semiconductor metal oxide material layer 130L is formed in the processing step of Figure 3In one embodiment, a single semiconductor metal oxide layer 130 and a single hydrogen-containing metal layer 140 may be present in the memory material layer stack (130, 140). In this embodiment, the single hydrogen-containing metal layer 140 may be located above or below the single semiconductor metal oxide layer 130. In another embodiment, a single semiconductor metal oxide layer 130 and two hydrogen-containing metal layers 140 may be present in the memory material layer stack (130, 140). In this embodiment, the single semiconductor metal oxide layer 130 may be located between two hydrogen-containing metal layers 140. In yet another embodiment, there may be two semiconductor metal oxide layers 130 and one hydrogen-containing metal layer 140 layer stack (130, 140) in the memory material. In this embodiment, a single hydrogen-containing metal layer 140 may be located between the two semiconductor metal oxide layers 130. In yet another embodiment, there may be at least two semiconductor metal oxide layers 130 and at least two hydrogen-containing metal layers 140 in the memory material layer stack (130, 140). In this embodiment, the at least two semiconductor metal oxide layers 130 and the at least two hydrogen-containing metal layers 140 may be arranged in a vertically alternating order, wherein each vertically adjacent layer pair includes a corresponding semiconductor metal oxide layer 130 and a corresponding hydrogen-containing metal layer 140.

[0072] A two-dimensional array of memory cells 150 may be provided. Each memory cell 150 may include, from bottom to top, a first electrode 126, a memory layer stack (130, 140) located on the first electrode 126 and including at least one semiconductor metal oxide layer 130 and at least one hydrogen-containing metal layer 140, and a second electrode 158 located above the memory layer stack (130, 140). The first electrode 126 may be a first metal electrode mainly composed of at least one metal material. The second electrode 158 may be a second metal electrode substantially composed of at least one metal material. Each of the at least one hydrogen-containing metal layers may include and / or may be substantially composed of at least 90% by atomic percentage of at least one metal selected from platinum, iridium, osmium, and ruthenium, and / or may be substantially composed of hydrogen atoms in an atomic percentage in the range of 0.001% to 10%.

[0073] In one embodiment, each of the at least one semiconducting metal oxide layer 130 contacts a horizontal surface of a corresponding one of the at least one hydrogen-containing metal layer 140 within each memory layer stack (130, 140). In one embodiment, the memory layer stack (130, 140) may include and / or may consist essentially of a single semiconducting metal oxide layer 130 and a single hydrogen-containing metal layer 140 in contact with each other. In one embodiment, the single semiconducting metal oxide layer 130 contacts one of the first electrode 126 and the second electrode 158, and the single hydrogen-containing metal layer 140 contacts the other of the first electrode 126 and the second electrode 158. The photoresist layer 177 may be subsequently removed, for example, by ashing.

[0074] refer to Figure 5 , the dielectric diffusion barrier material layer may be conformally deposited over the two-dimensional array of memory cells 150 by a conformal deposition process such as a chemical vapor deposition process. The dielectric diffusion barrier material layer includes a hydrogen diffusion barrier material layer that blocks hydrogen diffusion. For example, the dielectric diffusion barrier material may include silicon nitride. The thickness of the dielectric diffusion barrier material layer may be in a range from 5 nm to 50 nm, such as from 10 nm to 25 nm, but smaller and larger thicknesses may also be used.

[0075] An anisotropic etching process may be performed to remove horizontal portions of the dielectric diffusion barrier material layer. The remaining vertically extending portions of the dielectric diffusion barrier material layer include dielectric diffusion barrier spacers 156 that contact and laterally surround corresponding pillar structures in the memory cell 150 .

[0076] Each hydrogen-containing metal layer 140 serves as a hydrogen storage for one or both semiconductor metal oxide layers 130. The first electrode 126 and the second electrode 158 may include a metal material that prevents hydrogen atoms from diffusing therethrough. The dielectric diffusion barrier spacer 156 serves as a shell that prevents hydrogen atoms from escaping from the corresponding memory cell 150.

[0077] In general, hydrogen atoms within each memory cell 150 may be moved between the at least one hydrogen-containing metal layer 140 and the at least one semiconducting metal oxide layer 130 by applying a programming pulse across the first electrode 126 and the second electrode 158. Thus, applying a first programming pulse having a first polarity to the second electrode 158 relative to the first electrode 126 may cause the selected memory cell 150 to be programmed to a hydrogenated state in which one or more and / or all of the at least one semiconducting metal oxide layer 130 include a high atomic concentration of hydrogen atoms, which may be in a range from 0.001% to 10%, such as from 0.01% to 5% and / or from 0.1% to 3%. Applying a second programming pulse of a second polarity to the second electrode 158 relative to the first electrode 126 can cause the selected memory cell 150 to be programmed to a dehydrogenated state in which one or more and / or all of the at least one semiconducting metal oxide layer 130 includes a low atomic concentration of hydrogen atoms, which can be in a range from 0.0001% to 3.3%, such as from 0.001% to 1.67% and / or from 0.01% to 1%. Typically, the ratio of the atomic percentage of hydrogen atoms in the hydrogenated state of the semiconducting metal oxide layer 130 to the atomic percentage of hydrogen atoms in the dehydrogenated state of the semiconducting metal oxide layer 130 can be in a range of 3-100, such as from 5 to 10, although smaller and larger ratios can also be used.

[0078] Without wishing to be bound by any particular theory, it is believed that applying a negative voltage to one side of a metal (e.g., the first electrode 126 or the second electrode 158) that includes hydrogen atoms has a tendency to attract hydrogen because the hydrogen atoms are in a partial donor state, in which a partial negative charge of an electron can be donated to the common conduction band of the metal. The polarity of the programming pulse can be determined based on the direction in which the hydrogen atoms need to move for programming purposes. The amplitude of the programming pulse depends on the thickness and composition of the layer stack within each memory layer stack (130, 140). In an illustrative example, a programming pulse with an amplitude ranging from 3V to 30V can be used. Because the resistance of the current path within each memory cell 150, i.e., the resistance of the current path extending through each layer within the memory layer stack (130, 140) between the first electrode 126 and the second electrode 158, is relatively high, the current through each selected memory cell 150 when programming can be small, and power consumption can be small despite the relatively high operating voltage.

[0079] The presence of hydrogen atoms in each semiconducting metal oxide layer 130 increases the conductivity of the semiconducting metal oxide layer 130. Without wishing to be bound by any particular theory, it is believed that the hydrogen atoms located in the interstitial positions act as secondary donors and increase the conductivity of the material of the semiconducting metal oxide layer 130. Therefore, the hydrogenated state and the dehydrogenated state of each semiconducting metal oxide layer 130 can be distinguished by measuring the magnitude of the leakage current through each selected memory cell 150 between the corresponding first electrode 126 and the corresponding second electrode 158.

[0080] refer to Figure 6 , a memory level dielectric layer 170 can be formed around and above the memory cell array 150 and the array of dielectric diffusion barrier spacers 156. The memory level dielectric layer 170 includes a planarized dielectric material, such as undoped silicate glass or doped silicate glass. The dielectric material of the memory level dielectric layer 170 can be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarization deposition process (e.g., spin coating). Optionally, the top surface of the memory level dielectric layer 170 can be planarized, such as by chemical mechanical planarization. The vertical distance between the top surface of the memory level dielectric layer 170 and the top surface of the memory cell 150 can be in the range from 50nm to 500nm, but smaller and larger vertical distances can also be used.

[0081] At least one photolithographic patterning step and at least one anisotropic etching process can be used to form an interconnect cavity in the memory level dielectric layer 170. For example, a first photoresist layer (not shown) can be applied on the memory level dielectric layer 170 and can be photolithographically patterned to form an array of discrete openings in the first photoresist layer. A first anisotropic etching process can be performed to form a via in the memory level dielectric layer 170. In one embodiment, a via can be formed above each memory cell 150. A photoresist layer (not shown) can be applied on the memory level dielectric layer 170 and can be photolithographically patterned to form a linear opening in a second photoresist layer. A second anisotropic etching process can be performed to form a line cavity in the memory level dielectric layer 170. The second photoresist layer can then be removed. In one embodiment, the interconnect cavity can be formed as an integrated line and via cavity. In this embodiment, each integrated line and via cavity may include a line cavity within an upper portion of the memory level dielectric layer 170 and at least one via cavity adjacent to a bottom of the line cavity and extending vertically through a lower portion of the memory level dielectric layer 170 .

[0082] In one embodiment, a two-dimensional array of via cavities may be formed in the memory array region 100 such that each top surface of the memory cell 150 is physically exposed below a corresponding one of the via cavities in the two-dimensional array of via cavities. The top surface of the underlying metal interconnect structure, such as the fourth metal line structure 648 embedded in the upper portion of the fourth line and via level dielectric material layer 640, may be physically exposed at the bottom of at least a subset of the interconnect cavities in the memory level dielectric layer 170 in the peripheral region 200. In general, at least a subset of the interconnect cavities extending vertically between the top surface of the memory level dielectric layer 170 and the top surface of the underlying metal line structure may be formed through the memory level dielectric layer 170 in the peripheral region 200.

[0083] At least one metal material may be deposited in the interconnect cavity in the memory array region 100 and the peripheral region 200. The at least one metal material is referred to herein as at least one memory level metal material. In one embodiment, a metal barrier material layer (e.g., a TiN layer, a TaN layer, and / or a WN layer) and a metal fill material (e.g., W, Cu, Co, Ru, Mo, or an intermetallic alloy) may be deposited in the interconnect cavity and over the memory level dielectric layer 170.

[0084] A planarization process such as a chemical mechanical planarization process may be performed to remove at least one memory level metal material from above the memory level dielectric layer 170. The remaining portion of the at least one memory level metal material fills the interconnect cavity in the memory array region 100 including the array contact metal interconnect structure 664. The remaining portion of the at least one memory level metal material filling the interconnect cavity in the peripheral region 200 includes a peripheral metal interconnect structure 666. The metal interconnect structure 664 and the peripheral metal interconnect structure 666 are collectively referred to as the memory level metal interconnect structure 666.

[0085] Typically, a first metal interconnect structure embedded in the first dielectric material layer may be formed before forming the memory cell two-dimensional array 150. Each first metal interconnect structure may contact the bottom surface of a corresponding first electrode 126 in the memory cell two-dimensional array 150. A second metal interconnect structure (e.g., an array contact metal interconnect structure 664) embedded in a second dielectric material layer (e.g., a memory level dielectric layer 170) may be formed on the surface of a corresponding one of the second electrodes 158 on top. Typically, each first electrode 126 may be electrically connected to a node of an electrical switch, which may include one of the field effect transistors located on a semiconductor substrate (e.g., substrate 9). Similarly, each second electrode 158 may be electrically connected to a node of an electrical switch, which may include another field effect transistor located on a semiconductor substrate (e.g., substrate 9).

[0086] refer to Figure 7, by omitting the formation of the dielectric diffusion barrier spacer 156, a first alternative configuration of the first exemplary structure may be obtained from Figure 6 The first exemplary structure shown is derived. In this embodiment, the memory level dielectric layer 170 may include a hydrogen diffusion barrier dielectric material, such as silicon nitride. Alternatively, the memory level dielectric layer 170 may include a layer stack including a hydrogen diffusion barrier material liner (e.g., a silicon nitride liner) and an interlayer dielectric material layer (e.g., undoped silicate glass, doped silicate glass, organic silicate glass, or a porous dielectric material).

[0087] refer to Figure 8 A second alternative configuration of the first exemplary structure can be derived from the first exemplary structure by forming a combination of a permeable dielectric spacer 256 and a dielectric diffusion barrier spacer 156 in place of each dielectric diffusion barrier spacer 156. Figure 4 After removing the photoresist layer 177 from the first exemplary structure shown, a permeable dielectric material layer through which hydrogen atoms can permeate can be conformally formed. The permeable dielectric material layer may include a dielectric material, such as silicon oxide, organic silicate glass, or a porous dielectric material. Anisotropic etching may be performed to remove horizontal portions of the permeable dielectric material layer, and each remaining vertically extending portion of the permeable dielectric material layer constitutes a permeable dielectric spacer 256. The lateral thickness of each permeable dielectric spacer 256 between the inner sidewall and the outer sidewall may range from 1 nm to 50 nm, such as 3 nm to 20 nm, but smaller and larger thicknesses may also be used. The top surface of the permeable dielectric spacer 256 may be located below the horizontal plane including the top surface of the second electrode 158 to facilitate the subsequently formed dielectric diffusion barrier spacer 156 to cover the top of the permeable dielectric spacer 256.

[0088] Then, you can execute Figure 5 The processing steps are repeated to form an array of dielectric diffusion barrier spacers 156. Each dielectric diffusion barrier spacer 156 can encapsulate a corresponding one of the permeable dielectric spacers 256. Subsequently, a dielectric diffusion barrier spacer 156 can be formed. Figure 6 In this configuration, the permeable dielectric spacer 256 serves as an additional reservoir for hydrogen atoms, while the dielectric diffusion barrier spacer 156 serves as an encapsulation structure that prevents hydrogen atoms from escaping from each memory cell 150. For each memory cell 150 that includes a pillar structure, the permeable dielectric spacer 256 including a hydrogen permeable dielectric material may contact and may laterally surround the pillar structure, and the dielectric diffusion barrier spacer 156 including a hydrogen diffusion barrier material may contact and may laterally surround the permeable dielectric spacer 256.

[0089] refer to Fig. 9, by reversing the positions of the semiconductor metal oxide layer 130 and the hydrogen-containing metal layer 140, a third alternative configuration of the first exemplary structure can be obtained from Figure 6 The first exemplary structure shown is derived. Generally, the hydrogen-containing metal layer 140 can be covered on the semiconductor metal oxide layer 130, and each layer stacks the hydrogen-containing metal layer 140 and the semiconductor metal oxide layer 130 as shown in FIG. Figure 6 As shown, or as Figure 6 The hydrogen-containing metal layer 140 of each stack of the illustrated hydrogen-containing metal layer 140 and the semiconductor metal oxide layer 130 may be located below the semiconductor metal oxide layer 130. Depending on whether the hydrogen-containing metal layer 140 is above or below the semiconductor metal oxide layer 130, the polarity of the program pulse may be reversed during programming.

[0090] refer to Fig.10 By using multiple hydrogen-containing metal layers 140, Figures 6 to 10 Any configuration of the first exemplary structure shown in derives a fourth alternative configuration of the first exemplary structure. For the purpose of programming each memory cell 150, asymmetry across the first electrode 126 and the second electrode 158 can be introduced by using hydrogen-containing metal layers 140 of different thicknesses. The memory cell 150 may include a single hydrogen-containing metal layer 140, or may include multiple hydrogen-containing metal layers 140. In one embodiment, the at least one hydrogen-containing metal layer 140 within each memory cell 150 may include multiple hydrogen-containing metal layers 140, and one or more of the at least one semiconductor metal oxide layer 130 (which may be a single semiconductor metal oxide layer 130 or multiple semiconductor metal oxide layers 130) and / or each 130 may contact two of the multiple hydrogen-containing metal layers 140.

[0091] refer to Fig.11 By using a staggered stack of at least two hydrogen-containing metal layers 140 and at least two semiconductor metal oxide layers 130, Figures 6 to 10Any configuration of the first exemplary structure shown in derives a fifth alternative configuration of the first exemplary structure. The thickness of each hydrogen-containing metal layer 140 can be in the range of 1 nm to 30 nm, such as from 2 nm to 15 nm, although smaller and larger thicknesses can also be used. The thickness of each semiconductor metal oxide layer 130 can be in the range of 1 nm to 30 nm, such as from 2 nm to 15 nm, although smaller and larger thicknesses can also be used. Asymmetry across the first electrode 126 and the second electrode 158 for the purpose of programming each memory cell 150 can be introduced by tailoring the thickness of each layer within the staggered layer stack of at least two hydrogen-containing metal layers 140 and at least two semiconductor metal oxide layers 130. For example, the thickness of each hydrogen-containing metal layer 140 can decrease with the distance from the first electrode 126, and the thickness of each semiconductor metal oxide layer 130 can increase with the distance from the first electrode, or vice versa.

[0092] refer to Fig. 12A and Fig. 12B , shows a second exemplary structure that can be used to form a semiconductor device such as a field effect transistor that can store a memory bit in the form of a resistance state of a channel region. A semiconductor metal oxide layer 30 can be formed over the dielectric material layer 20. The dielectric material layer 20 can be Figure 1 The dielectric material layer 20 may be any one of the contact level dielectric material layer 601, the first metal line level dielectric material layer 610, the second line and via level dielectric material layer 620, the third line and via level dielectric material layer 630, and the fourth line and via level dielectric material layer 640. Figure 1 A first exemplary structure or Figures 6 to 11 Any dielectric material layer above the first exemplary structure of. In this embodiment, the area where the second exemplary structure is formed is selected so that there is no metal interconnection structure on the portion of the dielectric material layer 20 on which the second exemplary structure is formed. Alternatively, a contact via structure (not shown) and a metal line (not shown) can be formed on the upper portion of the dielectric material layer 20 so that the contact via structure or the metal line contacts the source region or drain region of the field effect transistor. Optionally, the dielectric material layer 20 may include a portion of a shallow trench isolation structure 720 that extends over a relatively large area such as a device area. Alternatively, the dielectric material layer 20 may be provided as an insulating material layer deposited on a substrate such as a semiconductor substrate. Alternatively, the dielectric material layer 20 may be provided as part of an insulating substrate. Although only a single field effect transistor is shown to describe the semiconductor device of the second embodiment of the present disclosure, embodiments in which an array of field effect transistors (e.g., a two-dimensional array of field effect transistors) is formed on a substrate are clearly contemplated.

[0093] The semiconductor metal oxide layer 30 may have the same material composition as the semiconductor metal oxide material layer 130L of the first exemplary structure, and may be formed by the same deposition process (e.g., physical vapor deposition process). The thickness of the semiconductor metal oxide layer 30 may be in the range of from 1 nm to 100 nm, for example, from 2 nm to 50 nm and / or from 4 nm to 25 nm, but smaller and larger thicknesses may also be used. The semiconductor metal oxide layer 30 may be patterned, for example, by applying a photoresist layer (not shown) on the semiconductor metal oxide layer 30, patterning the photoresist layer by photolithography to include discrete photoresist material portions, and by etching portions of the unmasked semiconductor metal oxide layer 30. The semiconductor metal oxide layer 30 patterned by the etching process may have a length along the first hierarchical direction hd1 and a width along the second hierarchical direction hd2. The length may be in the range of from 50 nm to 1 micron, and the width may be in the range of from 30 nm to 1 micron, but smaller and larger lengths and widths may also be used. The photoresist layer may then be removed, for example, by ashing. A suitable cleaning process may be optionally performed.

[0094] refer to Fig.13A and Fig. 13B , a blanket hydrogen-containing metal layer and a gate electrode material layer may be deposited over the semiconductor metal oxide layer 30. The blanket hydrogen-containing metal layer and the gate electrode material layer may be deposited as a blanket material layer, i.e., a material layer without a pattern. The blanket hydrogen-containing metal layer of the second exemplary structure may have the same material composition as the hydrogen-containing metal layer 140L of the first exemplary structure, and may be formed by the same deposition process (e.g., a physical vapor deposition process). The thickness of the blanket hydrogen-containing metal layer of the second exemplary structure may be in a range from 1 nm to 100 nm, for example from 2 nm to 50 nm and / or from 4 nm to 25 nm, but smaller and larger thicknesses may also be used.

[0095] The gate electrode material layer includes a metal gate electrode material. In one embodiment, the gate electrode material layer includes any metal material that can be used for the first electrode material layer or the second electrode material layer in the first exemplary structure. For example, the gate electrode material layer may include and / or may be substantially composed of a conductive metal nitride material and / or an elemental metal and / or an intermetallic alloy. For example, the conductive metal nitride material that can be used for the gate electrode material layer includes TiN, TaN or WN. The elemental metals that can be used for the gate electrode material layer include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co and Ni. Typically, elemental metals that prevent hydrogen diffusion can be used for the gate electrode material layer. In one embodiment, a refractory metal having a melting point higher than 2000 degrees Celsius can be used for the gate electrode material layer. The gate electrode material layer can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the gate electrode material layer can be in the range of from 50nm to 200nm, but smaller and larger thicknesses can also be used. A stack of multiple metal layers can be used as the gate electrode material layer.

[0096] A photoresist layer (not shown) may be applied on the gate electrode material layer and may be photolithographically patterned into a gate pattern. For example, a rectangular region extending through the middle portion of the semiconductor metal oxide layer 30 may be used as a masking region for the gate pattern. An anisotropic etching process may be performed to etch the gate electrode material layer and the unmasked portion of the blanket hydrogen-containing metal layer. In one embodiment, the anisotropic etching process may include a first anisotropic etching step of etching the unmasked portion of the gate electrode material layer, which is selective to the material of the blanket hydrogen-containing metal layer, and a second anisotropic etching step, which is selective to the material of the semiconductor metal oxide layer 30 to etch the unmasked portion of the blanket hydrogen-containing metal layer. The photoresist layer may then be removed, for example, by ashing.

[0097] The remaining portion of the gate electrode material layer covering the semiconductor metal oxide layer 30 includes a gate electrode 50. The remaining portion of the blanket hydrogen-containing metal layer below the gate electrode 50 includes a hydrogen-containing metal layer 40, which is incorporated into a semiconductor device of the second exemplary structure. The gate stack of the hydrogen-containing metal layer 40 and the gate electrode 50 can span the central portion of the semiconductor metal oxide layer 30 along the second hierarchical direction hd2. The dimension of the gate stack (40, 50) along the first hierarchical direction hd1 is referred to herein as a gate length, which can be in the range of 10nm to 300nm, for example 30nm to 100nm, but smaller and larger gate lengths can also be used.

[0098] The hydrogen-containing metal layer 40 is located on the surface of the semiconductor metal oxide layer 30, and includes and / or is substantially composed of at least 90% of at least one metal selected from platinum, iridium, osmium and ruthenium and hydrogen atoms in the atomic percentage range of 0.001% to 10% (e.g., from 0.01% to 5% and / or from 0.1% to 3%). The gate electrode 50 is located on the hydrogen-containing metal layer 40. The sidewalls of the gate electrode 50 and the sidewalls of the hydrogen-containing metal layer 40 may overlap vertically, that is, they may be located in a common vertical plane.

[0099] refer to Fig.14A and Fig. 14B , suitable electrical dopants may be implanted into the unmasked portion of the semiconductor metal oxide layer 30 by performing an ion implantation process. During the ion implantation process, the gate electrode 50 may be used as an ion implantation mask. Electrical dopants that may form excess holes or excess electrons in the implanted portion of the semiconductor metal oxide layer 30 include, but are not limited to, Na, K, Mg, Ca, Sr, Y, La, B, Al, Ga, N, P, As, Sb, F, Cl, and other elements that may cause hole or excess electron formation in the semiconductor metal oxide layer 30. Alternatively or additionally, plasma treatment may be optionally performed to improve the electrical properties of the semiconductor metal oxide material in the semiconductor metal oxide layer 30. The source region 32 is formed on one side of the semiconductor metal oxide layer 30, and the drain region 38 is formed on the other side of the semiconductor metal oxide layer 30. The semiconductor metal oxide layer 30 constitutes a channel region 35 located below the gate electrode 50.

[0100] The dielectric diffusion barrier material layer can be conformally deposited on the gate electrode 50 and the semiconductor metal oxide layer 30 by a conformal deposition process such as a chemical vapor deposition process. The dielectric diffusion barrier material layer includes a hydrogen diffusion barrier material layer that blocks hydrogen diffusion. For example, the dielectric diffusion barrier material can include silicon nitride. The thickness of the dielectric diffusion barrier material layer can be in the range of from 5nm to 50nm, for example from 10nm to 25nm, but smaller and larger thicknesses can also be used.

[0101] An anisotropic etching process may be performed to remove horizontal portions of the dielectric diffusion barrier material layer. The remaining vertically extending portion of the dielectric diffusion barrier material layer includes a dielectric diffusion barrier spacer 56, which contacts and laterally surrounds the gate stack (40, 50) including the hydrogen-containing metal layer 40 and the gate electrode 50. The hydrogen-containing metal layer 40 serves as a hydrogen reservoir for the channel region 35. Hydrogen atoms may be injected from the hydrogen-containing metal layer 40 into the channel region 35 to program the channel region 35 to a hydrogenated state. In addition, hydrogen atoms may be extracted from the channel region 35 into the hydrogen-containing metal layer 40 to program the channel region 35 to a dehydrogenated state. The gate electrode 50 may include a metal material that prevents hydrogen atoms from diffusing therefrom. The dielectric diffusion barrier spacer 56 serves as a shell that prevents hydrogen atoms from escaping from the field effect transistor.

[0102] Typically, programming the channel region 35 of the field effect transistor to the hydrogenated state may be achieved by applying a first programming pulse to the gate electrode 50, the first programming pulse having a first polarity with respect to the source region 32 and / or with respect to the drain region 38. Programming the channel region 35 of the field effect transistor to the dehydrogenated state may be achieved by applying a second programming pulse to the gate electrode 50, the second programming pulse having a second polarity opposite to the first polarity with respect to the source region 32 and / or with respect to the drain region 38. In one embodiment, during programming the channel region 35 to the hydrogenated state or into the dehydrogenated state, the source region 32 and the drain region 38 may be biased with the same voltage.

[0103] In one embodiment, the hydrogenated state of the channel region 35 includes hydrogen atoms at a high atomic concentration, which may be in a range from 0.001% to 10%, such as from 0.01% to 5% and / or from 0.1% to 3%. The dehydrogenated state of the channel region 35 includes hydrogen atoms at a low atomic concentration, which may be in a range from 0.0001% to 3.3%, such as from 0.001% to 1.67% and / or from 0.01% to 1%. Typically, the ratio of the atomic percentage of hydrogen atoms in the hydrogenated state of the channel region 35 of the semiconducting metal oxide layer 30 to the atomic percentage of hydrogen atoms in the dehydrogenated state of the channel region 35 of the semiconducting metal oxide layer may be in a range of 3-100, such as 5-10, although smaller and larger ratios may also be used.

[0104] refer to Fig.15A and Fig. 15B , a dielectric material layer may be deposited over the gate electrode 50 and the semiconductor metal oxide layer 30. The dielectric material layer is referred to herein as a contact via level dielectric layer 70. The contact via level dielectric layer 70 may include a planarizable dielectric material (e.g., undoped silicate glass or doped silicate glass) or a self-planarizing dielectric material (e.g., flowable oxide (FOX)). Optionally, a chemical mechanical planarization process may be performed to planarize the top surface of the contact via level dielectric layer 70.

[0105] A contact via cavity may be formed by a contact via level dielectric layer 70. The top surface of the source region 32, the top surface of the drain region 38, and the top surface of the gate electrode 50 may be physically exposed to the bottom of the contact via cavity. At least one conductive material, such as a conductive metal liner material (e.g., TiN, TaN, and / or WN) and a conductive metal filling material (e.g., W, Cu, Co, Mo, Ru, another elemental metal, or an intermetallic alloy) may be deposited in the contact via cavity. Physical vapor deposition, chemical vapor deposition, electroplating, and / or chemical plating may be used to deposit the at least one conductive material. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact via level dielectric layer 70 by a planarization process such as a groove etch and / or a chemical mechanical planarization process. The remaining portion of the at least one conductive material filling the contact via cavity includes a source contact via structure 72, a drain contact via structure 78, and a gate contact via structure 75. The source contact via structure 72 may contact the source region 32 , the drain contact via structure 78 may contact the drain region 38 , and the gate contact via structure 75 may contact the gate electrode 50 .

[0106] refer to Fig.16A and Fig. 16B By omitting the formation of the dielectric diffusion barrier spacer 56, it is possible to Fig.15A and Fig. 15B The first alternative configuration of the second exemplary structure is derived from the second exemplary structure of FIG. In this embodiment, the contact via level dielectric layer 70 may include a hydrogen diffusion barrier material such as silicon oxide. Alternatively, the contact via level dielectric layer 70 may include a stack including a hydrogen diffusion barrier material liner (e.g., a silicon nitride liner) and an interlayer dielectric material layer (e.g., undoped silicate glass, doped silicate glass, organic silicate glass, or a porous dielectric material).

[0107] refer to Fig.17A and Fig. 17B By forming a combination of a permeable dielectric spacer 456 and a dielectric diffusion barrier spacer 56 instead of the dielectric diffusion barrier spacer 56 in the second exemplary structure, it is possible to obtain Fig.15A and Fig. 15BThe second exemplary structure in the embodiment derives a second alternative configuration of the second exemplary structure. In the present embodiment, after forming the source region 32 and the drain region 38, a permeable dielectric material layer through which hydrogen atoms can permeate can be conformally formed directly on the sidewalls of the gate stack (40, 50). The permeable dielectric material layer may include a dielectric material, such as silicon oxide, organic silicate glass, or a porous dielectric material. Anisotropic etching may be performed to remove a horizontal portion of the permeable dielectric material layer, and each remaining vertical extension of the permeable dielectric material layer constitutes a permeable dielectric spacer 456. The lateral thickness between the inner sidewall and the outer sidewall of each permeable dielectric spacer 456 may range from 1 nm to 50 nm, such as 3 nm to 20 nm, but smaller and larger thicknesses may also be used. The top surface of the permeable dielectric spacer 456 may be located below a horizontal plane including the top surface of the gate electrode 50 to facilitate the top of the permeable dielectric spacer 456 to be covered by a subsequently formed dielectric diffusion barrier spacer 56.

[0108] Subsequently, dielectric diffusion barrier spacers 56 may be formed on the permeable dielectric spacers 456. Each dielectric diffusion barrier spacer 56 may encapsulate a corresponding one of the permeable dielectric spacers 456. Fig.15A and Fig. 15B In this configuration, the permeable dielectric spacer 456 serves as an additional reservoir for hydrogen atoms, and the dielectric diffusion barrier spacer 56 serves as a packaging structure to prevent hydrogen atoms from escaping from each field effect transistor. The permeable dielectric spacer 456 comprising a hydrogen permeable dielectric material may contact and may laterally surround the gate stack (40, 50), and the dielectric diffusion barrier spacer 56 comprising a hydrogen diffusion barrier material may contact and may laterally surround the permeable dielectric spacer 456.

[0109] refer to Fig.18A and Fig.18B By forming a groove in the dielectric material layer 20 before forming the semiconductor metal oxide layer 30, and by filling the groove with a metal line forming the backside gate electrode 350 of the field effect transistor, it is possible to FIG. 15A to FIG. 17B Any configuration of the second exemplary structure shown in derives a third alternative configuration of the second exemplary structure. In an embodiment, the dielectric material layer 20 is an interconnect level dielectric material layer located in a back-end process structure, such as Figure 1As shown in the contact level dielectric material layer 601, the first metal line level dielectric material layer 610, the second line and via level dielectric material layer 620, the third line and via level dielectric material layer 630, or the fourth line and via level dielectric material layer 640, the backside gate electrode 350 can be formed simultaneously with the metal line structure embedded in the interconnect level dielectric material layer, such as the first metal line structure 618, the second metal line structure 628, the third metal line structure 638, or the fourth metal line structure 648. In addition, it is expressly contemplated that the backside gate electrode 350 includes an embodiment of a metal line structure in an upper metal interconnect structure covering the fourth line and via level dielectric material layer 640. The dielectric material layer 20 may include a shallow trench isolation structure.

[0110] The thickness of the backside gate electrode 350 can be in the range of from 20nm to 200nm, but smaller and larger thicknesses can also be used. The backside gate electrode 350 can include a metal that prevents hydrogen diffusion. For example, the backside gate electrode 350 can include a conductive metal nitride material and / or an elemental metal and / or an intermetallic alloy. For example, the conductive metal nitride material that can be used for the backside gate electrode 350 includes TiN, TaN or WN. The elemental metals that can be used for the backside gate electrode 350 include, but are not limited to, W, Ta, Re, Nb, Mb, Ru, Co and Ni. Typically, elemental metals that prevent hydrogen diffusion can be used for the backside gate electrode 350. In one embodiment, a refractory metal with a melting point higher than 2,000 degrees Celsius can be used for the backside gate electrode 350. The semiconductor metal oxide layer 30 can be formed above the planarized top surface of the backside gate electrode 350. The area of ​​the backside gate electrode 350 can overlap with the area of ​​the gate electrode 50. The combination of the gate electrode 50 and the backside gate electrode 350 provides a dual-gate configuration that can more strictly control the threshold voltage. The backside gate electrode 350 can provide a variable channel bias voltage to compensate for drift of transistor characteristics of the field effect transistor including the source region 32 , the drain region 38 , the channel region 35 , the hydrogen-containing metal layer 40 , and the gate electrode 50 , which may be caused by gradual loss of hydrogen atoms during long-term use.

[0111] refer to Fig.19A and Fig.19B By forming a recessed trench in the dielectric material layer 20, by forming a backside dielectric diffusion barrier spacer 356 including a hydrogen-blocking dielectric material (e.g., silicon nitride) around the sidewalls of the recessed trench, and by forming a stack of a backside gate electrode 350 and a backside hydrogen-containing metal layer 340 within the recessed trench, the backside gate electrode 350 can be formed. FIG. 15A to FIG. 17B Any configuration of the second exemplary structure shown in derives a fourth alternative configuration of the second exemplary structure.

[0112] The backside dielectric diffusion barrier spacer 356 may be formed by conformally depositing a backside dielectric diffusion barrier layer and anisotropically etching the backside dielectric diffusion barrier layer. The backside gate electrode 350 may be formed by depositing at least one conductive material in a cavity laterally surrounded by the backside dielectric diffusion barrier spacer 356, and by vertically recessing the at least one conductive material below a horizontal plane including its top surface. The dielectric material layer 20 is removed by using a planarization process including a recess etching process. For example, a chemical mechanical planarization process may be used to remove a portion of the at least one conductive material from above a horizontal plane including the top surface of the dielectric material layer 20, and a recess etching process may be performed to vertically recess the top surface of the remaining portion of the at least one conductive material. The remaining portion of the at least one conductive material in the recessed trench constitutes the backside gate electrode 350. The recess depth may be the same as the thickness of the backside hydrogen-containing metal layer 340 formed subsequently. For example, the recess depth may be in the range of from 1 nm to 100 nm, such as from 2 nm to 50 nm and / or from 4 nm to 25 nm, although smaller and larger recess depths may also be used. The backside gate electrode 350 may include Fig.18A and Fig.18B The same materials are shown in the third alternative configuration of the second exemplary structure.

[0113] The backside hydrogen-containing metal layer 340 may be formed by using the same processing steps as used to form the hydrogen-containing metal layer 140L in the first exemplary structure. The backside hydrogen-containing metal layer 340 may have the same material composition and the same thickness range as any hydrogen-containing metal layer 140L that may be used in the first exemplary structure. Subsequently, the backside hydrogen-containing metal layer 340 may be formed by using the same processing steps as used to form the hydrogen-containing metal layer 140L in the first exemplary structure. FIG. 12A to FIG. 17B The processing steps to provide FIG. 12A to FIG. 17B A fourth configuration of the second exemplary structure is shown.

[0114] refer to FIG. 12A to FIG. 18B and related drawings, according to an embodiment of the present invention, there is provided a semiconductor device, which includes a semiconductor metal oxide layer 30 located on a dielectric material layer 20, including a source region 32, a drain region 38, and a channel region 35 located between the source region 32 and the drain region 38; a hydrogen-containing metal layer 40 is located on the surface of the channel region 35, including at least 90% atomic percentage of at least one metal selected from platinum, iridium, osmium and ruthenium, and including hydrogen atoms and a gate electrode 50 located on the hydrogen-containing metal layer 40.

[0115] In one embodiment, the semiconductor device includes a dielectric diffusion barrier spacer 56 that includes a hydrogen diffusion barrier material and contacts and laterally surrounds the hydrogen-containing metal layer 40 and the gate electrode 50 .

[0116] In one embodiment, the semiconductor device includes a permeable dielectric spacer 456, which includes a hydrogen permeable dielectric material and contacts and laterally surrounds the gate electrode 50 and the hydrogen-containing metal layer 40; and a dielectric diffusion barrier spacer 56, which includes a hydrogen diffusion barrier material and contacts and laterally surrounds the permeable dielectric spacer 456.

[0117] In one embodiment, the semiconductor device includes: a backside gate electrode 350 embedded in the dielectric material layer 20; a backside hydrogen-containing metal layer 340, including at least one additional metal selected from platinum, iridium, osmium and ruthenium, with an atomic percentage of at least 90% and including 0.001% to 10% of hydrogen atoms, and located between the bottom surface of the channel region 35 and the backside gate electrode 350. The at least one additional metal can be the same as or different from the at least one metal of the hydrogen-containing metal layer 40.

[0118] In one embodiment, the semiconductor device includes a backside gate electrode 350 embedded in the dielectric material layer 20 and in contact with a backside surface of the channel region 35 .

[0119] refer to Fig. 20 , the flowchart illustrates the general processing steps of the method for manufacturing the memory device of the first embodiment of the present disclosure. Referring to step 2010 and Figure 1 and Figure 2 , a dielectric material layer (eg, connecting via level dielectric layer 110, fourth line and via level dielectric material layer 640, any other interconnect level dielectric layer or shallow trench isolation structure 720) is formed over substrate 9. See steps 2020 and Figure 3 The material layer stack (126L, 130, 140L, 158L) includes a first electrode material layer 126L, at least one semiconductor metal oxide material layer 130L, at least one hydrogen-containing metal layer 140L, and a second electrode material layer 158L that can be formed above the dielectric material layer 20. Referring to steps 2030 and Figure 4 , the material layer stack (126L, 130, 140L, 158L) may be patterned into at least one pillar structure including the first electrode 126, the memory layer stack (130, 140) and the second electrode 158. Subsequently, Figures 5 to 11 The processing steps.

[0120] refer to Fig.21 , the flowchart shows the general processing steps of the method for manufacturing a semiconductor device (which may be a memory device) according to the second embodiment of the present disclosure. Referring to step 2110, Fig. 12A and Fig. 12B , Fig.18A and Fig.18B ,as well as Fig.19A and Fig.19B, forming a semiconductor metal oxide layer 30 on the dielectric material layer 20. Referring to steps 2120 and Fig.13A and Fig. 13B , Fig.18A and Fig.18B as well as Fig.19A and Fig.19B , a hydrogen-containing metal layer 40 and a gate electrode 50 may be formed on the semiconductor metal oxide layer 30. Fig.14A and Fig. 14B , Fig.18A and Fig.18B as well as Fig.19A and Fig.19B , a source region 32 and a drain region 38 may be formed in the semiconductor metal oxide layer 30. Subsequently, FIG. 14A to FIG. 19B additional processing steps.

[0121] refer to Fig. 22 , the flowchart shows the general steps for operating the semiconductor device of the present disclosure, the semiconductor device can be any one of the first exemplary structure and the second exemplary structure. Referring to step 2210 and Figures 6 to 11 and FIG. 15A to FIG. 19B , the semiconductor device includes a layer stack {(130, 140) or (30, 40)} between a first electrode (126 or 32) and a second electrode (158 or 38), wherein the layer stack includes at least one semiconductor metal oxide layer (130 or 30), and at least one hydrogen-containing metal layer (140 or 40) is provided on the dielectric material layer {(110 or 640) or 20}. In the second exemplary structure, the source region 32 serves as the first electrode and the drain region serves as the second electrode. Each of the at least one hydrogen-containing metal layers (140 or 40) includes at least one metal selected from platinum, iridium, osmium and ruthenium, the atomic percentage of which is at least 90%, and includes hydrogen atoms in an atomic percentage ranging from 0.001% to 10%.

[0122] Referring to step 2220, the semiconductor device may be programmed to a hydrogenated state or a dehydrogenated state by applying a programming pulse across the first electrode 126 and the second electrode 158 or across the gate electrode 50 located on at least one hydrogen-containing metal layer 40 and one of the first electrode (including the source region 32) and the second electrode (including the drain region 38). The hydrogenated state is a state in which at least one semiconductor metal oxide layer (130, 30) is impregnated with hydrogen atoms, and the dehydrogenated state is a state in which at least one semiconductor metal oxide layer (130, 30) is hydrogen-deficient. Referring to step 2230, the memory state of the semiconductor device may be determined by measuring the conductance of a measurement current path between the first electrode (126 or 32) and the second electrode (158 or 38) under a measurement bias condition.

[0123] In a first embodiment, a current path extending through each layer in the layer stack (130, 140) in a direction perpendicular to each interface between each pair of adjacent layers in the layer stack semiconductor metal oxide is measured. A sense amplifier can be used to measure the magnitude of the measured current and determine the memory state of the memory cell 150. In one embodiment, programming the semiconductor device to the hydrogenated state includes applying a first programming pulse having a first polarity to the second electrode 158 relative to the first electrode 126, and programming the semiconductor device to the dehydrogenated state includes applying a second programming pulse having a second polarity opposite to the first polarity to the second electrode 158 relative to the first electrode 126.

[0124] In the second embodiment, at least one semiconductor metal oxide layer includes a semiconductor metal oxide layer 30 including a source region 32 (as a first electrode), a drain region 38 (as a second electrode), and a channel region 35 located between the source region 32 and the drain region 38. The first electrode includes the source region 32, and the second electrode includes the drain region 38. The conductive path extends through the channel region 35 in a direction parallel to an interface between the channel region 35 and at least one hydrogen-containing metal layer 40 in contact with the channel region 35. A sense amplifier can be used to measure the magnitude of the measurement current and determine the memory state of the semiconductor device, which includes a field effect transistor with a variable threshold voltage modulated by the hydrogen level in the channel region 35.

[0125] In one embodiment, programming the semiconductor device to the hydrogenated state includes applying a first programming pulse having a first polarity to the gate electrode 50 relative to one (or both) of the first electrode (including the source region 32) and the second electrode (including the drain region 38); programming the semiconductor device to the dehydrogenated state includes applying a second programming pulse having a second polarity opposite to the first polarity to the gate electrode 50 relative to one (or both) of the first electrode and the second electrode.

[0126] Various embodiments of the present disclosure provide semiconductor metal oxide memory devices using hydrogen-mediated threshold voltage modulation. Specifically, the amount of hydrogen in at least one semiconductor metal oxide layer (130, 30) determines the conductivity of at least one semiconductor metal oxide layer (130, 30) and provides a hydrogen-mediated threshold voltage for the semiconductor metal oxide memory device. The current flowing through at least one semiconductor metal oxide layer (130, 30) can be higher or lower than a predetermined threshold level, depending on whether at least one semiconductor metal oxide layer (130, 30) is in a hydrogenated state or in a dehydrogenated state. Therefore, at least one semiconductor metal oxide layer (130, 30) can encode bits in a non-volatile and reversible manner. The device of the present disclosure can provide a non-volatile memory device with a long life.

[0127] In some embodiments, a memory device includes: a first electrode; a memory layer stack located on the first electrode and including at least one semiconductor metal oxide layer and at least one hydrogen-containing metal layer, the hydrogen-containing metal layer including at least 90 atomic percent of at least one metal selected from platinum, iridium, osmium and ruthenium and including hydrogen atoms; and a second electrode located above the memory layer stack.

[0128] The memory device further comprises: a first metal interconnect structure embedded in the first dielectric material layer and contacting the bottom surface of the first electrode; and a second metal interconnect structure embedded in the second dielectric material layer and contacting the top surface of the second electrode.

[0129] In the above-mentioned memory device, it also includes: a semiconductor substrate located below the first dielectric material layer; and a field effect transistor located on the semiconductor substrate, wherein the first electrode or the second electrode is electrically connected to one of the field effect transistors through an additional metal interconnection structure located between the semiconductor substrate and the first dielectric material layer.

[0130] In the above memory device, each of the at least one semiconductor metal oxide layer contacts a horizontal surface of a corresponding one of the at least one hydrogen-containing metal layer.

[0131] In the above-mentioned memory device, the memory layer stack includes a single semiconductor metal oxide layer and a single hydrogen-containing metal layer in contact with each other; the single semiconductor metal oxide layer contacts one of the first electrode and the second electrode; and the single hydrogen-containing metal layer contacts the other of the first electrode and the second electrode, wherein the single hydrogen-containing metal layer includes hydrogen atoms with an atomic percentage of less than 10%.

[0132] In the above memory device, the at least one hydrogen-containing metal layer includes a plurality of hydrogen-containing metal layers; and one of the at least one semiconductor metal oxide layer contacts two of the plurality of hydrogen-containing metal layers.

[0133] In the above memory device, the memory layer stack includes an alternating layer stack of at least two hydrogen-containing metal layers and at least two semiconductor metal oxide layers.

[0134] In the above-mentioned memory device, the combination of the first electrode, the memory layer stack and the second electrode includes a column structure, the top surface of the column structure is the top surface of the second electrode, the bottom surface is the bottom surface of the first electrode, and the side wall extends straight between the periphery of the top surface of the second electrode and the periphery of the bottom surface of the first electrode.

[0135] In the above memory device, a dielectric diffusion barrier spacer is further included, which includes a hydrogen diffusion barrier material and laterally surrounds the contact pillar structure.

[0136] In the above memory device, it also includes: a permeable dielectric spacer including a hydrogen permeable dielectric material and laterally surrounding the contact pillar structure; and a dielectric diffusion barrier spacer including a hydrogen diffusion barrier material and laterally surrounding the contact permeable dielectric spacer.

[0137] In some embodiments, a semiconductor device includes: a semiconductor metal oxide layer, which is located on a dielectric material layer and includes a source region, a drain region and a channel region located between the source region and the drain region; a hydrogen-containing metal layer, which is located on the surface of the channel region and includes at least 90 atomic percent of at least one metal selected from platinum, iridium, osmium and ruthenium and includes hydrogen atoms; and a gate electrode, which is located on the hydrogen-containing metal layer.

[0138] In the above semiconductor device, a dielectric diffusion barrier spacer is further included, the dielectric diffusion barrier spacer includes a hydrogen diffusion barrier material and laterally surrounds the contact hydrogen-containing metal layer and the gate electrode.

[0139] In the above semiconductor device, it also includes: a permeable dielectric spacer including a hydrogen permeable dielectric material and laterally surrounding the contact gate electrode and the hydrogen-containing metal layer; and a dielectric diffusion barrier spacer including a hydrogen diffusion barrier material and laterally surrounding the contact permeable dielectric spacer.

[0140] In the above-mentioned semiconductor device, it also includes: a back gate electrode, embedded in the dielectric material layer; and a back hydrogen-containing metal layer, including at least 90 atomic percent of at least one additional metal selected from platinum, iridium, osmium and ruthenium and including less than 10 atomic percent of hydrogen atoms, and located between the bottom surface of the channel region and the back gate electrode, wherein at least one additional metal is the same as or different from at least one metal of the hydrogen-containing metal layer.

[0141] In the above semiconductor device, it also includes a backside gate electrode embedded in the dielectric material layer and in contact with the backside surface of the channel region.

[0142] In some embodiments, a method of operating a semiconductor device includes: providing a semiconductor device including a layer stack located between a first electrode and a second electrode, wherein the layer stack includes at least one semiconductor metal oxide layer and at least one hydrogen-containing metal layer located above a dielectric material layer, wherein each of the at least one hydrogen-containing metal layer includes at least 90 atomic percent of at least one metal selected from platinum, iridium, osmium and ruthenium and includes hydrogen atoms; programming the semiconductor device to a hydrogenated state or a dehydrogenated state by applying a programming pulse across the first electrode and the second electrode or across a gate electrode located on at least one hydrogen-containing metal layer and one of the first electrode and the second electrode, wherein the hydrogenated state is a state in which at least one semiconductor metal oxide layer is impregnated with hydrogen atoms, and wherein the dehydrogenated state is a state in which at least one semiconductor metal oxide layer is hydrogen-deficient; and determining the memory state of the semiconductor device by measuring the conductance of a measurement current path between the first electrode and the second electrode under measurement bias conditions.

[0143] In the above method, the measurement current path extends through each layer in the layer stack in a direction perpendicular to each interface between each adjacent pair of layers in the layer stack.

[0144] In the above method, programming the semiconductor device to the hydrogenated state includes applying a first programming pulse having a first polarity to the second electrode relative to the first electrode; and

[0145] Programming the semiconductor device to the dehydrogenated state includes applying a second programming pulse having a second polarity opposite to the first polarity to the second electrode relative to the first electrode.

[0146] In the above method, at least one semiconductor metal oxide layer includes a semiconductor metal oxide layer including a source region, a drain region, and a channel region located between the source region and the drain region; the first electrode includes the source region, and the second electrode includes the drain region; and the measurement current path extends through the channel region along a direction parallel to an interface between the channel region and at least one hydrogen-containing metal layer, and the at least one hydrogen-containing metal layer contacts the channel region.

[0147] In the above method, programming the semiconductor device to a hydrogenated state includes applying a first programming pulse having a first polarity relative to one of the first electrode and the second electrode to a gate electrode; and programming the semiconductor device to a dehydrogenated state includes applying a second programming pulse having a second polarity opposite to the first polarity to the gate electrode of one of the first electrode and the second electrode.

[0148] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A memory device, comprising: a first electrode; a memory layer stack located on the first electrode and including at least one semiconductor metal oxide layer and at least one hydrogen-containing metal layer, the hydrogen-containing metal layer including at least 90 atomic percent of at least one metal selected from platinum, iridium, osmium and ruthenium and including hydrogen atoms; and The second electrode is located above the memory layer stack.

2. The memory device according to claim 1, further comprising: a first metal interconnect structure embedded in the first dielectric material layer and contacting a bottom surface of the first electrode; and A second metal interconnect structure is embedded in the second dielectric material layer and contacts the top surface of the second electrode.

3. The memory device according to claim 2, further comprising: A semiconductor substrate, located below the first dielectric material layer; and A field effect transistor is located on the semiconductor substrate, wherein the first electrode or the second electrode is electrically connected to one of the field effect transistors through an additional metal interconnect structure located between the semiconductor substrate and the first dielectric material layer.

4. The memory device according to claim 1, wherein: Each of the at least one semiconductive metal oxide layers contacts a horizontal surface of a corresponding one of the at least one hydrogen-containing metal layers.

5. The memory device according to claim 1, wherein: The memory layer stack includes a single semiconductor metal oxide layer and a single hydrogen-containing metal layer in contact with each other; The single semiconducting metal oxide layer contacts one of the first electrode and the second electrode; and The single hydrogen-containing metal layer contacts the other of the first electrode and the second electrode, wherein the single hydrogen-containing metal layer includes less than 10 atomic % of hydrogen atoms.

6. The memory device according to claim 1, wherein: The at least one hydrogen-containing metal layer comprises a plurality of hydrogen-containing metal layers; and One of the at least one semiconducting metal oxide layer contacts two of the plurality of hydrogen-containing metal layers.

7. The memory device according to claim 1, wherein: The memory layer stack includes an alternating layer stack of at least two hydrogen-containing metal layers and at least two semiconducting metal oxide layers.

8. The memory device according to claim 1, wherein: The combination of the first electrode, the memory layer stack and the second electrode includes a pillar structure, the top surface of the pillar structure is the top surface of the second electrode, the bottom surface is the bottom surface of the first electrode, and the side wall extends straight between the periphery of the top surface of the second electrode and the periphery of the bottom surface of the first electrode. 9 . The memory device of claim 8 , further comprising a dielectric diffusion barrier spacer comprising a hydrogen diffusion barrier material and laterally surrounding and contacting the pillar structure.

10. The memory device according to claim 8, further comprising: a permeable dielectric spacer comprising a hydrogen permeable dielectric material and laterally surrounding and contacting the pillar structure; and A dielectric diffusion barrier spacer includes a hydrogen diffusion barrier material and laterally surrounds and contacts the permeable dielectric spacer.

11. A semiconductor device comprising: A semiconductor metal oxide layer, located on the dielectric material layer, and comprising a source region, a drain region, and a channel region located between the source region and the drain region; a hydrogen-containing metal layer located on the surface of the channel region and including at least 90 atomic % of at least one metal selected from platinum, iridium, osmium and ruthenium and including hydrogen atoms; and The gate electrode is located on the hydrogen-containing metal layer. 12 . The semiconductor device of claim 11 , further comprising a dielectric diffusion barrier spacer comprising a hydrogen diffusion barrier material and laterally surrounding and contacting the hydrogen-containing metal layer and the gate electrode.

13. The semiconductor device according to claim 11, further comprising: a permeable dielectric spacer comprising a permeable hydrogen dielectric material and laterally surrounding and contacting the gate electrode and the hydrogen-containing metal layer; and A dielectric diffusion barrier spacer includes a hydrogen diffusion barrier material and laterally surrounds and contacts the permeable dielectric spacer.

14. The semiconductor device according to claim 11, further comprising: a backside gate electrode embedded in the dielectric material layer; and a back side hydrogen-containing metal layer, comprising at least 90 atomic percent of at least one additional metal selected from platinum, iridium, osmium and ruthenium and comprising less than 10 atomic percent of hydrogen atoms, and being located between the bottom surface of the channel region and the back side gate electrode, The at least one additional metal is the same as or different from the at least one metal of the hydrogen-containing metal layer. 15 . The semiconductor device according to claim 11 , further comprising a backside gate electrode embedded in the dielectric material layer and contacting a backside surface of the channel region.

16. A method for operating a semiconductor device, comprising: Providing a semiconductor device comprising a layer stack between a first electrode and a second electrode, wherein the layer stack comprises at least one semiconductor metal oxide layer and at least one hydrogen-containing metal layer located above a dielectric material layer, wherein each of the at least one hydrogen-containing metal layer comprises at least 90 atomic percent of at least one metal selected from platinum, iridium, osmium and ruthenium and comprises hydrogen atoms; Programming the semiconductor device to a hydrogenated state or a dehydrogenated state by applying a programming pulse across the first electrode and the second electrode, or across a gate electrode located on the at least one hydrogen-containing metal layer and one of the first electrode and the second electrode, wherein the hydrogenated state is a state in which the at least one semiconductor metal oxide layer is impregnated with hydrogen atoms, and wherein the dehydrogenated state is a state in which the at least one semiconductor metal oxide layer is hydrogen-deficient; and A memory state of the semiconductor device is determined by measuring the conductance of a measurement current path between the first electrode and the second electrode under measurement bias conditions.

17. The operating method according to claim 16, wherein: The measurement current path extends through each layer in the layer stack in a direction perpendicular to each interface between each adjacent pair of layers in the layer stack.

18. The operating method according to claim 17, wherein: Programming the semiconductor device to the hydrogenated state includes applying a first programming pulse having a first polarity to the second electrode relative to the first electrode; and Programming the semiconductor device to the dehydrogenated state includes applying a second programming pulse having a second polarity opposite to the first polarity to the second electrode relative to the first electrode.

19. The operating method according to claim 16, wherein: The at least one semiconductor metal oxide layer includes a semiconductor metal oxide layer including a source region, a drain region, and a channel region located between the source region and the drain region; The first electrode includes the source region, and the second electrode includes the drain region; and The measurement current path extends through the channel region in a direction parallel to an interface between the channel region and the at least one hydrogen-containing metal layer, the at least one hydrogen-containing metal layer being in contact with the channel region.

20. The operating method according to claim 19, wherein: Programming the semiconductor device to the hydrogenated state includes applying a first programming pulse having a first polarity relative to one of the first electrode and the second electrode to the gate electrode; and Programming the semiconductor device to the dehydrogenated state includes applying a second programming pulse having a second polarity opposite to the first polarity to the gate electrode of one of the first electrode and the second electrode.

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