Electrostatic discharge circuit and control method thereof, power switch circuit

Abstract

An embodiment of the present invention provides an electrostatic discharge circuit comprising: a series connection of NMOS transistors, including a first NMOS transistor operably connected in series to a second NMOS transistor; a first single-gate oxide electrostatic discharge control circuit, coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an electrostatic discharge event, the first single-gate oxide control circuit being coupled to a bus of the first NMOS transistor at a first voltage and a first node of a second voltage; a second single-gate oxide electrostatic discharge control circuit, which is operably coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an electrostatic discharge event and to turn off the second NMOS during normal operation; and a voltage divider circuit, operably connected to a first bus of the first voltage and a second bus of the ground voltage.

Description

Technical Field

[0001] The embodiments of the present invention relate to an electrostatic discharge circuit and a control method thereof, and a single-gate oxide layer level converter circuit. Background Art

[0002] There is an increasing demand for smaller devices (e.g., shorter channel lengths and lower channel lengths and gate oxide thicknesses) that can operate at higher speeds for high density and high performance integrated circuits. Continuous device shrinking in core logic circuits reduces channel lengths and reduces operating voltages, thereby reducing power consumption. Such core logic circuits from advanced technologies are often connected to conventional peripherals (e.g., I / O devices) that typically operate at higher voltages (e.g., 3.3 volts) and are supported by metal oxide semiconductor (MOS) transistors that have longer channels (e.g., 0.35 microns) and thicker gate oxides (e.g., 7 nanometers) than the core devices. Voltage input signals from I / O devices, especially from previous generations of technology, can cause damage to the core devices, which can only operate at low voltages without appropriate voltage protection devices.

[0003] In order to protect the devices in the core logic circuits, some form of electrostatic discharge (ESD) protection is usually required to absorb the current from the ESD source to ground in order to reduce the voltage level applied to the core devices. As device dimensions continue to shrink, the variability of semiconductor manufacturing processes increases, and preventing ESD damage becomes more difficult. Traditionally, so-called dual-gate or multi-gate oxide layer technology is used, that is, a combination of devices with two or more different gate thicknesses operating at different voltages. However, due to the use of multiple gate thicknesses, this conventional technology requires different mask sets for different gate oxides, which represents a major technical and economic disadvantage. Specifically, this conventional technology substantially increases the number of processing steps within the semiconductor manufacturing process, increases the cost of manufacturing integrated circuits, and ultimately may also reduce production yields. Therefore, there is a need for a circuit that can be used at a lower supply voltage while also using a single oxide layer technology to withstand higher input signal voltages from input / output (I / O) devices to minimize manufacturing steps and reduce costs. Summary of the invention

[0004] Some embodiments of the present application provide a device characterized by comprising: a series connection of NMOS transistors, comprising a first NMOS transistor operably connected in series to a second NMOS transistor, wherein the series connection of the NMOS transistors is operably coupled to a first bus that receives an electrostatic discharge pulse signal; a first single-gate oxide electrostatic discharge control circuit, which is coupled to the first NMOS transistor and is configured to turn on the first NMOS transistor during an electrostatic discharge event, the first single-gate oxide control circuit being coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate oxide electrostatic discharge control circuit, which is operably coupled to the first bus at a first voltage and a first node at a second voltage. a second single-gate oxide electrostatic discharge control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during the electrostatic discharge event and to turn off the second NMOS transistor during normal operation, wherein the second single-gate oxide electrostatic discharge control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate oxide electrostatic discharge control circuit and the second single-gate oxide electrostatic discharge control circuit at the first node.

[0005] In addition, other embodiments of the present application provide a method for controlling an electrostatic discharge circuit, characterized in that it includes: detecting an electrostatic discharge pulse signal through at least two high-pass filter circuits; charging the first node; charging the second node and the third node; and charging the fourth node and the fifth node to turn on the first NMOS transistor and the second NMOS transistor to discharge the electrostatic discharge signal.

[0006] In addition, other embodiments of the present application provide a power switch circuit, characterized in that it includes: a voltage divider circuit, operably coupled to a first bus at a first voltage and a second bus at a second voltage, wherein the voltage divider circuit is operably configured to provide a third voltage; at least two level converter circuits, wherein the first level converter circuit operates in a first voltage supply range between the second voltage and the third voltage, and the second level converter circuit operates in a second voltage supply range between the third voltage and the first voltage; at least two driver buffer circuits are coupled to the at least one corresponding level converter circuit; at least one output buffer circuit is coupled to the at least two driver buffer circuits to provide a power switch output voltage, wherein the at least two level converter circuits, the at least two driver buffer circuits and the output buffer circuit each include multiple single-gate oxide layer devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read with the accompanying drawings, the aspects of the present disclosure can be best understood from the following detailed description. It is worth noting that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features can be arbitrarily increased or reduced for clarity of illustration.

[0008] Figure 1 An exemplary circuit diagram of an electrostatic discharge (ESD) protection circuit based on single gate oxide technology according to some embodiments of the present disclosure is shown.

[0009] Figure 2 An exemplary circuit diagram of an ESD protection circuit based on single gate oxide layer technology according to some embodiments of the present disclosure is shown.

[0010] Figure 3 is a block diagram of the operation of an ESD protection circuit based on single gate oxide technology according to some embodiments of the present disclosure.

[0011] Figure 4 is an exemplary circuit diagram showing a power switch circuit based on single gate oxide technology according to some embodiments of the present disclosure.

[0012] Figure 5 is an exemplary circuit diagram showing a level shifter circuit based on single gate oxide technology according to some embodiments of the present disclosure.

[0013] Figure 6 is an exemplary circuit diagram of a level shifter circuit based on single gate oxide technology according to some embodiments of the present disclosure.

[0014] Figure 7 is a block diagram illustrating a method of operating a power switch circuit based on single gate oxide technology according to some embodiments of the present disclosure.

[0015] Description of Figure Numbers

[0016] 100: Protection circuit

[0017] 101, 201: core circuit

[0018] 102, 202: pads, I / O nodes

[0019] 103, 203: First bus, bus

[0020] 104, 204: Second bus, bus

[0021] 105, 110, 205: Voltage divider circuit

[0022] 106: High-pass filter, ESD control circuit

[0023] 107: ESD control circuit

[0024] 108, 208, 209, 210: Bypass circuit

[0025] 111, 112, 116, 211, 212, 213, 214: resistor

[0026] 113, 118, 240, 242, 411a, 413a, 415a, 419a, 421a, 423a, 431, 432, 511, 512, 516, 517, 518, 531, 532, 536, 537, 538, 611, 612, 621, 622, 631: PMOS transistors

[0027] 114, 117, 120, 220, 221, 222, 223, 224, 406G, 406SD, 410G, 410SD, 412G, 412SD, 414G, 414SD, 418G, 418SD, 420SD, 422SD, 519, 520, 521, 522, 523, 539, 540, 541, 542, 543, 614, 615, 624, 625, 635, ENM, ENMB: nodes

[0028] 115, 119, 121, 122, 230, 231, 232, 233, 234, 411b, 413b, 415b, 419b, 421b, 423b, 433, 434, 513, 514, 515, 533, 534, 535, 613, 623, 633: NMOS transistors

[0029] 200, 208: ESD circuit

[0030] 206, 207: High-pass filter circuit

[0031] 300, 700: Method

[0032] 302, 304, 306, 308, 310, 312, 314, 316, 318, 702, 704, 706: Operation

[0033] 400: Single-gate oxide power switch, power inverter circuit, power switch circuit

[0034] 402a, 402b: Level converter circuit

[0035] 406: Output buffer circuit

[0036] 404a, 404b: Driver buffer circuit

[0037] 410, 412, 414, 418, 420, 422: Inverter circuits

[0038] 501, 601: First circuit block

[0039] 502, 602: Second circuit block

[0040] 552, 554: Voltage Tracker

[0041] 630: Inverter

[0042] B, D, G, S: Terminals

[0043] EN, ENB: Input terminal

[0044] GND: Ground

[0045] LS1: Level Shifter

[0046] MHV, PHV: Input voltage DETAILED DESCRIPTION

[0047] The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, it will be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or one or more intermediate components may be present.

[0048] The features described herein may be embodied in different forms and are not constructed to be limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete and convey the full scope of the disclosure to those of ordinary skill in the art. Certain embodiments are not described in more detail with reference to the accompanying drawings.

[0049] In the following description, the same reference numerals are used for the same components even in different drawings. The contents defined in the description, such as detailed construction and components, are provided to help fully understand the preset examples. Therefore, it is apparent that the embodiments can be carried out without those matters specifically described. In addition, well-known functions or structures are not described in detail because they would obscure the embodiments with unnecessary details.

[0050] Although expressions such as "first" or "second" may be used to refer to various components, the components are not limited by the expressions. The expressions are used only for the purpose of distinguishing one component from another.

[0051] These expressions are only used for the purpose of explaining specific embodiments and are not restrictive. Unless otherwise specified, expressions in the singular include plural meanings. Throughout the specification, the expression "including" or "having" is only used to indicate the presence of the characteristics, numbers, steps, operations, components, parts or combinations thereof described herein, but does not exclude the possibility of the presence of one or more other characteristics, numbers, steps, operations, components, parts or combinations of these or other aspects.

[0052] The following description is merely exemplary in nature and is in no way intended to limit the present disclosure, its application or use. For clarity, the same reference numerals are used in the accompanying drawings to identify similar components. As used herein, at least one of the phrases A, B, and C should be interpreted as using a non-exclusive logical or to represent a logical structure (A or B or C). It should also be understood that the steps within the method may be performed in a different order without changing the principles of this example.

[0053] The present invention shows an electrostatic discharge circuit and a power switch circuit based on a single-gate oxide semiconductor device that can operate at a low voltage, so as to reduce the manufacturing process and increase the production yield to reduce the cost.

[0054] Figure 1 An exemplary circuit diagram of an electrostatic discharge (ESD) protection circuit 100 based on single-gate oxide technology according to some embodiments of the present disclosure is shown. The ESD protection circuit 100 (hereinafter referred to as "ESD circuit 100") includes a voltage divider circuit 105, a high-pass filter 106 (hereinafter referred to as "high-pass filter 106"), a single-gate oxide ESD control circuit 107 (hereinafter referred to as "ESD control circuit 107") and a bypass circuit 108, wherein the ESD control circuit 107 and the bypass circuit 108 are respectively coupled between the first bus 103 and the second bus 104.

[0055] The voltage divider circuit 105 includes a plurality of impedance components connected in series, which are used for voltage division. According to some embodiments, two resistors 111 and 112 connected in series are used in voltage division. In some embodiments, the impedance component is a CMOS (complementary metal oxide semiconductor) diode connected to another CMOS diode. In some embodiments, the impedance component can be a suitable MOS transistor configured as a diode. In some embodiments, it can be a combination of various impedance components.

[0056] The PMOS transistor 113 is configured as a P-channel MOS capacitor. In order to function as a MOS capacitor, the source (hereinafter indicated as terminal "S"), the drain (hereinafter indicated as terminal "D") and the body (hereinafter indicated as terminal "B") terminals of the PMOS transistor 113 are connected to a power supply terminal, such as PHV, which is the first bus 103, and its electrode terminal (hereinafter indicated as terminal "G") is connected to a node 114, which is at a lower voltage level. The first bus 103. Similarly, the NMOS transistor 115 is configured as an N-channel MOS capacitor, and its terminals S, B and D are connected to the bus 104, which is GND, and its terminal G is connected to one end of a resistor 116 at a node 117, which is at a higher voltage level. The other end of the resistor 116 is connected to the terminal G of the transistor 113 at the node 114. In some embodiments, the same end of the resistor 116 connected to the terminal G of the transistor 115 is also connected to the terminals G of two transistors including the PMOS transistor 118 and the NMOS transistor 119. Terminal D of PMOS transistor 118 is also connected to terminal S of NMOS transistor 119 at node 120. Terminals S and B of PMOS transistor 118 are connected to terminal G of NMOS transistor 113 at node 114, while terminals B and D of NMOS transistor 119 are connected to second bus 104 of GND. As shown, terminal S of NMOS transistor 121 is operably coupled to bus 103 receiving ESD voltage and PHV, and terminal D thereof is operably coupled to terminal S of series NMOS transistor 122. Terminal D of NMOS transistor 122 is connected to second bus 104. Terminals G of NMOS transistors 121 and 122 are also connected to nodes 114 and 120, respectively. It should be noted that additional components may be placed between first bus 103 and transistor 121.

[0057] During operation, when an ESD pulse is applied from the I / O node or pad 102 to the first bus 103, the high frequency pass filter formed by the resistor 116 and the NMOS transistor 115, which functions as a MOS capacitor, pulls the voltage on the node 117 down to the voltage (e.g., GND) on the second bus 104. Similarly, the PMOS transistor 113, which functions as a MOS capacitor, also pulls the voltage on the node 114 to the voltage (e.g., PHV) on the first bus 103. Since the voltage level at the node 114 is pulled up to PHV, the voltage difference between the node 114 and the second bus 104 and thus the voltage drop from the terminal G to the terminal B of the NMOS transistor 121 generates an electric field, which absorbs sparse electrons from the P-type substrate and concentrates them near the gate oxide layer. This charge redistribution causes a continuous N-type channel, allowing current to flow from the terminal S to the D in the NMOS transistor 121. Therefore, the NMOS transistor 121 is turned on. Since the voltage level at the node 117 is GND, which pulls the voltage at the terminal G of the PMOS transistor 140 to GND, the voltage difference between the nodes 114 and 117, and thus the voltage drops from the terminal G to the terminal B, generates an electric field, which absorbs the positively charged mobile charges in the N-type substrate and concentrates them near the oxide layer. This charge redistribution causes a continuous P-type channel and allows current to flow from the terminal S to the D in the PMOS transistor 140. Therefore, the PMOS transistor 140 is then turned on.

[0058] At the same time or subsequently, since there is no voltage difference between terminals G and B on NMOS transistor 119, NMOS transistor 119 is turned off. The voltage level at node 120 may be charged to the voltage (e.g., PHV) on node 114. Since the voltage level at node 120 is pulled to PHV, it pulls the voltage on terminal G of NMOS transistor 122 to PHV, so NMOS transistor 122 is turned on due to the voltage difference between terminal G and terminal B. Therefore, the ESD pulse can be directed from I / O node 102 to second bus 104, such as GND, through two NMOS transistors 121 and 122 in bypass circuit 108.

[0059] Meanwhile, when an ESD pulse on the first bus 103 is present together with the input voltage PHV (e.g., 1.8V) from the I / O node 102, the voltage on the node 114 is controlled by the resistance values ​​of the resistor components 111 and 112 in the voltage divider circuit 105. In some embodiments, if the resistance values ​​of the two resistors 111 and 112 are equal, the voltage at the node 114 may be half of the voltage on the first bus 103 (PHV / 2, e.g., 0.9V). As described above, the NMOS transistor 115 configured as a MOS capacitor forms a high-pass filter together with the resistor component 116, which pulls the voltage at the node 117 to the voltage at the second bus 104, i.e., GND. At the same time or subsequently, since the voltage level at the node 117 is GND, the PMOS transistor 118 is turned on and the NMOS transistor 119 is turned off. Since the PMOS transistor 118 is turned on and the NMOS transistor 119 is turned off, it pulls the voltage level at the node 120 to the voltage level at the node 114. The voltage applied to the terminal G of the NMOS transistor 121 is determined by the resistance values ​​of the resistors 111 and 112 in the voltage divider circuit 110. In some embodiments, the voltage applied to the terminal G of the NMOS transistor 121 is half of the PHV, for example, 0.9V. In addition, since the voltage level at the node 120 is half of the PHV, the NMOS transistor 122 is turned on. Therefore, the ESD signal can be routed (e.g., discharged) to GND (i.e., bus 104) through the NMOS transistors 121 and 122 (e.g., bypass circuit 108), while the PHV can still be delivered to the core circuit 101.

[0060] Since the voltage divider circuit 105 is used in the ESD protection circuit, the maximum voltage between the terminals G and S / D of all NMOS and PMOS transistors 115, 119, 121, 122 and 113, 118 is less than PHV. In some embodiments, if PHV is 1.8V, the maximum voltage that can be applied to these active transistor devices, including NMOS transistors 130, 132, 133 and 134, and PMOS transistor 140, is 0.9V if the resistance values ​​of resistors 111 and 112 are equal. In some embodiments, if the resistance values ​​of resistors 111 and 112 are different, the voltages on all NMOS and PMOS transistors may be different.

[0061] During normal operation, NMOS transistor 113 and PMOS transistor 115, which are configured as MOS capacitors, are turned off. The voltage at node 117 is then pulled to the voltage level at node 114, which turns on NMOS transistor 119 and turns off PMOS transistor 118. Due to the voltage difference between terminals G and B, NMOS transistor 119 turns on and pulls the voltage at node 120 down to GND, which then turns off NMOS transistor 122. Therefore, the voltage input of PHV from I / O node 102 can be transmitted to core circuit 101.

[0062] The ESD circuit is preferably composed of only single gate oxide devices, so that NMOS and PMOS transistors 113, 115, 118, 119, 121 and 122 all have the same gate oxide thickness. Resistor components 111, 112 and 116 can be formed on the integrated circuit by diffusion, or they can be polysilicon resistors. In some embodiments, the thickness of the gate oxide can be thin (e.g., no more than 3 nanometers).

[0063] Figure 2 An exemplary circuit diagram of an ESD protection circuit 200 based on single-gate oxide technology according to some embodiments of the present disclosure is shown. The ESD protection circuit includes a voltage divider circuit 205, two high-pass filter circuits 206 and 207, two ESD control circuits 208, and a bypass circuit 210. Each of the voltage divider circuit 205, the high-pass filter circuits 206 and 207, the ESD circuit 208, and the bypass circuit 209 will be described below. In some embodiments, the voltage divider circuit 205 includes two resistors 211 and 212; the high-pass filter circuit 206 includes a resistor 213 and a transistor 231; the high-pass filter circuit 207 includes a resistor 214 and a transistor 230; the ESD control circuit includes two transistors 232 and 240; and the bypass circuit 208 includes two transistors 233 and 234. According to some embodiments of the present disclosure, the transistors 230, 231, 232, 233, and 234 can each be implemented as an N-type metal oxide semiconductor (NMOS) field effect transistor (FET). In some embodiments, transistors 240 and 242 may each be implemented as a P-type metal oxide semiconductor (PMOS) field effect transistor (FET). However, it should be noted that transistors 230, 231, 232, 233, 234, 240, and 242 may each be implemented as a transistor of various types (e.g., a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), etc.) while remaining within the scope of the present disclosure.

[0064] More specifically, in Figure 2In the illustrated embodiment, with respect to the high pass filter circuit 207, one end of the resistor 214 is connected to the node 220, and the other end is connected to the terminal "G" of the transistor 230. The transistor 230 includes four terminals S, D, G, and B. More specifically, in some embodiments, the terminal G of the transistor 230 is coupled to the resistor 214 at the node 222, and the terminals S, D, and B of the transistor 230 are respectively coupled to the second bus 204, i.e., GND. In this way, the transistor 230 can be used as an N-channel MOS capacitor, which will be described in further detail below.

[0065] When an ESD signal occurs, high pass filter circuits 206 and 207 determine the presence of the ESD signal and can cause other parts of the circuit to respond accordingly to enable bypass circuits. Detailed operations of each ESD circuit in ESD and normal operating modes according to some embodiments are described below.

[0066] Each of the two high pass filter circuits includes a resistor and an NMOS transistor configured as a MOS capacitor. In some embodiments, one end of the resistor 213 in the high pass filter 206 is coupled to the terminal G of the NMOS transistor 231 and the PMOS transistor 242. The other end of the resistor 213 is coupled to the first bus 203 at a voltage level of PHV. In some embodiments, one end of the resistor 214 in the high pass filter 207 is coupled to the terminal G of the NMOS transistors 230, 232 and the PMOS transistor 240. The other end of the resistor component 214 is coupled to the node 220 at an intermediate voltage level determined by the voltage divider circuit 205.

[0067] During operation, when an ESD pulse is present on the first bus 203, the high frequency pass filter formed by the resistor 213 and the NMOS transistor 231 configured as a capacitor pulls the voltage on the node 221 down to a first voltage level, which turns on the PMOS transistor 242. Simultaneously or subsequently, the voltage level at the node 223 may be charged to a second voltage level, which may then turn on the NMOS transistor 234.

[0068] The high frequency pass filter 207 formed by the resistor 214 and the NMOS transistor 230 configured as a MOS capacitor pulls the voltage on the node 222 to a third voltage level. The third voltage level is close to GND, which can turn off the NMOS transistor 232 and turn on the PMOS transistor 240, which pulls the voltage level at the node 224 to the voltage level at the node 223, for example, the second voltage level, which can also turn on the NMOS transistor 234. Therefore, the NMOS transistors 231 and 233 are turned on by the voltage difference between the terminals G and S / D of these transistors, which is less than 1V so that the core circuit devices can operate normally. The ESD signal can be routed (e.g., discharged) to GND (i.e., the second bus 204) through the NMOS transistors 231 and 233 (e.g., the bypass circuit 208), and the PHV can still be transmitted from the I / O node 202 to the core circuit 201.

[0069] During normal operation, since the NMOS transistors 231 and 230 configured as MOS capacitors in the high-pass filter circuits 206 and 207 are turned off. The voltage levels at the nodes 221 and 222 are pulled up to the voltage level (e.g., PHV) at the bus 203 and the node 220 (e.g., the intermediate voltage level). In some embodiments, the voltage level at the first bus 203 and the node 220 may be 1.8V and 0.9V, respectively. At the same time, since the voltage levels at the nodes 221 and 222 are pulled up, the two PMOS transistors 242 and 240 are turned off, and the NMOS transistor 232 is turned on. Since the NMOS transistor 232 is turned on, the voltage level at the node 224 is pulled down to GND. The voltage applied to the terminal G of the NMOS transistor 233 is GND, which turns off the NMOS transistor 233. Therefore, the voltage input of the PHV from the I / O node 202 can be transmitted to the core circuit 201.

[0070] Due to the use of voltage divider 205 and high pass filter circuits 206 and 207 in the ESD protection circuit, the maximum voltage level that can be applied to all NMOS and PMOS transistors is 230, 231, 232, 233, 234, 240 and 242. In some embodiments, if PHV is 1.8V, the maximum voltage that can be applied to these active transistors can be 0.9V. Therefore, the ESD circuit can preferably be composed of only single gate oxide layer devices, so that NMOS and PMOS transistors 230, 231, 232, 233, 234, 240 and 242 all have the same gate oxide layer thickness. Resistor components 211 and 212 can be formed on the integrated circuit by diffusion, or it can be a polysilicon resistor. In some embodiments, the thickness of the gate oxide layer can be thin (e.g., not more than 3 nanometers).

[0071] Figure 3 FIG. 1 is an exemplary flow chart of a method 300 for operating an ESD circuit based on single gate oxide technology according to some embodiments of the present disclosure. In some embodiments, the operation of the method 300 is performed by Figure 1-2 For the purpose of discussion, the Figure 2 The following embodiment of method 300 is described. The illustrated embodiment of method 300 is merely an example. Therefore, it should be understood that any of the various operations may be omitted, reordered, and / or added while remaining within the scope of the present disclosure.

[0072] Method 300 begins with operation 302, where the ESD circuit 200 detects the presence of an ESD event according to various embodiments. Figure 2 In the above example, the high pass filter circuits 206 and 207 of the ESD circuit 200 are configured to detect whether there is an ESD pulse signal in the first bus 203. If there is no such ESD pulse signal, the method 300 proceeds to operations 304, 306 and 308. However, if the ESD pulse signal exists together with the PHV on the first bus 203, the method 300 proceeds to operations 310, 312 and 314. The two routes of the method 300 will be discussed separately below.

[0073] If no ESD pulse signal is detected at operation 302, the method 300 proceeds to operation 304, where the first node of the ESD circuit 200 is combined by the first and second resistors at an intermediate voltage level. In some embodiments, if the resistance values ​​of the first and second resistors are equal, the intermediate voltage level (MHV) can be half of the voltage on the first bus 203, such as PHV / 2.

[0074] The method 300 continues to operation 306, where the second node of the ESD circuit 200 is charged to PHV through the third resistor, and the third node of the ESD circuit 200 is charged to an intermediate level (e.g., MHV). According to some embodiments, the fourth resistor of the ESD circuit 200. More specifically, continuing the above example, the second node, such as node 221, can be charged to a voltage level through resistor 213 (third resistor) that is substantially close to the PHV on the bus 203. The third node, such as node 222, can be charged to MHV determined by the first and second resistors through resistor 214 (fourth resistor).

[0075] Method 300 continues with operation 308, according to some embodiments, wherein the first and second P-type transistors are turned off, the first N-type transistor is turned on, and the fourth node is charged to the intermediate voltage level, and the fifth node is charged to GND. Still taking the same example, since node 221 is pulled to PHV and node 222 is pulled to MHV, transistors 242 (the first P-type transistor) and 240 (the second P-type transistor) are turned off, and transistor 232 (the first N-type transistor) is turned on. Therefore, node 223 (the fourth node) is pulled to MHV, and node 224 (the fifth node) is pulled to GND.

[0076] Method 300 continues with operation 310, where, according to some embodiments, the second N-type transistor is turned on and the third N-type transistor is turned off. Still using the same example, transistor 234 (the second N-type transistor) is turned on and transistor 233 (the third N-type transistor) is turned off. Therefore, the PHV propagating on the I / O node or contact (e.g., 202) can be delivered to the core circuit, such as 201.

[0077] If an ESD pulse signal is detected together with the input voltage from the I / O node or pad, the method 300 continues to operation 312, where the first node of the ESD circuit 200 is set at an intermediate voltage level by the first and second resistors. In some embodiments, if the resistance values ​​of the first and second resistors are equal, the intermediate voltage level can be half of the voltage on the bus 203, such as MHV.

[0078] The method 300 continues to operation 314, where, according to some embodiments, the second and third nodes of the ESD circuit 200 are pulled down to GND. More specifically, continuing the above example, the second node, such as node 221, can be charged to a voltage level that is substantially close to GND on the second bus 204. The third node, such as node 222, can be charged to a voltage level close to the second bus 204, such as GND.

[0079] Method 300 continues with operation 316, where the first and second P-type transistors are turned on, the first N-type transistor is turned off, and the fourth and fifth nodes are charged to PHV and MHV, according to some embodiments. Still taking the same example, since node 221 is pulled to the intermediate voltage level and 222 is pulled to a voltage level close to GND, transistors 242 (the first P-type transistor) and 240 (the second P-type transistor) are both turned on, and transistor 232 (the first N-type transistor) is turned off. Therefore, node 223 (the fourth node) is pulled to the intermediate voltage level, and node 224 (the fifth node) is pulled to a level on node 223 that is less than the intermediate voltage level.

[0080] The method 300 continues with operation 318, where the second and third N-type transistors are turned on according to some embodiments. Still using the same example, transistor 234 (the second N-type transistor) and transistor 233 (the third N-type transistor) are turned on by the voltage levels of nodes 223 and 234. Therefore, the PHV propagated on the I / O node or contact (e.g., 202) can be transmitted to the core circuit, such as 201, and the ESD pulse signal is released to GND through the second and third N-type transistors.

[0081] Figure 4 A circuit diagram of a single-gate oxide power switch 400 based on single-gate oxide technology according to some embodiments of the present disclosure is shown. The single-gate oxide power switch 400 includes a voltage divider circuit 205, two level shifting circuits 402a and 402b, two driver buffer circuits 404a and 404b, and an output buffer circuit 406. The first and second level shifter circuits 402a and 402b each include 5 terminals: 2 power terminals, 2 input terminals, and 1 output terminal. The first and second level shifters (LS) 402a and 402b operate at different input levels, wherein the first LS 402a operates in the MHV and PHV range, and the second LS 402b operates in the LV (low voltage) and MHV range, in some embodiments. The connection and operation of the circuit will be described in detail in detail. Figure 5 and Figure 6 This is discussed in further detail in .

[0082] The voltage divider circuit 205 includes a plurality of impedance components connected in series as a voltage divider. According to some embodiments, in the illustrated embodiment, the voltage divider circuit 205 includes two resistors 211 and 212 connected in series as a voltage divider. The voltage divider circuit 205 is used to provide MHV to the level converter 402a / 402b, the driver buffer circuit 404a / 404b, and the output buffer circuit 406. For example, when PHV is 1.8V, the MHV of the node 220 may be 0.9V.

[0083] The level converter 402a operates in the voltage range of MHV to PHV, and the level converter 402b operates in the voltage range of LV to MHV. In some embodiments, the level converter 402a can convert the voltage from LV to MHV or from MHV to PHV. The configuration and operation of the level converters 402a and 402b are as follows: Figure 5 and Figure 6 This will be discussed in detail.

[0084] Each of the first and second driver buffer circuits 404a and 404b includes three inverters. Specifically, the first driver buffer circuit 404a includes inverter circuits 410, 412, and 414, and the second driver buffer circuit 404b includes inverter circuits 418, 420, and 422. The three inverters in the driver buffer circuit 404 are each composed of a PMOS transistor and an NMOS transistor, which are connected in series (e.g., the terminal D of the PMOS transistor is connected to the terminal S of the NMOS transistor). All terminals S of the PMOS transistors (e.g., 411a, 413a, and 415a) of the first driver buffer circuit 404a are connected to PHV. All terminals D of the NMOS transistors (e.g., 411b, 413b, and 415b) of the first driver buffer circuit 404a are connected to MHV by the node 220 of the voltage divider circuit 205. In addition, the terminals G of the two PMOS and NMOS transistors in the inverter circuit are connected together. Specifically, in the first inverter 410 of the first driver buffer circuit 404a, the node at which the terminal S of the PMOS transistor 411a is connected to the terminal D of the NMOS transistor 411b is hereinafter represented as "410SD". The node at which the terminal G of the PMOS transistor 411a and the NMOS transistor 411b are connected is hereinafter represented as "410G". The second and third inverters 412 and 414 are also configured similarly to the first inverter 410. The three inverters in the driver buffer circuit are operatively connected in series, with the node 412G connected to the node 410SD and the node 414G connected to the node 412SD. Finally, the node 410G of the first inverter is connected to the output terminal of the first level converter 402a, and the node 414SD is connected to the terminal G of the PMOS transistor 431 in the output buffer 406.

[0085] The second driver buffer circuit 404b is configured similarly to the first driver buffer circuit 404a. The three inverters each include a PMOS transistor and an NMOS transistor. All terminals S of the PMOS transistors (e.g., 419a, 421a, and 423a) of the second driver buffer circuit 404b are connected to MHV. All terminals D of the NMOS transistors (e.g., 419b, 421b, and 423b) of the second driver buffer circuit 404b are connected to GND. The nodes G of each inverter 420 and 422 are connected to the nodes SD of the corresponding inverters 418 and 420. Finally, the node 418G of the first inverter 418 of the second driver buffer 404b is connected to the output terminal of the second level conversion device 402b, and the node 422SD of the third inverter 422 of the second driver buffer 404b is connected to the terminal G of the NMOS transistor 434 in the output buffer 406. Additionally, a node 418SD in the second driver buffer circuit 404b is connected to the ENMB input of the first level shifter 402a, and a node 420SD of the second driver buffer circuit 404b is coupled to the ENM of the first level shifter 402a.

[0086] The output buffer 406 includes two PMOS transistors, such as 431 and 432, connected in series, and two NMOS transistors, such as 433 and 434. Specifically, the terminal D of the first PMOS transistor 431 is connected to the terminal S of the second PMOS transistor 432. The terminal D of the second PMOS transistor 432 is connected to the terminal S of the first NMOS transistor 433. Then, the terminal S of the first NMOS transistor 433 is connected to the terminal S of the second NMOS transistor 434. The terminal S of the first PMOS transistor is connected to PHV, and the terminal D of the second NMOS transistor 434 is connected to GND. In addition, the terminal G of the second PMOS transistor 432 and the first NMOS transistor 433 are connected together, which is further connected to MHV. The terminal S of the second PMOS transistor 432 and the terminal D of the first NMOS transistor 433 are used as output terminals of the power inverter circuit 400. The P-type substrates of the NMOS transistors 433 and 434 are connected to the GND voltage level, and the N-type substrates of the PMOS transistors 431 and 432 are connected to the terminals S of the corresponding transistors.

[0087] During operation, when a voltage level between MHV and PHV at the output terminal of the first level shifter 402a is applied to the first driver buffer circuit 404a and the voltage level swings between 0V and MHV at the output terminal of the second level shifter 402b applied to the second driver buffer circuit 404b, the NMOS transistor 411b is turned on and the PMOS transistor 411a is turned off, pulling the voltage at the node 410SD to GND. The voltage level of GND applied to the node 412G of the second inverter 412 turns on the PMOS transistor 413a and turns off the NMOS transistor 413b, which pulls the voltage at the node 412SD to PHV. The voltage level is further inverted twice by the third and fourth inverters, and then the voltage level swinging from MHV to PHV at the node 416SD is output. Similarly, a voltage level swinging from 0 to MHV at the node 424SD can be achieved.

[0088] When two logic low voltages, MHV and 0V, are at nodes 414SD and 422SD, respectively, the PMOS transistor 431 is turned on to pull the voltage between the terminal D of the first PMOS transistor 431 and the terminal S of the second PMOS transistor 432 to PHV. Due to the MHV at the terminal D, the second PMOS transistor 432 can be turned on to further pull the voltage between the terminal D of the second PMOS transistor 432 and the terminal S of the first NMOS transistor 433 to PHV. The second NMOS transistor 434 is turned off and the first NMOS transistor 433 is turned on. Therefore, when the outputs of the level converters 402a and 402b are at their logic high levels, the output at the node 406SD of the output buffer 406 is at its logic high level, such as PHV. Similarly, when the outputs of the level converters 402a and 402b are at their logic low levels, the output at the node 406SD is at its logic low level, such as 0V.

[0089] This single gate oxide level shifter (LS) 402a is used to convert the logic signal of the core circuit having an operating voltage swinging between 0V and MHV (e.g., 0.9V) to an I / O output terminal having a higher voltage level. From 0V to PHV, such as 1.8V, while maintaining the voltage difference above its gate oxide below the breakdown voltage. Specifically, since the terminals B / S of the PMOS transistors and the terminals B / D of the NMOS transistors in the first driver buffer 404a are connected to PHV and MHV respectively, the voltage difference between the terminals G and S / D of all transistors is limited. Therefore, all PMOS and NMOS transistors in the first driver buffer 404a can be thin gate oxide devices. Similarly, the voltage difference between the terminals G and S / D of the two PMOS transistors in the output buffer 404 and all transistors in the second driver buffer 404b are also limited by the intermediate voltage. Therefore, all PMOS and NMOS transistors in the driver buffer 404 and the output buffer 406 can also be gate oxide devices with the same oxide thickness. In some embodiments, the thickness of the gate oxide may not exceed 3 nanometers. All transistors may also be thick gate oxide devices to allow operation at higher voltages. In some other embodiments, the gate oxide thickness may not exceed 7 nanometers.

[0090] Figure 5 A circuit diagram 402a of a first single-gate oxide level shifter having a high voltage circuit and a low voltage circuit in a power switch circuit 400 according to some embodiments of the present disclosure is shown. The first single-gate oxide level shifter 402a includes two identical circuit blocks 501 and 502. The two identical circuit blocks 501 and 502 each include five PMOS transistors and three NMOS transistors.

[0091] In the first circuit block 501, transistors including two PMOS transistors (511 and 512) and three NMOS transistors (513, 514 and 515) are connected in series through their terminals S and D. Specifically, the terminal D of the first PMOS transistor 511 is connected to the terminal S of the second PMOS transistor 512. The terminal D of the second PMOS transistor 512 is also connected to the terminal S of the first NMOS transistor 513. The terminal D of the first NMOS transistor 513 is connected to the terminal S of the second NMOS transistor 514. The terminal S of the second NMOS transistor 514 is connected to the terminal S of the third NMOS transistor 515. The terminal S of the first PMOS transistor 511 and the terminal D of the third NMOS transistor 515 are also connected to PHV and GND, respectively. The terminal G of the second PMOS transistor 512 is connected to MHV. The terminal G of the third NMOS transistor 515 is connected to ENM as an input terminal. All terminals B of the PMOS transistors are connected to their respective terminals S. All terminals B of the NMOS transistors are connected to GND. A terminal S of the third PMOS transistor 516 is connected to a terminal G of a fourth PMOS transistor 517, which is further connected to a terminal D of the second PMOS transistor 512 and a terminal S of the first NMOS transistor 513 at a node 519. A terminal S of the third PMOS transistor 517 is connected to a terminal G of the fourth PMOS transistor 516, which is further connected to MHV. Terminals B of the third and fourth PMOS transistors 516 and 517, a terminal D of the third PMOS transistor 516, and a terminal G of the first NMOS transistor 513 are connected together at a node 520. The node 520 is also connected to a terminal D of the first PMOS transistor 511 and a terminal S of the second PMOS transistor 512 at a node 521. A terminal S of the fifth PMOS transistor 518 is connected to a terminal D of the fourth PMOS transistor 517. A terminal B of the fifth PMOS transistor 518 is connected to a node 520. A terminal D of the fifth PMOS transistor 518 is connected to a terminal G of the second NMOS transistor 514 at a node 522, and the node 522 is also connected to MHV. Finally, terminal G of fifth PMOS transistor 518 is connected to terminal D of first NMOS transistor 513 and terminal S of second NMOS transistor 514 at node 523. Transistors 516, 517 and 518 in first circuit block 501 of level shifter circuit 500 are coupled together as voltage tracker 552 to protect second NMOS transistor 514.

[0092] The structure of the second circuit block 502 in the level converter circuit 500 is similar to that of the first circuit block 501. In the second circuit block 502, a series of two PMOS transistors and three NMOS transistors are connected in series through their terminals S and D. Specifically, the terminal D of the first PMOS transistor 531 is connected to the terminal S of the second PMOS transistor 532. The terminal D of the second PMOS transistor 532 is also connected to the terminal S of the first NMOS transistor 533. The terminal D of the first NMOS transistor 533 is connected to the terminal S of the second NMOS transistor 534. The terminal S of the second NMOS transistor 534 is connected to the terminal S of the third NMOS transistor 535. The terminal S of the first PMOS transistor 531 and the terminal D of the third NMOS transistor 535 are also connected to PHV and GND, respectively. The terminal G of the second PMOS transistor 532 is connected to MHV. The terminal G of the third NMOS transistor 535 is connected to ENMB as an input terminal. All terminals B of the PMOS transistors (e.g., 531 and 532) are connected to their respective terminals S. All terminals B of the NMOS transistors (e.g., 533, 534, and 535) are connected to GND. Terminal S of the third PMOS transistor 536 is connected to terminal G of the fourth PMOS transistor 537, and is also connected to terminal D of the second PMOS transistor 532 and terminal S of the first NMOS transistor 533 at node 539. Terminal S of the third PMOS transistor 537 is connected to terminal G of the fourth PMOS transistor 536, which is further connected to MHV. Terminals B of the third and fourth PMOS transistors 536 and 537, terminal D of the third PMOS transistor 536, and terminal G of the first NMOS transistor 533 are connected together at node 540. Node 540 is also connected to terminal D of the first PMOS transistor 531 and terminal S of the second PMOS transistor 532 at node 541. Terminal S of the fifth PMOS transistor 538 is connected to terminal D of the fourth PMOS transistor 537. Terminal B of the fifth PMOS transistor 538 is connected to node 540. Terminal D of the fifth PMOS transistor 538 is connected to terminal G of the second NMOS transistor 534 at node 542, which is also connected to MHV. Finally, terminal G of the fifth PMOS transistor 538 is connected to terminal D of the first NMOS transistor 533 and terminal S of the second NMOS transistor 534 at node 543. Transistors 536, 537, and 538 in the second circuit block 502 of the level shifting circuit 500 are coupled together as a voltage tracker 554 to protect the second NMOS transistor 534.

[0093] The two circuit blocks 501 and 502 are electrically coupled by connecting a node 521 in the first circuit block 501 to a terminal G of a first PMOS transistor 531 of the second circuit block 502 and connecting a node 541 of the second circuit block 502 to a terminal G of a first PMOS transistor 511 of the first circuit block 501. Finally, the output terminals are connected to nodes 540 and 541.

[0094] During operation, circuit block 501 receives input voltages at nodes ENM and ENMB from corresponding nodes (eg, 418SD and 420SD) in driver buffer circuit 404, where a supply voltage is applied at nodes PHV and MHV, as shown in FIG. Figure 5 As shown, the output voltage is generated within a predetermined range through the circuit 502. When MHV=0.9V and PHV=1.8V, and when ENM=0.9V and ENMB=0V are applied to the first level converter 402a, transistors 514 and 515 are turned on, which pull the voltage level of node 523 to GND. Transistor 512 is turned off. The low voltage level of the gate of transistor 518 turns on transistor 518. Transistors 516 and 517 are then configured to set node 519 to GND. Similarly, transistor 534 is turned on and transistor 535 is turned off, which pulls the voltage level of node 543 to a high level. Transistors 536 and 537 are turned off, and transistor 532 is turned on to pull the voltage level of node 541 high, thereby turning off transistor 511 and turning on transistor 531. In this configuration, the voltage level of the output node is equal to the voltage level of node 540, which is 1.8V. Similarly, when MHV=0.9V and PHV=1.8V, and when ENM=0V and ENMB=0.9V are applied to the first level converter circuit 402a, the voltage level of the output node is equal to the voltage level of the node 540, which is 0.9V.

[0095] One advantage of the proposed single gate oxide level shifter is that its manufacturing cost is much lower than that of the conventional double gate oxide level shifter. Another advantage of the proposed level shifter is that its switching speed can be improved since no thick gate oxide device is used.

[0096] Figure 6 A circuit diagram 402b of a second level shifter for interfacing a low voltage circuit with a high voltage circuit according to some embodiments of the present disclosure is shown. Figure 4The second level converter circuit 402b of the medium power switch circuit 400 includes two identical circuit blocks 601 and 602 and an inverter. The inverter 630 includes an NMOS transistor 633 and a PMOS transistor 631. The terminal D of the PMOS transistor 631 is coupled to the terminal S of the NMOS transistor 633, and the terminal D of the PMOS transistor 631 is further coupled to the ENB node of the first circuit block 601, while the terminal S of the PMOS transistor 631 is coupled to LV and the terminal D of the NMOS transistor 633 is coupled to GND. The NMOS transistor 633 is coupled to EN together with the terminal G of the PMOS transistor 631.

[0097] Each of the two circuit blocks 601 and 602 includes 2 PMOS transistors and 1 NMOS transistor. Specifically, in the first circuit block 601 of the second level converter circuit 402b, the first PMOS transistor 611 and the NMOS transistor 613 are connected in parallel by connecting the terminal G of the two transistors, and the terminal D of the first PMOS transistor 611 and the terminal S of the NMOS transistor 613 are also connected at the node 614. The terminals G of the transistors 611 and 613 are also connected to ENB as an input terminal. The terminal S of the first PMOS transistor 611 is also connected to the terminal D of the second PMOS transistor 612. Then the terminal S of the second PMOS transistor 612 is connected to MHV. All the terminals B of the PMOS transistors 611 and 612 are connected to their respective terminals S, and the terminal B of the NMOS transistor 613 is connected to GND.

[0098] The structure of the second circuit block 602 in the level converter circuit 402b is similar to that of the first circuit block 601. In the second circuit block 602, the first PMOS transistor 621 and the NMOS transistor 623 are connected in parallel to the terminals G of the two transistors and the terminal D of the first PMOS transistor 621 and the terminal S of the NMOS transistor 623 are also connected at the node 624. The terminals G of the transistors 621 and 623 are also connected to EN as an input terminal. The terminal S of the first PMOS transistor 621 is also connected to the terminal D of the second PMOS transistor 622. Then, the terminal S of the second PMOS transistor 622 is connected to MHV. All the terminals B of the PMOS transistors 621 and 622 are connected to their respective terminals S, and the terminal B of the NMOS transistor 623 is connected to GND.

[0099] The two circuit blocks 601 and 602 are electrically coupled by connecting a node 614 in the first circuit block 601 to a terminal G of a second PMOS transistor 622 of the second circuit block 602 and connecting a node 624 of the second circuit block 602 to a terminal G of a second PMOS transistor 612 of the first circuit block 601. Finally, an output terminal is connected to the node 614.

[0100] When MHV is applied to the input terminal ENB, the NMOS transistor 613 of the first circuit block 601 is turned on, the first PMOS transistor 612 of the first circuit block 601 is turned off, and then the voltage node 614 is pulled to GND. Since GND is applied to the terminal G of the first PMOS transistor 621 of the second circuit block 602, the first PMOS transistor 621 of the second circuit block 602 is turned on, which pulls the voltage 625 at the node to MHV. When GND is applied to the input terminal EN, the first PMOS transistor 621 of the second circuit block 602 is turned on, and the NMOS transistor 623 of the second circuit block 602 is turned off. Then the voltage at the node 624 is pulled up to the voltage level of MHV at the node 625. When MHV is applied to the input terminal EN, the NMOS transistor 623 of the second circuit block 602 is turned on, the first PMOS transistor 621 of the second circuit block 602 is turned off, and then the voltage node 624 is pulled to GND. Since GND is applied to the terminal G of the second PMOS transistor 611 of the first circuit block 601, the second PMOS transistor 611 is turned on, which pulls the voltage at the node 615 to MHV. When GND is applied to the input EN, the second NMOS transistor 623 is turned off and the PMOS transistor 622 is turned on.

[0101] Similarly, when GND is applied to the input terminal ENB, the NMOS transistor 613 of the first circuit block 601 is turned off, and the first PMOS transistor 612 of the first circuit block 601 is turned on, and then the voltage at the node 614 is pulled to the voltage level at the node 615. When GND is applied to the input terminal EN, the first PMOS transistor 621 of the second circuit block 602 is turned on, and the NMOS transistor 623 of the second circuit block 602 is turned off. Then the voltage at the node 624 is pulled up to the voltage level at the node 625. When MHV is applied to the input terminal EN, the NMOS transistor 623 of the second circuit block 602 is turned on, and the first PMOS transistor 621 of the second circuit block 602 is turned off, and then the voltage at the node 624 is pulled to GND. Since GND is applied to the terminal G of the second PMOS transistor 611 of the first circuit block 601, the second PMOS transistor 611 is turned on, which pulls the voltage at the node 615 to MHV. Since the first PMOS transistor 611 of the first circuit block 601 is turned on, the voltage level MHV at the node 614 turns off the second PMOS transistor 622 in the second circuit block 602 .

[0102] When ENB=0V and EN=0.7V are applied to the second level converter 402b, transistor 611 is turned on and transistor 613 is turned off, which pulls the voltage level of node 614 to 0.9V. Similarly, transistor 621 is turned off and transistor 623 is turned on, which pulls the voltage level of node 624 to GND. The voltage levels of nodes 614 and 624 turn on and off transistors 612 and 614, respectively, which results in the output of node 614 being 0.9V. Similarly, when ENB=0.7V and EN=0V are applied to the second level converter 402b, transistor 611 is turned off and transistor 613 is turned on, which pulls the voltage level of node 614 to GND, which results in the output of 0V.

[0103] Figure 7 The following are some examples according to the present disclosure. Figure 4 A block diagram of a method 700 for operating a power switch circuit is shown in FIG. 1 . It should be appreciated that some additional operations may be performed in Figure 7 The before, during, and after of method 700 are provided, and some operations may be omitted or reordered.

[0104] Method 700 begins at operation 702, where an intermediate voltage level is provided according to some embodiments of the present disclosure. In some embodiments, the intermediate voltage level is provided by a voltage divider circuit. In some embodiments, voltage divider circuit 205 includes a plurality of impedance components connected in series to act as a voltage divider. In an exemplary embodiment, voltage divider circuit 205 has two resistors 211 and 212 connected in series to act as a voltage divider according to some embodiments. Voltage divider 205 provides MHV to level converter 402a / 402b, driver buffer circuit 404a / 404b, and output buffer circuit 406. For example, when PHV of 1.8V is provided, MHV of 0.9V may be obtained at node 220.

[0105] The method 700 continues with step 704, where an input voltage is provided according to some embodiments of the present disclosure. In some embodiments, the input voltage provided to the second level converter 402b swings between a voltage range of 0 to LV, and the second level converter 402b provides an output voltage to the driver buffer circuit 404b. In some embodiments, the driver buffer circuit 404b operates between a voltage range of MHV and GND to provide a voltage output swinging between 0 and MHV. Two internal nodes of the second level converter 402b are further coupled to the first level converter 402a, which converts the input voltage to a voltage range between MHV and PHV. The output of the first level converter 402a is further coupled to the driver buffer circuit 404a, which provides a voltage output swinging between MHV and PHV.

[0106] The method 700 continues with step 706, where two output voltages are provided to an output buffer circuit to provide a power switch output according to some embodiments of the present disclosure. In some embodiments, the two output voltages are applied to two transistors (e.g., 431 and 434) of the output buffer circuit 406 to turn the transistors on and off when corresponding output voltage levels are provided. Terminals G of transistors 432 and 433 of the output buffer circuit 406 are coupled to MHV to maintain the voltage difference across their gate oxides below a breakdown voltage. When EN is applied to 0V, the power switch outputs 0V, and when EN is applied to LV (e.g., 0.7V), the power switch outputs PHV at 1.8V.

[0107] In an embodiment, an electrostatic discharge (ESD) circuit includes: a series of NMOS transistors, including a first NMOS transistor operably connected in series to a second NMOS transistor, wherein the series of NMOS transistors is operably coupled to a first bus that receives an electrostatic discharge pulse signal; a first single-gate oxide electrostatic discharge control circuit, coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an electrostatic discharge event, the first single-gate oxide control circuit is coupled to a first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate oxide electrostatic discharge control circuit, which is operably coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an electrostatic discharge event and turn off the second NMOS transistor during normal operation, wherein the second single-gate oxide electrostatic discharge control circuit is coupled between a first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit, operably connected to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operably coupled to the first single-gate oxide electrostatic discharge control circuit and the second single-gate oxide electrostatic discharge control circuit at the first node.

[0108] According to some embodiments, the voltage divider circuit in the single gate oxide layer electrostatic discharge includes at least two resistors connected in series between the first bus receiving the electrostatic discharge and the second bus.

[0109] According to some embodiments, the first single-gate oxide electrostatic discharge control circuit and the second single-gate oxide electrostatic discharge control circuit include single-gate oxide devices having a gate thickness of 3 nanometers or less.

[0110] According to some embodiments, the second single-gate oxide electrostatic discharge control circuit includes an inverter circuit.

[0111] According to some embodiments, the second NMOS transistor is protected from the electrostatic discharge event by the first NMOS transistor.

[0112] According to some embodiments, the electrostatic discharge circuit further includes: two high-pass filter circuits, which are respectively operably coupled to the two single-gate oxide layer electrostatic discharge control circuits during an electrostatic discharge event to set the first node to an intermediate voltage level and the third node to a low voltage level.

[0113] According to some embodiments, the two high pass filter circuits each include a resistive component and a capacitive component.

[0114] According to some embodiments, the capacitive component in each of the two high-pass filter circuits may be a single-gate oxide MOS component configured as a capacitor.

[0115] According to some embodiments, the resistance component in each of the two high-pass filter circuits sets the first voltage for the first single-gate oxide electrostatic discharge control circuit and the second single-gate oxide electrostatic discharge control circuit.

[0116] In another embodiment, a method for controlling electrostatic discharge (electrostatic discharge circuit having a single-gate oxide semiconductor device, comprising: detecting an electrostatic discharge pulse signal through at least two high-pass filter circuits; charging a first node; charging a second node and a third node; and charging a fourth node and a fifth node to turn on a first NMOS transistor and a second NMOS transistor to discharge the electrostatic discharge signal.

[0117] According to some embodiments, the charging of the first node to the intermediate voltage level is operably controlled by a voltage divider circuit.

[0118] According to some embodiments, the voltage divider circuit includes at least two resistors connected in series between the first bus and the second bus.

[0119] According to some embodiments, the charging of the second node and the third node is operably controlled by a first high pass filter circuit and a second high pass filter circuit.

[0120] According to some embodiments, the charging of the fourth node and the fifth node is operably controlled by a first single gate oxide electrostatic discharge control circuit and a second single gate oxide electrostatic discharge control circuit.

[0121] According to some embodiments, the first single-gate oxide electrostatic discharge control circuit and the second single-gate oxide electrostatic discharge control circuit each include a single-gate oxide device having a gate thickness, wherein the gate thickness is equal to or less than 3 nanometers.

[0122] However, in another embodiment, a power switch circuit is characterized in that it includes: a voltage divider circuit, operably coupled to a first bus at a first voltage and a second bus at a second voltage, wherein the voltage divider circuit is operably configured to provide a third voltage; at least two level converter circuits, wherein the first level converter circuit operates in a first voltage supply range between the second voltage and the third voltage, and the second level converter circuit operates in a second voltage supply range between the third voltage and the first voltage; at least two driver buffer circuits are coupled to the at least one corresponding level converter circuit; at least one output buffer circuit is coupled to the at least two driver buffer circuits to provide a power switch output voltage, wherein the at least two level converter circuits, the at least two driver buffer circuits and the output buffer circuit each include multiple single gate oxide layer devices.

[0123] According to some embodiments, the voltage divider circuit includes at least two resistors connected in series between the first bus and the second bus.

[0124] According to some embodiments, the at least two driver buffer circuits further include a plurality of inverters, wherein the plurality of inverters each operate in the same power supply level range as the at least one corresponding level shifter.

[0125] According to some embodiments, the plurality of single gate oxide devices have the same gate oxide thickness.

[0126] According to some embodiments, the first level shifter further comprises a voltage tracker, wherein the voltage tracker is configured to protect.

[0127] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An electrostatic discharge circuit, characterized in that: include: a series connection of NMOS transistors, including a first NMOS transistor operably connected in series to a second NMOS transistor, wherein the series connection of the NMOS transistors is operably coupled to a first bus receiving an electrostatic discharge pulse signal; a first single-gate oxide electrostatic discharge control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an electrostatic discharge event, the first single-gate oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; and A voltage divider circuit is operably connected to the first bus at the first voltage and a second bus at a ground voltage, wherein the voltage divider circuit is operably coupled to the first single-gate oxide electrostatic discharge control circuit at the first node.

2. The electrostatic discharge circuit according to claim 1, characterized in that: In single gate oxide electrostatic discharge, the voltage divider circuit includes at least two resistors connected in series between the first bus receiving electrostatic discharge and the second bus.

3. The electrostatic discharge circuit according to claim 1, characterized in that: The first single-gate oxide layer electrostatic discharge control circuit includes a single-gate oxide layer device, and the gate thickness of the single-gate oxide layer device is 3 nanometers or less.

4. A method for controlling an electrostatic discharge circuit, characterized in that: include: Detecting electrostatic discharge pulse signals through a first high-pass filter circuit and a second high-pass filter circuit; operatively controlling the charging of the first node to an intermediate voltage level by a voltage divider circuit, wherein the voltage divider circuit comprises at least two resistors connected in series between the first bus and the second bus; charging a second node in the first high-pass filter circuit and a third node in the second high-pass filter circuit; and A fourth node and a fifth node are charged to turn on the first NMOS transistor and the second NMOS transistor to discharge the electrostatic discharge pulse signal, wherein the fourth node is a gate terminal of the first NMOS transistor, and the fifth node is a gate terminal of the second NMOS transistor.

5. The method for controlling an electrostatic discharge circuit according to claim 4, characterized in that: The second node charging is operatively controlled by the first high pass filter circuit.

6. The method for controlling an electrostatic discharge circuit according to claim 5, characterized in that: The charging of the third node is operatively controlled by the second high pass filter circuit.

7. The method for controlling an electrostatic discharge circuit according to claim 4, characterized in that: The voltage divider circuit is operably coupled to a first single gate oxide electrostatic discharge control circuit and a second single gate oxide electrostatic discharge control circuit located at the first node.

8. The method for controlling an electrostatic discharge circuit according to claim 4, characterized in that: The charging of the fourth node and the fifth node is operably controlled by a first single gate oxide electrostatic discharge control circuit and a second single gate oxide electrostatic discharge control circuit.

9. The method for controlling an electrostatic discharge circuit according to claim 8, characterized in that: The first single-gate oxide electrostatic discharge control circuit and the second single-gate oxide electrostatic discharge control circuit each include a single-gate oxide device having a gate thickness, wherein the gate thickness is equal to or less than 3 nanometers.

10. A power switch circuit, characterized in that: include: a voltage divider circuit operably coupled to a first bus at a first voltage and a second bus at a second voltage, wherein the voltage divider circuit is operably configured to provide a third voltage; at least two level shifter circuits, wherein a first level shifter circuit operates in a first voltage supply range between the second voltage and the third voltage, and a second level shifter circuit operates in a second voltage supply range between the third voltage and the first voltage; at least two driver buffer circuits, each coupled to a corresponding one of the at least two level shifter circuits; as well as The at least two level shifter circuits and the at least two driver buffer circuits each include a plurality of single gate oxide devices.

11. The power switch circuit according to claim 10, characterized in that: The voltage divider circuit includes at least two resistors connected in series between the first bus and the second bus.

12. The power switch circuit according to claim 10, characterized in that: The at least two driver buffer circuits further include a plurality of inverters, wherein each of the plurality of inverters operates in the same power supply level range as the at least two corresponding level shifters.

13. The power switch circuit according to claim 10, characterized in that: The plurality of single gate oxide devices have the same gate oxide thickness.

14. The power switch circuit according to claim 10, characterized in that: The first level converter further includes a voltage tracker.

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