Composite single-crystal piezoelectric substrate and method for manufacturing the same

Abstract

The present applicant provides a composite single-crystal piezoelectric substrate and a preparation method thereof. The composite single-crystal piezoelectric substrate comprises, from bottom to top, a high acoustic impedance substrate layer (1), a low acoustic impedance layer (2), a buffer layer (3), and a single-crystal piezoelectric layer (4). The low acoustic impedance layer (2) has a porosity of 8×10 19 ~1×10 22 H atoms / cm 3 , and a water diffusion at room temperature of greater than 3×10 ‑17 cm 2 / s, so that the generated water can be absorbed by the low acoustic impedance layer (2) or escape from the composite single-crystal piezoelectric substrate along the loose structure of the low acoustic impedance layer (2), thereby reducing or even eliminating defects such as cavity formation at the interface between the high acoustic impedance substrate layer (1) and the low acoustic impedance layer (2). The method can conveniently prepare a composite single-crystal piezoelectric substrate with a predetermined structure.

Description

Technical Field

[0001] This application belongs to the field of functional semiconductors, and specifically relates to a composite single-crystal piezoelectric substrate and its preparation method. Background Technology

[0002] The composite single-crystal piezoelectric substrate is designed based on the basic structure of a Bragg reflector. It consists of a laminated single-crystal piezoelectric layer, a low acoustic impedance layer, and a high acoustic impedance substrate layer. The single-crystal piezoelectric layer is the main functional layer and is generally made of piezoelectric materials such as lithium tantalate (LT) or lithium niobate (LN) to realize the mutual conversion between electrical signals and acoustic signals.

[0003] Currently, the mainstream technology for fabricating the aforementioned composite single-crystal piezoelectric substrates is ion implantation followed by direct bonding. Specifically, ion implantation is used to obtain the desired thin film, and then direct bonding is used to bond the various film layers together. Hydrophilic bonding is performed in an air environment. After etching the wafer surface, the surface can be cleaned, thus removing etching debris. However, hydrophilic bonding utilizes hydrogen bonds formed by hydroxyl groups on the bonding surfaces of the two wafers to form pre-bonding, and high-temperature annealing to form strong oxygen bonds for stable bonding. During oxygen bond formation, water is generated as a byproduct. If this water is not treated, it will form bubbles at high temperatures, disrupting the bond and leading to defects. Specifically, composite single-crystal piezoelectric substrates fabricated using hydrophilic bonding often have many voids at the bonding interface between the single-crystal piezoelectric layer and the low acoustic impedance layer, affecting the yield rate of downstream device manufacturing.

[0004] In addition, there are inevitably excess Si ions with positive charges near the interface between the low acoustic impedance layer and the high acoustic impedance substrate layer. These positive charges attract charge carriers, i.e. electrons, to concentrate in the high acoustic impedance substrate layer. Since the high density of charge carriers can move in the high acoustic impedance substrate layer, parasitic conductance is generated. In radio frequency (RF) applications, parasitic conductance interacts with the electromagnetic field and generates additional signal loss. Summary of the Invention

[0005] To address the problems of traditional composite single-crystal piezoelectric substrates and their fabrication processes, this application provides a composite single-crystal piezoelectric substrate. The low acoustic resistance layer in this substrate has a porous structure, exhibiting water diffusion greater than 3 × 10⁻⁶ at room temperature. -17 cm 2The porous structure allows water molecules generated by hydrophilic bonding to be absorbed by the low acoustic impedance layer or diffuse out of the resulting composite single-crystal piezoelectric substrate through its porous structure, thereby weakening or even eliminating the influence of water molecules on device performance. Furthermore, a buffer layer is introduced between the single-crystal piezoelectric layer and the low acoustic impedance layer in the composite single-crystal piezoelectric substrate, reducing the stress at the interface between the single-crystal piezoelectric layer and the low acoustic impedance layer, thus enhancing the overall structural stability of the composite single-crystal piezoelectric substrate. Additionally, an undoped amorphous silicon substrate sublayer is introduced into the high acoustic impedance substrate layer. This undoped amorphous silicon substrate sublayer can capture charge carriers, thereby weakening or even eliminating parasitic conductivity. Moreover, the acoustic impedance of the buffer layer is lower than that of the low acoustic impedance layer, thereby increasing the acoustic impedance difference at the interface between the low acoustic impedance layer and the high acoustic impedance substrate layer, further enhancing the confinement effect on sound wave energy, and improving the yield of optoelectronic devices fabricated using this composite single-crystal piezoelectric substrate.

[0006] The purpose of this application is to provide a composite single-crystal piezoelectric substrate, wherein the substrate comprises, from bottom to top, a high acoustic resistance substrate layer 1, a low acoustic resistance layer 2, a buffer layer 3, and a single-crystal piezoelectric layer 4, wherein the low acoustic resistance layer 2 has a water diffusion capacity greater than 3 × 10⁻⁶ at room temperature. -17 cm 2 / s, thereby enabling the water generated by bonding to be absorbed by the low acoustic resistance layer 2, or to escape from the composite single crystal piezoelectric substrate along the loose structure of the low acoustic resistance layer 2, thereby reducing the water content at the interface between the high acoustic resistance substrate layer 1 and the low acoustic resistance layer 2, and thus reducing or even eliminating defects such as voids at the interface between the high acoustic resistance substrate layer 1 and the low acoustic resistance layer 2.

[0007] In one feasible embodiment, the low acoustic resistance layer 2 has a porous structure; and / or, the porosity of the low acoustic resistance layer is 8 × 10⁻⁶. 19 ~1×10 22 H atoms / cm 3 For example, 1×10 20 atoms / cm 3 This provides ample space for the absorption and dispersion of water molecules.

[0008] In one feasible manner, the buffer layer 3 is formed by doping a first material with a second material, wherein the first material is the material used to prepare the single-crystal piezoelectric layer 4, and the second material is the material used to prepare the low acoustic impedance layer 2.

[0009] This application provides a buffer layer between the low acoustic impedance layer and the single crystal piezoelectric layer, so that the interfacial stress between the single crystal piezoelectric layer and the low acoustic impedance layer is dispersed in the buffer layer, thereby improving the structural stability of the composite single crystal piezoelectric substrate.

[0010] In one feasible approach, along the interface between the buffer layer 3 and the low acoustic impedance layer 2 to the interface between the buffer layer 3 and the monocrystalline piezoelectric layer 4, the concentration of the first material in the buffer layer 3 gradually decreases while the concentration of the second material gradually increases, resulting in a smooth transition between the monocrystalline piezoelectric layer and the low acoustic impedance layer, eliminating the obvious interface between them.

[0011] In one feasible manner, hydrogen is injected into the buffer layer 3, and the concentration of hydrogen gradually decreases along the central layer of the buffer layer 3 toward the two side interfaces.

[0012] In one possible implementation, the thickness of the buffer layer 3 is 1 to 10 nm; and / or the interface roughness of the buffer layer 3 is less than 0.3 nm. Since the buffer layer is a non-functional layer, it is necessary to minimize the thickness of the buffer layer. The present application selects the above-mentioned thickness so that the buffer layer 3 can both play a buffering role and minimize the thickness of the buffer layer to the greatest extent.

[0013] In one possible implementation, the high acoustic impedance substrate 1 includes a monocrystalline silicon substrate sublayer and an undoped amorphous silicon substrate sublayer 12, wherein the undoped amorphous silicon substrate sublayer 12 is in contact with the low acoustic impedance layer 2, and the undoped amorphous silicon substrate sublayer in contact with the low acoustic impedance layer can absorb charge carriers at its interface with the low acoustic impedance layer, thereby reducing parasitic conductivity.

[0014] Optionally, the undoped amorphous silicon substrate sublayer 12 is deposited on the monocrystalline silicon substrate sublayer 11.

[0015] Furthermore, the surface roughness of the undoped amorphous silicon substrate sublayer 12 is less than 0.3 nm; and / or, the resistivity is greater than 5000 Ω·cm.

[0016] In one feasible manner, the material used to prepare the single-crystal piezoelectric layer 4 includes lithium niobate or lithium tantalate; and / or, the material used to prepare the low acoustic impedance layer 2 includes silicon dioxide.

[0017] In one feasible manner, the composite single-crystal piezoelectric substrate can be fabricated by a method comprising the following steps:

[0018] An undoped amorphous silicon substrate sublayer is prepared on the single-crystal silicon substrate;

[0019] A low acoustic impedance layer is prepared on the undoped amorphous silicon substrate sublayer;

[0020] A single-crystal piezoelectric layer is prepared on the low acoustic impedance layer to obtain a composite single-crystal piezoelectric substrate.

[0021] Optionally, fabricating a single-crystal piezoelectric layer on the low acoustic impedance layer may include:

[0022] The preparation of the single-crystal piezoelectric implantation sheet includes a thin film layer 041, an ion implantation layer 042, and a residual material layer 043.

[0023] The thin film layer 041 of the single crystal piezoelectric implantation wafer is bonded to the single crystal silicon substrate on a low acoustic impedance layer;

[0024] Remove the excess material layer 043 along the ion implantation layer 042;

[0025] Trim the single-crystal piezoelectric thin film.

[0026] Another object of this application is to provide a method for preparing the aforementioned composite single-crystal piezoelectric substrate, the method comprising:

[0027] An undoped amorphous silicon substrate sublayer is prepared on the single-crystal silicon substrate;

[0028] A low acoustic impedance layer is prepared on the undoped amorphous silicon substrate sublayer;

[0029] A single-crystal piezoelectric layer is prepared on the low acoustic impedance layer to obtain a composite single-crystal piezoelectric substrate.

[0030] Optionally, fabricating a single-crystal piezoelectric layer on the low acoustic impedance layer may include:

[0031] A single-crystal piezoelectric implantation wafer is prepared, the single-crystal piezoelectric implantation wafer comprising a thin film layer 041, an ion implantation layer 042, and a residual material layer 043;

[0032] The thin film layer 041 of the single crystal piezoelectric implantation wafer is bonded to the single crystal silicon substrate on a low acoustic impedance layer;

[0033] Remove the excess material layer 043 along the ion implantation layer 042;

[0034] Trim the single-crystal piezoelectric thin film.

[0035] The preparation method provided in this application is simple and easy to implement, and the process conditions are easy to control. The resulting composite single crystal piezoelectric substrate has few or even no defects between the low acoustic impedance layer and the high acoustic impedance substrate layer.

[0036] Compared with the prior art, the composite single-crystal piezoelectric substrate provided in this application comprises a high acoustic resistance substrate layer, a low acoustic resistance layer, and a single-crystal piezoelectric layer in sequence. The low acoustic resistance layer has a porous structure, and its water diffusion at room temperature is greater than 3 × 10⁻⁶. -17 cm 2 / s, thereby enabling the water generated by bonding to be absorbed by the low acoustic impedance layer 2, or to escape from the composite single-crystal piezoelectric substrate along the loose structure of the low acoustic impedance layer 2, thereby reducing the water content at the interface between the high acoustic impedance substrate layer 1 and the low acoustic impedance layer 2, and thus reducing or even eliminating defects such as voids at the interface between the high acoustic impedance substrate layer 1 and the low acoustic impedance layer 2. In addition, the high acoustic impedance substrate layer includes a single-crystal silicon substrate sublayer and an undoped amorphous silicon substrate sublayer deposited on the single-crystal silicon substrate sublayer. The undoped amorphous silicon substrate sublayer can capture choke carriers, thereby weakening parasitic conductivity. The buffer layer is obtained by doping the low acoustic impedance layer material and the single-crystal piezoelectric layer material, thereby dispersing the interfacial stress between the low acoustic impedance layer and the single-crystal piezoelectric layer, thereby improving the overall structural stability of the composite single-crystal piezoelectric substrate.

[0037] The method for preparing the composite single-crystal piezoelectric substrate provided in this application can conveniently prepare a low acoustic impedance layer with a predetermined loose structure on a high acoustic impedance substrate. Furthermore, it can continue to prepare a single-crystal piezoelectric layer based on the low acoustic impedance layer, thereby obtaining a composite single-crystal piezoelectric substrate with a predetermined structure. The obtained composite single-crystal piezoelectric substrate overcomes the problems of parasitic conductivity and defects at the interface between the high acoustic impedance substrate and the low acoustic impedance layer that exist in existing composite single-crystal piezoelectric substrates. Attached Figure Description

[0038] Figure 1 This illustration shows a cross-sectional structural diagram of a composite single-crystal piezoelectric substrate provided in this example;

[0039] Figure 2 This image shows a cross-sectional scanning electron microscope (TEM) image of a composite single-crystal piezoelectric substrate provided in this application;

[0040] Figure 3 This diagram shows a cross-sectional structure of another composite single-crystal piezoelectric substrate in this example.

[0041] Figure 4 This example shows a scanning electron microscope (SEM) image of a sublayer of an undoped amorphous silicon substrate.

[0042] Figure 5 This image shows a scanning electron microscope (SEM) image of a high acoustic impedance substrate in this example.

[0043] Figure 6 A preferred preparation method is shown. Figure 1 The flowchart shown is for the composite single-crystal piezoelectric substrate.

[0044] Explanation of reference numerals in the attached figures

[0045] 1-High acoustic impedance substrate, 11-Monocrystalline silicon substrate sublayer, 12-Undoped amorphous silicon substrate sublayer, 2-Low acoustic impedance layer, 3-Buffer layer, 4-Monocrystalline piezoelectric layer. Detailed Implementation

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of methods consistent with some aspects of the invention as detailed in the appended claims.

[0047] The composite single-crystal piezoelectric substrate and its preparation method provided in this application are described in detail below through specific embodiments.

[0048] Figure 1 This example shows a cross-sectional structural diagram of a composite single-crystal piezoelectric substrate. Figure 1 As shown, the substrate comprises, from bottom to top, a high acoustic impedance substrate layer 1, a low acoustic impedance layer 2, a buffer layer 3, and a single crystal piezoelectric layer 4.

[0049] In this example, the low acoustic impedance layer 2 can be prepared from SiO2. This low acoustic impedance layer 2 serves as a low acoustic impedance layer for the Bragg reflector structure, and also has an opposite sound velocity-temperature coefficient to the single-crystal piezoelectric layer, thereby achieving temperature compensation to reduce the temperature coefficient of frequency (TCF) of the final device. In this example, the final device refers to a semiconductor device fabricated based on the composite single-crystal piezoelectric substrate, such as a surface acoustic wave filter.

[0050] In this example, the low acoustic resistance layer 2 has a loose structure, specifically a porous structure, or microporous structure. In this example, the porous structure is microscopic, meaning that the atoms in the low acoustic resistance layer 2 are irregularly arranged, forming atomic / molecular-level pores. However, the low acoustic resistance layer 2 as a whole still exhibits uniform and stable acoustic resistance and physicochemical properties such as refractive index. Therefore, water generated during the bonding process between the high acoustic resistance substrate 1 and the low acoustic resistance layer 2 can be absorbed by the low acoustic resistance layer 2, or escape from the composite single-crystal piezoelectric substrate along the porous structure of the low acoustic resistance layer 2, thereby reducing the water content at the interface between the high acoustic resistance substrate 1 and the low acoustic resistance layer 2, and thus reducing or even eliminating defects such as voids at the interface between the high acoustic resistance substrate 1 and the low acoustic resistance layer 2.

[0051] The applicant has discovered that the greater the porosity of the low acoustic impedance layer 2, the more favorable it is for the diffusion of water in the low acoustic impedance layer 2 during the annealing process, thereby suppressing the generation of defects at the interface of the high acoustic impedance substrate layer; and, the greater the porosity of the low acoustic impedance layer 2, the lower its acoustic impedance, thereby increasing the acoustic impedance difference at the interface of the low acoustic impedance layer / high acoustic impedance substrate layer, and thus enhancing the confinement effect of the single crystal piezoelectric layer on sound wave energy.

[0052] In this example, the porosity of the low acoustic resistance layer 2 can be characterized by its water diffusion coefficient. For example, the water diffusion coefficient of the low acoustic resistance layer 2 at room temperature is greater than 3 × 10⁻⁶. -17 cm 2 / s, meaning that the diffusion coefficient of water in a low acoustic impedance layer at room temperature is greater than 3×10⁻⁶. -17 cm 2 / s, preferably 5×10 -17 ~5×10 -16 cm 2 / s, for example, 1×10 -16 cm 2 / s, thus providing ample space for the absorption and dispersion of water molecules.

[0053] The applicant discovered that controlling the porosity of the low acoustic resistance layer to 8 × 10⁻⁶ is crucial. 19 ~1×10 22 H atoms / cm 3 For example, greater than 1×10 20 atoms / cm 3 This satisfies the aforementioned requirement of the low acoustic resistance layer 2 for the water diffusion coefficient. In this example, the content of H atoms can be used as a parameter to characterize the porosity of the low acoustic resistance layer 2. Alternatively, the content of other atoms can be used as a parameter to characterize the porosity of the low acoustic resistance layer 2. For ease of detection, the content of suitable particles can be used to characterize the porosity of the low acoustic resistance layer 2, such as water molecules, hydrogen ions, and hydrogen molecules. In this example, secondary ion mass spectrometry (SIMS) can be used to monitor the hydrogen content in the low acoustic resistance layer 2, i.e., the porosity.

[0054] In this example, the porosity of the low acoustic impedance layer 2 can be specifically set as needed, and can be controlled by controlling the parameters of the fabrication process. For example, the low acoustic impedance layer 2 can be prepared by chemical vapor deposition (CVD), including plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), etc. Furthermore, the deposition rate and compactness can be controlled by controlling parameters such as the gas flow rate, gas pressure, and fabrication temperature of the CVD process, thereby controlling the porosity of the low acoustic impedance layer 2.

[0055] Optionally, the surface roughness of the low acoustic impedance layer 2 in contact with the piezoelectric layer is less than 0.3 nm, thereby ensuring that the sound waves do not scatter at the interface between the low acoustic impedance layer 2 and the piezoelectric layer, thus preventing loss or noise. Furthermore, it ensures the bonding strength between the low acoustic impedance layer 2 and the piezoelectric layer. If the surface roughness of the low acoustic impedance layer 2 is greater than 0.3 nm, the contact distance between the low acoustic impedance layer 2 and the piezoelectric layer will be too large, making it impossible to form sufficient chemical bonds for stable bonding.

[0056] In this example, the thickness of the low acoustic impedance layer 2 is matched with the thickness of the single crystal piezoelectric layer 4 and the frequency of the final device application. For example, the thickness of the low acoustic impedance layer 2 can be 100-5000 nm, preferably 300-1000 nm, such as 600 nm.

[0057] Figure 2 This application provides a cross-sectional scanning electron microscope (TEM) image of a composite single-crystal piezoelectric substrate, as shown in the image. Figure 2 As shown, in this example, a buffer layer 3 can be introduced between the high acoustic impedance substrate layer 1 and the low acoustic impedance layer 2. The buffer layer 3 is formed by doping a first material and a second material, wherein the first material is the material used to prepare the single crystal piezoelectric layer 4, and the second material is the material used to prepare the low acoustic impedance layer 2.

[0058] The applicant has discovered that composite single-crystal piezoelectric substrates prepared using traditional processes often have lattice damage in their single-crystal piezoelectric layers. That is, the damaged lattice in the single-crystal piezoelectric layer changes from a regular arrangement to an irregular arrangement. Lattice damage reduces the performance of the single-crystal piezoelectric layer. Therefore, when preparing composite single-crystal piezoelectric substrates using traditional processes, a high-temperature annealing process is usually performed after bonding is completed, i.e., after obtaining the multilayer structure of the composite single-crystal piezoelectric substrate, to restore the damaged lattice in the single-crystal piezoelectric layer. Because the lattice size of the single-crystal piezoelectric layer changes before and after lattice damage recovery, while the low acoustic impedance layer 2 is amorphous and does not form lattice damage after bonding, the lattice size of the low acoustic impedance layer remains essentially unchanged before and after high-temperature annealing. This often results in significant interfacial stress at the interface between the single-crystal piezoelectric layer and the low acoustic impedance layer during high-temperature annealing. Furthermore, the thermal expansion coefficients of the single-crystal piezoelectric layer and the low acoustic impedance layer differ significantly. Therefore, high-temperature processes such as ion implantation and high-temperature annealing to recover lattice damage also generate substantial interfacial stress at the interface between the single-crystal piezoelectric layer and the low acoustic impedance layer. Even after cooling, this interfacial stress remains. These two types of interfacial stress not only reduce the overall structural stability of the composite single-crystal piezoelectric substrate but also cause warping of the composite single-crystal piezoelectric substrate, such as central bulges, and even detachment of the single-crystal piezoelectric layer.

[0059] This example controls the bonding conditions, for example, by surface activation of the bonding surfaces of the single-crystal piezoelectric layer and the low acoustic impedance layer before bonding, so that the two materials, the single-crystal piezoelectric layer and the low acoustic impedance layer, can fuse together during the bonding process to form a buffer layer 3.

[0060] The applicant discovered that, along the interface between the buffer layer 3 and the low acoustic impedance layer 2 to the interface between the buffer layer 3 and the single crystal piezoelectric layer 4, the concentration of the first material in the buffer layer 3 gradually decreases, while the concentration of the second material gradually increases. This results in a smooth transition between the single crystal piezoelectric layer 4 and the low acoustic impedance layer 2, eliminating the obvious interface between them. This disperses the stress present at the interface, improves the flexibility of the interface, and increases the structural stability of the composite single crystal piezoelectric substrate.

[0061] The applicant further discovered that the thickness and elemental distribution of the buffer layer 3 can be controlled by controlling process conditions, such as the degree of surface activation, thereby controlling the flexibility of the buffer layer 3 within an appropriate range.

[0062] This example uses a lithium tantalate wafer as the single-crystal piezoelectric layer and a silicon dioxide wafer as the low acoustic impedance layer. First, the bonding surfaces of the lithium tantalate wafer and the silicon dioxide wafer are activated separately. Then, the activated bonding surfaces of the silicon dioxide wafer and the lithium tantalate wafer are bonded together. During the bonding process, the bonding surfaces of the two wafers fuse to form a fused layer that diffuses into each other. This fused layer is the buffer layer. In the buffer layer, from the lithium tantalate wafer to the silicon dioxide wafer, the content of Li and Ta elements gradually decreases, the content of H element first increases and then decreases, and the content of O and Si elements gradually increases. The thickness of the buffer layer can be 1–10 nm, for example, 1–2 nm. This disperses the interfacial stress caused by the difference in thermal expansion coefficients over a 1–10 nm scale, thereby reducing the interfacial stress caused by the difference in thermal expansion coefficients between the single-crystal piezoelectric layer 4 and the low acoustic impedance layer 2, and thus improving the structural stability of the composite single-crystal piezoelectric substrate.

[0063] Since the buffer layer 3 is a non-functional layer, this example minimizes the thickness of the buffer layer 3. The above-mentioned thickness is selected in this application so that the buffer layer 3 can both play a buffering role and minimize the thickness of the buffer layer to the greatest extent.

[0064] In this example, the interface roughness between the buffer layer 3 and the low acoustic impedance layer 2 is less than 0.3 nm, thereby ensuring that sound waves do not scatter at the interface between the buffer layer 3 and the low acoustic impedance layer 2, and at the interface between the buffer layer 3 and the high acoustic impedance substrate layer 1, so as to reduce sound wave loss or noise generation.

[0065] Figure 3 This example shows a cross-sectional schematic diagram of another composite single-crystal piezoelectric substrate, as shown below. Figure 3 As shown, the high acoustic impedance substrate layer 1 may include a single crystal silicon substrate sublayer 11, and may also include an undoped amorphous silicon substrate sublayer 12 disposed on the single crystal silicon substrate sublayer 11, wherein the undoped amorphous silicon substrate sublayer 12 is in contact with the low acoustic impedance layer 2.

[0066] In this example, the undoped amorphous silicon substrate sublayer 12 can be deposited on the surface of the monocrystalline silicon substrate sublayer 11 by CVD, or it can be prepared on the surface of the monocrystalline silicon substrate sublayer 11 by other means.

[0067] Optionally, the deposition temperature for preparing the undoped amorphous silicon substrate sublayer 12 is between 450°C and 550°C, preferably between 480°C and 520°C, and the deposition rate is between 1 and 5 nm / min.

[0068] The applicant has discovered that charges and traps may exist at the interface between the low acoustic impedance layer 2 and the high acoustic impedance substrate layer 1, particularly at the interface of the monocrystalline silicon substrate sublayer 11. These charges and traps can cause an increase in carrier density near the interface of the monocrystalline silicon sublayer, leading to an increase in the conductivity of the monocrystalline silicon substrate sublayer 11 at that location. At the microscopic level, the undoped amorphous silicon substrate sublayer 12 is an amorphous material, meaning that it has lattice defects, specifically incompletely bonded silicon atoms at the boundaries of small amorphous packages. These lattice defects can be used to further trap carriers at the interface with the low acoustic impedance layer 2 and restrict carrier movement, thereby suppressing parasitic conductivity and helping to reduce RF losses.

[0069] In this example, the surface roughness of the undoped amorphous silicon substrate sublayer 12 is less than 0.3 nm, for example, less than 0.3 nm, thereby ensuring that the acoustic waves do not scatter at the interface between the undoped amorphous silicon substrate sublayer 12 and the single-crystal silicon substrate sublayer 11, and at the interface between the undoped amorphous silicon substrate sublayer 12 and the buffer layer 3, thereby reducing loss and noise; at the same time, it will not cause diffuse reflection of the laser at this interface in the subsequent photolithography process, affecting the photolithography pattern.

[0070] In this example, the resistivity of the undoped amorphous silicon substrate sublayer 12 can be greater than 5000 Ω·cm, thereby reducing signal loss.

[0071] In this example, the thickness of the undoped amorphous silicon substrate sublayer 12 can be 200nm to 30000nm, preferably 300 to 1500nm, for example 1000nm, to provide sufficient space for the full absorption of charge carriers.

[0072] Figure 4 This example shows a scanning electron microscope (SEM) image of a sublayer of an undoped amorphous silicon substrate, as shown. Figure 4 As shown in the white circle, the diameter of the amorphous package of the undoped amorphous silicon substrate sublayer 12 is less than 10 nm, which increases the defect density and achieves better carrier absorption.

[0073] Figure 5 This example shows a scanning electron microscope (SEM) image of a high acoustic impedance substrate, as shown. Figure 5As shown, in this example, the single-crystal silicon substrate sublayer 11 serves as a high acoustic impedance layer on one hand, and also as a supporting substrate for the overall structure of the composite single-crystal piezoelectric substrate on the other hand. Its surface roughness can be less than 0.3 nm to ensure that the sound waves at the interface with the low acoustic impedance layer do not scatter and generate loss or noise. Furthermore, the resistivity of the single-crystal silicon substrate sublayer 11 can be greater than 5000 Ω·cm, and the thickness can be 150-1000 μm.

[0074] In this example, the single-crystal piezoelectric layer 4 is the main functional layer of the composite single-crystal piezoelectric substrate. After fabricating the filter electrode structure on the single-crystal piezoelectric layer, the conversion and filtering of acoustic signals and electromagnetic signals can be realized. The material used to prepare the single-crystal piezoelectric layer 4 includes piezoelectric materials such as lithium niobate or lithium tantalate, and its thickness needs to match the frequency used by the device. Specifically, the thickness of the single-crystal piezoelectric layer 4 can be 100nm to 2000nm. The surface roughness of the bonding surface between the single-crystal piezoelectric layer 4 and the low acoustic impedance layer 2 is less than 0.3nm, thereby ensuring that the acoustic waves at the interface between the single-crystal piezoelectric layer 4 and the low acoustic impedance layer 2 do not scatter and generate loss or noise. In addition, the applicant has found that the bonding strength between the single-crystal piezoelectric layer 4 and the low acoustic impedance layer 2 can be guaranteed at the above surface roughness. If the surface roughness is greater than 0.3nm, it will cause the single-crystal piezoelectric layer and the low acoustic impedance layer to be too far apart when in contact, resulting in unstable bonding.

[0075] Figure 6 A preferred preparation method is shown. Figure 1 The flowchart of the composite single-crystal piezoelectric substrate is shown below. Figure 6 As shown, the composite single-crystal piezoelectric substrate can be prepared by a method including steps 1 to 6:

[0076] Step 1: Prepare an undoped amorphous silicon substrate sublayer on the single-crystal silicon substrate.

[0077] In this example, the method for preparing an undoped amorphous silicon substrate sublayer on the single-crystal silicon substrate can be any existing method for preparing undoped amorphous silicon on single-crystal silicon, such as CVD deposition.

[0078] After the undoped amorphous silicon substrate sublayer is prepared, a high acoustic impedance substrate layer is formed. The monocrystalline silicon substrate, as a monocrystalline silicon substrate sublayer, is the main high acoustic impedance functional layer, which supports the overall structure of the final product, the composite monocrystalline piezoelectric matrix.

[0079] The applicant discovered that within the aforementioned temperature range, the deposited undoped amorphous silicon sublayer exhibits an amorphous structure. The high defect density within this amorphous structure ensures the stability of the low acoustic impedance layer in suppressing parasitic conductivity. Furthermore, deposition within the aforementioned deposition rate range guarantees that the undoped amorphous silicon sublayer possesses good surface roughness, preventing acoustic wave scattering at the interface between the low acoustic impedance layer and the high acoustic impedance substrate, thereby reducing losses and noise; simultaneously ensuring the yield of subsequent photolithography processes. Conversely, if high-temperature deposition of polycrystalline silicon or high-speed deposition of amorphous silicon is used as the undoped amorphous silicon sublayer, the surface roughness of the obtained undoped amorphous silicon sublayer cannot meet the aforementioned requirements. Therefore, a chemical mechanical planarization (CMP) step is required after deposition, which increases production costs.

[0080] The physicochemical parameters of the undoped amorphous silicon substrate sublayer prepared in this step are as described above. For example, the thickness can be 200nm to 30000nm, preferably 300 to 1500nm, such as 1000nm; the surface roughness can be less than 0.3nm, such as less than 0.2nm; and the resistivity can be greater than 5000Ω·cm.

[0081] Step 2: Prepare a low acoustic impedance layer on the undoped amorphous silicon substrate sublayer.

[0082] In this example, the method for preparing the low acoustic impedance layer can be chemical vapor deposition (CVD), specifically including plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), etc.

[0083] The applicant has discovered that the low acoustic impedance layer prepared using the above-mentioned scheme has a loose structure, and that its loose structure can meet the aforementioned requirements for a low acoustic impedance layer.

[0084] Step 3: Prepare a single-crystal piezoelectric layer on the low acoustic impedance layer to obtain a composite single-crystal piezoelectric substrate.

[0085] In this example, the method for preparing a single-crystal piezoelectric layer on the low acoustic impedance layer can be ion implantation, film transfer, or direct bonding followed by thinning and polishing.

[0086] Taking ion implantation as an example, the fabrication of a single-crystal piezoelectric layer on the low acoustic impedance layer may include:

[0087] Step 3-1: Prepare a single-crystal piezoelectric implantation sheet, wherein the single-crystal piezoelectric implantation sheet includes a thin film layer 041, an ion implantation layer 042, and a residual material layer 043.

[0088] In this example, the preparation of the single-crystal piezoelectric implanted wafer can be carried out using any of the existing technologies based on the preparation of single-crystal piezoelectric wafers. The dose and energy of ion implantation can be specifically set according to the position and thickness of the thin film layer 041 of the desired implanted wafer.

[0089] Step 3-2: Bond the thin film layer 041 of the single crystal piezoelectric implantation wafer to the low acoustic resistance layer 2. After the thin film layer 041 is bonded to the low acoustic resistance layer 2, the single crystal piezoelectric layer 4 in the composite single crystal piezoelectric substrate is formed.

[0090] In this example, the bonding of the thin film layer 041 to the low acoustic impedance layer of the single-crystal piezoelectric implanted wafer can be achieved using methods such as room-temperature surface activation bonding. Specifically, this can include:

[0091] Step 3-2-1: Activate the bonding surfaces of the thin film layer 041 and the low acoustic impedance layer respectively. The activation can be carried out by chemical activation or plasma activation.

[0092] Taking plasma as an example, the activation ion energy used to activate the bonding surface of the thin film layer 041 is 50eV to 1000eV, and the activation time is 10s to 10min; the activation ion energy used to activate the bonding surface of the low acoustic impedance layer is 50eV to 1000eV, and the activation time is 10s to 10min.

[0093] The applicant has discovered that by activating the bonding surfaces of the two materials using the above-mentioned method, a buffer layer with a thickness of 1 to 10 nm can be obtained.

[0094] Step 3-2-2: The thin film layer 041 processed in step 3-2-1 is bonded to the bonding surface of the low acoustic impedance layer, and the bonded body is annealed at a temperature of 100–200°C. Annealing promotes the fusion of the activated surface layers of the two bonding surfaces to form a buffer layer and stabilizes the bonding.

[0095] Step 3-3: Remove the excess material layer along the ion implantation layer.

[0096] In this example, the ions implanted in the ion implantation layer 042 can be vaporized by means of heating or the like, thereby causing the residual material layer 043 to be peeled off from the film along the ion implantation layer 042.

[0097] In this example, the parameters used to remove the residual material layer 043 are not particularly limited. They can be specifically set according to the specific situation of the ion implantation layer 042 and the residual material layer 043, with the goal of completely peeling off the residual material layer 043 and forming a complete thin film layer 041.

[0098] Steps 3-4 involve trimming the single-crystal piezoelectric thin film.

[0099] In this example, the trimming includes trimming the thickness of the single-crystal piezoelectric layer film, restoring the lattice of the single-crystal piezoelectric film, and performing surface polishing on the single-crystal piezoelectric film, so that the thickness of the single-crystal piezoelectric film reaches the target thickness and has a regular lattice structure, and the surface roughness meets the usage requirements, thus providing sufficient piezoelectric function for the final device.

[0100] In this example, the parameter ranges for each specific operation of trimming the single-crystal piezoelectric thin film can be set according to specific needs.

[0101] Another object of this application is to provide a method for preparing the aforementioned composite single-crystal piezoelectric substrate, the method comprising:

[0102] Step 1': Prepare an undoped amorphous silicon substrate sublayer on the single-crystal silicon substrate;

[0103] The implementation method for this step is the same as that for step 1. Please refer to step 1 for details, which will not be repeated here.

[0104] Step 2': Prepare a low acoustic impedance layer on the undoped amorphous silicon substrate sublayer;

[0105] The implementation method of this step is the same as that of step 2. Please refer to step 2 for details, which will not be repeated here.

[0106] Step 3': Prepare a single-crystal piezoelectric layer on the low acoustic impedance layer to obtain a composite single-crystal piezoelectric substrate.

[0107] The implementation method for this step is the same as that for step 3. Please refer to step 3 for details, which will not be repeated here.

[0108] The preparation method provided in this application is simple and easy to implement, and the process conditions are easy to control. The resulting composite single crystal piezoelectric substrate has few or even no defects between the low acoustic impedance layer and the high acoustic impedance substrate layer.

[0109] Compared with the prior art, the composite single-crystal piezoelectric substrate provided in this application comprises a high acoustic resistance substrate layer, a low acoustic resistance layer, and a single-crystal piezoelectric layer in sequence. The low acoustic resistance layer has a porous structure, and its water diffusion at room temperature is greater than 3 × 10⁻⁶. - 17 cm 2 / s, thereby enabling the water generated by bonding to be absorbed by the low acoustic impedance layer 2, or to escape from the composite single-crystal piezoelectric substrate along the loose structure of the low acoustic impedance layer 2, thereby reducing the water content at the interface between the high acoustic impedance substrate layer 1 and the low acoustic impedance layer 2, and thus reducing or even eliminating defects such as voids at the interface between the high acoustic impedance substrate layer 1 and the low acoustic impedance layer 2. In addition, the high acoustic impedance substrate layer includes a single-crystal silicon substrate sublayer and an undoped amorphous silicon substrate sublayer deposited on the single-crystal silicon substrate sublayer. The undoped amorphous silicon substrate sublayer can capture choke carriers, thereby weakening parasitic conductivity. The buffer layer is obtained by doping the low acoustic impedance layer material and the single-crystal piezoelectric layer material, thereby dispersing the interfacial stress between the low acoustic impedance layer and the single-crystal piezoelectric layer, thereby improving the overall structural stability of the composite single-crystal piezoelectric substrate.

[0110] Example

[0111] Example 1: Fabrication of Composite Single-Crystal Piezoelectric Substrate

[0112] An amorphous silicon substrate sublayer was deposited on a single-crystal silicon wafer (8000Ω·cm) using the LPCVD method to form a high acoustic impedance substrate layer. The deposition temperature of the LPCVD method was controlled at 450℃ and the deposition rate was 3nm / min.

[0113] SiO2 was further deposited on the amorphous silicon substrate sublayer using PECVD. The resulting SiO2 layer served as a low acoustic impedance layer. The gas flow rate for SiO2 deposition was 25 sccm, the temperature was 150℃, and the deposition rate was 2 nm / min. The resulting SiO2 layer exhibited a water diffusion capacity of 3 × 10⁻⁶ at room temperature. -16 cm 2 / s, with a porosity of 1×10⁻⁶. 21 H atoms / cc, the thickness of the SiO2 layer is 800nm;

[0114] The SiO2 layer is polished to make the surface roughness of the bonding surface with the single crystal piezoelectric layer less than 0.3 nm;

[0115] Lithium tantalate ion implantation wafers were prepared by ion implantation, wherein the thickness of the thin film layer was 900 nm. The bonding surfaces of the SiO2 layer and the thin film layer were activated by plasma activation, respectively. The activation ion energy on the bonding surface of the SiO2 layer was 400 eV, and the activation ion energy on the bonding surface of the thin film layer was 400 eV. The activation time for both was 10 min, thereby obtaining a buffer layer with a thickness of 5 nm.

[0116] After bonding, the excess material layer is removed, and the lithium tantalate film layer is thinned and polished to obtain a composite single-crystal piezoelectric substrate.

[0117] Compared to composite single-crystal piezoelectric substrates prepared using conventional methods, the composite single-crystal piezoelectric substrates fabricated in this embodiment exhibit significantly increased structural stability, with bonding strength reaching 15 MPa. The surface acoustic wave device fabricated based on the composite single-crystal piezoelectric substrate of this embodiment has a Q value 1.3 times that of the substrate without an amorphous silicon sublayer.

[0118] Example 2: Fabrication of Composite Single-Crystal Piezoelectric Substrate

[0119] An amorphous silicon substrate sublayer was deposited on a single-crystal silicon wafer (resistivity 12000Ω·cm) using the LPCVD method to form a high acoustic impedance substrate layer. The deposition temperature of the LPCVD method was controlled at 530℃ and the deposition rate was 5nm / min.

[0120] SiO2 was further deposited on the amorphous silicon substrate sublayer using LPCVD. The resulting SiO2 layer served as a low acoustic impedance layer. The gas flow rate for SiO2 deposition was 50 sccm, the temperature was 600℃, and the deposition rate was 5 nm / min. The water diffusion coefficient of the resulting SiO2 layer was 8 × 10⁻⁶. -17 cm 2 / s, with a porosity of 1×10⁻⁶. 20 H atoms / cc, the thickness of the SiO2 layer is 500nm;

[0121] The SiO2 layer is polished to make the surface roughness of the bonding surface with the single crystal piezoelectric layer less than 0.3 nm;

[0122] Lithium tantalate ion implantation sheets were prepared by ion implantation, wherein the thickness of the thin film layer was 600 nm. The bonding surfaces of the SiO2 layer and the thin film layer were activated by plasma activation, respectively. The activation ion energy on the bonding surface of the SiO2 layer was 200 eV, and the activation ion energy on the bonding surface of the thin film layer was 300 eV. The activation time for both was 30 s, thereby obtaining a buffer layer with a thickness of 1 nm.

[0123] After bonding, the excess material layer is removed, and the lithium tantalate film layer is thinned and polished to obtain a composite single-crystal piezoelectric substrate.

[0124] Compared with composite single-crystal piezoelectric substrates prepared by conventional methods, the composite single-crystal piezoelectric substrates prepared in this embodiment have greatly increased structural stability, and the bonding strength can reach 10 MPa. The number of defects is reduced by 50% compared with composite single-crystal piezoelectric substrates containing dense low acoustic impedance layers.

[0125] The present application has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present application. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present application without departing from the spirit and scope of the present application, and all such modifications and improvements fall within the scope of the present application. The scope of protection of the present application is determined by the appended claims.

Claims

1. A composite single-crystal piezoelectric substrate, characterized by comprising: The composite single-crystal piezoelectric substrate comprises, from bottom to top, a high acoustic impedance substrate layer (1), a low acoustic impedance layer (2), a buffer layer (3) and a single-crystal piezoelectric layer (4), wherein the low acoustic impedance layer (2) has a diffusion to water greater than 3x10 -17 cm 2 / s at normal temperature; and the low acoustic impedance layer (2) has a porous structure.

2. The composite single crystalline piezoelectric substrate according to claim 1, characterized by The low acoustic impedance layer (2) has a porosity of 8 x 10 19 ~1 x 10 22 H atoms / cm 3 .

3. The composite single crystalline piezoelectric substrate according to claim 1 or 2, characterized by, The buffer layer (3) is doped with a first material and a second material, wherein the first material is a material for preparing the single-crystal piezoelectric layer (4), and the second material is a material for preparing the low acoustic impedance layer (2).

4. The composite single crystalline piezoelectric substrate according to claim 1 or 2, characterized by, The concentration of the first material in the buffer layer (3) gradually decreases, and the concentration of the second material gradually increases, from the interface between the buffer layer (3) and the low acoustic impedance layer (2) to the interface between the buffer layer (3) and the single-crystal piezoelectric layer (4).

5. The composite single crystalline piezoelectric substrate according to claim 1 or 2, characterized by, The thickness of the buffer layer (3) is 1-10 nm; and / or the interface roughness of the buffer layer (3) is less than 0.3 nm.

6. The composite single crystalline piezoelectric substrate according to claim 1 or 2, characterized by, The high acoustic impedance substrate layer (1) comprises a single-crystal silicon substrate sub-layer (11) and an undoped amorphous silicon substrate sub-layer (12), wherein the low acoustic impedance layer (2) is deposited on the undoped amorphous silicon substrate sub-layer (12).

7. The composite single crystalline piezoelectric substrate according to claim 6, wherein The undoped amorphous silicon substrate sub-layer (12) is deposited on the single-crystal silicon substrate sub-layer (11).

8. The composite single crystalline piezoelectric substrate according to claim 6, wherein The surface roughness of the undoped amorphous silicon substrate sub-layer (12) is less than 0.3 nm; and / or the resistivity is greater than 5000 Ω·cm.

9. The composite single crystalline piezoelectric substrate according to claim 6, wherein The composite single-crystal piezoelectric substrate is prepared by a method comprising the following steps: preparing an undoped amorphous silicon substrate sub-layer on the single-crystal silicon substrate sub-layer; preparing a low acoustic impedance layer on the undoped amorphous silicon substrate sub-layer; preparing a single-crystal piezoelectric layer on the low acoustic impedance layer to obtain a composite single-crystal piezoelectric substrate.

10. A method of producing the composite single-crystal piezoelectric substrate according to any one of claims 1 to 9, characterized by, The method comprises: preparing an undoped amorphous silicon substrate sub-layer on a single-crystal silicon substrate sub-layer; preparing a low acoustic impedance layer on the undoped amorphous silicon substrate sub-layer; preparing a single-crystal piezoelectric layer on the low acoustic impedance layer to obtain a composite single-crystal piezoelectric substrate.

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