Bus transceiver

Abstract

Embodiments of the present disclosure relate to bus transceivers. An integrated driver circuit for driving a two-wire line in a network node is described below. According to one embodiment, the driver circuit has a first terminal and a second terminal, both of which can be connected to a controller chip. The driver circuit also has at least one bus terminal connectable to a bus line. A control circuit of the driver circuit is designed to operate in a first mode or a second mode, and the control circuit is designed to output a receive signal at the second terminal in the second mode and to assume a low-power state in the first mode, the receive signal representing a bus signal received at the bus terminal. The control circuit is further designed to change from the first mode to the second mode when a first command is detected at the first terminal or the second terminal, and to change from the second mode to the first mode when the bus signal does not show any data for a predetermined period of time.

Description

Technical Field

[0001] This specification relates to a driver circuit (transceiver interface) for a serial bus, and more particularly to a driver circuit for a 2-wire Ethernet network node. Background Technology

[0002] Current developments in the field of driver assistance systems (ADAS) also necessitate improvements to so-called in-vehicle network (IVN) systems. Currently, one focus of development is improving Ethernet-based bus and network systems, with an emphasis on systems with high bandwidth and high data throughput. However, there are also applications dealing with lower bandwidth—particularly, but not limited to, the automotive industry. In these cases, lower data rates (e.g., 10 Mbit / s) are sufficient, and these are typically low-cost applications requiring simple, robust, and inexpensive drive circuitry, best known for example, from CAN (Controller Area Network) technology.

[0003] The IEEE 802.3cg standard describes Ethernet with a transmission rate of 10 Mbit / s, specifying 10BASE-T1S network technology (also known as 10SPE, 10 Mbit / s single-pair Ethernet). This standard was adopted by the Open Alliance Special Interest Group (OPG) to further develop Ethernet-based communication networks, particularly for automotive applications. OPG Technical Committee TC14 coordinated efforts to define common usability, compliance, and EMC (electromagnetic compatibility) requirements, and to develop test methods for the 10BASE-T1S PHY. PHY refers to Layer 1 (Physical Layer) according to the standardized OSI model. In this process, the interface between the digital and analog parts of 10BASE-T1S was specified.

[0004] One of the purposes of the invention described herein can be seen as contributing to the development and improvement of existing concepts as presented above. Summary of the Invention

[0005] The above-mentioned objectives are achieved by the circuits and methods according to the present invention. Various embodiments and further developments are described below.

[0006] The following describes an integrated driver circuit for driving a two-wire line in a network node. According to one embodiment, the driver circuit has a first connector and a second connector, both of which can be connected to a controller chip. The driver circuit also has at least one bus connector that can be connected to a bus line. The control circuitry of the driver circuit is designed to operate in either a first mode or a second mode, and is designed to: output a received signal at the second connector in the second mode, the received signal representing a bus line signal received at the bus connector; and occupy a low-power state in the first mode. The control circuitry is also designed to: switch from the first mode to the second mode when a first command is detected at the first or second connector, and switch from the second mode to the first mode when no data is displayed on the bus signal for a predetermined time period.

[0007] Furthermore, a method for driving a two-wire line in a network node using a driver circuit is described. According to one embodiment, the method includes receiving a first command at a first connector of the driver circuit or at a second connector of the driver circuit. The method further includes switching from a first mode to a second mode upon receiving the first command, wherein the driver circuit occupies a low-power state in the first mode. The method includes, in the second mode, receiving a bus signal at a bus connector of the driver circuit and outputting a received signal at the second connector of the driver circuit, the received signal representing data contained in the received bus signal. The method further includes switching from the second mode to the first mode when the bus signal does not display any data for a predetermined time period. Attached Figure Description

[0008] The embodiments are explained in detail below with the aid of the accompanying drawings. These drawings are not necessarily drawn to scale, and the embodiments are not limited to the aspects shown. Rather, the focus is on illustrating the principles on which the embodiments are based.

[0009] Figure 1 An example of an integrated driver circuit with eight pins is illustrated, which serve as an interface between the microcontroller and the 10BASE-T1S two-wire line (twisted pair).

[0010] Figure 2 This describes four different modes of driver circuitry (transceiver interface) as defined by the Open Consortium TC14.

[0011] Figure 3 The timing diagram illustrates the encoding of commands used to trigger mode changes.

[0012] Figure 4 The flowchart illustrates... Figure 1 Example of the structure of a driver circuit.

[0013] Figure 5 and Figure 6 According to the timing diagram... Figure 1 The driver circuit operates with multiple mode switching modes.

[0014] Figure 7 Explanation Figure 6 An extended example of the example.

[0015] Figure 8 According to the timing diagram... Figure 6 An alternative to the example. Detailed Implementation

[0016] Figure 1 A circuit with a microcontroller 10 and an integrated driver circuit 20 (driver IC) is shown, which represents the interface between the microcontroller 10 and a two-wire bus line in a network node. The example described herein relates to an Ethernet-based system (especially 10BASE-T1S). However, the concepts described herein can also be applied to other network technologies under certain circumstances. The driver IC 20 can have a standard chip case with eight pins (chip contacts). Figure 1 These pins are labeled TXD, RXD, ED, L+, L-, VCC, GND, and VIO.

[0017] According to the Open Consortium TC14 definition, five pins are required for communication: pins L+ and L- for connecting the two-wire line (bus line), and pins TXD, RXD, and ED for communication between microcontroller 10 and driver IC 20. At pin TXD, driver IC 20 receives serial data S from microcontroller 10. TX (Bitstream), at pin RXD, driver IC20 will transmit serial data S RX The bitstream is output to microcontroller 10, and pin ED indicates to microcontroller 10 whether active communication has occurred on the bus. Additionally, powering driver IC 20 requires two pins: one for receiving the supply voltage V. S The power supply pin VCC and the ground pin GND.

[0018] Pin 8, VIO, is not always necessary for communication; however, it can be used in practice because the power supply voltage of microcontroller 10 is not always the same, and microcontrollers with different operating voltages VDD (e.g., 3.3V, 5V, etc.) can be used depending on the application. The microcontroller's operating voltage VDD also defines the signal levels at pins RXD, TXD, and ED, so driver IC 20 must know the microcontroller's operating voltage VDD. Therefore, driver IC 20 receives the microcontroller's operating voltage VDD at pin VIO.

[0019] The driver IC 20 can operate in different modes. The currently defined mode of the Open Consortium TC14 is... Figure 2 The example is shown below. Figure 2 Possible modes include Boot Mode (M0), Normal Mode (M1), Transmit Mode (M2), Standby Mode (M3), and Config Mode (M4). Mode transitions from one mode to another are triggered by specific commands. Figure 2 In the example, these are labeled RESET, TRANSMIT, SLEEP, and CONFIG.

[0020] The RESET command is accepted in every mode and always triggers a transition to normal mode M1. The TRANSMIT command is accepted only in normal mode M1 and triggers a transition to transmit mode M2. The SLEEP command triggers a transition to standby mode M3, while the CONFIG command triggers a transition to configuration mode M4. The transition from transmit mode M2 ​​back to normal mode M1 can be triggered by the RESET command or by the expiration of a timer (Jabber timer). The Jabber timer is started with the transition to transmit mode M2 ​​and resets on each falling edge at the TXD pin. Once no more bits are transmitted, the Jabber timer counts to its maximum value (e.g., 8 μs). Once this maximum value is reached, a flag (jabber_timer_done) is set, and the transition back to normal mode M1 occurs.

[0021] Data output to the bus lines (i.e., pins L+ and L-) is only possible in transmit mode M2. Therefore, normal mode M1 is also called read-only mode. In startup mode M0, switching can only be performed via power-on reset (POR). CONFIG and SLEEP commands are accepted only in normal mode M1. Different modes can be implemented, for example, using a finite state machine. It should be emphasized here that... Figure 2 The patterns shown should be understood as examples only. Existing concepts and standards are constantly evolving, and therefore... Figure 2 The patterns and their names shown will also need some changes. In future systems, one or more patterns can be omitted, and new patterns can be added.

[0022] Due to the limited number of pins on the driver IC 20, the aforementioned command is encoded in the (binary) data signal S. TXIn this configuration, driver IC 20 receives the data signal from microcontroller 10 at the TXD pin. Examples of commands RESET, TRANSMIT, and SLEEP are provided in [the documentation / section]. Figure 3 The figures (a) to (c) are shown. Figure 3 Each diagram in the figure shows the data signal S received at pin TXD. TX And the commands associated with it, where NONE means "no command".

[0023] according to Figure 3 Figure (a) shows the duration t of the high level of the microcontroller 10. da and the duration t of the following low level rst Send a RESET command to driver IC 20 in signal form for at least a duration t gap A high level appears again. For example, the duration t. da It can be approximately 20 μs, with a duration of t. rst It can be approximately 80 μs. Duration t gap It can also be 20 μs. The RESET command has a duration t. rst It is valid at the end.

[0024] according to Figure 3 Figure (b) shows the duration t of the high level of the microcontroller 10. da Two subsequent low pulses send a TRANSMIT command to driver IC 20, the durations of which are t and t, respectively. pl Where, between these two low pulses for duration t h1 A high level is generated, and for at least a duration t after the second low pulse. h2 A high level appears again. For example, the pulse duration t of the low pulse. pl It can be approximately 20 μs. The pause between low pulses (duration t) h1 The duration can be approximately 180 μs, and the duration t h2 It can also be 20μs. The TRANSMIT command is valid at the end of the second low pulse. In transmit mode M2, driver IC 20 receives the DME bit stream (DME = Differential Manchester Encoded) on the TXD pin.

[0025] according to Figure 3 Figure (c) shows the microcontroller 10 transmitting a high level for a duration t. da and the duration t of the following low level slp (For example, at least 16μs) A command SLEEP is sent as a signal to driver IC 20, followed by a high level reappearance. The SLEEP command lasts for a duration of t.slp It is effective at the end. The SLEEP and RESET commands should not be confused, because the SLEEP command is only accepted in normal mode M1, in which the RESET command is meaningless and therefore not needed.

[0026] Figure 4 The block diagram illustrates examples of possible structures for driver IC 20. Driver IC 20, particularly logic 24 and mode control 23, is largely implemented using fixed-wired (hard-wired) digital circuitry. Alternatively, driver IC 20 may also include a processor designed to execute software instructions to provide the desired functionality. In this case, logic 24 and mode control 23 can also be software function blocks. Combinations of fixed-wired logic circuitry and programmable processors are also possible. Blocks 13, 14, and 15 of the microcontroller (logic, mode control, and communication control) are typically software / firmware function blocks executed by the microcontroller's processor. First, the functionality of the components of driver IC 20 will be described in more detail.

[0027] Logic circuit 24 receives data signal S at pin TXD. TX And based on data signal S TX The control signal generated is used by the driver circuit 25, which has differential outputs; that is, the two outputs of the driver circuit 25 are connected to pins L+ and L-. The bus voltage V between pins L+ and L- depends on the control signal fed to the driver circuit 25. BUS It can be positive, negative, or approximately zero. The bus voltage V is above, for example, a threshold of 30mV. BUS This can be interpreted as a high level. Similarly, a bus voltage V below, for example, a threshold of -30mV. BUS This can be interpreted as a low level. However, the peak-to-peak voltage between pins L+ and L- may be higher, for example, in the range of 0.8V-2V (depending on the line termination). Logic circuit 24 is also designed to decode the above command and forward the received command to mode control 23.

[0028] (Window) Comparator 22 can use the aforementioned threshold (±30mV) to measure the bus voltage V BUS Converted into the corresponding binary data signal S RX Then, it can be output at the RXD pin (via multiplexer 26). However, the specific value of the comparator threshold depends on the corresponding implementation. Comparator 21 (via multiplexer 27) generates the output signal S at the ED pin. ED This signal indicates activity on the bus. This means that signal S ED A high level indicates that a positive or negative bus voltage is being effectively applied to the bus (between pins L+ and L-). If the bus voltage V...BUS When the voltage is close to zero, the bus output of driver IC 20 is in a high-resistance (high Z) state. For example, the comparator threshold can be approximately 300mV and -300mV. That is, when the bus voltage V... BUS When the voltage is greater than 300mV or less than -300mV, the output signal S of comparator 21 ED Bus activity is indicated by a high level. The threshold can also be determined based on the actual bus voltage (peak-to-peak).

[0029] Mode control 23 “sees” the received commands (see Figure 3 The Jabber timer mentioned above and the signal S output at pin ED. ED This allows for the initiation of mode transitions. In some embodiments, mode transitions cause the driver IC20 to output a specific signal or a specific signal level at pins RXD and / or ED. For example, it might be desirable to output a high level at pin ED in standby mode M3, independent of bus communication (see also...). Figure 5 (The level change at ED at time point t5). Additionally or alternatively, it may be desirable to output an acknowledgment signal at the RXD pin after a mode change, indicating that the mode change has been performed. For example, an acknowledgment signal could be output at the RXD pin in standby mode, independent of bus communication, containing a defined bit pattern or having a defined level (see also...). Figure 7 To this end, driver IC 10 includes the aforementioned multiplexers 26 and 27, which can optionally connect the outputs of mode control 23 or comparators 22 and 21 to pins RXD or ED. Even in the absence of bus communication, i.e., the voltage V on the bus... BUS When the voltage is approximately 0 volts (between pins L+ and L-), multiplexers 26 and 27 can also enable mode control 23 to output signals on pins RXD and ED, respectively.

[0030] On the microcontroller 10 side, the mode controller 13 is designed to output a corresponding command to logic 14 in the event of a mode change, which outputs the command to signal S. TX like Figure 3 The command is output using the encoding shown. In transmit mode, communication control 15 generates a data stream (e.g., a data frame according to a communication protocol, such as an Ethernet frame). In the current example, this data stream is encoded by logic 14 using Differential Manchester Encoding (DME). The resulting DME bit stream is output at the output pin of microcontroller 10 and is sent to the TXD pin of driver IC 20. Buffers 11 and 12 receive signal S. RX and S ED They are then converted into corresponding logic levels. The communication controller 15 sees signal S at the outputs of buffers 11 and 12. RXand S ED The logical state.

[0031] In transmit mode M2, the bit stream received at pin TXD is output on the bus (the bus voltage V between pins L+ and L-). BUS Additionally (in other modes), the TXD pin can be used to transmit commands to the driver IC 20. The RXD pin is only needed in normal mode M1 when signals are received at pins L+ and L-. If this is not the case, the RXD pin can be used to send additional information to the microcontroller 10. According to the implementation, the receiver (comparator 22) can also function in transmit mode M2, so that signals sent to the bus are also simultaneously received (echoed back).

[0032] Figure 5 and Figure 6 The timing diagram illustrates the origin from... Figure 1 The driver IC 20 operates with multiple mode switching modes (starting from normal mode M1). Figure 5 In the example, microcontroller 10 sends a TRANSMIT command at time t0 (see...). Figure 3 (See Figure (b)). The TRANSMIT command becomes valid (takes effect) at time t1, and the time period between t0 (microcontroller startup command) and t1 (command takes effect in driver IC) is called the transition phase. Starting from time t1, driver IC 20 operates in transmit mode M2 ​​and is able to receive data at the TXD pin and output the corresponding bus voltage V on the bus (at pins L+ and L-). BUS Effective communication on the bus is achieved via the ED pin (signal S). ED The high level is displayed at the RXD pin (signal S). ED This displays the logical status on the bus. For example, S RX =High corresponds to V BUS >300mV, while S RX = Low corresponds to V BUS <-300mV. This value is, of course, just an example. Data transmission (e.g., frames) from time point t... A Start and at time t B The end. It goes without saying. Figure 5 The figure at time point t is shown A and t B The level transitions between these levels represent any sequence of data bits.

[0033] Starting at time t2, microcontroller 10 initiates another mode transition by sending a RESET command (see [link]). Figure 3(See Figure (a)). At time t3, the command takes effect in driver IC 20, and driver IC 20 switches back to normal mode M1. The time period between time points t2 and t3 is also known as the transition phase. In the example shown, driver circuit 25 (see Figure (a)) Figure 4 At the end of the transition phase (time point t3), it becomes invalid and outputs a bus voltage of approximately zero volts V with a relatively high output resistance (corresponding to the bus termination). BUS When V BUS When the voltage is 0V, the output of comparator 22 remains in its current state until the bus voltage V is reached. BUS Until the change occurs again. In normal mode M1, driver IC 20 is ready to receive data from the bus and output the corresponding data stream (data signal S) at the RXD pin. RX (See also) Figure 4 The received data is in Figure 5 The gray shaded area represents this. At time t4, microcontroller 10 initiates a SLEEP command, which becomes active in driver IC 20 at time t5. Driver IC 20 then transitions to standby mode M3 after the transition from t4 to t5. The signal S at the ED pin... ED It is designated as high level in standby mode M3.

[0034] Existing concepts and specifications rely on the fact that microcontroller 10 is always available and that communication between microcontroller 10 and driver IC 20 is always possible. However, if microcontroller 10 is damaged or shut down, has just been restarted, or is not functioning as expected due to other problems, driver IC 20 can no longer be controlled by microcontroller 10. From a safety perspective, this situation is generally undesirable. This problem is addressed through... Figure 6 The performance of the driver IC 20 shown is thus resolved so that when no valid communication is detected on the bus for a defined period of time (e.g., 100 μs), the driver IC 20 - does not receive the SLEEP command - automatically switches to standby mode M0.

[0035] Until time point t4, Figure 6 Examples and Figure 5 The same as the previous example. However, Figure 6 The example is based on the following assumption: Microcontroller 10 malfunctions sometime after time point t3 and (for whatever reason) is unable to send commands to driver IC 20. From time point t3 onwards, driver IC 20 is in normal mode and is able to receive data from the bus. Figure 6 In the example, bus communication ends at time t4, which is indicated by the signal S output at the ED pin. EDThe high-to-low level change indicates that once the signal level output at the ED pin is low, a timer (e.g., the timer included in mode control 23) is used to determine how long (in normal mode M1) there has been no bus communication. Within a defined time period T... S After 100μs (for example), even if no SLEEP command is received, driver IC 20 then switches to standby mode. That is, the time period T after activating normal mode M1. S When no communication is detected on the bus (signal S) ED When kept low; or when communication on the bus ends (signal S) ED During the time period from high level to low level, driver IC 20 automatically switches from normal mode M1 to standby mode M3 and does not receive the SLEEP command.

[0036] Figure 7 It shows Figure 6 An extension of the example. Figure 6 The timing diagram begins at time point t3 and shows the relationship between time points t3 and t5. Figure 6 The same situation applies. During the time period T after the bus communication ends... s At time t5, the automatic transition from standby mode M3 to standby mode is performed. During standby mode M3, driver IC 20 outputs a specific bit pattern (signal S) at the RXD pin. RX This signal notifies microcontroller 10 (once the microcontroller becomes available again, for example, after a reboot) that an automatic transition to standby mode M3 has been performed. The bit mode can be output periodically, for example, at pin RXD, until a RESET command is triggered, thus triggering another mode transition. In an embodiment, when driver IC 20 transitions to standby mode M3, the signal S at pin ED is output according to specifications. ED In these embodiments, the microcontroller 10 can, for example, be set to a high level based on signal S after a restart. ED -Based on the mentioned bit pattern-Identification: Driver IC 20 has not lost its power supply voltage and is in standby mode, although it is not triggered by the SLEEP command.

[0037] In the example above, driver IC 20 is designed to receive commands from microcontroller 10 at the TXD pin, where it also receives data to be sent to the bus. It may also be desirable to transmit data and commands to driver IC 20 in different ways. Figure 8For example, the RXD pin can be configured as both an output and input pin, where driver IC 20 is designed to output a "weak 1" in standby mode, which can be rewritten by microcontroller 10. In this case, a "weak 1" means that driver IC 20 is designed to output a high level at the RXD pin, where the voltage source generating this high level has relatively high internal voltage, so microcontroller 10 can easily pull the level at the RXD pin low. This low level can be detected by driver IC 20, thus the RXD pin can also be used as an input pin. During normal mode and transmit mode, driver IC 20 generates a "strong" signal level (i.e., with low internal voltage) at the RXD pin. In these cases, the RXD pin is used only as an output pin.

[0038] Figure 8 The example begins with the driver IC initially in standby mode. At time t0, microcontroller 10 initiates a RESET command, which—with… Figure 6 The example is different – ​​it is sent to the RXD pin (instead of the TXD pin). The RESET command becomes valid at time t1, and driver IC 20 switches to normal mode. Shortly thereafter, the microcontroller begins sending data, for which it first sends a TRANSMIT command to the TXD pin, which takes effect at time t2. That is, at time t2, driver IC 20 switches to transmit mode, and the data generated at the TXD pin is output to the bus (pins L+ and L-) (i.e., signal S). RX Indicates signal S TX In this example, the sending mode ends when the Jabber timer mentioned above expires at time t3 (the flag Jabber_timer_done is set).

[0039] From time point t3, driver IC 20 resumes normal operation and is ready to receive data. If—as in Figure 6 Same as in the previous example - for a specific time period T S No activity was detected on the bus (i.e., the voltage V between pins L+ and L-). BUS When the voltage is approximately zero volts, driver IC 20 switches to standby mode without an explicit SLEEP command. In this example, standby mode begins at time t4. With the start of standby mode, a weak 1 is output again at the RXD pin, and the RXD pin is used as an input pin again.

Claims

1. An integrated driver circuit, comprising the following: A first connector (TXD) and a second connector (RXD), both of which can be connected to a control chip; At least one bus connector (L+, L-) that can be connected to a bus line; A control circuit, designed to operate in standby mode (M3) or read-only mode (M1), wherein the control circuit is designed to: In the read-only mode (M1), a receive signal (S) is output at the second connector (RXD). RX The received signal refers to the bus signal (V) received at the bus connector (L+, L-). BUS );as well as It occupies a low-power state in the standby mode (M3); and The control circuit was also designed as follows: When a first command is detected at the first connector (TXD) or the second connector (RXD), the system switches from the standby mode (M3) to the read-only mode (M1); and When the bus signal (V) BUS For the scheduled time period (T) S When no data is displayed, the system switches from the read-only mode (M1) to the standby mode (M3). The control circuit is also designed to operate in transmit mode (M2), in which the bus signal (V) BUS The bus signal is output at the bus connector (L+, L-), and the bus signal represents the data signal (S) received at the first connector (TXD). TX ),as well as The control circuit is also designed to switch from the read-only mode (M1) to the transmit mode (M2) when a second command is detected at the first connector (TXD).

2. The driver circuit according to claim 1, The first command is represented by a binary signal with a sequence of level changes.

3. The driver circuit according to claim 1 or 2, The control circuit is also designed to: after the predetermined time period (T) S After switching from the read-only mode (M1) to the standby mode (M3), an acknowledgment signal is output at the second connector (RXD).

4. The driver circuit according to claim 1 or 2, The second connector (RXD) is configured as an input in the standby mode (M3), and The control circuit is designed such that when the first command is received at the second connector (RXD) configured as an input segment, the control circuit switches from the standby mode (M3) to the read-only mode (M1).

5. The driver circuit according to claim 4, The second connector (RXD) is configured as an output in the read-only mode (M1), and the received signal (S) RX It is output at the output terminal.

6. The driver circuit according to claim 1 or 2, The bus signal (V) received at the bus connector (L+, L-) in the read-only mode (M1) is... BUS It conforms to the 10BASE-T1S standard.

7. A network node having the following: Microcontroller (10); The integrated driver circuit according to any one of claims 1 to 6, wherein a first pin (OUT1) of the microcontroller is connected to the first connector (TXD) of the driver circuit (20), and a second pin (IN1) of the microcontroller is connected to the second connector (TXD) of the driver circuit (20); and A two-wire bus line is connected to the bus connector (L+, L-) of the driver circuit. The microcontroller (10) is designed to generate the first command and transmit the first command to the driver circuit (20).

8. A method for operating a driver circuit, the method comprising: The first command is received at the first connector (TXD) or the second connector (RXD) of the driver circuit (20); When the first command is received, the system switches from standby mode (M3) to read-only mode (M1), wherein the driver circuit occupies a low-power state in the standby mode (M3); In the read-only mode (M1): a bus signal (V) is received at the bus connectors (L+, L-) of the driver circuit. BUS ), and outputs a received signal (S) at the second connector (RXD) of the driver circuit. RX ), wherein the received signal (S) RX ) indicates that the received bus signal (V) BUS The data contained in ) When the bus signal (V) BUS For the scheduled time period (T) S When no data is displayed, the system switches from the read-only mode (M1) to the standby mode (M3). When a second command is detected at the first connector (TXD), the system switches from read-only mode (M1) to transmit mode (M2), wherein in transmit mode (M2), the bus signal (V) BUS The bus signal is output at the bus connector (L+, L-), and the bus signal represents the data signal (S) received at the first connector (TXD). TX ).

9. The method according to claim 8, further comprising: After the predetermined time period (T) S After switching from the read-only mode (M1) to the standby mode (M3), an acknowledgment signal is output at the second connector (RXD).

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