Semiconductor wafer manufacturing system and method for manufacturing semiconductor wafer

Abstract

The embodiments disclosed herein provide a semiconductor wafer manufacturing system and a method for manufacturing semiconductor wafers, the method for manufacturing semiconductor wafers comprising: moving a plurality of lifting pins of a wafer seat to a lifting position; moving a semiconductor wafer to above the wafer seat and placing the semiconductor wafer on the lifting pins at the lifting position; using a camera assembly to generate an image of the semiconductor wafer and the wafer seat; calculating position offset information of the semiconductor wafer based on the image; determining whether the position offset information of the semiconductor wafer is within an acceptable range; and when the position offset information is within the acceptable range, sending a driving signal to an actuator connected to the lifting pins based on the calculated position offset information, so that the actuator drives the displacement of the semiconductor wafer relative to the wafer seat.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor wafer and a semiconductor wafer manufacturing system, and more particularly to a method and a system for calibrating the position of a semiconductor wafer relative to a wafer seat. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layer materials, conductive layer materials, and semiconducting layer materials on a semiconductor substrate, followed by patterning the various material layers using a lithography process to form circuit components and parts on the semiconductor substrate. Technological advances in the materials and design of integrated circuits have led to the development of multiple generations of integrated circuits. Each generation has smaller and more complex circuits than the previous generation.

[0003] In the manufacture of semiconductor devices, a variety of manufacturing tools are used in sequence to manufacture integrated circuits on semiconductor wafers. In the manufacturing tools, a wafer bed is often used to carry the semiconductor wafer. However, if the semiconductor wafer placed on the wafer bed is not centered on the wafer bed, it will lead to poor uniformity defects during the semiconductor processing process. Summary of the invention

[0004] An embodiment of the present disclosure provides a method for manufacturing a semiconductor wafer, comprising moving a plurality of lifting pins of a wafer seat to a lifting position; moving a semiconductor wafer to above the wafer seat and placing the semiconductor wafer on the lifting pins at the lifting position; using a camera assembly to generate an image of the semiconductor wafer and the wafer seat; calculating position offset information of the semiconductor wafer based on the image; determining whether the position offset information of the semiconductor wafer is within an acceptable range; and when the position offset information is within the acceptable range, sending a driving signal to an actuator connected to the lifting pins based on the calculated position offset information, so that the actuator drives the displacement of the semiconductor wafer relative to the wafer seat.

[0005] Another embodiment of the present disclosure provides a semiconductor wafer manufacturing system, including a main body, configured to carry a semiconductor wafer and having a plurality of through holes; a rod, located below the main body; a plurality of lifting pins, connected to the rod and movably disposed in the through holes; a photographic assembly, disposed above the main body and configured to generate an image of the main body; a first actuator, connected to the rod and configured to control the displacement of the rod in a vertical direction; a plurality of second actuators, each connected to the lifting pin and configured to control the displacement of the lifting pin in a horizontal direction; and a control module, electrically connected to the photographic assembly and the second actuator, wherein the control module sends a control signal to the second actuator according to the image generated by the photographic assembly to control the displacement of the lifting pin in the horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of each feature may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A schematic diagram showing a semiconductor wafer manufacturing system for processing a semiconductor wafer according to some embodiments of the present disclosure;

[0008] Figure 2 A schematic diagram showing partial components of a processing tool according to some embodiments of the present disclosure;

[0009] Figure 3 A top view showing a wafer bed having a semiconductor wafer placed thereon according to some embodiments of the present disclosure;

[0010] Figure 4 show Figure 3 A cross-sectional view of the wafer base on the AA section line;

[0011] Figure 5A A schematic diagram showing a lifting pin according to some embodiments of the present disclosure;

[0012] Figure 5B A schematic diagram showing a lifting pin according to some other embodiments of the present disclosure;

[0013] Figure 6 A block diagram showing some components of a semiconductor wafer manufacturing system according to some embodiments of the present disclosure;

[0014] Figure 7 A flowchart showing a method of manufacturing a semiconductor wafer according to some embodiments of the present disclosure;

[0015] Figure 8 A schematic diagram showing some operations of a method of manufacturing a semiconductor wafer according to some embodiments of the present disclosure, wherein the lift pins are in a raised position;

[0016] Fig. 9 A schematic diagram showing some operations of a method for manufacturing a semiconductor wafer according to some embodiments of the present disclosure, wherein the semiconductor wafer is placed on lift pins by a robot arm;

[0017] Fig.10 A schematic diagram showing some operations of a method of manufacturing a semiconductor wafer according to some embodiments of the present disclosure, wherein the semiconductor wafer is placed on lift pins and is offset relative to a wafer bed;

[0018] Fig.11Displaying images generated by a photographic assembly according to some embodiments of the present disclosure;

[0019] Fig.12 A schematic diagram showing some operations of a method for manufacturing a semiconductor wafer according to some embodiments of the present disclosure, wherein the semiconductor wafer is placed on lift pins and centrally disposed relative to a wafer bed;

[0020] Fig.13 A schematic diagram showing a partial operation of a method for manufacturing a semiconductor wafer according to some embodiments of the present disclosure, wherein the semiconductor wafer is placed on the upper surface of a body of a wafer bed;

[0021] Fig.14 Schematic diagram showing some components of a processing component according to some embodiments of the present disclosure.

[0022]

Explanation of symbols

[0023] 1:Semiconductor wafer manufacturing system

[0024] 2: Mounting port

[0025] 3: Load lock chamber

[0026] 4: Wafer carrier

[0027] 5: Semiconductor wafer

[0028] 51: Edge

[0029] 6: Robotic Arm

[0030] 8: Measuring room

[0031] 10: Processing tools

[0032] 10b: Processing tools

[0033] 11: Reaction chamber

[0034] 111: reaction chamber wall

[0035] 112: reaction chamber bottom

[0036] 12: Upper electrode assembly

[0037] 120: Nozzle

[0038] 121: Flat electrode

[0039] 122: Ring electrode

[0040] 14: RF coil assembly

[0041] 15: First RF power supply

[0042] 16: Impedance matching circuit

[0043] 17: Second RF power supply

[0044] 18: Plasma

[0045] 20: Wafer seat

[0046] 21:Ontology

[0047] 211: Upper surface

[0048] 212: Lower surface

[0049] 213: Edge

[0050] 210: Perforation

[0051] 22: Support components

[0052] 221: Rod

[0053] 222: Extension

[0054] 223: Lifting pin

[0055] 223a: Lifting pin

[0056] 2230: Top

[0057] 224: Actuator (first actuator)

[0058] 225: Actuator (second actuator)

[0059] 226: Column

[0060] 2261: Top

[0061] 227: Rough structure

[0062] 40:Photographic Components

[0063] 41b: Photographic Components

[0064] 42b: Photographic Components

[0065] 43b: Photographic Components

[0066] 44b: Photographic Components

[0067] 90: Control module

[0068] 91: Processor

[0069] 92: Memory

[0070] S100: Method for manufacturing semiconductor wafer

[0071] S110: Operation

[0072] S120: Operation

[0073] S130: Operation

[0074] S140: Operation

[0075] S150: Operation

[0076] S160: Operation

[0077] S170: Operation

[0078] S180: Operation

[0079] C1: Center

[0080] C2: Center

[0081] D1: Position offset

[0082] D2: Position offset

[0083] D3: Position offset

[0084] D4: Position offset

[0085] D5: Distance

[0086] D6: Distance

[0087] M: Image

[0088] P1: Reference point

[0089] P2: Reference point

[0090] P3: Reference point

[0091] P4: Reference point DETAILED DESCRIPTION

[0092] The following disclosure provides many different embodiments or examples to implement the different features of the present disclosure. The following disclosure in this specification describes specific examples of various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the present disclosure. For example, if the following disclosure in this specification describes forming a first feature on or above a second feature, it means that it includes an embodiment in which the first feature formed is in direct contact with the second feature, and also includes an embodiment in which an additional feature can be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, different examples in the description of the present disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and / or the described appearance structures.

[0093] Furthermore, in order to facilitate the description of the relationship between an element or feature component and another (plural) element or (plural) feature component in the accompanying drawings, spatially related terms may be used, such as "under...", "below", "lower", "above", "upper" and similar terms. It is understood that in addition to the orientations shown in the accompanying drawings, spatially related terms cover different orientations of the device in use or operation. The device may also be positioned otherwise (for example, rotated 90 degrees or located in other orientations), and the description of the spatially related terms used may be interpreted accordingly. It is understood that additional operating steps may be provided before, during and after the method, and in some method embodiments, some of the operating steps described may be replaced or omitted.

[0094] It should be noted that the embodiments discussed herein may not necessarily describe every component or feature that may be present in the structure. For example, one or more components may be omitted from the drawings, such as when the discussion of the component may be sufficient to convey the various aspects of the embodiment. Furthermore, the method embodiments discussed herein may be discussed in a particular order of proceeding, however, in other method embodiments, they may be proceeded in any reasonable order.

[0095] Figure 1 A schematic diagram of a semiconductor wafer manufacturing system 1 for processing a semiconductor wafer 5 is shown in accordance with some embodiments. Figure 1 The semiconductor wafer manufacturing system 1 includes a load port 2 , a load lock chamber 3 , a robot arm 6 , a plurality of processing tools 10 , one or more metrology chambers 8 , and a control module 90 .

[0096] According to some embodiments, the semiconductor wafer 5 is made of silicon, germanium or other semiconductor materials. According to some embodiments, the semiconductor wafer 5 is made of a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). According to some embodiments, the semiconductor wafer 5 is made of an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbon (SiGeC), gallium arsenide phosphide (GaAsP) or gallium indium phosphide (GaInP). According to some embodiments, the semiconductor wafer 5 includes a crystal film layer. For example, the semiconductor wafer 5 has a crystal film layer covering a bulk semiconductor. According to some embodiments, the semiconductor wafer 5 may be a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate.

[0097] The semiconductor wafer 5 may include a plurality of device elements. For example, the device elements formed on the semiconductor wafer 5 may include a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor transistor (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field-effect transistor (PFET) or a p-type field-effect transistor (n-channel field-effect transistor (NFET), and / or other elements. The plurality of device elements on the semiconductor wafer 5 have undergone a plurality of processing steps, such as deposition, etching, ion implantation, photolithography, annealing, and / or other processes.

[0098] The loading port 2 is configured to support and dock a wafer carrier 4 to facilitate the delivery of semiconductor wafers 5 into the semiconductor wafer manufacturing system 1 and the subsequent removal of the semiconductor wafer manufacturing system 1. The wafer carrier 4 is configured to transport a plurality of semiconductor wafers, such as 6 wafers, 12 wafers, 24 wafers, etc. The wafer carrier 4 can be a Standard Mechanical Interface (SMIF) for loading semiconductor wafers each having a diameter of 18 mm. Alternatively, the wafer carrier 4 can be a Front Opening Unified Pod (FOUP), which can be used to load 300 mm or 450 mm semiconductor wafers or semiconductor wafers having a larger diameter. However, other types and / or sizes of wafer carriers are not excluded.

[0099] The load lock chamber 3 is disposed between the semiconductor wafer manufacturing system 1 and the loading port 2. The load lock chamber 3 is configured to isolate the air pressure in the semiconductor wafer manufacturing system 1 from the external environment to preserve the pressure in the semiconductor wafer manufacturing system 1. When the semiconductor wafer 5 from the wafer carrier 4 is sent into the load lock chamber 3, the door of the load lock chamber 3 is sealed. In this way, an airtight environment is constructed in the load lock chamber 3. The load lock chamber 3 can generate a pressure that matches the pressure in the semiconductor wafer manufacturing system 1 by changing the gas content inside. When the correct air pressure is reached, the robot 6 can move the semiconductor wafer 5 from the load lock chamber 3. The robot 6 transfers the wafer between the load lock chamber 3, the processing tool 10 and the metrology chamber 8. The robot 6 is operable to position and place the semiconductor wafer 5 in the processing tool 10 before processing, and remove the semiconductor wafer 5 from the processing tool 10 after processing.

[0100] The processing tool 10 is configured to perform one or more semiconductor processing processes, such as plasma processing, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), annealing, dry etching, degassing, pre-cleaning, cleaning, post-cleaning, etc. The metrology chamber 8 is configured to measure various properties of the wafer before or after processing. In some embodiments, one or more metrology chambers 8 are integrated into one or more processing tools 10. Figure 1 Although five processing tools 10 and two metrology chambers 8 are shown, the remaining number of processing tools 10 and / or metrology chambers 8 are included in the scope of the present disclosure. Similarly, in some embodiments, the semiconductor wafer manufacturing system 1 includes more than one robot arm 6 and / or load lock chamber 3. The control module 90 is configured to control the processing, transportation and measurement of the wafer. Figure 6 The detailed features of the control module 90 are further described.

[0101] Figure 2 A schematic diagram showing partial components of a processing tool 10 according to some embodiments. In some embodiments, the processing tool 10 is a plasma reaction chamber and is used to perform semiconductor wafer processing procedures including plasma etching processing. However, the processing tool 10 is not limited to performing the above-mentioned processing, and the processing tool 10 can be used to perform any process processing of semiconductor wafers. Although the embodiments of the present disclosure are expressed in this specific architecture, it can be understood that the present disclosure can also be applied to various other different architectures and designs. In addition, this processing tool 10 is only a simple drawing expression, and some components of the processing tool 10 are not shown. For example, valves, sealing components and other similar items are not shown. People familiar with this art can understand that these and other parts that make up the processing tool 10 can be included therein.

[0102] like Figure 2As shown, the processing tool 10 includes a reaction chamber 11, an upper electrode assembly 12, a radio frequency coil assembly 14, a wafer seat 20, a camera assembly 140 and a control module 90. The reaction chamber 11 defines an area for performing a processing process. In some embodiments, the reaction chamber 11 includes a reaction chamber wall 111 and a reaction chamber bottom 112. The reaction chamber wall 111 extends vertically from the edge of the reaction chamber bottom 112. In some embodiments, a slit valve that can be selectively sealed may be provided on the reaction chamber wall 111 to facilitate the transfer of the semiconductor wafer 5 into and out of the processing tool 10. In some embodiments, the reaction chamber bottom 112 includes an exhaust port (not shown) for extracting gas from the reaction chamber 11. For example, an exhaust system (including a throttle valve and a vacuum pump, etc.) may be connected to the exhaust port of the reaction chamber bottom 112. Once the slit valve is sealed, the exhaust system may be operated to extract and maintain the vacuum in the reaction chamber 11.

[0103] The upper electrode assembly 12 is located above the reaction chamber 11 and includes a plate electrode 121 and a ring electrode 122. The plate electrode 121 is located at the upper end of the reaction chamber 11, and the ring electrode 122 is disposed between the plate electrode 121 and the reaction chamber wall 111. In some embodiments, the plate electrode 121 defines a nozzle 120 for distributing gas. In this configuration, the plate electrode 121 can be used as a component for distributing gas to the reaction chamber 11 and is coupled to a gas source (not shown). This gas source contains precursors or process gases for processing the reaction chamber 11. In some embodiments, the plate electrode 121 is connected to a DC power source (e.g., ground). In some embodiments, the plate electrode 121, the reaction chamber wall 111, and a reaction chamber bottom 112 are connected to ground together.

[0104] In some embodiments, the RF coil assembly 14 surrounds the annular electrode 122 and is coupled to the first RF power source 15, and generates and maintains the plasma 18 in the reaction chamber 11 through the RF power provided by the first RF power source 15. In one embodiment, the first RF power source 15 is a high frequency RF power source. The first RF power source 15 is connected to the RF coil assembly 14 via an impedance matching circuit 16 to enhance the dissociation of the process gas and the plasma density. For example, the impedance matching circuit 16 may include one or more capacitors, inductors and other circuit components. The first RF power source 15 delivers RF power to the RF coil assembly 14 at a frequency of approximately 2 MHz or above, but the present disclosure is not limited to this. In some embodiments, the bias voltage of the first RF power source 15 is approximately between -30K and +30K volts, and the pulse width (pulse width) during operation is approximately between 5 and 300 microseconds, but is not limited thereto.

[0105] like Figure 2As shown, the wafer base 20 is located on the reaction chamber bottom 112 of the reaction chamber 11 and is configured to carry the semiconductor wafer 5. In some embodiments, the ring electrode 122 and the RF coil assembly 14 serve as the top electrode of the processing tool 10, and the wafer base 20 serves as the bottom electrode. The wafer base 20 can be any structure suitable for supporting a wafer, such as an electrostatic chuck or a vacuum chuck.

[0106] According to some embodiments of the present disclosure, the wafer bed 20 includes a body 21 and a support assembly 22. The body 21 includes a top surface 211 as a support surface for the semiconductor wafer 5, and its shape is generally consistent with the shape of the semiconductor wafer 5 to be supported thereon. For example, the top surface 211 of the wafer bed 20 is generally circular and is used to support a substantially circular semiconductor wafer 5. In some embodiments, the top surface 211 of the wafer bed 20 has a larger area than the semiconductor wafer 5. In one embodiment, the surface of the body 21 is connected to a wafer temperature control system (not shown), such as a resistance heating coil and / or a fluid channel connected to a heating or cooling fluid system. The body 21 can include any material used for the processing tool 10. For example, the material of the body 21 includes steel, other conductive metals or alloys. In some embodiments, the body 21 includes a vacuum system for holding and positioning the semiconductor wafer 5. In some embodiments, the body 21 is an electrostatic chuck (ESC).

[0107] The support assembly 22 is used to support the semiconductor wafer 5 when the semiconductor wafer 5 is placed above the body 21. In some embodiments, the support assembly 22 includes a rod 221, an extension portion 222, and a plurality of lifting pins 223. When the semiconductor wafer 5 is placed above the body 21, the support assembly 22 moves to a raised position (such as Fig. 9 ), to support the semiconductor wafer 5 above the body 21, and then descend to a descending position (as shown in Figure 4 ), so that the semiconductor wafer is placed on the upper surface 211 of the body 21. The position control of the support assembly 22 will be further described in detail in the description of the method S100 later.

[0108] In some embodiments, the rod 221 is located below the body 21 and extends in a vertical direction (e.g., Z-axis direction), and the extension 222 is connected to one end of the rod 221. The number of extensions 222 may correspond to the number of lift pins 223 and each extends radially outward from one end of the rod 221. The lift pins 223 are connected to the extension 222 and extend vertically upward to be inserted into the body 21. In other embodiments, the number of the segments of the extension 222 and the lift pins 223 are both 3, but the present disclosure is not limited thereto. In other embodiments, the extension 222 is omitted, and the rod 221 and the lift pins 223 extend vertically in a straight line.

[0109] Please also refer to Figure 3 and Figure 4 . Figure 3 A top view of a wafer bed 20 with a semiconductor wafer 5 placed thereon is shown in some embodiments of the present disclosure. Figure 4 show Figure 3 The cross-sectional view of the wafer seat 20 on the AA section line. In some embodiments, the body 21 has a plurality of through holes 210. The through holes 210 penetrate the upper surface 211 and the lower surface 212 of the body 21, and the lifting pins 223 are movably disposed in the through holes 210. It should be understood that even in Figure 3 In the embodiment shown, the body 21 has three through-holes 210 for accommodating three lifting pins 223, but the present disclosure is not limited thereto. The body 21 has more or fewer through-holes to accommodate different numbers of lifting pins 223, which all fall within the scope of the present disclosure. In one embodiment, the ratio of the width W1 of each lifting pin 223 to the width W2 of the corresponding through-hole 210 is between 0.25 and 0.75. Since the above ratio is smaller than the ratio of the lifting pins to the through-holes in the conventional wafer seat, the displacement of the lifting pins 223 in the through-holes 210 can be increased.

[0110] In some embodiments, Figure 4 As shown, the support assembly 22 also includes a plurality of actuators, such as a first actuator 224 and a plurality of second actuators 225. The first actuator 224 is configured to drive the support assembly 22 to move in the vertical direction (Z-axis direction), and the plurality of second actuators 225 are each configured to drive the lifting pin 223 to move in the horizontal direction relative to the extension 222. In some embodiments, the first actuator 224 includes a rotary motor and is connected to the bottom end of the rod 221. The outer surface of the rod 221 is provided with threads. When the first actuator 224 drives the rod 221 to rotate, the rod 221 moves in the vertical direction (Z-axis direction). In one embodiment, the first actuator 224 is driven according to a control signal from the control module 90, thereby controlling the vertical movement distance of the rod 221.

[0111] In some embodiments, a plurality of second actuators 225 are each disposed at the connection between the extension portion 222 and the lifting pin 223. The second actuators 225 may each include one or more micro motors. For example, the second actuator 225 includes a spherical motor to drive the displacement of the lifting pin 223. Alternatively, the second actuator 225 includes two micro linear motors stacked alternately, one of which is used to drive the displacement of the lifting pin 223 in the X-axis direction, and the other is used to drive the displacement of the lifting pin 223 in the Y-axis direction. In one embodiment, the second actuator 225 is driven according to a control signal from the control module 90, thereby controlling the horizontal movement distance of the lifting pin 223.

[0112] In one embodiment, the surface of the lifting pins 223 in contact with the semiconductor wafer 5 includes a rough surface to increase the friction between the lifting pins 223 and the semiconductor wafer 5. Figure 5A As shown, the lifting pin 223 includes a column 226, and a rough structure 227 is formed on the top 2261 of the column 226. The rough structure 227 can be engraved on the top 2261. Alternatively, the rough structure 227 is fixed to the top 2261 by gluing. In another example, the entire outer surface of the lifting pin 223a has a rough structure, not limited to the surface in contact with the semiconductor wafer 5.

[0113] Refer again Figure 1 In some embodiments, the second RF power source 17 is coupled to the body 21 of the wafer seat 20. The second RF power source 17 is a low-frequency RF power source that transmits RF power to the wafer seat 20 at a frequency of approximately 0.5 to 10 KHz, but is not limited thereto. In some embodiments, the bias voltage of the second RF power source 17 is approximately between -0.2 and 10 kilovolts, and the pulse width (pulse width) during operation is approximately between 20 and 100 microseconds, but is not limited thereto. In one embodiment, a bias voltage between the top electrode (the ring electrode 122 and the RF coil assembly 14) and the lower electrode (the wafer seat 20) is used to guide the ions of the plasma 18 to impact the surface of the semiconductor wafer 5, but the present disclosure is not limited thereto. In some embodiments, the second RF power source 17 can also be a DC bias source.

[0114] In some embodiments, the camera assembly 40 is disposed at any position above the wafer bed 20 and is used to generate images of the wafer bed 20. In one embodiment, the camera assembly 40 includes a camera for generating static images or dynamic images of the wafer bed 20. The camera assembly 40 transmits image data of the wafer bed 20 to the control module 90 for image analysis to determine the displacement distance of the lifting pins 223.

[0115] Figure 6A block diagram showing some components of the semiconductor wafer manufacturing system 1 of the present disclosure. In some embodiments, the control module 90 includes a processor 91 and a memory 92. The processor 91 is configured to execute and / or interpret one or more sets of instructions stored in the memory 92. In some embodiments, the processor 91 is a microprocessor (MCP), a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC) and / or a suitable processor.

[0116] The memory 92 includes a random access memory or other dynamic storage device for storing data and / or instructions for execution by the processor 91. In some embodiments, the memory 92 is used to store process values, temporary variables, or other intermediate information in performing a manufacturing process. For example, the memory 92 is configured to store image information generated by the camera assembly 40 and / or the memory 92 is configured to store image data related to the correct placement of the semiconductor wafer 5 on the wafer bed 20.

[0117] In some embodiments, the memory 92 includes a read-only memory or other static storage device for storing static information and instructions for the processor 91. In some embodiments, the memory 92 stores the position information of the semiconductor wafer 5 disposed centered above the wafer chuck 20. In some embodiments, the memory 92 is an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor system (or device or apparatus). For example, the memory 92 includes semiconductor or solid-state memory, magnetic tape, removable computer hard disk, random access memory (RAM), read-only memory (ROM), optical disk and / or memory.

[0118] In some embodiments, Figure 6 As shown, the image data 95 from the camera assembly 40 is output to the control module 90 for analysis to determine the offset of the semiconductor wafer 5 relative to the wafer bed 20. Subsequently, the control module 90 sends a control signal 96 to the actuator of the support assembly 22, such as the first actuator 224 ( Figure 4 ) or the second actuator 225 ( Figure 4 ) to control the displacement of the support assembly 22. In other embodiments, the photography assembly 40 includes a dedicated processor or hardware for performing calculations, and outputs an analysis signal about the offset of the semiconductor wafer 5 relative to the wafer base 20 to the control module 90, and then the control module 90 sends a control signal 96 to the actuator of the support assembly 22 according to the analysis signal.

[0119] Figure 7A flowchart of a method S100 for manufacturing a semiconductor wafer according to some embodiments of the present disclosure is shown. For example, the process is illustrated by the schematic diagrams of FIGS. 1, 8-13. In different embodiments, some stages may be replaced or eliminated. The following description is only exemplary and is not intended to limit the contents described in the scope of the subsequent patent application. It is understood that in the case of Figure 7 Additional steps may be provided before, during, and after the illustrated steps, and additional embodiments of the method may replace or reduce some of the operations described below, and the order of the operations described below may be interchanged.

[0120] The method S100 for manufacturing a semiconductor wafer includes an operation S110 of moving the lifting pins 223 of the wafer bed 20 to a raised position. In one embodiment, before the semiconductor wafer 5 is moved into the processing tool 10, no semiconductor wafer is placed on the wafer bed 20. Furthermore, the first brake 224 of the wafer bed 20 controls the support assembly 22 according to the control signal of the control module 90, and raises the height of the support assembly 22 from Figure 4 The lowered position shown moves to Figure 8 In the lowered position, the top end 2230 of the lifting pin 223 of the support assembly 22 is located below the upper surface 211 of the body 21. In the raised position, the top end 2230 of the lifting pin 223 of the support assembly 22 is located above the upper surface 211 of the body 21 and is spaced apart from the upper surface 211 of the body 21 by a distance.

[0121] The method S100 for manufacturing a semiconductor wafer further includes an operation S120 of moving the semiconductor wafer 5 above the wafer bed 20 and placing the semiconductor wafer 5 on the lifting pins 223. Fig. 9 As shown, after the lifting pins 223 of the wafer bed 20 are in the raised position, the semiconductor wafer 5 can be moved into the processing tool 10 to a position above the wafer bed 20 by the robot arm 6. Then, the robot arm 6 lowers the height of the semiconductor wafer 5 so that the semiconductor wafer 5 contacts the top 2230 of the lifting pins 223. The descending action of the robot arm 6 will continue to make all the lifting pins 223 contact the semiconductor wafer 5, and will not stop until the semiconductor wafer 5 is separated from the robot arm 6. In this way, Fig.10 As shown, the semiconductor wafer 5 is placed on the lifting pins 223 and supported by the lifting pins 223. Then, the robot arm 6 withdraws from the processing tool 10 to carry other semiconductor wafers 5 into other processing tools 10 or move them out of other processing tools 10.

[0122] The method S100 for manufacturing a semiconductor wafer further includes an operation S130 of generating images of the semiconductor wafer 5 and the wafer bed 20 using the photographing assembly 40. In one embodiment, the photographing assembly 40 photographs the semiconductor wafer 5 and the wafer bed 20 when the lifting pins 223 of the wafer bed 20 are in the raised position, and generates image information of the semiconductor wafer 5 and the wafer bed 20. Fig.11 The image M of the semiconductor wafer 5 and the wafer bed 20 generated by the camera assembly 40 in one embodiment is shown.

[0123] In some embodiments, the semiconductor wafer 5 is placed on an orienter (not shown) for positioning before being sent to the processing tool 10, and then sent to the processing tool 10 by the robot arm 6. If the adjustment of the orienter produces an error, the semiconductor wafer 5 sent to the processing tool 10 by the robot arm 6 will not be placed in the center above the wafer seat 20. Fig. 9 As shown in the image M, the center C1 of the wafer seat 20 is offset from the center C2 of the semiconductor wafer 5. If the semiconductor wafer 5 is directly processed without correcting the offset, the problem of reduced processing uniformity may occur. Therefore, to avoid this problem, the method S100 of manufacturing a semiconductor wafer in the embodiment of the present disclosure further includes the following steps to correct the position of the semiconductor wafer 5.

[0124] In operation S140, the offset information of the semiconductor wafer 5 is calculated. In one embodiment, the offset information of the semiconductor wafer 5 is obtained by analyzing the images of the semiconductor wafer 5 and the wafer bed 20 generated by the camera assembly 40. For example, Fig.11 As shown, after the photographic component 40 generates the image M of the semiconductor wafer 5 and the wafer base 20, the processor of the photographic component 40 itself or the processor of the control module 90 will analyze the offset information of the edge 51 of the semiconductor wafer 5 and the edge 213 of the wafer base 20 in the image M at multiple positions.

[0125] In one embodiment, the offset information generated by the processor of the photographic component 40 itself or the processor of the control module 90 includes the position offsets D1, D2, D3, and D4 of the four semiconductor wafers. The position offset D1 represents the offset of the edge 51 of the semiconductor wafer 5 relative to the reference point P1 on the edge 213 of the body 21. The position offset D2 represents the offset of the edge 51 of the semiconductor wafer 5 relative to the reference point P2 on the edge 213 of the body 21. The position offset D3 represents the offset of the edge 51 of the semiconductor wafer 5 relative to the reference point P3 on the edge 213 of the body 21. The position offset D4 represents the offset of the edge 51 of the semiconductor wafer 5 relative to the reference point P4 on the edge 213 of the body 21. The reference point P1 and the reference point P3 are respectively located in the positive X direction and the negative X direction of the center C1 of the wafer seat 20, and the reference point P2 and the reference point P4 are respectively located in the negative Y direction and the positive Y direction of the center C1 of the wafer seat 20. The X direction and the Y direction may be parallel to the X direction and the Y direction of the control knob of the second actuator 225 .

[0126] It is understood that although the position offsets D1, D2, D3, and D4 of four semiconductor wafers are generated in the above embodiment, the embodiments of the present disclosure are not limited thereto. In other embodiments, the processor of the photographic component 40 itself or the processor of the control module 90 can generate more or less information about the offset of the semiconductor wafer. In another embodiment, the processor of the photographic component 40 itself or the processor of the control module 90 only generates the position offsets D1 and D2, but does not generate the position offsets D3 and D4. In another embodiment, the processor of the photographic component 40 itself or the processor of the control module 90 does not generate the position offsets D1, D2, D3, and D4, but compares the image information of the edge 51 of the semiconductor wafer 5 with the position information stored in the database. The above position information presents the position of the edge 51 of the semiconductor wafer 5 when it is placed in the middle of the wafer seat 20.

[0127] In operation S150, it is determined whether the position offset of the semiconductor wafer is within an acceptable range. In one embodiment, the position offsets D1, D2, D3, and D4 of the four semiconductor wafers are each compared with a predetermined parameter stored in a database, and when the comparison result shows whether the difference between the position offsets D1, D2, D3, and D4 and the predetermined parameter is greater than a threshold. This threshold may represent the spacing between the lifting pin 223 and the edge of the through hole 210 in each direction. If the difference between the position offsets D1, D2, D3, and D4 and the predetermined parameter is greater than the above threshold, it means that the offset of the semiconductor wafer 5 is too large and cannot be corrected by adjusting the position of the lifting pin 223. Otherwise, it can be corrected by adjusting the position of the lifting pin 223.

[0128] If the position offset information (or position offset amount) of the semiconductor wafer 5 exceeds the acceptable range, the method S100 for manufacturing semiconductor wafers proceeds to operation S180 to issue an alarm. After receiving the alarm notification, the control module 90 can drive the robot arm 6 to re-enter the processing tool 10, remove the semiconductor wafer 5 from the lifting pins 223 and send it to the direction controller for positioning, and then the method S100 for manufacturing semiconductor wafers repeats to step S120.

[0129] If the position offset information (or position offset amount) of the semiconductor wafer 5 exceeds the acceptable range, the method for manufacturing a semiconductor wafer S100 proceeds to operation S160, and sends a driving signal to the second actuator 225 connected to the lifting pins 223 according to the position offset amounts D1, D2, D3, and D4, so that the second actuator 225 drives the displacement of the semiconductor wafer 5 relative to the wafer bed 20. In one embodiment, the control parameters of the second actuator 225 include the displacement amount in the X direction and the displacement amount in the Y direction.

[0130] In some embodiments, the calculation method of the displacement of the second actuator 225 in the X direction includes comparing the position offset D1 with the position offset D3 to determine whether the second actuator 225 moves in the positive X direction or in the negative X direction; and subtracting a reference spacing from the larger value of the position offset D1 and the position offset D3 to determine the displacement in the direction. For example, the position offset D1 is 3 mm, the position offset D3 is 1 mm, and the reference spacing is 2 mm. Since the position offset D1 is greater than the position offset D3, it is determined that the second actuator 225 moves in the positive X direction, and the displacement is 1 mm (that is, 3 mm-2 mm).

[0131] In some embodiments, the calculation method of the displacement of the second actuator 225 in the Y direction includes comparing the position offset D2 with the position offset D4 to determine whether the second actuator 225 moves in the positive Y direction or in the negative Y direction; and subtracting a reference spacing from the larger value of the position offset D2 and the position offset D4 to determine the displacement in the direction. For example, the position offset D2 is 3 mm, the position offset D4 is 1 mm, and the reference spacing is 2 mm. Since the position offset D2 is greater than the position offset D4, it is determined that the second actuator 225 moves in the negative Y direction, and the displacement is 1 mm (i.e., 3 mm-2 mm).

[0132] After the lifting pin 223 is displaced according to the position offset, Fig.12As shown, the lifting pin 223 is offset relative to the center of the through hole 210. In one embodiment, after the lifting pin 223 moves, the lifting pin 223 is closely attached to the side wall of the through hole 210. In addition, the distance D5 and the distance D6 of the semiconductor wafer 5 relative to the edge 21 of the wafer base 20 in different directions are adjusted to be the same.

[0133] In some embodiments, Figure 5A and Figure 5B As shown, the surface of the lifting pin 223 or the lifting pin 223a in contact with the semiconductor wafer 5 has a rough structure, so when the lifting pin 223 or the lifting pin 223a is displaced, there is a higher friction between the lifting pin 223 or the lifting pin 223a and the semiconductor wafer 5, thereby preventing the lifting pin 223 or the lifting pin 223a from sliding relative to the semiconductor wafer 5.

[0134] After operation S160 is completed, the method S100 for manufacturing a semiconductor wafer continues to operation S170, moving the lifting pins 223 of the wafer bed 20 from the raised position to the lowered position. In one embodiment, the camera assembly 40 is further configured to confirm whether the spacing D5 and the spacing D6 are the same after operation S160 is completed. If it is determined that they are different, the method S100 for manufacturing a semiconductor wafer may repeat operations S140-S160. If it is determined that they are the same, the control module 90 sends a control signal to the first driver 224 to freely move the position of the support assembly 22. Fig.12 Move the raised position shown to Fig.13 Lowered position shown.

[0135] After operation S170 is completed, the processing tool 10 can start processing the semiconductor wafer 5. In one embodiment, the processing of the semiconductor wafer 5 by the processing tool 10 is plasma etching processing. Since the semiconductor wafer 5 is centrally disposed above the wafer bed 20, the temperature and bias voltage of the semiconductor wafer 5 can be correctly adjusted through the wafer bed 20, so the uniformity of the plasma etching processing can be improved. On the other hand, since the semiconductor wafer 5 is centrally disposed above the wafer bed 20, the erosion efficiency of the plasma on the surrounding components (e.g., focusing ring) can be maintained consistent, so the service life of these components can be extended.

[0136] Fig.14 A schematic diagram showing some components of a processing device 10b according to some embodiments of the present disclosure. Fig.14 In the embodiment shown, Figure 3The same components in the illustrated embodiment will be given the same reference numerals, and their features will not be repeated to simplify the description. In one embodiment, the difference between the processing element 10b and the processing element 10 is that the processing element 10b includes a plurality of camera components, such as camera components 41b, 42b, 43b, 44b. The camera components 41b, 42b, 43b, 44b can each be used to generate images of reference points P1, P2, P3, P4 on the edge 213 of the body 21 of the wafer bed 20, and transmit the generated image data to the control module 90. By generating images of the semiconductor wafer 5 and the wafer bed 20 by the plurality of camera components 41b, 42b, 43b, 44b, the method S100 for manufacturing a semiconductor wafer can be applied to a processing tool for a large-sized semiconductor wafer without being limited by the shooting angle of the camera components.

[0137] The semiconductor wafer manufacturing system disclosed herein generates images of the semiconductor wafer and the wafer base through a photographic component, and determines the displacement of the lifting pins used to support the semiconductor wafer through the above images, thereby improving the offset problem of the semiconductor wafer relative to the wafer base body. In this way, the uniformity of subsequent processing applied to the semiconductor wafer can be improved.

[0138] The features or examples of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications herein can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor wafer, characterized in that: include: A plurality of lifting pins for moving a wafer bed are moved from a lowered position to a raised position; moving a semiconductor wafer over the wafer bed and placing the semiconductor wafer on the plurality of lift pins in the raised position; Using a camera assembly to generate an image of the semiconductor wafer and the wafer bed; Calculating position offset information of the semiconductor wafer according to the image, wherein the position offset information of the semiconductor wafer includes a first offset between a first reference point of the wafer bed and an edge of the semiconductor wafer, a second offset between a second reference point of the wafer bed and the edge of the semiconductor wafer, a third offset between a third reference point of the wafer bed and the edge of the semiconductor wafer, and a fourth offset between a fourth reference point of the wafer bed and the edge of the semiconductor wafer; Determining whether the position offset information of the semiconductor wafer is within an acceptable range; and When the position offset information does not fall within the acceptable range, the first offset and the third offset are numerically compared to obtain a first reference spacing, and the second offset and the fourth offset are numerically compared to obtain a second reference spacing, and a driving signal is sent to an actuator connected to the lifting pin according to the first reference spacing and the second reference spacing, so that the actuator drives the displacement of the lifting pin, thereby changing the position of the semiconductor wafer relative to the wafer base.

2. The method for manufacturing a semiconductor wafer according to claim 1, characterized in that: Also includes: After the actuator moves the plurality of lift pins, the plurality of lift pins are moved from the raised position to the lowered position; When in the raised position, a top end of the lifting pin is located above an upper surface of a body of the wafer seat; when in the lowered position, the top end of the lifting pin is located below the upper surface of the body of the wafer seat.

3. The method for manufacturing a semiconductor wafer according to claim 1, characterized in that: Also includes: When the position offset information of the semiconductor wafer does not fall within the acceptable range, an alarm is issued.

4. The method for manufacturing a semiconductor wafer according to claim 1, wherein: The actuator can be displaced in at least two different directions.

5. A semiconductor wafer manufacturing system, characterized in that: include: A body configured to carry a semiconductor wafer and having a plurality of through holes, an edge of the body having a first reference point, a second reference point, a third reference point, and a fourth reference point, wherein the first reference point and the third reference point are intersection points of a first direction from a center of the body and the edge of the body, the second reference point and the fourth reference point are intersection points of a second direction from the center of the body and the edge of the body, the first direction being perpendicular to the second direction; A rod, located below the body; A plurality of lifting pins connected to the rod and movably disposed in the plurality of through holes; A plurality of photographic components are disposed above the body and are configured to respectively generate images of the first reference point, the second reference point, the third reference point, and the fourth reference point on the edge of the body, wherein the plurality of photographic components are configured: calculating a first offset between the first reference point of the body and an edge of the semiconductor wafer, a second offset between the second reference point of the body and the edge of the semiconductor wafer, a third offset between the third reference point of the body and the edge of the semiconductor wafer, and a fourth offset between the fourth reference point of the body and the edge of the semiconductor wafer; Comparing the first offset with the third offset to obtain a first reference distance, and comparing the second offset with the fourth offset to obtain a second reference distance; a first actuator connected to the rod and configured to control the displacement of the rod in a vertical direction; a plurality of second actuators, each connected to the plurality of lift pins and configured to control the displacement of the plurality of lift pins in a horizontal direction; as well as A control module is electrically connected to the plurality of photographic components and the second actuator, wherein the control module sends a control signal to the second actuator according to the first reference spacing and the second reference spacing generated by the plurality of photographic components, and the second actuator controls the displacement of the plurality of lifting pins in the horizontal direction according to the control signal.

6. The semiconductor wafer manufacturing system according to claim 5, characterized in that: A top end of the lifting pin has a rough structure, and the rough structure is in direct contact with the semiconductor wafer.

7. The semiconductor wafer manufacturing system according to claim 5, characterized in that: The plurality of second actuators are used to control the displacement of the plurality of lifting pins in two vertical components in the horizontal direction.

8. The semiconductor wafer manufacturing system according to claim 5, characterized in that: The control module is electrically connected to each of the plurality of photographic components and sends the control signal to the second actuator according to the images generated by the plurality of photographic components.

9. The semiconductor wafer manufacturing system according to claim 5, characterized in that: The ratio of the width of the lifting pin to the width of the through hole is between 0.25 and 0.75.

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