Alarm handling

Abstract

The IC chip can provide silicon root of trust (RoT) functionality. In the described embodiment, the IC chip includes a processor, an alarm handler (110) and a plurality of peripheral devices (250), the peripheral devices generating an alarm indication (352). The alarm handler processes the alarm indication, the alarm indication having a security impact. The alarm handler includes a plurality of alarm receiver modules (312) to communicate with the plurality of peripheral devices. The alarm handler also includes a controller (310), a plurality of accumulation units (306), a plurality of upgrade timers (308) and a plurality of upgrade transmitter modules (314). These components can be organized into a hierarchy of increasing upgrade severity. In operation, the controller classifies the alarms and flexibly implements an adaptable alarm handler path, which is established by the upgrade component in response to the classification and based on the source of the alarm. The path can end with an upgrade transmitter module, which commands the upgrade handler (350) to implement security countermeasures. Thus, the flexible path can handle different types of alarms.

Description

Background Art

[0001] Electronic devices play an integral role in manufacturing, communications, transportation, healthcare, commerce, social interaction, and entertainment. For example, electronic devices power server farms that provide cloud-based distributed computing capabilities for commerce and communications. Electronic devices are also embedded in many different types of modern devices, from medical devices to appliances and from vehicles to industrial tools. Personal electronic devices enable portable video viewing and access to smart digital assistants. Additionally, one multifunctional electronic device—the smartphone—has become a virtual necessity at your fingertips. As electronic devices have become pervasively critical to many aspects of modern life, device security has become imperative.

[0002] Many people are familiar with malware, which is sometimes collectively referred to as "computer viruses." Some malware is designed to gain unauthorized access to information stored on electronic devices or to otherwise compromise electronic devices. Several strategies can help keep users' information and devices safe from security threats by combating many types of malware. These strategies include adopting and regularly updating resilient operating systems, engaging in secure computing practices, and installing anti-malware programs. Unfortunately, these strategies do not make electronic devices impervious to malware attacks.

[0003] Further, electronic devices may also be vulnerable to other types of attacks in addition to those performed by software-based malware. Physical attacks on hardware and radio frequency attacks on wireless communications may compromise the safe and reliable operation of electronic devices and the security of information stored by such devices. In other words, some forms of attack may circumvent or undermine the above-described policies, enabling bad actors to compromise electronic devices and potentially gain access to any accounts used with the device.

[0004] Typically, an electronic device includes at least one integrated circuit (IC) that provides intelligence to enable some desired functionality. This functionality may be critical to facilitating commerce, providing healthcare services, or implementing one of the other services identified above. Such electronic devices may also store or otherwise utilize information that requires protection. To support these functions and facilitate secure operation, some electronic devices include hardware-based protection in the form of secure circuitry. Unfortunately, existing secure circuitry is unable to counter the various software, hardware, and wireless attacks currently launched on electronic devices. Summary of the invention

[0005] Certain electronic devices, such as server computers and smartphones, are responsible for providing services to users. Users rely on these electronic devices to provide key services, such as banking or air travel, that are accessed using one or more accounts. Due to the link between the electronic device and the account, a compromised electronic device may allow unwanted access to services linked to the account or directly to the account itself. Further, in order to provide services associated with the account, these electronic devices may store account information that needs to be protected, such as financial data, usernames, passwords, and keys for encryption. Unfortunately, anti-malware programs cannot block all avenues of attack against electronic devices. For example, an anti-malware program may not be able to provide protection against direct physical attacks that use a miniature probe to detect voltage levels on an integrated circuit (IC) chip. Therefore, it is beneficial to incorporate hardware-based measures into electronic devices that can identify, block, repel, or otherwise hinder attacks on electronic devices, including physical attacks.

[0006] Thus, electronic devices may include secure circuit systems to combat attacks from bad actors. In some cases, the secure circuit system detects inappropriate or suspicious activity and takes protective measures. The secure circuit system may be implemented in different ways. For example, a computer engineer may implement the secure circuit system as a standalone IC chip or as part of another chip, such as a system on a chip (SoC). In either case, the secure circuit system may be part of a protected enclave, a trusted chip platform, a hardware-based root of trust (RoT) (e.g., a silicon RoT), and the like. Regardless of how or where the secure circuit system is incorporated into an electronic device, computer engineers may design the secure circuit system to combat many different types of attacks.

[0007] Attacks on electronic devices can take the form of programs that observe repetitive behavior to infer information (such as malware), programs that attempt to read data from protected areas of memory to perform direct physical probing of hardware circuit systems, and the like. The secure circuit system performs a variety of functions to combat these attacks. For example, the secure circuit system can protect encryption keys during adoption and transmission. To this end, dedicated memory and private data buses can be used. The secure circuit system can also generate high-quality pseudo-random numbers or operate an encryption engine in an area separate from an application that can run as malware. Further, the secure circuit system can ensure that the hardware is started using the correct, untampered startup basic input / output system (BIOS). Therefore, the secure circuit system can be responsible for implementing a variety of functions to combat a variety of attacks on electronic devices. However, existing secure circuit system methods use relatively rigid and inflexible hardware architectures.

[0008] In contrast, methods are described herein that provide an adaptable and flexible platform or framework that can generate resilient and programmable secure hardware to counter various forms of attacks on electronic devices. In some embodiments of a secure circuit system, different types of circuits communicate using an extended protocol that enables circuits providing different functions to interact seamlessly in accordance with a design framework. The design framework and protocol generate suitable components so that even circuit components that are designed separately from each other are suitable for being deployed together with stable, predictable interactions. For example, communications and other forms of interaction (e.g., shared resources such as buses, interfaces, or memories) can be at least partially standardized to provide a measure of predictability and interoperability. As used herein, "suitable components" include components that are designed in a consistent manner so that the components are suitable for use together.

[0009] In some embodiments of the security circuit system, the alarm handler interacts with the peripheral device and / or the upgrade handler to generate, share, process and / or respond to the security alarm. The alarm handler can be constructed as a suitable component. The security alarm can include an alarm that communicates between different circuit components implemented as peripheral devices on the chip. The alarm handler can be implemented as part of a silicon root of trust (RoT) chip, as part of a system on chip (SoC), or both. In an example operation, the alarm handler receives an alarm indication from a peripheral device, which can be generated in response to sensed suspicious activity. The controller and other parts of the alarm handler process the alarm indication using a flexible scheme that can be customized based on the source of the peripheral device or the possible severity of the security threat.

[0010] Typically, alerts are considered more important or worthy of more attention than mere interrupts. In other words, security risks that should not be ignored in a RoT or other secure silicon environment may be designated as alerts rather than just default processor interrupts. Nonetheless, the system can still attempt to leverage the intelligence and resources of the processor to resolve potential security events. To do this, in response to receiving an alert indication from a peripheral device, an alert handler may send an interrupt (e.g., a non-maskable interrupt (NMI)) to the processor to give the processor an opportunity to resolve the security event. If the processor cannot resolve the interrupt, the alert handler takes remedial action, including potentially indicating activation of security countermeasures.

[0011] In an example embodiment, an alarm handler includes one or more alarm receiver modules that are coupled to at least one alarm transmitter module of a peripheral device. If the alarm receiver module receives an alarm indication from the alarm transmitter module, the alarm receiver module provides a trigger alarm to a controller of the alarm handler. The controller classifies the trigger alarm into one of a plurality of classes based on the alarm receiver module, the class of alarms corresponding to the peripheral device or the detected potential security threat. Based on the classification, the controller can transmit an interrupt to the processor as described above. The controller also starts an escalation timer based on the classification of the nature of the trigger alarm. When the escalation timer expires, if the processor has not cleared the interrupt, the alarm handler can start another escalation timer to escalate the timing process along the hierarchy of escalation timers, which are sorted according to the increasing severity of the potential security threats.

[0012] The alarm handler also includes one or more upgrade transmitter modules that are coupled to at least one upgrade receiver module of the upgrade handler. The upgrade handler can implement security countermeasures, including erasing data, resetting digital circuit systems, or converting the device to an invalid life cycle state. After one or more upgrade timers expire, the alarm handler instructs the upgrade transmitter module to send an upgrade command to the upgrade handler to implement security countermeasures. Flexible schemes enable the alarm handler to customize alarm processing and upgrade responses in various ways. For example, these ways include the length of each upgrade timer, the order or length of at least a portion of the hierarchy of the upgrade timer, the determination of which upgrade transmitter module is activated first, and so on. The customization can be at least partially established using one or more registers.

[0013] The safety circuit system may include other components and features. For example, the alarm handler may include a ping monitor that uses ping messages that function similarly to bidirectional heartbeat signaling to monitor the health of peripheral devices and / or upgrade handlers. The signaling paths between modules in the alarm handler and modules in the peripheral devices and / or upgrade handlers may be implemented through different paths to improve resilience. Further, the alarm handler may include an integrity fault circuit system that checks the signaling path for correct differential function. In order to make the transmission of alarm indications more robust, the same wires can be used for alarm indications and ping messaging. The alarm handler may also include an accumulation unit. The alarm handler upgrades the response process based on a number of triggered alarms tracked using the accumulation unit.

[0014] In these ways, a security circuit system can be incorporated into a silicon RoT chip and / or SoC. The security circuit system can include an alarm handler that is compatible with other components to ensure expected compatibility and consistent communication. The alarm handler can provide a flexible solution to address potential security alarms generated by a variety of components, which are referred to herein as peripherals, as alarm indications are generated due to various sensed stimuli. The alarm handler escalates the alarm indication in a variety of ways depending at least in part on the source or cause of the alarm indication. The remedial response can be customized as part of the escalation process to ultimately include at least one security countermeasure. Thus, adaptive security responses can be implemented in a trusted manner to provide security functionality.

[0015] The following aspects include an integrated circuit for alarm handling. The integrated circuit includes multiple peripheral devices and an alarm handler. The alarm handler includes multiple alarm receiver modules and multiple upgrade timers. Each alarm receiver is coupled to a peripheral device in the multiple peripheral devices. Each corresponding upgrade timer corresponds to a corresponding upgrade severity in multiple upgrade severities. The alarm handler also includes a controller, which is coupled to the multiple alarm receiver modules and the multiple upgrade timers. The controller is configured to classify a trigger alarm from an alarm receiver module in the multiple alarm receiver modules into an alarm classification in a plurality of alarm classifications based on the alarm receiver module. The controller is also configured to start an upgrade timer in the multiple upgrade timers based on the alarm classification.

[0016] The following aspects include an alarm handling method that can be performed by at least a portion of an integrated circuit. The method includes monitoring a plurality of peripheral devices with a plurality of alarm receiver modules. The method also includes receiving a trigger alarm from an alarm receiver module in the plurality of alarm receiver modules based on a peripheral device in the plurality of peripheral devices. The method also includes classifying the trigger alarm into an alarm classification in a plurality of alarm classifications based on the alarm receiver module. The method further includes starting an escalation timer in a plurality of escalation timers based on the alarm classification, wherein each respective escalation timer corresponds to a respective escalation severity in a plurality of escalation severities.

[0017] The following aspects include an integrated circuit for alarm processing. The integrated circuit includes a plurality of upgrade handlers and an alarm handler. Each upgrade handler is configured to implement at least one security countermeasure. The alarm handler includes a plurality of upgrade transmitter modules and a plurality of upgrade timers. Each upgrade transmitter module is coupled to an upgrade handler in the plurality of upgrade handlers. Each corresponding upgrade timer corresponds to a corresponding upgrade severity in a plurality of upgrade severities, wherein each upgrade timer is coupled to at least one upgrade transmitter module in the plurality of upgrade transmitter modules. The alarm handler also includes a controller coupled to the plurality of upgrade timers. The controller is configured to start an upgrade timer in the plurality of upgrade timers in response to a triggering alarm. In response to the expiration of the started upgrade timer and based on the triggering alarm, the alarm handler is configured to selectively start another upgrade timer in the plurality of upgrade timers or transmit an upgrade command from an upgrade transmitter module in the plurality of upgrade transmitter modules to an upgrade handler in the plurality of upgrade handlers. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Devices and techniques for alarm handling are described with reference to the following figures. The same numbers are used throughout the drawings to reference the same features and components.

[0019] Figure 1 An example apparatus having an integrated circuit (IC) including the safety circuitry described herein for implementing alarm handling is illustrated.

[0020] Figure 2 An example safety circuit system is illustrated that includes multiple circuit components including an alarm handler and multiple peripheral devices.

[0021] Figure 3 An example alarm handler coupled to a plurality of peripheral devices and a plurality of escalation handlers is illustrated.

[0022] Figure 4-1 Additional example aspects of an alarm handler coupled to a plurality of peripheral devices and a plurality of upgrade handlers are illustrated.

[0023] Figure 4-2 Additional example aspects of an alert handler related to escalating hierarchical levels of severity are illustrated.

[0024] Figure 5-1 to Figure 5-3 An example alarm handling path within an alarm handler is illustrated.

[0025] Figure 6 An example communication relationship between an alarm receiver module of an alarm handler and an alarm transmitter module of a peripheral device is illustrated.

[0026] Figure 7An example communication relationship between an upgrade transmitter module of an alert handler and an upgrade receiver module of an upgrade handler is illustrated.

[0027] Figure 8 An example method of an apparatus for implementing alarm handling is illustrated. DETAILED DESCRIPTION

[0028] Overview

[0029] Electronic devices have made vital contributions to modern society, such as contributions to communications, security, and manufacturing. Every electronic device relies on an integrated circuit (IC) with processing capabilities to provide some functionality. Due to the critical nature of many of these functions, electronic devices may include ICs with secure circuitry to provide protective measures. Secure circuitry reduces the chances of information being inadvertently exposed or some functionality being used in a harmful or otherwise unauthorized manner. Secure circuitry can be implemented in a variety of forms, one of which involves a root of trust (RoT) paradigm.

[0030] With Silicon RoT, hardware-based mechanisms keep computing secure in terms of preventing inappropriate access to information, blocking unauthorized use of devices, and more. Silicon RoT principles can help ensure that both the hardware infrastructure and the software executing on it maintain their intended, trusted state. To this end, Silicon RoT can verify key system components with authorized and verifiable code. Silicon RoT can provide additional or alternative security benefits. For example, it can ensure that a server or other electronic device boots up with the correct firmware and that the firmware has not been infected with low-level malware. Silicon RoT can also provide a cryptographically unique machine identity; this unique identity enables operators to verify that the electronic device is legitimate. Further, it can keep cryptographic keys and other information in tamper-proof silos so that even someone with physical access cannot obtain the information. RoT services anchored in hardware can also provide authoritative, tamper-proof audit records and other runtime security services.

[0031] Chip designers can incorporate silicon RoT technology into separate IC chips that focus on providing security functions. Alternatively, RoT silicon can be integrated with other circuit systems, including in a central processing unit (CPU) chip or package, in a graphics processing unit (GPU) chip or card, in a system on chip (SoC), in a memory storage device, and so on. Typically, secure circuit systems can operate in server motherboards, network cards, client devices (e.g., laptops and smartphones), consumer routers, and Internet of Things (IoT) devices, just to name a few examples. Whether it is an application or an electronic device, by anchoring the RoT in silicon, security is enhanced across hardware, firmware, and software levels. Silicon RoT also enhances security on different devices that communicate directly with each other or use a network to communicate. Although some secure circuit systems and circuit design principles are described in this article using a silicon or hardware RoT environment, this is done only by example, because the principles described are generally applicable to secure circuit systems, including secure circuit systems that support specialized circuits such as graphics or artificial intelligence (AI) processors, secure circuit systems incorporated into general-purpose processors or SoCs, and discrete secure circuit systems.

[0032] In today's computing environment, bad actors can attack electronic devices at countless levels using a variety of attack vectors. For example, an attack could be carried out using malware that is transmitted over the Internet in an attempt to gain access to information stored on a laptop that the user would like to keep safe. Additionally, an attack could involve injecting malware into a device used to boot an electronic device during transportation or when the device is operated in an unobserved location - such as a As another example, a bad actor may steal an electronic device and have enough time to conduct a direct physical attack on the device. This direct physical attack may include cutting wires, probing voltages, running code over and over to observe trends and infer information, etc.

[0033] Therefore, the types and approaches of attacks on electronic devices can be many and varied. Nevertheless, some existing RoT methods rely on relatively simple or intuitive processing paradigms. For example, these paradigms may lack clear and flexible protocols to enable different circuit components of the security circuit system to communicate with each other. Such communication can facilitate the detection of security threats and effectively hinder actual security attacks. Due to poor communication between components, another attack path is effectively created for potential bad actors. These inadequate paradigms may also involve fixed and inflexible processing flows for processing alarms generated due to potential attacks or other suspicious activities that have been detected. If the fixed processing flow is too aggressive, the security circuit system may terminate the operation of the circuit component, chip or even the entire device because of a security threat that is actually small or even a false alarm. On the other hand, if the fixed processing flow is not aggressive enough, the security circuit system may not initiate the shutdown of the chip or its circuit components before the actual security threat has caused damage (such as unauthorized access to an account or theft of valuable information).

[0034] In contrast, a flexible and adaptive security circuit system method is described herein. For example, with respect to a processing flow or an alarm handling path, an alarm handler can establish a processing flow of different lengths and aggressiveness. Each alarm handling path can be selected in response to the possible severity of the alarm. For an alarm corresponding to a possible small threat or a possible false alarm, the alarm handler establishes a processing flow that includes a longer or more escalation timer, or starts with a security countermeasure response that is less aggressive or less persistent. On the other hand, for an alarm that is considered to be potentially serious, the alarm handler establishes a relatively fast escalation processing flow. For a serious security threat, fewer or even one or zero escalation timers can be used in a shorter duration. Additionally or alternatively, the alarm handler can trigger a countermeasure response with a relatively more serious repercussion, such as erasing information or resetting an IC chip. By customizing the response to the detected security alarm, the described alarm handler implementation can counter attacks of various types and approaches while reducing the chance that the response is too aggressive or too slow to counter the attack.

[0035] Other aspects and embodiments for alarm handling are also described herein. Each of these aspects and embodiments and embodiments can be used alone or in any combination. For a given safety circuit system architecture, safety issues may be considered more threatening or have a higher priority than other issues. These other issues can be transmitted between architectures as interrupts. Compared with interrupts that may occur frequently or about various events, safety-related events and alarms announcing these events are not expected to occur frequently. In some cases, the alarm handler responds to the alarm indication and sends the interrupt to the processor according to the selected alarm handling path. The processor is expected to respond to the interrupt appropriately and pass this to the alarm handler. If the processor cannot clear the interrupt within some time period, or if the alarm indication continues to be generated, the alarm handler uses one or more upgrade timers or upgrades the alarm processing by taking some actions.

[0036] In some embodiments, the alarm handler includes at least one controller, multiple upgrade timers, and multiple upgrade transmitter modules. The controller uses at least one register associated with the security alarm to determine the alarm handling path for handling a given security alarm. The controller can use, for example, a classification system including multiple classes to determine the alarm handling path. In order to enable flexible response to security alarms of different severities, a large number of upgrade timers or a large number of upgrade transmitter modules (including a large number of both) used along the processing flow can vary according to one or more registers associated with the classified security alarms. Sending interrupts to the processor in a given processing flow can also depend on the security alarm. For example, one upgrade timer and one upgrade transmitter module can be used in one processing flow, while three upgrade timers and two upgrade transmitter modules can be used in another processing flow.

[0037] The register library can initially be configured to set one or more variables that establish an alarm handling path for different alarms. For example, the length of each escalation timer can also be programmed according to the security alarm. Further, the path through the hierarchy of escalation timers or escalation transmitter modules can be adjusted. For example, three escalation timers can be traversed in a specific order along the timer hierarchy in one processing flow, but the "intermediate" escalation timer can be skipped in another processing flow. Once activated, the escalation transmitter module of the alarm handler sends an escalation command to the corresponding escalation handler, which can implement security countermeasures. Therefore, a flexible alarm handling path for traversing escalation timers or escalation transmitter modules is provided, enabling the alarm handler to appropriately customize the response to perceived threats.

[0038] In other embodiments, the alarm handler can reliably communicate with one or more other circuit components, which are referred to as peripheral devices in this article. To this end, the alarm handler includes a plurality of alarm receiver modules, which are used to communicate with corresponding alarm transmitter modules in corresponding peripheral devices. In order to support robust communication, each alarm receiver module can be coupled to the alarm transmitter module via a signaling path, and the signaling path includes at least two wires to enable differential signaling. Differential signaling enables attacks on the communication path to be more easily detected. In operation, if the peripheral device detects suspicious activity, the alarm transmitter module of the peripheral device sends an alarm indication through the signaling path. The alarm receiver module can provide an alarm confirmation to the alarm transmitter module.

[0039] The alarm handler may also include a ping monitor. The ping monitor uses a pseudo-random value to select a peripheral device or determine the time duration for sending the next ping request signal. The ping monitor instructs the alarm receiver module to use the signaling path coupled between them to send the ping request signal to the corresponding alarm transmitter module at the peripheral device. In response, the alarm transmitter module transmits the ping response back to the alarm receiver module at the alarm handler. If the ping response is not received within a certain time period (which can be programmable), the ping monitor sends an alarm ping failure to the controller of the alarm handler. The reliability of the communication path is improved by using the same communication path as the communication path used by the ping protocol for alarm transmission and confirmation. For example, if the signaling path for transmitting the alarm indication has been cut off, the ping protocol detects the failure of the path. The ping protocol can also be applied between multiple upgrade receiver modules and multiple upgrade transmitter modules of multiple upgrade handlers.

[0040] In further embodiments, the alarm can be generated in different ways. First, the alarm can be generated "externally" by a peripheral device. In this case, the peripheral device uses an alarm transmitter module at the peripheral device and a signaling path coupled to an alarm receiver module at the alarm handler to pass the security alarm to the alarm handler. Secondly, the alarm can be generated "internally" by the alarm handler, such as due to a ping protocol failure about the peripheral device or the upgrade handler. In each case, the alarm handler can implement a programmable alarm handling path to process the security alarm based on the possible level of the threat using a classification system. At the end of the alarm handling path or during the alarm handling path, the alarm handler can enable the upgrade transmitter module to trigger an upgrade activity, such as a security countermeasure, based on the current upgrade severity level along the alarm handling path. In operation, the upgrade transmitter module transmits an upgrade command to the upgrade receiver module at the upgrade handler. In response to the upgrade command, the upgrade handler implements at least one protection action. Examples of such protection actions include weakening peripheral devices, deleting information, terminating processes, resetting IP chips or parts thereof, and the like.

[0041] In these approaches, the security circuit system can be incorporated into a silicon RoT chip and / or SoC. The security circuit system can include an alarm handler that is compatible with other components to ensure expected compatibility and consistent communication. The alarm handler provides a flexible solution for addressing potential security alarms generated by diverse components as alarm indications due to various sensed stimuli. The diverse components or peripherals use a signaling path to provide alarm indications that can propagate robust differential signaling. The alarm handler upgrades the alarm indication in a variety of ways, depending at least in part on the source or cause of the alarm indication. The alarm handling path for upgrading alarm processing can be based on the classification of the alarm. The remedial response or protective action can be customized as part of the upgrade process to ultimately include at least one security countermeasure. Therefore, adaptive security responses can be implemented in a trusted manner to provide functionality in a flexible and secure environment at the hardware level.

[0042] The following will discuss example implementations at various levels of detail with reference to the associated figures. The following discussion first sets forth an example operating environment, then describes example hardware, schemes, and techniques. Example methods are then described with reference to flowcharts or schematic diagrams.

[0043] Example operating environment for alert handling

[0044] Figure 1An example device 102 having an integrated circuit 104 (IC 104) including a safety circuit system 106 for implementing alarm handling as described herein is generally illustrated at 100. In this example, the device 102 is depicted as a smartphone. However, the device 102 may be implemented as any suitable computing or electronic device.

[0045] Examples of apparatus 102 include a mobile electronic device, a mobile communication device, a modem, a cellular or mobile phone, a mobile station, a gaming device, a navigation device, a media or entertainment device (e.g., a streaming media player or game controller), a laptop computer, a desktop computer, a tablet computer, a smart home appliance, a vehicle-based electronic system, a wearable computing device (e.g., clothing, a watch, or reality-altering glasses), an Internet of Things (IoT) device, a sensor, an inventory management device, an electronic portion of a machine or device (e.g., a vehicle or robot), a memory storage device (e.g., a solid-state drive (SSD)), a server computer or portion thereof (e.g., a server blade or other portion of a rack or data center), etc. The illustrated examples of apparatus 102 include a tablet device 102-1, a smart TV 102-2, a desktop computer 102-3, a server computer 102-4, a smart watch 102-5, a smart phone (or file reader) 102-6, and smart glasses 102-7.

[0046] In an example embodiment, the apparatus 102 includes at least one integrated circuit 104. The integrated circuit 104 may be mounted on a module, a card, or a printed circuit board (PCB) (not shown). Examples of PCBs include flexible PCBs, rigid PCBs, single-layer or multi-layer PCBs, surface mount or through-hole PCBs, combinations thereof, and the like. Each integrated circuit 104 may be implemented as a general-purpose processor, a system on a chip (SoC), a security-oriented IC (e.g., a RoT IC chip), a memory chip, a communication IC (e.g., a modem or a radio frequency IC), a graphics processor, an artificial intelligence (AI) processor, a combination thereof, and the like. The IC 104 may be packaged alone or together with other IC chips.

[0047] As shown, integrated circuit 104 includes a safety circuit system 106. The safety circuit system 106 may include a variety of components, including a plurality of circuit components 108-1...108-C, where C represents a positive integer. An example of circuit component 108 is an alarm handler 110. Although Figure 1106. Although not explicitly shown in the figure, the integrated circuit 104 may include other parts in addition to the secure circuit system 106. Although the multiple circuit components 108-1...108-C and the alarm handler 110 can be integrated together on a single IC as shown, the components can alternatively be distributed on two or more ICs. For example, the secure circuit system 106 can be implemented as a protected enclave, a trusted chip platform, a hardware-based root of trust (RoT) (e.g., a silicon RoT), etc. Regardless of how or where the secure circuit system is incorporated into the electronic device, the secure circuit system can resist many different types of attacks.

[0048] In example operation, upon detecting an attack - or potential attack, a component generates an alarm 112. For example, the circuit component 108 may generate the alarm 112 externally from the alarm handler 110 and transmit the alarm 112 to the alarm handler 110. Additionally or alternatively, the alarm handler 110 may generate the alarm 112 internally. Responsive to the nature of the source of the alarm 112, the alarm handler 110 selectively implements flexible processing flows to resolve the alarm 112. These flexible processing flows and other aspects of the alarm handler 110 and the security circuit system 106 are described herein. Figure 5-1 to Figure 5-3 An example process flow or alert handling path is described. However, next, refer to Figure 2 An example architecture for the safety circuit system 106 is described.

[0049] Figure 2 An example safety circuit system 106 is illustrated that includes a plurality of circuit components, including an alarm handler 110. As shown, the safety circuit system 106 includes a processor coupled to an interconnect 204. The interconnect 204 may be implemented using a bus, a switch fabric, or a bus network that enables the various circuit components to communicate. In addition to the alarm handler 110, ( Figure 1 The plurality of circuit components 108 - 1 . . . 108 -C may include a plurality of memories and a plurality of peripheral devices. Each of the alarm handler 110 , the plurality of memories, and the plurality of other peripheral devices 250 is coupled to the interconnect 204 directly or indirectly.

[0050] In an example embodiment, the plurality of memories may include a read-only memory 206 (ROM 206), a static random access memory 208 (SRAM 208), and a flash memory 210. The plurality of peripheral devices 250 may include an advanced encryption standard (AES) engine 212 (AES engine 212), a hash-based message authentication code (HMAC) engine 214 (HMAC engine 214), a serial peripheral interface (SPI) device 230 (SPI device 230), and a flash controller 216. The plurality of peripheral devices 250 may also include a universal asynchronous receiver / transmitter (UART) unit 218 (UART unit 218), a general purpose input / output (GPIO) interface 220 (GPIO interface 220), a pin multiplexer 222 (pin mux 222), and a board controller 224. The plurality of peripheral devices 250 may further include a random number generator 232 (RNG 232) and a timer 234. Additionally, the peripheral devices 250 may include any memory, such as Figure 2 Although Figure 2 Certain examples of memory and other peripherals 250 are depicted in or described herein, but a given implementation of the secure circuit system 106 may include more, fewer, and / or different instances of processors, controllers, memory, modules, or peripherals, including copies thereof.

[0051] The circuit components shown can operate synchronously based on one or more clock signals. Figure 2 106. Although not shown in the drawings, the safety circuit system 106 may include at least one clock generator for generating a clock signal or may include a reset circuit system for resetting one or more independent components separately from each other, resetting multiple components jointly, or resetting the entire IC chip. Alternatively, the safety circuit system 106 may receive at least one clock signal or reset signal from a source external to the safety circuit system 106, which may or may not be on a separate chip. One or more separate peripheral devices 250 may operate in corresponding independent clock domains. For example, an input / output (I / O) peripheral device may be synchronized to a clock that is local to the corresponding I / O device or channel. Peripherals in different clock domains may operate or communicate asynchronously with each other.

[0052] An example implementation of the components shown is described below. Processor 202 may be implemented as a "main," "central," or "core" processor of the security circuit system 106. As just one example, processor 202 may be implemented with a 32-bit, in-order reduced instruction set computing (RISC) core with multiple pipeline stages. With, for example, a RISC-V instruction set, the processor may implement M (machine) and U (user) modes. Activating a reset pin (not shown) (e.g., by deasserting a low-level active reset pin) causes processor 202 to exit reset and begin executing code at its reset vector. The reset vector may start in ROM 206, which verifies the code therein before jumping to an emulated embedded flash memory (e-flash). In other words, the code should have been instantiated into e-flash before the reset is released. In some cases, according to compatibility specifications, resets throughout the security circuit system 106 may be set to asynchronous low-level active to support interoperability between various circuit components. Resets may be generated internally via alarm handler 110, as described below; by a watchdog timer; and the like. The reset signal may also be sent to other circuit components, such as one of the memories or one of the peripheral devices 250 .

[0053] Coupled to the processor 202 is a debug module 226 (DM 226) and an interrupt controller 228 (ItC 228). The debug module 226 provides debug access to the processor 202. By interfacing with certain pins of the IC, the logic in the debug module 226 allows the processor 202 to enter a debug mode and provides the ability to inject code into a device (e.g., by emulating instructions) or memory. The interrupt controller 228 can be located close to the processor 202. The interrupt controller 228 can accept interrupt source vectors from within the secure circuit system 106. The interrupt controller 228 can also assign levels and priorities to interrupts before forwarding them to the processor 202 for processing.

[0054] Processor 202 may provide any desired level of performance or include any internal circuit components. For example, processor 202 may include at least one arithmetic logic unit (ALU) (e.g., including an "additional" ALU to calculate branch targets to eliminate latency cycles on taken conditional branches) and multiple pipeline stages. Using multiple pipeline stages, the pipeline may perform register writebacks to reduce latency cycles from loads and stores and prevent pipeline stages available for response to loads or stores from stalling in the cycle after the request. Processor 202 may implement a single-cycle multiplier or generate an imprecise exception on an erroneous response to a store, which allows the processor to continue execution after a store without waiting for a response. Although not depicted, processor 202 specifically or secure circuit system 106 generally may include an instruction cache for providing single-cycle access time for instructions.

[0055] In the example shown, secure circuit system 106 includes three memory address spaces for instructions and data. ROM 206 is the target of processor 202 after reset release. ROM 206 contains hard-coded instructions for performing a subset of platform checks before checking the next level of code. The next level of code (e.g., a boot loader stored in embedded flash memory) may be the first piece of code that is not hard-coded into the silicon of the device. Therefore, this next level of code is signature checked for integrity to increase security. ROM 206 can perform this signature check by implementing an RSA check algorithm on the entire contents of the boot loader.

[0056] Flash memory 210 may be implemented as an e-flash memory for code storage. Such e-flash may be loaded with the boot loader described above as well as the operating system and applications at the top level. SPI device 230 may be used to batch load the e-flash memory. Debug module 226 may also be used for code loading. SRAM 208 may operate as a scratchpad SRAM that may be used for data storage (e.g., for stacks and heap information) of processor 202. SRAM 208 may also store code.

[0057] The security circuit system 106 may include a series of "peripherals" or "peripherals." These peripherals 250 may be slave execution units coupled to the processor 202 via the interconnect 204. Each of these peripherals 250 may follow an interface scheme that ensures compatibility with each other and with the processor 202. The compatibility protocol may specify how the processor 202 communicates with a given peripheral (e.g., using the interconnect 204), how the peripheral communicates with the chip I / O (e.g., via fixed or multiplexable I / O), how the peripheral communicates with the processor 202 (e.g., using interrupts), and how the peripheral communicates security events (e.g., using alarm indications) to other circuit components, such as the alarm handler 110. Although in Figure 2 2, but the alarm handler 110 may also include peripherals 250, at least relative to the processor 202. The peripherals 250 depicted may include peripherals relative to the alarm-related functions provided by the alarm handler 110. In these contexts, the memory may also include peripherals 250 relative to the alarm-related functions provided by the alarm handler 110.

[0058] The circuit or chip I / O peripherals include a pin multiplexer 222 and a board controller 224. The pin multiplexer 222 provides signaling routing between the peripherals 250 and the available, multiplexable I / O nodes of the security circuit system 106 (e.g., pins of a chip in which various components are integrated). The board controller 224 manages control or board properties such as drive strength, technology, pull-up versus pull-down, etc. of the external I / O of the circuit (e.g., chip). The pin multiplexer 222 and board controller 224 are themselves peripherals on the interconnect 204. Each may have or otherwise be associated with at least one set of registers that provide software configurability.

[0059] The UART unit 218 can implement UART features, such as single-channel duplex UART functions. Its output and input can be configured to be connected to any circuit I / O via a pin multiplexer 222. The GPIO interface 220 creates a G-bit bidirectional communication to an external circuit system through a pin multiplexer 222, where G is a positive integer, such as 16, 32 or 64. The SPI device 230 can implement a firmware mode. Here, the firmware mode can enable the following features, which provide an external drive with the ability to send firmware upgrade code to a library of the flash memory 210 for field firmware updates. The firmware mode can include addressing of the memory using SPI transactions. Although not depicted, the security circuit system 106 can include an inter-integrated circuit (I2C) host to enable commanding of I2C devices. Such commands of I2C devices can include standard, complete and fast modes.

[0060] Several security-centric peripherals are also depicted, including an encryption engine and an alarm handler 110. The AES engine 212 can provide symmetric encryption and decryption using one or more protocols and different key sizes, such as 128b, 192b, or 256b. The component can choose to encrypt or decrypt arriving data, for example, the number of 16 bytes to decrypt or encrypt using different block cipher operation modes. The AES engine 212 can support electronic codebook (ECB) mode, cipher block chaining (CBC) mode, cipher feedback (CFB) mode, output feedback (OFB) mode, counter (CTR) mode, etc. The data transfer can be processor-available, for example, keys and data materials can be passed into the component via register writes. Alternatively, a private channel for transferring keys and data materials can be included to reduce exposure to potential untrusted processor activity.

[0061] For example, the HMAC engine 214 can utilize the secure hash algorithm (SHA) SHA-256 as a hash algorithm. SHA-256 is a member of the SHA-2 family of hash algorithms, in which the digest (or hash output) has a length of 265b, regardless of the data size of the input to be hashed. After declaring the start of a hash request, data is sent to the HMAC peripheral. This resets the internal state to an initial state, 32b at a time. Once the data has been sent by the component client, the client can indicate the completion of the hash request (with an optional partial word final write). The HMAC engine 214 generates a hash result and makes it available to the register that the requesting client reads. The data transfer can be available to the processor or private to reduce exposure to potential untrusted processor activity.

[0062] HMAC is a message authentication protocol layered on top of a hash function (e.g., SHA-256), and HMAC is mixed in with a secret key for encryption purposes. HMAC is a specific application of appending a secret key (such as twice) in a prescribed manner around the hash of the message (via SHA-256). To provide this functionality, a 256b secret key may be programmed into the circuit assembly before the message hashing begins. The timing of the completion of the authentication may vary, and the delay may be longer than that using native SHA-256. Also here, the hash information or secret key may be made available to the processor for convenience or processing efficiency, or may be rendered private in some manner to improve security.

[0063] The alarm handler 110 is responsible for processing and responding to alarms, including those provided by other peripherals 250. Alarms can be considered security-sensitive interrupts that are handled in a timely manner in response to perceived security threats. Unlike "standard" interrupts, alarms are not handled solely by software executing on the processor 202. Alarms can trigger a first-stage request as a "regular" interrupt to be handled by software. However, if the software cannot respond and remedy the interrupt triggered by the alarm, the alarm handler 110 triggers a second-stage response. This ensures that the underlying problem - the perceived security threat - can be resolved even if the processor 202 is busy, plugged in, or also attacked.

[0064] Each peripheral device 250 can present a list of individual alarms representing individual potential threats to be handled. These alarms can be transmitted to the alarm handler 110 as alarm indications using a specific encoding mechanism. Figure 3 The alarm handler 110 is further described. As described above, the alarm handler 110 may also be a peripheral device 250 on the interconnect 204, at least with respect to the processor 202.

[0065] The secure circuit system 106 may also include RNG 232. Randomness may contribute to security functions by providing execution variations that can prevent attackers from predicting the best time to launch an attack. Random numbers can provide secret materials for identity and encryption purposes. RNG 232 can be embedded in algorithmic calculations to obscure sensitive data values. Generally, RNG 232 can perform better because its digital generation becomes more and more truly random, and to a certain extent, it can also become stronger to resist attacks. RNG 232 can be implemented as a "true" RNG (TRNG), which may involve a design with an analog part to take advantage of some uncertain physical events or processes. Example TRNG designs rely on metastability, electronic noise, timing variations, thermal noise, quantum variations, etc. TRNG filters the result variables and sends them to an entropy pool, which the device can sample for the current random function at a given time. In some cases, the interface of the entropy pool may include a read request for available random bits. The TRNG interface indicates how many bits are available, and to the extent that the bits are available, a request peripheral device or software can read from this pool. Attempting to read an unavailable entropy bit can trigger an interrupt or alarm.

[0066] Two other peripherals 250 include a timer 234 and a flash controller 216. For example, the timer 234 can support accurate performance of the processor 202. The timer 234 is formed of a plurality of bits (e.g., 64 bits) and operates as a free-running timer to ensure a frequency within a certain percentage. Another timer (not explicitly shown) can act as a watchdog timer to support the processor 202 when the processor becomes unresponsive. The unresponsiveness may be caused by inserted exploit code, security attacks, etc.

[0067] Flash controller 216 controls flash memory 210, which can be used for code and data storage. The main read path for this data can be in the standard memory address space. However, writing to this address space can be ignored because flash memory is not written in a standard way. Instead, in order to write to flash memory 210, software interacts with flash controller 216. Flash functions can include three main commands: read, erase, and program. Reading can be standardized and uses the chip memory address space. Erasing is performed at the page level, where the page size can be parameterized by flash controller 216. Upon receiving an erase request, flash controller 216 erases all the contents of the target page, which presents the data in a "1" state (e.g., 0xFFFFFFFF per word). Afterwards, software can program independent words to any value. In the absence of another erase, the flash bit returns to the "1" state, so the future content is actually effectively changed with the AND of the current content and the written value. Erase and program commands are relatively slow. Typical erase times are measured in milliseconds, and programming times are in the microsecond range. Security is also a concern because secret data may be stored in flash memory 210. Therefore, some memory protection may be provided by flash controller 216. For example, memory (e.g., e-flash or SRAM) may be protected with encryption. In some cases, to reduce the processing burden and thereby enable less complex hardware to perform encryption and decryption, relatively lightweight encryption or memory scrambling techniques may be implemented using reduced strength ciphers.

[0068] exist Figure 2 , a security circuit system 106 is depicted as having a particular set of circuit components. However, a given security circuit system 106 may have more, fewer, or different circuit components. The circuit components may also be interconnected in different ways or operate in ways other than the examples described above. Further, some circuit components may be omitted, while other circuit components are implemented in multiple instances. For example, the alarm handler 110 may be duplicated, or multiple AES encryption engines 212 may appear as part of some security circuit systems 106. Further, the GPIO interface 220 may be omitted from the peripheral device 250 that interacts with the alarm handler 110 of the IC chip, where the security circuit system 106 forms one of dozens of cores.

[0069] Example scenarios, techniques and hardware for alert handling

[0070] (For example, Figure 2The safety circuit system 106 may at least partially use the alarm handler 110 to handle the alarm. Example functionality of the alarm handling mechanism is described herein. The alarm handler 110 may be implemented as a component operating as a peripheral device 250 on the interconnect 204. Thus, the alarm handler 110 may comply with the compatibility specifications of the safety circuit system 106. Figure 1 The alarm 112 may be implemented as an interrupt type signal or alarm indication that is received from other peripheral devices and indicates a potential security threat. In operation, the alarm handler 110 may collect alarms from other circuit components of the device and convert them into interrupts that the processor 202 may resolve. However, if the processor 202 does not clear the interrupt, the alarm handler 110 provides a hardware response to resolve the potential security threat.

[0071] Certain example embodiments may provide one or more of the following features. First, the alarm handler 110 receives alarm indications from peripheral device sources that are issued in different ways, synchronously or asynchronously. The peripheral device 250 can generate an alarm based on the function, knowledge, or sensed parameters of the peripheral device 250. Secondly, the alarm handler 110 performs a ping test of the alarm source. The ping monitor requests periodic alarm responses from each alarm source to ensure that the communication channel with the alarm source is running. Third, register locking can be implemented on the configuration registers. Once locked, the register cannot be modified by software until the next system reset.

[0072] Fourth, the alarm handler 110 implements an assignment mechanism to assign independent alarms to specific alarm classes using, for example, register-based techniques. The system can implement any number of alarm classes, such as 3 or 4, and any class can be disabled individually. The alarm handler 110 generates an interrupt corresponding to the assigned alarm class for transmission to the processor 202. Fifth, the alarm handler 110 stores a disambiguation history to enable software to determine which alarm caused a given class interrupt. Although the disable command can allow an alarm to be ignored, the disable is used in situations where the alarm is erroneous. By locking the register state after the initial configuration is created, unwanted access can be prevented.

[0073] Sixth, each alarm class has a configurable response time or number of alarms before taking the upgrade step. The alarm handler 110 can implement register-based upgrade control. In some cases, the duration of the upgrade timer can be established with a register. In other cases, a large number of alarms can be established to control the upgrade. To this end, the value in the register represents the number of alarms that occurred in a given class before the upgrade step is implemented. The timeout of an unresolved interrupt request (IRQ) sent in response to an alarm can also trigger an upgrade. Seventh, the configurable upgrade mechanism of the alarm handler 110 enables multiple upgrade command signals (e.g., 4) to be generated in sequence or in response to an event. As part of the upgrade mechanism, the alarm handler 110 can map a given upgrade alarm to a non-maskable interrupt (NMI), an erase secret signal, a privilege reduction of another component, a chip reset, and the like. The upgrade command signal can be issued in different ways, and the signaling path to the upgrade handler can be protected using a heartbeat verification technology. The failure of the heartbeat verification can detect whether there is a problem with the upgrade handler. The alarm handler 110 can also implement a configurable time for each step between the upgrade levels.

[0074] Eighth, the alarm handler 110 generates two locally sourced hardware alarms. If the differential signaling with the alarm source or escalation handler fails—for example, if the signal integrity check fails, then a first locally sourced alarm is generated. If the alarm source or escalation handler fails to respond to the ping request, then the alarm handler 110 generates a second such alarm. In general, the alarm handler 110 can receive incoming alarms from the entire system, classify the alarms, issue interrupts based on the classified alarms, and if the processor 202 does not clear the issued interrupt, then the interrupt is upgraded to a hardware-based response. Thus, if the processor cannot or does not handle the security alarm, the alarm handler 110 can act, for example, as a stand-in for the security response.

[0075] In some of the described architectures, security alarms are intended to be rare events, at least relative to "standard" interrupts. Thus, during the design phase, possible events may be designated as alarm events to the extent that the event is expected to occur infrequently and if the event has potential security consequences. Examples of such events are parity errors (which may indicate an attack), unauthorized actions on cryptographic or security-related components, values ​​sensed from physical sensors indicating environmental changes (e.g., voltage or temperature), and so forth. In addition to voltage sensors or temperature sensors, examples of physical sensors include rupture sensors for detecting punctures or other intrusions through physical shielding, light sensors for detecting laser pulses, and fault sensors for detecting transient fluctuations or faults, to name a few. The system routes the alarm through the alarm handler 110, which converts the alarm into an interrupt that the processor 202 potentially resolves. For some embodiments, it is potentially desirable that the secure operating system have a protocol to handle any such alarm-derived interrupts in software. If so, the secure operating system should typically resolve the interrupt and then clear the interrupt with the alarm handler 110.

[0076] Nonetheless, if the processor 202 becomes untrusted, the alarm handler 110 can enable the security circuit system 106 to respond to the security threat, thereby enabling at least a portion of the IC chip to respond to the security threat. The processor 202 may become untrusted if it is attacked, if it does not respond, and so on. To help combat security issues, the alarm handler 110 escalates the alarm to exceed the processor interrupt. The alarm handler 110 can provide multiple escalation signals that are routed to different chip functions to respond to the attack. These functions can include such functions as erasing secrets on the chip, powering off at least a portion of the chip, resetting at least a portion of the chip, and so on.

[0077] To simplify software management of alarms, the alarm handler 110 may provide an alarm classification mechanism in which each alarm is classified into one of a plurality of classes. Classification may be performed in any of a number of possible ways using a configurable processing flow to provide a flexible alarm handling mechanism. Alarms with similar profiles may be classified together. The profiles may be associated with risk of occurrence, degree of security concern, frequency of false triggering, etc. For each alarm class, a counter of the alarm may be maintained in an accumulator. If the counter meets a programmable maximum value for the corresponding class, an escalation protocol for that class is initiated. The counter may be cleared by the alarm handler 110, software, etc. These features, functions, and techniques may be provided by Figure 3 The components shown are provided.

[0078] Figure 3An example alarm handler 110 is generally illustrated at 300, which is coupled to a plurality of peripheral devices 250-1...250-P and a plurality of upgrade handlers 350-1...350-E. Variables P and E represent positive integers that may be the same or different from each other. In an example embodiment, the alarm handler 110 is coupled to a plurality of peripheral devices 250-1...250-P and a plurality of upgrade handlers 350-1...350-E. The alarm handler 110 includes a plurality of alarm receiver modules 312-1...312-M, a plurality of upgrade transmitter modules 314-1...314-N, at least one controller 310, at least one ping monitor 302, at least one register bank 316, and integrity fault circuitry 318. Variables M and N represent positive integers that may be the same or different from each other and other variables used herein. The alarm handler 110 also includes a plurality of IRQ units 304 - 1 . . . 304 -N, a plurality of accumulation units 306 - 1 . . . 306 -N, and a plurality of escalation timers 308 - 1 . . . 308 -N.

[0079] Although certain sets of circuit components are represented as having a number N, each set may have a different number of such components, depending on the context or implementation. Therefore, variables P, E, M, and N may be the same or different from each other. For example, a given peripheral device 250 may have two or more alarm transmitter modules 322. In this case, variable M may be greater than variable P. This occurs if, for example, peripheral device 250 is monitoring multiple different potential security threats. As another example, each upgrade handler 350 may include an upgrade receiver module 324. If so, variables N and E may be equal.

[0080] Each alarm receiver module 312 of the plurality of alarm receiver modules 312-1...312-M is coupled to at least one peripheral device 250 of the plurality of peripheral devices 250-1...250-P. Each upgrade transmitter module 314 of the plurality of upgrade transmitter modules 314-1...314-N is coupled to at least one upgrade handler 350 of the plurality of upgrade handlers 350-1...350-E. A plurality of upgrade timers 308-1...308-N are coupled to the plurality of upgrade transmitter modules 314-1...314-N. Each corresponding upgrade timer 308 can correspond to a corresponding upgrade severity of the plurality of upgrade severities. Similarly, each corresponding upgrade handler 350 of the plurality of upgrade handlers 350-1...350-E can correspond to a corresponding upgrade severity of the plurality of upgrade severities. Figure 4-1 and Figure 4-2 Example escalation severity levels that may be configured across escalation circuit components are described.

[0081] In an example operation, the controller 310 is coupled to a plurality of alarm receiver modules 312-1...312-M and a plurality of escalation timers 308-1...308-N. The controller 310 classifies the trigger alarm received from the alarm receiver module 312 into a classification in a plurality of classifications or an alarm classification in a plurality of alarm classes. The classification may be based on the alarm receiver module 312, the corresponding peripheral device 250, its alarm transmitter module 322, etc. The controller 310 starts an escalation timer 308 in the plurality of escalation timers 308-1...308-N based on the classification. Figure 4-1 The classification is further described.

[0082] Each peripheral device 250 of the plurality of peripheral devices 250-1...250-P includes at least one alarm transmitter module 322 of the plurality of alarm transmitter modules 322-1...322-M. Each corresponding alarm receiver module 312 of the plurality of alarm receiver modules 312-1...312-M is coupled to a corresponding alarm transmitter module 322 of the plurality of alarm transmitter modules 322-1...322-M via a corresponding signaling path 332 of the plurality of signaling paths 332-1...332-M. Each upgrade handler 350 of the plurality of upgrade handlers 350-1...350-E includes at least one upgrade receiver module 324 of the plurality of upgrade receiver modules 324-1...324-N. Each respective upgrade transmitter module 314 in the plurality of upgrade transmitter modules 314-1...314-N is coupled to a respective upgrade receiver module 324 in the plurality of upgrade receiver modules 324-1...324-N via a respective signaling path 334 in the plurality of signaling paths 334-1...334-N. Each signaling path 332 and 334 includes at least one differential path.

[0083] In an example operation, the controller 310 can process alarms from internal and external sources. The external source includes a plurality of peripheral devices 250. The alarm receiver module 312 receives an alarm indication 352 from a corresponding alarm transmitter module 322. The alarm receiver module 312 forwards the alarm indication 352 to the controller 310 as a trigger alarm 362. At this time, the trigger alarm 362 corresponds to an unclassified trigger alarm. The alarm indication 352 reflects that the corresponding peripheral device 250 has detected a potential security threat. For clarity, certain signals are described with respect to a circuit component, even though such signals may apply to other instances of the same type of circuit component. For example, although the alarm indication 352 is depicted as being transmitted from the alarm transmitter module 322-1 of the peripheral device 250-1 to the alarm receiver module 312-1 of the alarm handler 110, the alarm transmitter module 322-M of the peripheral device 250-P may also transmit the alarm indication 352 to the alarm receiver module 312-M of the alarm handler 110.

[0084] Internal or local sources of alarms that can also be processed by the controller 310 include the ping monitor 302 and the integrity fault circuit system 318. Because the alarm handler 110 communicates with the peripheral device 250 and the upgrade handler 350, and because the fault may be related to the signal integrity or ping mechanism of the various signaling paths 332 and 334, these internal sources can generate four different alarms (for example, two types of security issues, each of which can correspond to two types of components, equivalent to four different alarms). Alarms from these internal sources include alarm ping fault 364, upgrade ping fault 366, alarm integrity fault 368, and upgrade integrity fault 370. Each of these alarms can be transmitted using a corresponding signal.

[0085] Each signaling path 332 or 334 can be implemented using one or more conductors. If a differential signaling protocol is implemented on the path, two or more conductors can implement the signaling path 332 or 334. Compared with single-ended signaling, with differential signaling, additional integrity checks can be performed for safety purposes to ensure that the signaling path has not been damaged. The integrity fault circuit system 318 can perform one or more such checks. For example, the integrity fault circuit system 318 can monitor the wire pairs used for differential signaling to ensure that the pair voltage is applied to the two wires at least during the signaling time. If the signaling path 332 coupled to the peripheral device 250 is damaged, the integrity fault circuit system 318 sends an alarm integrity fault signal 368 to the controller 310. If the signaling path 334 coupled to the upgrade handler 350 is damaged, the integrity fault circuit system 318 sends an upgrade integrity fault signal 370 to the controller 310. An example method for the controller 310 to process these path integrity fault signals 368 and 370 is described below.

[0086] The alarm handler 110 also uses an example ping mechanism to ensure that the peripheral device 250 and the upgrade handler 350 are running and communication is possible. The ping monitor 302 implements the ping mechanism in conjunction with the communication module. The ping monitor 302 issues a ping command 358. The alarm receiver module 312-M receives the ping command 358. In response to the ping command 358, the alarm receiver module 312-M transmits a ping request 354 to the alarm transmitter module 322-M of the peripheral device 250-P. To confirm that the peripheral device 250-P is running and the signaling channel 332-M is working, the alarm transmitter module 322-M returns a ping response 356 to the alarm receiver module 312-M.

[0087] Based on the confirmation ping response signal 356, the alarm receiver module 312-M provides a pingokay message 360 ​​to the ping monitor 302. If the ping monitor 302 receives the ping okay message 360 ​​within the ping duration period after issuing the ping instruction 358, the ping monitor 302 identifies the peripheral device 250-P as operating in this round. On the other hand, if the ping okay message 360 ​​is not returned within the ping duration period, the ping monitor 302 issues an alarm ping failure signal 364 to the controller 310. The ping duration can be configurable, including by programming registers of the register bank 316. An example method for the controller 310 to handle such a failure signal 364 is described below.

[0088] The ping mechanism is also responsible for ensuring that the upgrade handler 350 is communicating with the alarm handler 110 and is running using one or more ping requests. The ping monitor 302 issues a ping command 358 to the upgrade sender module 314-N, and the upgrade sender module 314-N receives the ping command 358. In response to the ping command 358, the upgrade sender module 314-N transmits a ping request 380 to the upgrade receiver module 324-N of the upgrade handler 350-E. In order to confirm that the upgrade handler 350-E is running and the signaling channel 334-N is working, the upgrade receiver module 324-N returns a ping response 382 to the upgrade sender module 314-N.

[0089] Based on the confirmation ping response signal 382, ​​the upgrade sender module 314-N provides a pingokay message 360 ​​to the ping monitor 302. If the ping monitor 302 receives the ping okay message 360 ​​within the ping duration period after issuing the ping instruction 358, the ping monitor 302 identifies the upgrade handler 350-E as running in this round of ping. On the other hand, if the ping okay message 360 ​​is not returned within the ping duration period, the ping monitor 302 sends an upgrade ping failure signal 366 to the controller 310. An example method for the controller 310 to process the signal 366 is described below.

[0090] The ping monitor 302 can determine a wait period between commands for a ping exchange and a target of a ping instruction 358. Each wait period can be randomly determined to increase the security provided by the ping mechanism. Therefore, the ping monitor 302 can use a random number generator (RNG) (e.g., a pseudo RNG (PRNG) or a true RNG (TRNG)) to establish each wait period (e.g., a randomized time duration) between consecutive issuances of ping instructions 358 to the same module or the next module. Additionally or alternatively, the next target of the ping message exchange (e.g., the peripheral device 250 or the upgrade handler 350) can also be randomly determined. Randomization makes it more difficult to spoof a correct ping okay message 360 ​​by artificially transmitting a ping response signal 356 or 382 from the correct component at the correct time.

[0091] After receiving the alarm signal, the controller 310 processes the alarm signal. As described above, the alarm signal may include a trigger alarm 362 received from the alarm receiver module 312 but "originating" from the peripheral device 250, an alarm ping failure signal 364, an upgrade ping failure signal 366, an alarm integrity failure signal 368, an upgrade integrity failure signal 370, etc. The controller 310 assigns a classification to the alarm signal based at least in part on the source of the alarm signal, the cause of the alarm signal, or the meaning of the alarm signal. The source or cause may include the peripheral device 250 or a corresponding alarm receiver or transmitter module, the upgrade handler 350 or a corresponding upgrade transmitter or receiver module, the integrity failure circuit system 318, the ping monitor 302, etc. The meaning may be related to a communication failure due to an integrity or ping failure, a positive alarm issued from the peripheral device due to an alarm event, the nature of the alarm event, a combination thereof, etc. The nature of the alarm event may be related to how severe the attack - if it occurs - is in terms of exposed information, compromised account access, device damage, etc.

[0092] Based on the determined classification, the controller 310 initiates at least one alarm handling path. Each alarm handling path corresponds to at least one classification level. The alarm handling path may advance or flow through one or more of the plurality of IRQ units 304-1...304-N, one or more of the plurality of accumulator units 306-1...306-N, one or more upgrade timers 308-1...308-N, one or more upgrade transmitter modules 314-1...314-N, and one or more upgrade receiver modules 324-1...324-N to potentially reach at least one upgrade handler 350 of the plurality of upgrade handlers 350-1...350-E. Various configurable alarm handling paths may be selected to flexibly address a large number of potential vectors that may be used to attack the IC chip. Refer to the following Figure 5-1 to Figure 5-3 An example alarm handling path is described. In some cases, the determined alarm classification corresponds to an alarm handling path that begins at the first classification level. If so, the controller 310 causes the IRQ unit 304-1 to send an interrupt to the processor 202 or an associated interrupt controller 228 (ItC 228) ( Figure 2308-1) issues an interrupt 384. The controller 310 also starts an escalation timer, such as the escalation timer 308-1, and will wait for the timer to expire. At the same time, the controller 310 can track or maintain the total number of alarms received at the first classification level or from the same alarm receiver module 312 using the accumulation unit 306-1. In general, each corresponding accumulation unit 306 can accumulate, for example, a corresponding count of alarms corresponding to a corresponding alarm classification. If the processor 202 does not resolve and clear the interrupt before the timer expires, or in response to the controller 310 not receiving a response from the processor 202 to the interrupt, the controller 310 can escalate the process along the corresponding alarm handling path. Therefore, if the timer expires or if the accumulated number reaches a threshold, the controller 310 responds along the alarm handling path. For example, the path can proceed from the accumulation unit 306-1 to the escalation timer 308-1 or from the escalation timer 308-1 to the escalation transmitter module 314-1 (or both).

[0093] However, in this example, the controller 310 advances the alarm handling path from the first classification level to the Xth classification level, which corresponds to the Nth circuit component shown, namely the Nth accumulation unit 306-N, the upgrade timer 308-N, and the upgrade transmitter module 314-N. To this end, the controller 310 issues a trigger-type alarm 372 to any one or more of the following: the IRQ unit 304-N, the accumulation unit 306-N, or the upgrade timer 308-N. In response, the IRQ unit 304-N can issue an interrupt 384 for the processor to handle. The accumulation unit 306-N can also increase the accumulation value, which indicates the number of Xth classification level alarms that have been triggered or represents the number of alarms from a given alarm receiver module 312. Further, the upgrade timer 308-N can start the upgrade timer of the Xth classification level.

[0094] When the upgrade timer is elapsed and the triggered alarms are accumulated, the controller 310 compares the number of triggered alarms with the alarm number threshold. If the accumulated count of the accumulation unit 306-N reaches the alarm number threshold (e.g., for the Xth classification level), the accumulation unit 306 generates a class accumulation indication 374 for the Xth separation level. The accumulation unit 306 provides the class accumulation indication 374 to the upgrade timer 308-N. In response, the upgrade timer 308-N can start a new or unstarted timer, advance a started timer by some amount, ignore the indication, or issue an upgrade instruction 376. Further, the upgrade timer 308-N can issue an Xth classification upgrade instruction 376 based on the expiration of the timer of the upgrade timer 308-N. The upgrade timer 308-N provides the upgrade instruction 376 to one or more of the plurality of upgrade transmitter modules 314-1...314-N.

[0095] In this example alarm handling path, the upgrade timer 308-N issues an upgrade instruction 376 to the upgrade transmitter module 314-1. More generally, the controller 310 may be responsible for instructing the upgrade transmitter module 314 to send an upgrade command 378 to the upgrade handler 350. In response, the upgrade transmitter module 314-1 transmits the upgrade command 378 to the upgrade receiver module 324-1 of the upgrade handler 350-1 via the signaling path 334-1. In response to receiving the upgrade command 378, the upgrade handler 350-1 executes at least one security countermeasure. For example, the security countermeasure may include erasing stored data, disconnecting a suspicious peripheral device from at least one interconnection among a plurality of peripheral devices, causing a power domain including the suspicious peripheral device to collapse, resetting at least a portion of the integrated circuit, and the like. Refer to the following Figure 7 Described is an example communication between the alarm handler 110 and the escalation handler 350. Figure 4-1 Describes example power domains.

[0096] Figure 4-1 Additional example aspects of an alarm handler 110 are illustrated at 400-1, which is coupled to a plurality of peripheral devices 250-1...250-P and a plurality of upgrade handlers 350-1...350-P. As shown, a first alarm receiver module 312-1 is coupled to a first alarm transmitter module 322-1 of the first peripheral device 250-1 via a first signaling path 332-1, and a second alarm receiver module 312-2 is coupled to a second alarm transmitter module 322-2 of the first peripheral device 250-1 via a second signaling path 332-2. Thus, a single peripheral device 250 may include multiple alarm transmitter modules, and the alarm handler 110 may include a corresponding alarm receiver module for each alarm transmitter module. A third alarm receiver module 312-3 is coupled to a third alarm transmitter module 322-3 of the second peripheral device 250-2 via a third signaling path 332-3. Likewise, the first upgrade transmitter module 314-1 is coupled to the first upgrade receiver module 324-1 of the first upgrade handler 350-1 through the first signaling path 334-1.

[0097] In some embodiments (e.g., Figure 1 and Figure 2 The root of trust (ROT) chip or other secure circuit system 106 includes multiple clock domains 410 to enable different components to operate at different clock frequencies at different times, or to enable clock jitter of certain components to achieve security purposes. Figure 4-1, the circuit system includes a first clock domain 410-1 and a second clock domain 410-2. The first peripheral device 250-1 is arranged in the second clock domain 410-2, but the other components shown operate in the first clock domain 410-1. Therefore, the communication between the first alarm receiver module 312-1 and the second alarm receiver module 312-2 and the first alarm transmitter module 322-1 and the second alarm transmitter module 322-2 across the first signaling path 332-1 and the second signaling path 332-2 can be performed asynchronously to accommodate potential different clock frequencies. Due to the common clock domain, the communication across the third (alarm) signaling path 332-3 and the first (upgrade) signaling path 334-1 can be performed synchronously.

[0098] In an example implementation, the controller 310 classifies a trigger alarm 362 received from an alarm receiver module 312, such as a second alarm receiver module 312-2. The classification 404 or classification operation 404 is performed in response to the trigger alarm 362 and based on the second alarm receiver module 312-2 providing the trigger alarm. Based on the identity of the original peripheral device, in this example, the first peripheral device 250-1, it is known that the second alarm receiver module 312-2 corresponds to a given peripheral device 250 or its alarm event. Therefore, the classification 404 is also based on the peripheral device 250 or the alarm event detected thereby. Although in Figure 4-1 4. Although not shown, classification 404 may also be performed in response to an "internal alarm" of alarm handler 110. Internal alarms include alarm ping failure, upgrade ping failure, alarm integrity failure, and upgrade integrity failure, as described above with reference to Figure 3 as described.

[0099] The classification operation 404 classifies the alarm into an alarm category 406 in a plurality of alarm categories 406-1...406-N using, for example, one or more registers. In some cases, a variable N of a plurality of alarm levels may correspond to a variable N of a plurality of accumulation units 306, an upgrade timer 308, etc. In other cases, the two variables may have different values. Figure 4-2 An example system is described having four levels of alarm classification 406 and four levels of classification severity.

[0100] The ping monitor 302 may include a ping timer 402. The ping timer 402 enables the ping monitor 302 to perform ping operations based on time intervals or time durations. The duration or timeout tracked by the ping timer 402 may be pseudo-randomly determined using a linear feedback shift register (LFSR). An example method of random number generation is described below.

[0101] In some embodiments, the inputs of the ping command signal 358 at the plurality of alarm receiver modules 312 and the plurality of upgrade transmitter modules 314 within the alarm handler 110 are coupled to the ping monitor 302. This is referred to above Figure 3 The ping monitor 302 determines a random number of waiting periods between consecutive ping requests. Further, the ping monitor 302 also randomly selects a specific differential path, peripheral device 250, or upgrade handler 350 to ping. This makes it more difficult to predict the next ping occurrence based on past observations.

[0102] ( Figure 4-1 The ping timer 402 may be implemented using a Galois or Fibonacci type LFSR-based PRNG. To increase the entropy of the pseudo-random sequence, a random bit or bits from the TRNG are XORed into the LFSR state each time a new random number is drawn (e.g., once every 10k cycles). The LFSR is m bits wide. The bits used for the random timer count include n bits, where m>n. The remaining (m-n) bits are used to randomly select the peripheral device 250 to ping next.

[0103] After selecting one of the peripheral devices 250 to ping, the ping monitor 302 waits until the corresponding ping okay message is asserted or until a programmable ping timeout value is reached. In both cases, the ping monitor 302 continues to perform the next ping. However, in the second case, the ping monitor 302 additionally generates a "ping failure" alarm 364 or 366 for the alarm path or the escalation path. The timeout value can be a function of the ratio between the alarm handler clock and any peripheral clock present in the multi-clock domain system. The timeout value can be set at startup time via (e.g., Figure 4-2 424 of the register bank 316. When the initial configuration phase is complete and the registers 424 of the register bank 316 have been locked, the ping timer 402 can be started. In some cases, if no requested suspicious "ping ok" message arrives, the ping monitor 302 can directly mark a "ping failure" alarm.

[0104] Figure 4-2Additional example aspects related to the escalation severity of the alarm handler 110 are illustrated. As shown, the register bank 316 includes a plurality of registers 424-1, 424-2, ... 424-R, where R represents a positive integer. The plurality of registers 424-1, ... 424-R can be configured by software or firmware during design / manufacturing or operation. Each register 424 stores at least one value that establishes some programmable aspects of processing an alarm using at least one alarm handler path. For example, the register 424 can establish a counting threshold for at least one accumulation unit 306, a time duration of at least one escalation timer 308, routing information for adapting an alarm handling path, and the like.

[0105] In an example implementation, each upgrade timer 308 may be coupled to more than one upgrade transmitter module 314. For example, each upgrade timer 308 may selectively issue an upgrade instruction 376 to any one of the plurality of upgrade transmitter modules 314. As shown, the plurality of upgrade timers 308 are coupled to the plurality of upgrade transmitter modules 314 via at least one switch matrix 422. For example, the switch matrix 422 may include a set of multiplexers (not explicitly shown) that may selectively couple the upgrade instruction 376 sent by any upgrade timer 308 to any upgrade transmitter module 314.

[0106] exist Figure 4-2 In the example shown, there are four levels of components. Therefore, the variables N of the IRQ unit 304, the accumulation unit 306, the escalation timer 308, the escalation sender module 314, the alarm category 406, etc. are equivalent to the following description Figure 4-2 and Figure 5-1 to Figure 5-3 Each component level corresponds to an upgrade severity 426 in a plurality of upgrade severities 426-1, 426-2, 426-3, ... 426-S, where S corresponds to a positive integer. Figure 4-2 Four levels of escalation severity 426 (eg, S=4) are depicted in FIG. 4 and described herein, but the safety circuit system may provide or implement a different number of levels.

[0107] As the alarm classification and escalation severity level increase, the components shown form a logical hierarchy of increasing escalation severity. Relative to the multiple escalation timers 308-1...308-4 in the group 432 of escalation timers 308, a hierarchy 434 of increasing escalation importance 426 is indicated. Although not explicitly shown, each group of components, such as multiple accumulation units 306-1 to 306-4 or multiple escalation transmitter modules 314-1 to 314-4, may also represent a hierarchy of increasing escalation severity. When processing an alarm, the alarm handling path can step along the hierarchy 434 to the next component (e.g., the next escalation timer 308). Alternatively, the alarm handling path can skip the next component along the hierarchy 434 to reach another component (e.g., another escalation timer 308) along the hierarchy 434 of a group of components. By skipping components along the hierarchy 434, the alarm handler 110 can advance to a higher escalation severity 426 more quickly along the hierarchy 434, or bypass security countermeasures that are not applicable to offset a given alarm. Refer to the following Figure 5-1 to Figure 5-3 Example alert handling paths are described.

[0108] With respect to alarm classification and interrupt signaling, in some embodiments, each incoming and local alarm signal may generally be classified into one of N classes or disabled in the absence of classification. Using a four-class example (e.g., N=4), the four alarm classifications 406-1 to 406-4 may be designated as classes A, B, C, and D. Each alarm classification may be defined in hardware, firmware, and / or software. Factors to consider include: some alarm types are similar to other alarm types, some alarm types are "noisier" than other alarm types (e.g., when triggered, they remain on for longer periods of time), some alarm types are more critical than other alarm types, and so on.

[0109] For each Alert Class (AD), an interrupt may be sent. Like interrupts sent from "standard" peripherals, for interrupts sent by the Alert Handler 110, there may be three registers, e.g., enable, status, and test. Thus, as with other interrupts, software executing on the processor may be able to handle the source of the interrupt (e.g., in this case the original alarm event detected by the peripheral 250), and then clear the register states. Because the interrupt class is disassociated from the original alarm (due to the Classification 404 process), software may be granted access to the registers to determine which alarms have been raised since the last clear.

[0110] The issuance of each of the four class-based interrupts may optionally trigger a timeout timer (e.g., which may be physically identical to the counter for the corresponding escalation timer 308) that triggers further escalation if the interrupt is not handled and cleared within a certain time frame, as described herein. In some cases, the interrupt may be configured to be issued once an alarm has been registered in the corresponding alarm classification. In other words, the interrupt may be independent of an escalation mechanism, such as an alarm accumulation counter or escalation timer as described herein.

[0111] With regard to the escalation mechanism, in some embodiments, each class has at least two mechanisms that can trigger the corresponding escalation protocol-for example, implementing the corresponding security countermeasures for each escalation severity level. The first mechanism involves an accumulation unit 306 having a counter, which counts the number of alarm occurrences within a specific alarm classification. An alarm classified as class A means that the accumulation counter of class A is increased on each received trigger alarm 362. In order to simplify the hardware, because the alarm is expected to be rare or never occur, the alarm handler 110 does not need to try to count each alarm for each clock cycle. On the contrary, in some cases, the alarm triggers of each class are ORed together before sending the result of the OR operation as the increment signal at the accumulation unit 306 to the accumulation counter. Once the corresponding alarm quantity threshold has been reached, the next occurrence triggers the escalation protocol for a given class. The counter can be implemented with, for example, a saturation counter so that once it reaches the maximum representable count, it will not wrap around.

[0112] The alarm count accumulation mechanism can be associated with two control and status registers (CSRs) for each classification. The first register is for the cumulative maximum value. This indicates the total number of triggered alarms that need to be reached to enter the escalation phase (e.g., the sum of alarms classified in the corresponding group). This value is also referred to herein as the alarm quantity threshold. The second register is the current accumulation register. This clearable register indicates how many alarms have been accumulated so far. If escalation is to be avoided, it is desirable that the software clear this register before the maximum accumulation threshold setting is reached.

[0113] The second upgrade mechanism involves an upgrade timer circuit system (e.g., in upgrade timer 308), which has an interrupt timeout counter or timer that triggers an upgrade if the alarm interrupt is not handled within a programmable timeout window. Once the timeout counter reaches a timeout threshold (e.g., rises to a specific positive value or counts down to zero), the upgrade protocol is triggered. The interrupt timeout upgrade mechanism can also be associated with two CSRs for each classification. The first register is used to set the interrupt timeout value, which can have units of clock cycles. If this register is set to zero, the interrupt timeout can be disabled. The second register is for the current interrupt timeout value, which counts down or up. This timer register can be readable. If you want to avoid upgrading, you want the software to clear the corresponding interrupt status bit for a given classification before the timeout. In some cases, a single physical counter for each classification can be used for the interrupt timeout feature and the upgrade phase timer. If the interrupt timeout period and the upgrade phase do not overlap (e.g., upgrade is performed first when the upgrade is triggered), this circuit system reduction strategy can be implemented.

[0114] With respect to the programmable escalation protocol, in some embodiments, there are four output escalation signals—0, 1, 2, and 3—for four example levels of escalation severity 426-1 through 426-4. Examples of escalation signals or security countermeasures triggered by such escalation signals include, but are not limited to, processor non-maskable interrupts (NMIs), privilege reduction, secret erase, chip reset, etc. In some cases, the hierarchical order across escalation severity can range from escalation level 0 as the first trigger to escalation levels 1, 2, and 3. System operation can simulate a "fuse" in that, without active intervention, once the first escalation level is triggered, the alarm handling path continues—e.g., by the processor clearing an interrupt, resetting a bit in a register, etc.

[0115] Each corresponding class can be programmed with a corresponding upgrade protocol. If one of the above two mechanisms is triggered (for example, the counter accumulation mechanism or the upgrade timer mechanism), another timer of the corresponding class is started. The timer can be programmed with up to X delays using one or more registers. Each of the X delays represents a different upgrade stage (0-3) (for example, where X=4). Each of the four upgrade severity outputs (0-3) is "default" configured to assert at the corresponding stage. In other words, severity output 0 asserts at stage 0, output severity 1 asserts at stage 1, and so on. However, by modifying the corresponding enable / stage mapping using one or more registers 424, this mapping can be reallocated away from the default value. After the initial configuration is established, this mapping can be locked together with the alarm enable setting.

[0116] Software may stop a triggered upgrade protocol by, for example, clearing the corresponding upgrade counter. Protection for this clear operation may be granted in software. Each of the upgrade phases has a duration of at least one clock cycle, even if the cycle count for a particular phase has been set to zero.

[0117] The following example relates to the accumulation of alarms until the escalation protocol finally takes effect. The first alarm triggers an interrupt to class A. Assume that the processor is inserted or taken over, in which case the processor does not handle interrupts. Once enough alarms have been collected (for example, 16), the first escalation phase is entered. The first escalation phase is followed by three additional escalation phases, each of which has its own programmable length using at least one corresponding register. Here, the accumulator alarm quantity threshold is set to 15 to trigger when the 16th alarm occurs. If the escalation is to be triggered on the first occurrence in the alarm classification, the alarm quantity threshold is set to zero. Similarly, the circuit system may require one clock cycle to trigger the next escalation mechanism and enter phase 0.

[0118] In another example, the interrupt is still not handled by the processor. Therefore, when the interrupt handling timer expires, the interrupt timeout counter triggers an escalation. Assuming the alarm is not cleared, each of the four escalation severity stages may be entered after each corresponding timer expires. For each escalation stage, the escalation transmitter module communicates with the escalation receiver module of the escalation handler. As shown below with reference to Figure 7 As described, an applicable differential upgrade signaling protocol can distinguish between a "true" upgrade condition and pure ping signaling by encoding the upgrade command as a pulse that is K+1 cycles long, where K is a positive integer.

[0119] Figure 5-1 to Figure 5-3 Example alarm handling paths 502-1 to 502-6 are illustrated as extending within the alarm handler 110. The alarm handling paths appear in an example alarm handler architecture having four levels of alarm classification 406 and escalating severity 426. However, the principles are relevant to other architectures. The various example alarm handling paths 502 can all be established using registers 424 of the register bank 316. Also, although not shown in the figure, each alarm handling path 502 can advance to a higher level of escalating severity if a lower level (e.g., an initial classification level) does not result in the alarm being cleared.

[0120] Usually in Figure 5-1At 500-1 in FIG. 5 , the first alarm handling path 502-1 is associated with an alarm classified as a first alarm classification level. Therefore, the first IRQ unit 304-1 transmits an interrupt to the processor. The controller 310 also increases the count of the first accumulation unit 306-1 and may start the timer of the first upgrade timer 308-1. In response to the count reaching the threshold number of alarms of the first classification level or the start timer expiring (e.g., after the interrupt timer has also expired), the first upgrade timer 308-1 issues an upgrade instruction 376 to the first upgrade transmitter module 314-1.

[0121] The second alarm handling path 502-2 is associated with an alarm classified as a third alarm classification level. In this case, components corresponding to the first classification level and the second classification level are skipped along the hierarchy of increasing escalation severity. Therefore, the third IRQ unit 304-3 transmits the interrupt to the processor. The controller 310 also increases the count of the third accumulation unit 306-3, and can start the timer of the third upgrade timer 308-3 (for example, after the interrupt timer expires). If the processor clears the interrupt, the alarm handling can be terminated. Otherwise, in response to the count reaching the alarm number threshold of the third classification level or the expiration of the started timer, the alarm handler 110 (for example, the third upgrade timer 308-3) sends an upgrade instruction 376 to the third upgrade transmitter module 314-3.

[0122] For the first alarm handling path 502-1 and the second alarm handling path 502-2, each path is "limited" to the components corresponding to a given escalation severity 426. However, other alarm handling paths may traverse components of multiple escalation severities 426. Figure 5-2 At 500 - 2 in FIG. 5 , the third alarm handling path 502 - 3 and the fourth alarm handling path 502 - 4 both traverse components at two different classification levels because the paths are routed along a hierarchy of increasing escalation severity.

[0123] The third alarm handling path 502-3 is associated with an alarm classified as the first alarm classification level, such as the first alarm handling path 502-1. The difference between the first alarm handling path 502-1 and the third alarm handling path 502-3 is when the escalation instruction 376 is issued. For the third alarm handling path 502-3, the first escalation timer 308-1 uses the switch matrix 422 to issue the escalation instruction 376 to the second escalation transmitter module 314-2 instead of to the first escalation transmitter module 314-1. Therefore, the third alarm handling path 502-3 uses (for example, Figure 4-1 ) of the first escalation severity 426-1 circuit system interrupt, count threshold and timer duration to handle (e.g., Figure 3 and Figure 4-1) given triggering alarm 362. However, the security countermeasure implemented for the third alarm handling path 502-3 corresponds to the security countermeasure of the second escalated severity 426-2.

[0124] Therefore, the processing of two alarms that are both classified as the first alarm classification level may be different from each other. The deviation between the two alarm handling paths 502 can be controlled by at least one register 424 based on the origin of the triggering alarm, for example, the alarm receiver module 312 or the alarm transmitter module 322 of the peripheral device 250. The fourth alarm handling path 502-4 is associated with an alarm classified as the second alarm classification level. When the time period of the second upgrade timer 308-2 expires, the upgrade instruction 376 has not yet been issued. Instead, the fourth alarm handling path 502-4 is routed to the third upgrade timer 308-3. When the time period of the third upgrade timer 308-3 expires, the third upgrade timer 308-3 issues an upgrade instruction 376 to the third upgrade transmitter module 314-3. The third upgrade transmitter module 314-3 then transmits an upgrade command 378 according to the third upgrade severity 426-3.

[0125] Usually in Figure 5-3 At 500-3 in FIG. 5 , additional adaptive features are shown to describe how the alarm handling path 502 can be flexibly implemented. In the fifth alarm handling path 502-5, the path branches. Each of the two conditions can trigger the issuance of an upgrade instruction 376 to the upgrade transmitter module 314. The count value is tracked by the first accumulation unit 306-1. The timer is also monitored by the first upgrade timer 308-1. Neither of the two conditions - sequentially or partially overlapping - needs to be met to trigger the upgrade instruction. Instead, if the count meets the alarm quantity threshold of the first upgrade severity 426-1 (as determined by the first accumulation unit 306-1) or if the timer of the first upgrade severity 426-1 expires (as determined by the first upgrade timer 308-1), the alarm handler 110 (e.g., the first upgrade timer 308-1) issues an upgrade instruction 376 to the first upgrade transmitter module 314-1 through the switch matrix 422.

[0126] The sixth alarm handling path 502-6 depicts an example conditional branch between the levels of the escalation severity 426. The trigger alarm 362 is classified as the third level. The third IRQ unit 304-3 issues an interrupt, and the third escalation timer 308-3 starts a timer immediately or after the interrupt timeout expires. The third accumulation unit 306-3 also continues or begins to accumulate alarms classified as the third level. If the escalation timer expires first, the third escalation timer 308-3 issues an escalation instruction with the third level of escalation severity 426-3. However, if the alarm is incoming at such a speed that the alarm quantity threshold of the third level is met before the escalation timer expires, the sixth alarm handling path 502-6 is routed to a higher escalation severity level, namely the fourth escalation severity 426-4 in this example. Therefore, the fourth escalation timer 308-4 starts the timer duration of the fourth level, which may be significantly shorter than the timer duration of the third level. If the escalation timer of the fourth level expires first, the fourth escalation timer 308-4 issues an escalation instruction 376 to the fourth escalation transmitter module 314-4, as shown. On the other hand, if the timer of the third escalation timer 308-3 expires first, the third escalation timer 308-3 may issue an escalation instruction (not explicitly shown) to the third escalation transmitter module 314-3. In other words, the alarm handler 110 is configured to escalate an apparent third level class alarm to a fourth level security countermeasure if a large number of alarms arrive very quickly. Otherwise, the third level classification may result in the execution of the third level security countermeasure for the sixth alarm handling path 502-6.

[0127] Figure 6 An example communication relationship 600 between the alarm receiver module 312 of the alarm handler 110 and the alarm transmitter module 322 of the peripheral device 250 is illustrated. As shown, the signaling path 332 includes multiple pairs of wires (e.g., three pairs) to enable differential signaling across three differential paths. Each pair of wires includes a positive wire and a negative wire. The modules can communicate synchronously or asynchronously across the signaling path 332.

[0128] In an example implementation, the peripheral device 250 detects an alarm event 602. The alarm event 602 may correspond to a sensor input (e.g., a parameter sensed by a sensor), an observed activity pattern, an indication received from another component, etc. In response to the alarm event signal 602, the alarm transmitter module 322 transmits an alarm indication 352 to the alarm receiver module 312 over a first pair of wires (e.g., the upper pair depicted). In response to receiving the alarm indication 352, the alarm receiver module 312 provides a trigger alarm 362 to the controller 310. The alarm receiver module 312 also transmits an alarm confirmation signal 604 back to the alarm transmitter module 322 over a second pair of wires (e.g., the middle pair depicted) to confirm receipt of the alarm indication signal 352.

[0129] For the pinging protocol, the alert receiver module 312 receives the alert from (e.g., Figure 3 and Figure 4-1 358 pings the monitor 302. Prompted by the ping instruction 358, the alert receiver module 312 transmits a ping request 354 to the alert transmitter module 322 on a third pair of wires (e.g., the lower pair depicted). To indicate that the connection with the peripheral device 250 is valid and functional, the alert transmitter module 322 transmits a ping response 356 back to the alert receiver module 312—e.g., on the first pair of wires. For resiliency, the alert transmitter module 322 can transmit the alert indication 352 and the ping response 356 on the same pair of wires. This ensures that a bad actor has not cut the wires of the alert indication 352 while leaving the wires of the ping response 356 intact. The alert receiver module 312 receives the ping response 356 from the alert transmitter module 322. To complete the ping protocol cycle, the alert receiver module 312 forwards a ping okay message 360 ​​to the ping monitor 302 in response to receiving the ping response 356.

[0130] In some cases, at least a portion of integrity fault circuitry 318 is coupled to or incorporated into alarm receiver module 312. This integrity fault circuitry 318 monitors at least one pair of conductors to determine if proper differential signaling exists on the differential path and if the expected signaling pattern matches the actual signaling pattern. If not, integrity fault circuitry 318 generates an alarm integrity fault signal 368 and provides the signal to controller 310 as an internal alarm of alarm handler 110 (e.g., as an example). Figure 3 shown).

[0131] In some embodiments, the alarm is differentially encoded and signaled using a "full" handshake on the positive / negative alarm indication wires (e.g., the first pair of wires) and the positive / negative alarm confirmation wires (e.g., the second pair of wires). Employing a full handshake protocol allows the alarm signaling mechanism to be used with an asynchronous clock strategy, where some peripheral devices may reside in a clock domain 410 different from the alarm handler 110. The full handshake protocol ensures that the alarm message is correctly back-pressed and that the alarm is not "lost" at an asynchronous boundary due to a (possibly variable) clock ratio greater than or less than 1.0. If the alarm event 602 is still true within the peripheral device 250, the local alarm indication can be repeated on the differential alarm indication wires. Therefore, the handshake pattern can be repeated while the alarm is true. The alarm transmitter module 322 can wait for two cycles between handshakes.

[0132] In an asynchronous environment, once the initial level change on the alarm indication wire has been received and synchronized with the local clock at the alarm receiver module 312, the alarm indication 352 can be propagated "immediately" to the trigger alarm signal 362. This ensures that the first occurrence of the alarm indication 352 is propagated, even if the handshake line has been manipulated to simulate back pressure. In a scenario with simulated back pressure, subsequent alarm indications may be depressed; however, the ping test mechanism described herein ultimately detects that the bad actor has tampered with the wire.

[0133] In some embodiments, to ensure that the alarm transmitter module 322 has not been compromised, the alarm receiver module 312 periodically (e.g., every few microseconds) "pings" or line tests the transmitter with a ping or heartbeat message. The ping timing can be randomized so that the occurrence of the ping request 354 message cannot be predicted. The ping timing is generated by a LFSR-based central timer within the alarm handler 110 (e.g., using the ping timer 402 of the ping monitor 302), which randomly asserts the ping command signal 358 of a particular alarm receiver module 312.

[0134] Once the ping instruction signal 358 is asserted, the alarm receiver module 312 encodes the ping request message 354 as a level change on the ping request differential path (e.g., the third pair of wires). The alarm receiver module 312 waits until the alarm transmitter module 322 responds to a complete handshake on the positive / negative alarm indication wire (e.g., the first pair of wires) and the positive / negative alarm confirmation wire (e.g., the second pair of wires). Once the handshake is complete, the alarm receiver module 312 asserts a ping okay message 360. The LFSR-based timer can have a programmable ping timeout. After the programmable ping timer expires without a complete handshake occurring, the ping monitor 302 asserts a "ping failure" internal alarm using an alarm ping failure signal 364. This timeout can be a function of the clock ratios present in the system and can be programmed accordingly at system startup.

[0135] In the relatively unlikely event that a ping request 354 collides with a local alarm indication 352 at the alarm sender module 322, the alarm indication 352 is blocked until the ping handshake protocol is complete. Although this approach slightly delays the transmission of the alarm indication 352, the alarm indication 352 is eventually signaled. Further, if an alarm indication 352 is sent from the alarm sender module 322 before the ping request 354 arrives at the alarm sender module 322, the alarm receiver module 312 treats the alarm indication 352 as a ping response. The "true" ping response still returns after the alarm handshake is complete, so the alarm is sent with only a slight delay, and the alarm receiver module 312 interprets it as such. In both collision situations, the signaling delay is approximately the length of the handshake plus a constant number of pause cycles (e.g., two sender cycles) between handshakes.

[0136] In some embodiments, the differential pair is monitored for signal integrity issues by the integrity fault circuit system 318. If an encoding fault is detected, the alarm receiver module 312 asserts the alarm integrity fault signal 368. This occurs at least in the following fault conditions: First, the alarm indication differential path (e.g., the first pair of wires) may not be correctly encoded at the alarm receiver module 312. This can be directly marked as an integrity fault on the receiver side. Second, the confirmation differential path (e.g., the second pair of wires) or the ping request differential path (e.g., the third pair of wires) may not be correctly encoded at the alarm transmitter module 322. Either of the latter two faults can be signaled to the alarm receiver module 312 by having the alarm transmitter module 322 set the positive and negative alarm indication wires to the same value. Further, the alarm transmitter module 322 can continuously toggle the value. This implicitly triggers a signal integrity alarm at the alarm receiver module 312. There are several signaling patterns that can indicate a fault. For example, if both the positive and negative wires of the differential pair have a low voltage or both have a high voltage at the same time, a fault is observed.

[0137] Figure 7 An example communication relationship 700 between the upgrade transmitter module 314 of the alarm handler 110 and the upgrade receiver module 324 of the upgrade handler 350 is illustrated. As shown, the signaling path 334 includes multiple pairs of wires (e.g., two pairs) to enable differential signaling across two differential paths. Each pair of wires includes a positive wire and a negative wire. The modules can communicate at least synchronously across the signaling path 334. In an example embodiment, the upgrade handler 350 executes or at least initiates a security countermeasure based on the activation countermeasure instruction 702.

[0138] As (for example, Figure 5-1 to Figure 5-3As part of the (e.g., also 3) alarm handling path 502, the escalation timer 308 provides an escalation instruction 376 to the escalation transmitter module 314. In response to receiving the escalation instruction 376, the escalation transmitter module 314 transmits the escalation command 378 to the escalation receiver module 324 on a second pair of wires (e.g., the lower pair depicted). In response to receiving the escalation command 378, the escalation receiver module 324 generates an activate countermeasure indication 702. Thus, in response to the transmitted escalation command 378, the escalation handler 350 at least initiates execution of the security countermeasure.

[0139] For the pinging protocol, the upgrade sender module 314 receives the upgrade from (e.g., Figure 3 and Figure 4-1 358 pings the monitor 302. Prompted by the ping instruction 358, the upgrade transmitter module 314 transmits a ping request 380 to the upgrade receiver module 324 on the second pair of wires. To indicate that the connection with the upgrade handler 350 is valid and functional, the upgrade receiver module 324 transmits a ping response 382 back to the upgrade transmitter module 314 on the first pair of wires (e.g., the upper pair depicted). The upgrade transmitter module 314 receives the ping response 382 from the upgrade receiver module 324. To complete the ping protocol cycle, the upgrade transmitter module 314 forwards a ping okay message 360 ​​to the ping monitor 302 in response to receiving the ping response 382.

[0140] In some cases, at least a portion of the integrity fault circuitry 318 is coupled to or incorporated into the upgrade transmitter module 314. This integrity fault circuitry 318 monitors at least one pair of conductors to determine if proper differential signaling is present on the differential path and if the expected signaling pattern matches the actual signaling pattern. If not, the integrity fault circuitry 318 generates an upgrade integrity fault signal 370 and provides the signal to the controller 310 as an internal alarm for the alarm handler 110.

[0141] It is possible that a bad actor attacks the alarm handler 110 directly. If the alarm handler 110 is plugged in or damaged during a tampering attempt, the upgrade transmitter module 314 can periodically stop sending ping requests 380. As another defense mechanism, the upgrade handler 350, such as its upgrade receiver module 324, can include a ping verification circuit system (not shown) to monitor incoming ping requests 380 and respond with countermeasures when pings stop. For example, the ping verification circuit system can include a timeout counter. In this case, each time the upgrade receiver module 324 receives a ping request 380, the ping verification circuit system resets the timeout counter. Therefore, if there is a lack of one or more pings for a time period exceeding the length of the timeout counter, it is possible that an attack has occurred on the alarm handler 110. In order to counter the detected attack or the inferred potential attack, the ping verification circuit system issues an activation countermeasure indication 702 in response to the expiration of the timer to trigger the corresponding countermeasure, thereby causing an upgrade.

[0142] In some embodiments, for each upgrade severity in the S upgrade severity 426 (where S represents a positive integer, such as 4), the alarm handler 110 instantiates the upgrade transmitter module 314. The S upgrade handlers 350 each instantiate a corresponding upgrade receiver module 324. The upgrade signaling mechanism is similar to the alarm signaling mechanism. However, if the upgrade handler 350 is located in the same clock domain as the alarm handler 110, the upgrade signaling mechanism can be a fully synchronous protocol. In order to facilitate synchronous communication, the upgrade transmitter module 314 and the upgrade receiver module 324 can use the same clock and reset signals.

[0143] like Figure 7 As shown, each transmitter-receiver pair is connected in parallel with two differential wire pairs. One pair extends from the transmitter to the receiver, and the other pair extends from the receiver to the transmitter. When receiving the upgrade command signal 376 having a pulse width of K>0, the upgrade transmitter module 314 encodes the signal as a differential pulse having a width of (K+1) on the differential path of the ping request 380 (e.g., on the second pair of wires). The upgrade receiver module 324 decodes the message and asserts the activate countermeasure 702 output after one delay cycle. Further, the upgrade receiver module 324 confirms receipt of the message by continuously switching the positive / negative signal on the first pair of wires as long as the upgrade command 378 is asserted. Failure of the upgrade receiver module 324 to respond properly triggers the upgrade integrity fault signal 370 from the integrity fault circuit system 318.

[0144] Further, the differential signaling mismatch on any pair of wires also triggers the alarm of the upgrade integrity fault 370. The mismatch on the first pair of wires for the ping response and confirmation can be directly detected at the upgrade transmitter module 314. The mismatch on the second pair of wires for the upgrade command and ping request is signaled back to the upgrade transmitter module 314 by the upgrade receiver module 324. For this reason, the upgrade receiver module 324 sets the positive and negative response wires of the first pair of wires to the same value and switches the value at each clock cycle. This implicitly triggers the upgrade signal integrity alarm on the transmitter side. This reverse signaling mechanism can be used to quickly track the upgrade, and if the alarm handler 110 detects that a specific upgrade signaling path has been tampered with, another countermeasure is used.

[0145] In some embodiments, the ping test of the upgrade handler is similar to the ping test of the alarm signaling scheme. The upgrade signaling line can be pinged and / or line tested to determine whether the upgrade receiver module 324 has been tampered with. This can be achieved by asserting the input of the ping instruction 358 at the upgrade transmitter module 314. The ping request 380 is encoded as a single cycle pulse on the second pair of wires, which is also used to transmit the upgrade command 378. However, with the single cycle pulse of the ping request 380, the upgrade receiver module 324 does not decode the signaling as an upgrade command. Instead, the upgrade receiver module 324 responds to the "1010" pattern on the first pair of wires to transmit the ping response 382.

[0146] In response, if the pattern is correctly received after a delay period, the upgrade transmitter module 314 asserts the ping okay message 360. Otherwise, the upgrade transmitter module 314 first asserts the upgrade integrity fault signal 370 to notify the controller 310. Later, after the programmable ping timeout is reached, the ping monitor 302 generates a "ping failure" alarm using the upgrade ping failure signal 366. In this case, the upgrade transmitter module 314 triggers the upgrade integrity fault signal 370 because "no ping response" and "wrong ping response" are ambiguous in this context.

[0147] Further, in this upgrade and countermeasure scenario, the upgrade signal takes precedence over the ping message delivery. Thus, if the upgrade instruction 376 has been asserted, the ping instruction 358 is confirmed with a ping okay message 360. If the upgrade instruction 376 becomes asserted, the ongoing ping sequence will also be aborted. In some cases, after the ping request or upgrade command has been issued, it is expected that the ping and upgrade response sequence will start a cycle. Otherwise, the upgrade sender module 314 asserts the upgrade integrity fault signal 370.

[0148] Having generally described schemes, techniques, and hardware for alarm processing, the discussion now turns to example methods.

[0149] Example method for alert handling

[0150] Refer to the following Figure 8 The flowchart of FIG. 1 depicts an example method. Figure 8 An example method of implementing alarm handling by an apparatus is illustrated with a flowchart 800. The flowchart 800 includes four blocks 802 to 810. In block 802, multiple peripheral devices are monitored with multiple alarm receiver modules. For example, the alarm handler 110 can monitor multiple peripheral devices 250-1...250-P with multiple alarm receiver modules 312-1...312-M. As part of the monitoring, the alarm receiver module 312 can monitor the signaling path 332 to receive the alarm indication 352 by implementing a pinging message protocol or by checking the wire and signaling integrity.

[0151] In block 804, a trigger alarm is received from an alarm receiver module in the plurality of alarm receiver modules based on a peripheral device in the plurality of peripheral devices. For example, the alarm handler 110 may receive a trigger alarm 362 from an alarm receiver module 312 in the plurality of alarm receiver modules 312-1...312-M based on a peripheral device 250 in the plurality of peripheral devices 250-1...250-P. For example, the controller 310 of the alarm handler 110 may receive the trigger alarm 362 from the alarm receiver module 312. The controller 310 may at least implicitly identify the alarm originating alarm transmitter module 322 to determine the nature of the alarm based on the transmitting alarm receiver module 312.

[0152] In block 806, based on the alarm receiver module, the trigger alarm is classified into an alarm classification in a plurality of alarm classifications. For example, the alarm handler 110 may classify the trigger alarm 362 into an alarm classification 406 in a plurality of alarm classifications 406-1...406-N based on the alarm receiver module 312 providing the trigger alarm 362. In some cases, the controller 310 may perform the classification 404 using at least one register 424 of the register bank 316. The value stored in the register 424 may link the peripheral device 250 or its alarm event 602 with the corresponding alarm classification 406. The level of the determined alarm classification 406 may establish an initial escalation severity 426.

[0153] In block 808, an escalation timer of a plurality of escalation timers is started based on the alarm classification, wherein each respective escalation timer corresponds to a respective escalation severity of a plurality of escalation severities. For example, the alarm handler 110 may start an escalation timer 308 of a plurality of escalation timers 308-1 ... 308-N based on the alarm classification 406, wherein each respective escalation timer 308 corresponds to a respective escalation severity 426 of a plurality of escalation severities 426-1 ... 426-S. The length of the timer duration of the started timer may be established by at least one register 424 corresponding to the alarm classification 406. The escalation timer 308 may be started when a trigger alarm 362 is received, after an interrupt timer corresponding to the IRQ unit 304 expires, in response to an accumulation counter of the accumulation unit 306 reaching an alarm quantity threshold, some combination thereof, and the like.

[0154] Aspects of these methods may be implemented in, for example, hardware (e.g., fixed logic circuitry or a processor in conjunction with a memory), firmware, or some combination thereof. The methods may use Figures 1 to 7 The present invention is implemented by one or more devices or components shown, which can be further divided, combined, etc. The devices and components of these figures generally represent hardware (such as electronic devices, PCBs, package modules, IC chips, components or circuits), firmware or a combination thereof. Therefore, these figures illustrate some of the many possible systems or devices that can implement the described methods.

[0155] For the methods and associated flow charts described herein, the order in which operations are shown and / or described is not intended to be construed as limiting. Instead, any number or combination of the described method operations may be combined in any order to implement a given method or an alternative method. Operations may also be omitted from or added to the described method. Further, the described operations may be implemented in a completely or partially overlapping manner.

[0156] Additional Examples

[0157] In the following, some examples are described.

[0158] Example 1: An integrated circuit comprising: a plurality of peripheral devices; and an alarm handler, the alarm handler comprising: a plurality of alarm receiver modules, each alarm receiver module being coupled to a peripheral device among a plurality of peripheral devices; a plurality of upgrade timers, each respective upgrade timer corresponding to a respective upgrade severity among a plurality of upgrade severities; and a controller, the controller being coupled to the plurality of alarm receiver modules and the plurality of upgrade timers, the controller being configured to: classify a trigger alarm received from an alarm receiver module among the plurality of alarm receiver modules into an alarm classification among a plurality of alarm classifications based on at least one of the alarm receiver modules or the trigger alarm; and to start an upgrade timer among the plurality of upgrade timers based on the alarm classification.

[0159] Example 2: The integrated circuit according to Example 1 further includes: an interconnect; and a processor, which is coupled to an alarm handler via the interconnect, wherein a controller of the alarm handler is configured to: generate an interrupt based on a triggered alarm; issue an interrupt to the processor; wait for an upgrade timer to expire; and in response to not receiving a response to the interrupt from the processor, upgrade the triggered alarm to exceed the upgrade timer.

[0160] Example 3: An integrated circuit according to Example 1 or 2, wherein the controller of the alarm handler is configured to upgrade the triggered alarm to exceed the upgrade timer by at least one of the following: issuing another interrupt to the processor, the other interrupt corresponding to an interrupt level higher than the interrupt level of the interrupt; starting another upgrade timer among multiple upgrade timers, the other upgrade timer corresponding to an upgrade severity higher than the upgrade severity of the upgrade timer among multiple upgrade severities; or instructing the upgrade transmitter module to send an upgrade command to the upgrade handler.

[0161] Example 4: An integrated circuit according to any of the preceding examples, wherein, in response to the expiration of an upgrade timer, the alarm handler is configured to selectively upgrade the triggered alarm by at least one of the following: stepping along the hierarchy of increasing upgrade severity to the next upgrade timer among multiple upgrade timers; or skipping the next upgrade timer along the hierarchy of increasing upgrade severity to reach another upgrade timer among the multiple upgrade timers.

[0162] Example 5: According to any of the above examples, the integrated circuit further includes: multiple upgrade handlers, each upgrade handler is configured to implement at least one security countermeasure, wherein: the alarm handler includes multiple upgrade transmitter modules, each upgrade transmitter module is coupled to the upgrade handler in the multiple upgrade handlers; and multiple upgrade timers are coupled to the multiple upgrade transmitter modules.

[0163] Example 6: An integrated circuit according to any of the preceding examples, wherein: the alarm handler includes at least one of a switch matrix or a multiplexer set; and at least a portion of the multiple upgrade timers are selectively coupled to multiple of the multiple upgrade transmitter modules via the switch matrix or the multiplexer set.

[0164] Example 7: An integrated circuit according to any of the preceding examples, wherein, in response to expiration of an upgrade timer, the alarm handler is configured to selectively upgrade the triggered alarm by at least one of the following: instructing an upgrade transmitter module among multiple upgrade transmitter modules to transmit an upgrade command to an upgrade handler among multiple upgrade handlers, the upgrade transmitter module having an upgrade severity corresponding to the upgrade severity of the upgrade timer; or instructing another upgrade transmitter module among multiple upgrade transmitter modules to send an upgrade command to another upgrade handler among multiple upgrade handlers, the other upgrade transmitter module having an upgrade severity higher than the upgrade severity of the upgrade transmitter module.

[0165] Example 8: An integrated circuit according to any of the preceding examples, wherein: in response to receiving an upgrade command from an alarm handler, at least one of the multiple upgrade handlers is configured to implement at least one security countermeasure; and the at least one security countermeasure includes: erasing stored data; disconnecting a suspicious peripheral device among the multiple peripheral devices from at least one interconnect; crashing a power domain including the suspicious peripheral device among the multiple peripheral devices; resetting at least a portion of the integrated circuit; or converting at least a portion of the integrated circuit to an invalid life cycle state.

[0166] Example 9: An integrated circuit according to any of the preceding examples, wherein the alarm handler further comprises: a ping monitor coupled to multiple alarm receiver modules and a controller, the ping monitor being configured to: instruct multiple alarm receiver modules to transmit one or more ping requests to multiple peripheral devices; and notify the controller of an alarm ping failure.

[0167] Example 10 The integrated circuit of any preceding example, wherein the ping monitor is configured to instruct the plurality of alert receiver modules to transmit one or more ping requests to the plurality of peripheral devices based on a randomized time duration.

[0168] Example 11: An integrated circuit according to any of the preceding examples, wherein: the alarm handler further includes at least one accumulation unit coupled to the controller and at least one upgrade timer among a plurality of upgrade timers; the at least one accumulation unit is configured to accumulate a count indicating a number of alarms received from a peripheral device among a plurality of peripheral devices; and the controller is configured to upgrade the alarm based on the count and in response to the peripheral device.

[0169] Example 12: An integrated circuit according to any of the preceding examples, wherein: each of a plurality of peripheral devices includes at least one alarm transmitter module among a plurality of alarm transmitter modules; the integrated circuit further includes a plurality of signaling paths, each corresponding signaling path being coupled between a corresponding alarm receiver module among a plurality of alarm receiver modules and a corresponding alarm transmitter module among a plurality of alarm transmitter modules; and each of the plurality of signaling paths includes at least one differential path.

[0170] Example 13: An integrated circuit according to any of the preceding examples, wherein: the alarm handler further includes an integrity fault circuit system, which is coupled to the controller and multiple alarm receiver modules; and the integrity fault circuit system is configured to generate an alarm integrity fault signal in response to detecting an integrity fault in a differential path of a signaling path in multiple signaling paths.

[0171] Example 14: An integrated circuit according to any of the preceding examples, wherein the integrated circuit comprises at least one of the following: a system on chip (SoC) or a root of trust (RoT) chip.

[0172] Example 15: An alarm handling method, the method comprising: monitoring multiple peripheral devices with multiple alarm receiver modules; receiving a trigger alarm from an alarm receiver module among the multiple alarm receiver modules based on a peripheral device among the multiple peripheral devices; classifying the trigger alarm into an alarm category among multiple alarm categories based on at least one of the alarm receiver modules or the trigger alarm; and starting an upgrade timer among multiple upgrade timers based on the alarm classification, each corresponding upgrade timer corresponding to a corresponding upgrade severity among multiple upgrade severities.

[0173] Example 16: The method of Example 15, further comprising: adapting an alarm handling path based at least in part on the identity of the peripheral device, the alarm handling path proceeding through at least a portion of a plurality of escalation timers and at least one escalation transmitter module.

[0174] Example 17: The method according to Example 15 or 16 further includes: transmitting a ping request from the alarm receiver module to an alarm transmitter module of the peripheral device; and in response to failing to receive the ping request from the alarm transmitter module, triggering an alarm ping failure signal, which starts another upgrade timer among multiple upgrade timers.

[0175] Example 18: The method according to any one of Examples 15 to 17 further includes: accumulating the number of triggered alarms received from an alarm receiver module, the alarm receiver module is coupled to a peripheral device; comparing the number of triggered alarms with an alarm number threshold; and based on the comparison, instructing the upgrade transmitter module to transmit an upgrade command to an upgrade handler among a plurality of upgrade handlers.

[0176] Example 19: An integrated circuit comprising: a plurality of upgrade handlers, each upgrade handler being configured to implement at least one security countermeasure; and an alarm handler, the alarm handler comprising: a plurality of upgrade transmitter modules, each upgrade transmitter module being coupled to an upgrade handler among the plurality of upgrade handlers; a plurality of upgrade timers, each respective upgrade timer corresponding to a respective upgrade severity among a plurality of upgrade severities, each upgrade timer being coupled to at least one upgrade transmitter module among the plurality of upgrade transmitter modules; and a controller, the controller being coupled to the plurality of upgrade timers, the controller being configured to start an upgrade timer among the plurality of upgrade timers in response to triggering an alarm, the alarm handler being configured to selectively: start another upgrade timer among the plurality of upgrade timers in response to expiration of the started upgrade timer and based on the triggering alarm; or transmit an upgrade instruction from an upgrade transmitter module among the plurality of upgrade transmitter modules to an upgrade handler among the plurality of upgrade handlers.

[0177] Example 20: The integrated circuit of Example 19, wherein: the alarm handler includes at least one register coupled to the controller; and the selection between starting the other escalation timer or transmitting the escalation command is programmable by software using the at least one register.

[0178] Unless the context dictates otherwise, the use of the word "or" herein may be considered as use of "includes or" or as allowing inclusion or application of a term that includes one or more items connected by the word "or" (e.g., the phrase "A or B" may be interpreted as allowing only "A", only "B", or both "A" and "B"). Similarly, as used herein, a phrase referring to "at least one of" a series of items refers to any combination of those items, including single members. For example, "at least one of a, b, or c" may encompass a, b, c, ab, ac, bc, and abc, as well as any combination of multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). Further, the items shown in the drawings and the terms discussed herein may indicate one or more items or terms, and thus in this written description, the singular or plural forms of the items and terms may be referenced interchangeably. Although embodiments for alarm processing have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example embodiments for alarm processing.

Claims

1. An integrated circuit, comprising: Multiple peripherals; Alarm handler, including: a plurality of alert receiver modules, each alert receiver module coupled to a peripheral device of the plurality of peripheral devices; a plurality of escalation timers, each escalation timer corresponding to a respective escalation severity of the plurality of escalation severities; a plurality of upgrade transmitter modules coupled to the plurality of upgrade timers; and a controller coupled to the plurality of alarm receiver modules and the plurality of escalation timers, the controller configured to: categorizing a triggering alarm received from an alarm receiver module of the plurality of alarm receiver modules into an alarm classification of a plurality of alarm classifications based on at least one of: the alarm receiver module and the triggering alarm; initiating an escalation timer of the plurality of escalation timers based on the alarm classification; and instructing at least one upgrade transmitter module of the plurality of upgrade transmitter modules to transmit at least one upgrade command in response to expiration of the upgrade timer; and A plurality of upgrade handlers, each upgrade handler is coupled to an upgrade transmitter module among the plurality of upgrade transmitter modules, each upgrade handler is configured to implement at least one security countermeasure, and at least one upgrade handler among the plurality of upgrade handlers is configured to implement the at least one security countermeasure in response to receiving the at least one upgrade command from at least one upgrade transmitter module among the plurality of upgrade transmitter modules.

2. The integrated circuit of claim 1 , further comprising: interconnection; as well as a processor coupled to the alarm handler via the interconnect, Wherein, the controller of the alarm handler is configured as follows: generating an interrupt based on the triggering alert; issuing the interrupt to the processor; Waiting for the upgrade timer to expire; and In response to a failure to receive a response to the interrupt from the processor, the trigger alarm is escalated to exceed the escalation timer.

3. The integrated circuit according to claim 2, wherein: The controller of the alarm handler is configured to escalate the trigger alarm to exceed the escalation timer by at least one of: issuing another interrupt to the processor, the another interrupt corresponding to an interrupt level higher than the interrupt level of the interrupt; Starting another escalation timer among the plurality of escalation timers, the another escalation timer corresponding to an escalation severity among the plurality of escalation severities higher than the escalation severity of the escalation timer; as well as The at least one upgrade transmitter module is instructed to transmit the at least one upgrade command to the at least one upgrade handler.

4. The integrated circuit according to claim 1, wherein: In response to expiration of the escalation timer, the alarm handler is configured to selectively escalate the triggering alarm by at least one of: stepping along a hierarchy of increasing escalation severity to a next escalation timer of the plurality of escalation timers; as well as The next escalation timer is skipped along the hierarchy of increasing escalation severity to another escalation timer of the plurality of escalation timers.

5. The integrated circuit according to claim 1, wherein: The alarm handler further comprises: a ping monitor coupled to the plurality of alarm receiver modules and the controller, the ping monitor being configured to: instructing the plurality of alert receiver modules to transmit one or more ping requests to the plurality of peripheral devices; and The controller is notified of alarm ping failures.

6. The integrated circuit according to claim 5, wherein: The ping monitor is configured to instruct the plurality of alert receiver modules to transmit the one or more ping requests to the plurality of peripheral devices based on a randomized time duration.

7. The integrated circuit of claim 1, wherein: The alarm handler further includes at least one accumulation unit coupled to the controller and at least one escalation timer of the plurality of escalation timers; The at least one accumulation unit is configured to accumulate a count indicating a number of alarms received from a peripheral device among the plurality of peripheral devices; as well as The controller is configured to escalate the alarm based on the count and in response to the peripheral device.

8. The integrated circuit of claim 1, wherein: Each peripheral device of the plurality of peripheral devices includes at least one alarm transmitter module of a plurality of alarm transmitter modules; The integrated circuit further includes a plurality of signaling pathways, each signaling pathway coupled between a corresponding alarm receiver module of the plurality of alarm receiver modules and a corresponding alarm transmitter module of the plurality of alarm transmitter modules; as well as Each signaling path of the plurality of signaling paths includes at least one differential path.

9. The integrated circuit of claim 8, wherein: The alarm handler further includes integrity fault circuitry coupled to the controller and the plurality of alarm receiver modules; as well as The integrity fault circuitry is configured to generate an alarm integrity fault signal in response to detecting an integrity fault of a differential path of a signaling path of the plurality of signaling paths.

10. The integrated circuit of claim 1, wherein: The integrated circuit comprises at least one of the following: System on Chip SoC; and Root of Trust RoT chip.

11. The integrated circuit of claim 1 , wherein: at least one upgrade transmitter module of the plurality of upgrade transmitter modules is configured to transmit the at least one upgrade command from the alarm handler, and The upgrade receiver module of the at least one upgrade handler is configured to receive the at least one upgrade command from the at least one upgrade transmitter module.

12. The integrated circuit of claim 1, wherein: The alarm handler includes at least one of: a switch matrix and a set of multiplexers; and At least a portion of the plurality of upgrade timers are selectively coupled to a plurality of the plurality of upgrade transmitter modules via the switch matrix or the set of multiplexers.

13. The integrated circuit of claim 1, wherein: In response to expiration of the escalation timer, the alarm handler is configured to selectively escalate the triggering alarm by at least one of: instructing an upgrade transmitter module of the plurality of upgrade transmitter modules to transmit an upgrade command to an upgrade handler of the plurality of upgrade handlers, the upgrade transmitter module having an upgrade severity corresponding to the upgrade severity of the upgrade timer; as well as Another upgrade transmitter module among the plurality of upgrade transmitter modules is instructed to transmit an upgrade command to another upgrade handler among the plurality of upgrade handlers, the another upgrade transmitter module having an upgrade severity higher than that of the upgrade transmitter module.

14. The integrated circuit of claim 1, wherein: The at least one security countermeasure comprises: Erasing stored data; disconnecting a suspected peripheral device among the plurality of peripheral devices from at least one interconnect; crashing a power domain including the suspected peripheral device among the plurality of peripheral devices; resetting at least a portion of the integrated circuit; and At least a portion of the integrated circuit is transitioned to an invalid life cycle state.

15. A method for handling an alarm, the method comprising: monitoring multiple peripheral devices using multiple alarm receiver modules; receiving a triggered alert from an alert receiver module among the plurality of alert receiver modules based on a peripheral device among the plurality of peripheral devices; classifying the triggering alarm into an alarm classification of a plurality of alarm classifications based on at least one of the alarm receiver module and the triggering alarm; starting an escalation timer of a plurality of escalation timers based on the alarm classification, each escalation timer corresponding to a respective escalation severity of a plurality of escalation severities; instructing at least one upgrade transmitter module of a plurality of upgrade transmitter modules to transmit at least one upgrade command in response to expiration of the upgrade timer; receiving, by at least one upgrade handler among a plurality of upgrade handlers, the at least one upgrade command from the at least one upgrade transmitter module among the plurality of upgrade transmitter modules; as well as At least one security countermeasure is implemented by the at least one upgrade handler of the plurality of upgrade handlers in response to receiving the at least one upgrade command from the at least one upgrade transmitter module of the plurality of upgrade transmitter modules.

Images