Semiconductor module and semiconductor device

Abstract

A technique is provided that enables the configuration of a driven component with a short wiring distance for the power supply terminals of a semiconductor element mounted in a semiconductor module. In the semiconductor module (1), a plurality of first connection terminal groups (81) with connection terminals (8) arranged at a first interval (G1) and a second connection terminal group (82) surrounding them and arranged in a rectangular ring with connection terminals (8) at a second interval (G2) are configured to have a second set of intervals (G12) wider than the first interval (G1) and the second interval (G2). The first power supply terminal (26) of the first semiconductor element (2) and a target terminal group (81A) within the first connection terminal group (81) overlap in plan view, and the connection terminal (8) in the target terminal group (81A) that supplies power to the first semiconductor element (2) is connected to the first power supply terminal (26). The second power supply terminal (36) of the second semiconductor element (3) and the second connection terminal group (82) overlap in plan view, and the connection terminal (8) in the second connection terminal group (82) that supplies power to the second semiconductor element (3) is connected to the second power supply terminal (36).

Description

Technical Field

[0001] The present invention relates to a semiconductor module having a surface having a plurality of connection terminals facing a main substrate and mounted thereon, and to a semiconductor device having the semiconductor module mounted on the main substrate. Background Technology

[0002] Semiconductor modules that mount processors (collectively known as "System-on-a-Chip" or "System-in-a-Package") on a module substrate, and semiconductor modules that mount processors and peripheral components such as memory on a module substrate, are called "multi-chip modules" and have been put into practical use. As shown in International Publication No. 2017 / 038905, SoCs, SiPs, and other processors typically include connectors called Ball Grid Arrays (BGAs). Furthermore, synchronous dynamic random access memory (SDRAM) is often used in the memory that works with the processor, but high-capacity SDRAMs include BGA-type connectors. Moreover, such multi-chip modules that include processors and memory typically also have BGA-type connectors as connection terminals.

[0003] As disclosed in the aforementioned international publication, semiconductor components such as processors and memory are mounted on one side of the module substrate of the multi-chip module, and connection terminals are formed on the other side. The multi-chip module is mounted with the side having the connection terminals facing the substrate of the product (hereinafter referred to as the "main substrate"). Within the connection terminals of the semiconductor components such as processors and memory, the connection terminals connected to the main substrate are connected to the connection terminals of the multi-chip module via through-holes formed in the module substrate, and are connected to the main substrate via the connection terminals of the multi-chip module.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2017 / 038905 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] Furthermore, in semiconductor devices with BGA-type connectors, power terminals are typically distributed in multiple locations to uniformly supply power to the cells within the package. Also, driven components such as bypass capacitors are usually placed near the power terminals of the semiconductor device to reduce noise. However, in the case of a planar extended BGA connector, if a bypass capacitor is placed relative to the semiconductor device along the substrate surface of the module substrate, the wiring distance may increase, thus limiting the noise reduction effect. Here, considering a direction orthogonal to the substrate surface, for example, consider mounting a bypass capacitor on a main substrate on which a multi-chip module is mounted. That is, consider the case where a bypass capacitor is mounted on a surface opposite to one side (mounting surface) of the main substrate on which the multi-chip module is mounted. However, in the case of a BGA-type connector for the multi-chip module, in order to lead wiring from the connector, when viewed from a direction orthogonal to the substrate surface, a through-hole is typically formed in the main substrate at a position corresponding to the connector of the multi-chip module, and an opening for the through-hole is also formed on the surface opposite to the mounting surface. Therefore, it is usually difficult to ensure the location of the bypass capacitor on the side opposite to the mounting surface of the main substrate.

[0009] In view of the above background, it is desirable to provide a technology that enables the configuration of slave components with short wiring distances for the power supply terminals of semiconductor elements mounted in a semiconductor module.

[0010] Problem-solving methods

[0011] In view of the above-described semiconductor module, as one embodiment, a first semiconductor element and a second semiconductor element are mounted on a first surface of a rectangular module substrate, and a plurality of connection terminals are disposed on a second surface opposite to the first surface. The semiconductor module is mounted on the main substrate with the second surface facing the main substrate. Among the plurality of connection terminals disposed on the second surface, there are a plurality of regularly arranged connection terminal groups. The plurality of connection terminal groups include: a plurality of first connection terminal groups, in which adjacent connection terminals are arranged in a grid pattern with a first interval; and a second connection terminal group, arranged to surround the plurality of first connection terminal groups, in which adjacent connection terminals are arranged in a rectangular ring pattern with a second interval. The adjacent connection terminals between different first connection terminal groups are configured with a first set of intervals having more than the first interval and the second interval. The adjacent connection terminals between the first connection terminal group and the second connection terminal group are configured with a second set of intervals having a wider than the first interval and the second interval. In a top view viewed from a direction orthogonal to the module substrate, the power supply terminal of the first semiconductor element, i.e., the first power terminal, overlaps with one of the plurality of first connection terminal groups, i.e., the target terminal group. The connection terminal in the target terminal group that supplies power to the first semiconductor element is connected to the first power terminal. In the same top view, the power supply terminal of the second semiconductor element, i.e., the second power terminal, overlaps with the second connection terminal group. The connection terminal in the second connection terminal group that supplies power to the second semiconductor element is connected to the second power terminal.

[0012] According to this structure, in the target terminal group, the connection terminal supplying power to the first semiconductor element and the first power supply terminal can be connected with a short wiring distance along a direction orthogonal to the module substrate. Similarly, in the second connection terminal group, the connection terminal supplying power to the second semiconductor element and the second power supply terminal can also be connected with a short wiring distance along a direction orthogonal to the module substrate. Here, a second set of intervals is provided between the target terminal group (first connection terminal group) and the second connection terminal group. Therefore, as explained below, using this gap, components can be mounted on the main substrate near the first and second power supply terminals. For example, on the main substrate, there is a case where a through-hole is formed between the mounting surface on which the semiconductor module is mounted and the surface opposite to it, electrically connecting the opposite surface to the connection terminal. Therefore, on the opposite surface, there is a case where an opening of the through-hole is formed according to the arrangement of the connection terminals. On the surface opposite to the mounting surface, a component cannot be mounted at a position overlapping with such an opening in plan view. However, since there are no connection terminals in the area corresponding to the second set of intervals, such an opening is not formed. Therefore, on the side of the main substrate opposite to the mounting surface, a component can be mounted in an area that corresponds to the gap of the second set of intervals when viewed from above. That is, according to this structure, the driven component can be arranged with a short wiring distance for the power supply terminals of the semiconductor element mounted on the semiconductor module.

[0013] Preferably, the first semiconductor element is a processor, and the second semiconductor element is a memory. In other words, the semiconductor module mounts the processor and memory on a first side of a rectangular module substrate, and a plurality of connection terminals are disposed on a second side opposite to the first side. The semiconductor module is mounted on the main substrate with the second side facing the main substrate. The plurality of connection terminals disposed on the second side include a plurality of regularly arranged connection terminal groups. The plurality of connection terminal groups include: a plurality of first connection terminal groups, in which adjacent connection terminals are arranged in a grid pattern with a first interval; and a second connection terminal group, arranged to surround the plurality of first connection terminal groups, in which adjacent connection terminals are arranged in a rectangular ring pattern with a second interval. The adjacent connection terminals between different first connection terminal groups are configured with a first set of intervals having more than the first interval and the second interval, and the adjacent connection terminals between the first connection terminal group and the second connection terminal group are configured with a second set of intervals wider than the first interval and the second interval. In a top view viewed from a direction orthogonal to the module substrate, the power supply terminal of the processor, i.e., the first power supply terminal, overlaps with one of the plurality of first connection terminal groups, i.e., the target terminal group, and the connection terminal in the target terminal group that supplies power to the processor is connected to the first power supply terminal. In the same top view, the power supply terminal of the memory, i.e., the second power supply terminal, overlaps with the second connection terminal group, and the connection terminal in the second connection terminal group that supplies power to the memory is connected to the second power supply terminal.

[0014] In many cases, the processor and memory work together, resulting in a large number of signal lines connecting only the processor and memory. Therefore, this typically allows a semiconductor module containing both a processor and memory to have fewer connection terminals than the total number of connection terminals for the processor and memory. Consequently, mounting the semiconductor module on the main substrate improves wiring and installation efficiency compared to mounting the processor and memory on the main substrate. Processors consume a large amount of current and typically have numerous power supply terminals. Furthermore, since the bare die constituting the processor is positioned in the center of the package, the power supply terminals are usually located in the center, for example, in the case of a BGA connection for the processor. Additionally, in memory applications that are moving towards higher capacity, power supply terminals are typically distributed to distribute power evenly among the memory cells. When the driven component is connected to the power supply terminals of the processor and memory, the wiring distance becomes longer, potentially limiting the effectiveness of the driven component. However, according to this structure, as described above, the driven component can be mounted in an area corresponding to a second set of intervals when viewed from above on the side of the main substrate opposite to the mounting surface. That is, it is possible to connect the driven component to the power terminals of the processor and the power terminals of the memory with a short wiring distance along a direction orthogonal to the module substrate and the main substrate.

[0015] Further features and advantages of the semiconductor module and the semiconductor device in which the semiconductor module is mounted are made clear in the following description of embodiments illustrated with reference to the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a schematic exploded perspective view of a semiconductor device.

[0017] Figure 2 This is a component configuration diagram of a semiconductor module.

[0018] Figure 3 This is a perspective top view showing an example of the connection terminals of a semiconductor module.

[0019] Figure 4 This is a perspective top view showing an example of the connection terminals of an SDRAM.

[0020] Figure 5 This is a perspective top view showing an example of the connection terminals of the system LSI.

[0021] Figure 6 This is a perspective top view illustrating an example of the relationship between the connection terminal group of a semiconductor module and the connection terminals of a semiconductor element.

[0022] Figure 7 This is a schematic cross-sectional view of a semiconductor device.

[0023] Figure 8This is a circuit block diagram illustrating an example of the relationship between SDRAM and bypass capacitors.

[0024] Figure 9 This is a circuit block diagram illustrating an example of the relationship between SDRAM and an LC filter.

[0025] Figure 10 This is a perspective top view showing other examples of connection terminals of a semiconductor module.

[0026] Figure 11 This is a perspective top view showing other examples of connection terminals of a semiconductor module.

[0027] Figure 12 This is a perspective top view showing other examples of connection terminals of a semiconductor module. Detailed Implementation

[0028] The following describes embodiments of the semiconductor module and semiconductor device based on the accompanying drawings. Figure 1 As shown in the schematic exploded perspective view, the semiconductor device 10 is configured to have a semiconductor module 1 and a main substrate 5. At least the semiconductor module 1 is mounted on a first surface (first surface 5a) of the main substrate 5. The semiconductor module 1 has a system LSI 2 (processor, first semiconductor element) and a memory 3 (second semiconductor element) mounted on a first surface (first surface 4a) of a rectangular module substrate 4. A plurality of connection terminals 8 (see reference numerals) are provided on a second surface 4b of the module substrate, opposite to the first surface 4a. Figure 3 , Figure 7 (etc.), and mount the semiconductor module 1 onto the main substrate 5 with the second side 4b of the module substrate facing the first side 5a of the main substrate 5.

[0029] Memory 3 is a memory that works in conjunction with system LSI2. In this embodiment, semiconductor module 1 also includes a portion of a power supply circuit (power supply IC 6 described later) for supplying power to memory 3. Figure 2 As shown in the component configuration diagram, at least the System on a Chip (SoC) as the system LSI2, two SDRAMs (Synchronous Dynamic Random Access Memory) as the memory 3, and a power IC 6 (PIC) as part of the power supply circuit are mounted on the module substrate 4. The system LSI2 (first semiconductor element) has a larger external shape than the memory 3 (second semiconductor element), and its area in top view is larger than that of the memory 3. In this embodiment, the system LSI2 (first semiconductor element) has a square shape, and the memory 3 (second semiconductor element) has a rectangular shape.

[0030] As described above, a System-on-a-Chip (SoC) is shown here as a System LSI2. However, the System LSI2 can also be a System-in-a-Package (SiP). Furthermore, SoCs also include Application-Specific Integrated Circuits (ASICs) with semi-custom LSIs and Application-Specific Standard Processors (ASSPs) with general-purpose LSIs. Additionally, ASICs are not limited to gate arrays or cell-based ICs (standard cells), but also include Programmable Logic Devices (PLDs) such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Arrays (PLAs).

[0031] Furthermore, SDRAM is preferably, for example, DDR3 (Double Data Rate 3) SDRAM, DDR4 (Double Data Rate 4) SDRAM, etc. Here, SDRAM is shown as memory 3, but other memory structures such as flash memory and static random access memory (SRAM) are not excluded. As described above, memory 3 cooperates with system LSI2. Therefore, the signal terminals (address terminals, data terminals, control terminals, etc.) of memory 3 are only connected to system LSI2 on module substrate 4. In addition, in this embodiment, the power for driving memory 3 is generated by a power supply circuit with power IC 6 mounted on module substrate 4 as its core. It should be noted that the driving power for input / output sections (input / output pads of terminals) connected to memory 3 in system LSI2 is also supplied through this power IC 6.

[0032] As described above, connection terminals 8 for connection to the main substrate 5 are regularly arranged on the second surface 4b (the facing surface opposite to the first surface 5a of the main substrate) of the semiconductor module 1. In this embodiment, a ball grid array (BGA) type semiconductor module 1 with hemispherical connection terminals 8 regularly arranged is exemplified. Figure 3 This is a perspective top view of the second side 4b of the module substrate, viewed from the first side 4a of the module substrate along the Z direction orthogonal to the module substrate 4, showing the semiconductor module 1 mounted on the main substrate 5. Figure 3In the diagram, solid lines represent the multiple connection terminals 8 disposed on the second surface 4b of the module substrate, while dashed lines represent the outlines of the system LSI 2 and the two memory modules 3 disposed within the components on the first surface 4a of the module substrate. Additionally, the outline of the bypass capacitor 7 (described in detail below), which serves as a driven component connected to the power supply terminals of the memory modules 3, disposed within the components on the second surface 5b of the main substrate opposite to the first surface 5a of the main substrate, is also represented by dashed lines.

[0033] like Figure 3 As shown, the plurality of connection terminals 8 disposed on the second surface 4b of the module substrate include a plurality of regularly arranged connection terminal groups 80. In this embodiment, the plurality of connection terminal groups 80 include a plurality of first connection terminal groups 81, a second connection terminal group 82, and a third connection terminal group 83. Four first connection terminal groups 81 are arranged such that they surround the center of gravity Q1 of the outline of the module substrate 4 when viewed in the Z direction. In each first connection terminal group 81, adjacent connection terminals 8 are arranged in a grid pattern with a first interval G1. Regardless of the thickness of the connection terminals 8, in each first terminal group, adjacent connection terminals 8 can be arranged in a grid pattern with a first pitch P1 (first repetition period). The second connection terminal group 82 is arranged to surround the plurality of first connection terminal groups 81, and adjacent connection terminals 8 are arranged in a rectangular ring pattern with a second interval G2. Similarly, the second connection terminal group 82 can be arranged to surround the plurality of first connection terminal groups 81, and adjacent connection terminals 8 can be arranged in a rectangular ring pattern with a second pitch P2 (second repetition period). The third connection terminal group 83 is configured to surround the second connection terminal group 82, and the adjacent connection terminals 8 are arranged in a rectangular ring with a third interval G3. Similarly, the third connection terminal group 83 can be configured to surround the second connection terminal group 82, and the adjacent connection terminals 8 are arranged in a rectangular ring with a third pitch P3 (third repetition period).

[0034] Adjacent connection terminals 8 between different first connection terminal groups 81 are configured with a first set of intervals G11 wider than the first interval G1 and the second interval G2. That is, multiple first connection terminal groups 81 are configured with a first set of intervals G11 in a direction along the substrate surface of the module substrate 4 and orthogonal to the sides of the rectangular module substrate 4. Furthermore, adjacent connection terminals 8 between the first connection terminal group 81 and the second connection terminal group 82 are configured with a second set of intervals G12 wider than the first interval G1 and the second interval G2. That is, the first connection terminal group 81 and the second connection terminal group 82 are configured with a second set of intervals G12 in a direction along the substrate surface of the module substrate 4 and orthogonal to the sides of the rectangular module substrate 4. Additionally, adjacent connection terminals 8 between the second connection terminal group 82 and the third connection terminal group 83 are configured with a third set of intervals G13 wider than the first interval G1, the second interval G2, and the third interval G3. That is, the second connection terminal group 82 and the third connection terminal group 83 are arranged in a direction along the substrate surface of the module substrate 4 and orthogonal to the side of the rectangular module substrate 4, having a third set of spacing G13.

[0035] Here, the first interval G1 (first pitch P1), the second interval G2 (second pitch P2), and the third interval G3 (third pitch P3) can be the same value or different values. In this embodiment, "first pitch P1 = second pitch P2 = third pitch P3" because the thickness of the connecting terminals 8 is all the same, thus "first interval G1 = second interval G2 = third interval G3". Here, the first pitch P1 (= P2, = P3) is, for example, 1 mm.

[0036] Furthermore, the first group interval G11, the second group interval G12, and the third group interval G13 can have the same value or different values. In this embodiment, the second group interval G12 and the third group interval G13 have the same value, and the first group interval G11 is larger than the second group interval G12 and the third group interval G13. The first group interval G11 is set to allow three connecting terminals 8 to be arranged at a first pitch P1 (=P2,=P3) between the first connecting terminal groups 81. The second group interval G12 and the third group interval G13 are set to allow two connecting terminals to be arranged at a first pitch P1 (=P2,=P3) between their respective adjacent terminal groups. When the first pitch P1 (=P2,=P3) is 1 [mm], the first group interval G11 is 2 [mm] or more and 4 [mm] or less (approximately 3 [mm] when the thickness of the connecting terminal 8 is set to less than 0.5 [mm]). In addition, the second group spacing G12 and the third group spacing G13 are 1 mm or more and 3 mm or less (approximately 2 mm when the thickness of the connecting terminal 8 is set to less than 0.5 mm).

[0037] like Figure 3 As shown, taking the center of gravity Q1 of the module substrate 4's shape when viewed from the Z direction as a reference point for rotational symmetry, multiple first connection terminal groups 81 are arranged in a fourfold symmetrical positional relationship. Similarly, second connection terminal groups 82 are also arranged in a fourfold symmetrical positional relationship with the center of gravity Q1 as a reference point for rotational symmetry. Likewise, third connection terminal groups 83 are also arranged in a fourfold symmetrical positional relationship with the center of gravity Q1 as a reference point for rotational symmetry. That is, all terminals of the multiple connection terminals 8 are arranged in a fourfold symmetrical positional relationship with the center of gravity Q1 as a reference point for rotational symmetry. Therefore, when the semiconductor module 1 is mounted on the main substrate 5, stress is applied to the connection terminals 8 approximately evenly. This ensures resistance to external forces (vibration, shock, etc.) on the semiconductor device 10, thereby improving the reliability of the semiconductor device 10.

[0038] Figure 4 A perspective top view (viewed from the Z direction) of the memory 3 mounted on the module substrate 4, taken from the first surface 4a side of the module substrate along the Z direction orthogonal to the module substrate 4, shows the arrangement of the connection terminals (memory terminals 38) of the memory 3. The memory 3 has four memory terminal groups 30 arranged in a 5×10 grid pattern. Similar to the first connection terminal group 81 of the semiconductor module 1, the four memory terminal groups 30 are configured in a 2×2 grid pattern and arranged in a fourfold symmetrical positional relationship with the center of gravity Q3 of the memory 3's shape as the reference point for rotational symmetry. A spacing is provided between each memory terminal group 30 to accommodate two memory terminals 38. The pitch (repetition period) of the memory terminals 38 is, for example, 0.65 mm.

[0039] exist Figure 4In the diagram, memory terminals 38 other than those in white are power-related terminals, and different shades are used to indicate terminals with different functions. Here, the memory terminals 38 of a DDR4 SDRAM are shown. The first memory power terminal 31, shaded by a diagonal line, supplies power (rated 1.2V in the case of DDR4) to drive the core of memory 3. The second memory power terminal 32, shaded by a vertical line, supplies power (rated 1.2V in the case of DDR4) to drive the input / output of memory 3. The third memory power terminal 33, shaded by a grid pattern, supplies power for writing data within memory 3 (power for supplying word line voltage: rated 2.5V in the case of DDR4). The memory ground terminal 39, indicated by black, is the memory terminal 38 connected to ground. The memory signal terminals 37, indicated by white, are memory terminals 38 for data signals, address signals, and control signals. Unused terminals may also be included in the memory signal terminals 37. Here, three types of terminals are shown as power terminals for memory 3, but these are collectively referred to as "memory power terminal 36 (second power terminal)".

[0040] Figure 5 A perspective top view (viewed from the Z direction) of the system LSI2 mounted on the module substrate 4, taken from the first surface 4a side of the module substrate along a direction Z orthogonal to the module substrate 4, shows the arrangement of the connection terminals (processor terminals 28) of the system LSI2 facing the first surface 4a of the module substrate. The processor terminals 28 also have multiple processor terminal groups 20. The processor terminals 28 have a central portion (the center of gravity Q2 of the system LSI2's shape, as shown in the reference section). Figure 2 , Figure 3 The processor terminals 28 are arranged in a grid pattern near the central terminal group 21 and a ring-shaped terminal group 22 arranged in a rectangular ring around the central terminal group 21. The pitch (repetition cycle) of the processor terminals 28 is, for example, 1 mm.

[0041] exist Figure 5 Only the properties of the processor terminal 28 of the central terminal group 21 are shown. Figure 5In the diagram, processor terminals 28, indicated by shading and blackening, are power-related terminals. The processor terminals 28, also indicated by shading, are processor power terminals 26 (first power terminals) supplying power to drive the system LSI2. In most cases, multiple power supplies are provided to the system LSI2, but this is not distinguished here. All processor power terminals 26 can be processor terminals 28 that input the same power, or they can be multiple types of processor terminals 28 that supply different power. The processor terminals 28 indicated by blackening are processor ground terminals 29 connected to ground. The ring-shaped terminal group 22 includes processor signal terminals 27 for signal input / output. Of course, the ring-shaped terminal group 22 may also include processor power terminals 26.

[0042] Figure 6 This is a perspective top view (viewed from the Z direction) of the semiconductor module 1, taken from the first surface 4a of the module substrate along the Z direction orthogonal to the module substrate 4, showing the opposing surfaces of the system LSI 2 and memory 3 facing the first surface 4a of the module substrate. To clarify the positional relationship between the system LSI 2 and memory 3 and the module substrate 4, the outline of the module substrate 4 is shown, and the distribution area of ​​the connection terminal group 80 on the second surface 4b of the module substrate is indicated by virtual lines. Additionally, Figure 7 A schematic cross-sectional view of the semiconductor device 10 is shown.

[0043] like Figure 3 and Figure 6 As shown, when viewed from the Z direction, the power supply terminal of the system LSI2, namely the processor power supply terminal 26 (first power supply terminal), overlaps with one of the multiple first connection terminal groups 81, namely the first object terminal group 81A (object terminal group). Furthermore, as... Figure 7 As shown, in the first object terminal group 81A, the connection terminal 8 that supplies power to the system LSI2 is connected to the processor power terminal 26. The processor power terminal 26 is connected to the pad L on the first surface 4a of the module substrate, and the pad L and the connection terminal 8 (belonging to the connection terminal 8 of the first object terminal group 81A) on the second surface 4b of the module substrate are connected via the through hole TH (TH5).

[0044] like Figure 3 and Figure 6As shown, when viewed from the Z direction, the power supply terminals of memory 3, namely memory power supply terminal 36 (second power supply terminal), overlap with the second connection terminal group 82. As described above, the memory power supply terminal 36 has three types: first memory power supply terminal 31, second memory power supply terminal 32, and third memory power supply terminal 33, and preferably at least the first memory power supply terminal 31 overlaps with the second connection terminal group 82. More preferably, the first memory power supply terminal 31, the second memory power supply terminal 32, and the second connection terminal group 82 overlap. Of course, all types of first memory power supply terminals 31, second memory power supply terminals 32, and third memory power supply terminals 33 may overlap with the second connection terminal group 82.

[0045] And, as Figure 7 As shown, in the second connection terminal group 82, the connection terminal 8 supplying power to the memory 3 and the memory power terminal 36 are connected. The memory power terminal 36 is connected to the pad L on the first surface 4a of the module substrate. The pad L and the connection terminal 8 (belonging to the connection terminal 8 of the second connection terminal group 82) on the second surface 4b of the module substrate are connected via a through-hole TH (H3). The connection terminal 8 is connected to the pad L formed on the first surface 5a of the main substrate, and is connected to the memory power side pad L76 formed on the second surface 5b of the main substrate via a through-hole TH (TH1) connecting the first surface 5a and the second surface 5b of the main substrate. A ground pad L79 is also formed on the second surface 5b of the main substrate, and a bypass capacitor 7 is installed between the memory power side pad L76 and the ground pad L79. The bypass capacitor 7 is a capacitor used to reduce high-frequency noise, for example, a ceramic capacitor of about 0.01 [μF] to 0.1 [μF].

[0046] Figure 8 The schematic circuit block diagram illustrates an example of the relationship between the memory 3 and the bypass capacitor 7. As described above, power is supplied from the power IC 6 mounted on the module substrate 4 to the memory power terminal 36 of the memory 3. As described above, the memory power terminal 36 is connected to the memory power side pad L76 of the main substrate 5, and a bypass capacitor 7 is connected between it and the ground pad L79 of the main substrate 5. The ground of the module substrate 4 (semiconductor module 1) and the ground of the main substrate 5 are electrically connected, and the ground (reference potential) of the circuits in the semiconductor module 1 and the circuits in the main substrate 5 is common. Therefore, by using vias TH and providing wiring connecting the memory power terminal 36 and the second surface 5b of the main substrate along the Z direction, the bypass capacitor 7 can be placed near the memory power terminal 36.

[0047] like Figure 4As shown, the memory power terminals 36 are distributed along the direction of the first surface 4a of the module substrate. Among the memory power terminals 36, there are also terminals located near the center of the memory 3's outline (center of gravity Q3) when viewed from the Z direction. Therefore, for example, if the bypass capacitor 7 is disposed on the first surface 4a of the module substrate, there is a possibility that the distance between the memory power terminals 36 and the bypass capacitor 7 will increase. However, as... Figure 3 , Figure 7 As shown, if a bypass capacitor 7 is disposed in the Z direction (the direction orthogonal to the substrate surface of the module substrate 4 (vertical direction)) of the memory power supply terminal 36, then it will be similar to the bypass capacitor 7 disposed in the direction along the substrate surface of the module substrate 4 (horizontal direction: for example...). Figure 7 Compared to the case where the bypass capacitor 7 is configured in the X direction, the wiring distance between the memory power supply terminal 36 and the bypass capacitor 7 can be shortened.

[0048] Reference Figure 8 As described above, since the grounding of the module substrate 4 (semiconductor module 1) and the grounding of the main substrate 5 are common, the memory ground terminal 39 may not be connected to the ground pad L79 on the second side 5b of the main substrate. However, since in the memory 3, the memory power terminal 36 and the memory ground terminal 39 are paired power-associated memory terminals 38, as... Figure 7 As shown, the memory ground terminal 39 and the ground pad L79 can also be connected via through holes TH (TH2, TH4).

[0049] In the above, also refer to Figure 7 This illustrates an embodiment where, when viewed from the Z direction, the power supply terminal of memory 3, namely memory power supply terminal 36 (second power supply terminal), and the second connection terminal group 82 overlap. However, as... Figure 3 and Figure 6 As shown, more preferably, when viewed from the Z direction, the memory power supply terminal 36 (second power supply terminal) and at least one first connection terminal group 81 (second object terminal group 81B) within the plurality of first connection terminal groups 81 that is different from the first object terminal group 81A further overlap. (Image omitted) Figure 7 Such a schematic cross-sectional view is exemplified, but in the second object terminal group 81B, the connection terminal 8 supplying power to the memory 3 and the memory power supply terminal 36 are connected. Similarly, like... Figure 7 An example of such a sectional view, but as Figure 3 and Figure 6 As shown, preferably, when viewed from the Z direction, the memory power terminal 36 and the third connection terminal group 83 overlap, and the connection terminal 8 in the third connection terminal group 83 that supplies power to the memory 3 is connected to the memory power terminal 36.

[0050] As mentioned above, bypass capacitor 7 is mostly a ceramic capacitor. In surface-mount ceramic capacitors (chip ceramic capacitors), standard mass-produced types include the 2125 (2mm × 1.25mm), 1608 (1.6mm × 0.8mm), and 1005 (1mm × 0.5mm). Among chip ceramic capacitors with capacitances around 0.01μF to 0.1μF, the 1608 and 1005 types are the mainstream (in terms of size), and mass production has reduced costs.

[0051] like Figure 3 As shown, when viewed from the Z direction, the bypass capacitor 7 is installed between the connection terminal groups 80. Therefore, the distance between the connection terminal groups 80 (terminal group spacing) is preferably greater than or equal to the size required to mount a chip ceramic capacitor. Figure 3 As shown, when viewed from the Z direction, the bypass capacitor 7 is disposed between the first connection terminal group 81 and the second connection terminal group 82, and between the second connection terminal group 82 and the third connection terminal group 83. Therefore, the second group spacing G12 and the third group spacing G13 are preferably set to a size or larger that allows the bypass capacitor 7 to be installed.

[0052] As described above, the second group spacing G12 and the third group spacing G13 are 1 mm or more and 3 mm or less (approximately 2 mm when the thickness of the connecting terminal 8 is less than 0.5 mm). Therefore, it is possible to appropriately arrange the 1608 type and 1005 type chip ceramic capacitors between the first connecting terminal group 81 and the second connecting terminal group 82, and between the second connecting terminal group 82 and the third connecting terminal group 83.

[0053] In the BGA-type semiconductor module 1, wiring W can be led out from the connection terminal 8 located on the outer periphery side on the first surface 5a of the main substrate (see reference). Figure 7 However, it is difficult to route wiring W on the first surface 5a of the main substrate near the center of gravity Q1. Therefore, when viewed from the Z direction, a through-hole TH is formed from the position overlapping with the connection terminal 8 (corresponding to the position of the pad L on the first surface 5a of the main substrate where the connection terminal 8 is connected, or the vicinity (up to the adjacent connection terminal 8 (pad L)) to the second surface 5b of the main substrate. That is, on the second surface 5b of the main substrate, within the arrangement range of the connection terminals 8 of the semiconductor module 1, the opening of the through-hole TH is arranged in the same manner as the connection terminals 8.

[0054] Since components cannot be mounted on the through-hole TH, the bypass capacitor 7 cannot be mounted on the second surface 5b of the main substrate if the connecting terminal 8 is arranged across the entire surface, or if the second group spacing G12 and the third group spacing G13 are less than 1 mm. As shown in this embodiment, by setting the second group spacing G12 and the third group spacing G13 to a size or larger that allows the bypass capacitor 7 (chip ceramic capacitor) to be mounted, the bypass capacitor 7 can be properly mounted on the second surface 5b of the main substrate.

[0055] like Figures 1-3 , Figure 6 As shown, in this embodiment, the center of gravity Q1 of the module substrate 4 and the center of gravity Q2 of the system LSI2 do not overlap when viewed from the Z direction, and the system LSI2 is positioned near one corner of the module substrate 4. Furthermore, the two memories 3 are positioned longitudinally and laterally along the L-shaped region of the module substrate 4 where the system LSI2 is not located, respectively. Here, one corner of the four corners of the module substrate 4 when viewed from the Z direction is designated as the target corner TE, and the other three corners are designated as asymmetrical corners NE. Additionally, the side that passes through the target corner TE when viewed from the Z direction is designated as the target side TS, and the side that does not pass through the target corner TE is designated as the non-target side NS. The system LSI2 is positioned closer to the target corner TE than all the asymmetrical corners NE when viewed from the Z direction, and the memories 3 are positioned on the non-target side NS that does not pass through the target corner TE when viewed from the Z direction. In this embodiment, the memories 3 have a rectangular shape, and the memories 3 are positioned with their long side along the non-target side NS.

[0056] As described above, when viewed from the Z direction, the distribution range of each of the multiple first connection terminal groups 81 is rectangular, and the four first connection terminal groups 81 are arranged in a 2x2 row and 2x2 column configuration. Furthermore, the second connection terminal group 82 is configured to surround the four first connection terminal groups 81. The third connection terminal group 83, which is also configured to surround the second connection terminal group 82, surrounds the four first connection terminal groups 81. On one side of the two object edges TS (on one side of the object corner TE), the area between the first connection terminal group 81 (first object terminal group 81A) and the second connection terminal group 82, and the area between the second connection terminal group 82 and the third connection terminal group 83, overlaps with the system LSI2 when viewed from the Z direction. However, on the two non-object edges NS, the entire area between the first connection terminal group 81 (second object terminal group 81B) and the second connection terminal group 82, and the entire area between the second connection terminal group 82 and the third connection terminal group 83, do not overlap with the system LSI2 when viewed from the Z direction. Therefore, by arranging the memory 3 in a manner that these regions overlap with the memory 3 when viewed from the Z direction, a bypass capacitor 7 can be arranged in a region on the second surface 5b of the main substrate that overlaps with these regions when viewed from the Z direction. That is, in the semiconductor device 10, the bypass capacitor 7 of the memory 3 is mounted on the second surface 5b of the main substrate at a position that overlaps with the region between the second connection terminal group 82 and other connection terminal groups 80 adjacent to the second connection terminal group 82 when viewed from the Z direction.

[0057] It should be noted that because the system LSI2 is configured close to the object corner TE side, thus on the object corner TE side, such as Figure 6 As shown, the signal terminals (processor signal terminals 27) of the system LSI2 overlap with multiple second connection terminal groups 82. Furthermore, as... Figure 7 As shown, in the second connection terminal group 82, the connection terminal 8 corresponding to the processor signal terminal 27 is connected to the processor signal terminal 27.

[0058] (Other implementation methods)

[0059] Other implementation methods are described below. It should be noted that the structures of the various implementation methods described below are not limited to their individual applications, and can be combined with the structures of other implementation methods as long as no contradictions are caused.

[0060] (1) In the above, an example is given of a semiconductor module 1 having a power supply IC 6 that generates power to supply the memory 3. However, as Figure 9As shown, a power supply circuit 60 for generating power to supply to the memory 3 can also be mounted on the main substrate 5, and the power can be supplied from the main substrate 5 to the semiconductor module 1. In this case, as a driven component, it is not limited to the bypass capacitor 7 described above; a filter 7f, such as an LC filter, can also be mounted on the second surface 5b of the main substrate, and the filter 7f and the memory power supply terminal 36 are connected via a connection terminal 8 and a through-hole TH on the main substrate 5. Figure 9 The LC filter shown is also mass-produced as a chip LC filter with the same shape as a chip ceramic capacitor. Therefore, as described above, the filter 7f can be mounted on the second surface 5b of the main substrate. Furthermore, the filter 7f is not limited to... Figure 9 The LC filter shown can also be replaced by an RC filter with a resistor instead of an inductor. This type of RC filter is also mass-produced as a chip RC filter with the same shape as a chip ceramic capacitor. Of course, as... Figure 9 As shown, in the case where the power supply circuit 60 for generating power to supply the memory 3 is mounted on the main substrate 5, a bypass capacitor 7 may also be mounted on the second surface 5b of the main substrate.

[0061] (2) In the above description, the connection of the bypass capacitor 7 to the memory 3 was given as an example, but the bypass capacitor 7, filter 7f and other driven components connected to the system LSI2 can also be mounted on the second side 5b of the main substrate in the same way.

[0062] (3) In the above description, the connection terminal 8 of the semiconductor module 1 is illustrated by having three types of connection terminal groups 80: a first connection terminal group 81, a second connection terminal group 82, and a third connection terminal group 83. However, as Figure 10 and Figure 11 As shown, the connecting terminal 8 can also be configured as having a plurality (4) of first connecting terminal groups 81 arranged in a grid pattern and a rectangular ring of second connecting terminal groups 82 surrounding the plurality of first connecting terminal groups 81. Since the first interval G1 (first pitch P1), the second interval G2 (second pitch P2), the first group interval G11, and the second group interval G12 are also in the same manner as described above, detailed descriptions are omitted. Figure 10 and Figure 11 As shown, in these configurations, when viewed from the Z-direction, the processor power terminal 26 of the system LSI2 also overlaps with the first object terminal group 81A, and the connection terminal 8 in the first object terminal group 81A that supplies power to the system LSI2 is connected to the processor power terminal 26. Additionally, when viewed from the Z-direction, the memory power terminal 36 of the memory 3 overlaps with the second connection terminal group 82, and the connection terminal 8 in the second connection terminal group 82 that supplies power to the memory 3 is connected to the memory power terminal 36.

[0063] (4) In the above description, the example was given where the first group interval G11 is wider than the first interval G1 and the second interval G2. However, the first group interval G11 can also be the same value as the first interval G1 and the second interval G2. That is, the first group interval G11 can also be an interval greater than or equal to the first interval G1 and the second interval G2. When the first group interval G11 is the same value as the first interval G1 and the second interval G2, such as... Figure 12 As shown, the first connection terminal group 81 can also be considered as a combined connection terminal group 80. However, as Figure 12 As shown, it can also be considered that there are virtually four first connection terminal groups 81. That is, in the case of... Figure 12 In the illustrated configuration, as described above, four first connection terminal groups 81 are also included, and first object terminal group 81A and second object terminal group 81B can be configured therein. Therefore, even as... Figure 12 The terminal configuration shown can also achieve the various methods described above. It should be noted that... Figure 12 The example shown is a configuration with a third connection terminal group 83, but it can also be configured with only a first connection terminal group 81 and a second connection terminal group 82.

[0064] (5) In the above description, a semiconductor module 1 having a system LSI2 (first semiconductor element) and a memory 3 (second semiconductor element) as semiconductor elements was used as an example. However, the semiconductor module 1 may also be configured to have, for example, multiple system LSI2s (processors). In the case where the semiconductor module 1 has multiple system LSI2s, it is preferable that, in top view, the shape of the first semiconductor element is larger than the shape of the second semiconductor element.

[0065] (6) In the above description, the example provided is that both the system LSI2 and the memory 3 have BGA-type connection terminals (28, 38). However, the system LSI2 and the memory 3 can also be quad flat J-leaded packages (QFJ) or small outline J-leaded packages (SOJ) that protrude outward from around the IC body and bend inward from below, with the contact portion located at the lower part of the IC body (the surface facing the first surface 4a of the module substrate). Alternatively, the system LSI2 and the memory 3 can also be small outline L-leaded packages (SOP) or quad flat gull-wing leaded packages (QFP) that have L-shaped connection terminals that protrude laterally towards the IC body rather than towards the lower part of the IC body.

[0066] (Summary of the implementation method)

[0067] The following is a brief overview of the semiconductor module (1) and semiconductor device (10) described above.

[0068] In one implementation, the semiconductor module (1) mounts a first semiconductor element (2) and a second semiconductor element (3) on a first surface (4a) of a rectangular module substrate (4), and a plurality of connection terminals (8) are disposed on a second surface (4b) opposite to the first surface (4a). The semiconductor module (1) is mounted on the main substrate (5) with the second surface (4b) facing the main substrate (5). Among the plurality of connection terminals (8) disposed on the second surface (4b), there are a plurality of regularly arranged connection terminal groups (80). The plurality of connection terminal groups (80) include: a plurality of first connection terminal groups (81), in which adjacent connection terminals (80) are arranged in a grid pattern with a first interval (G1); and a second connection terminal group (82), which is arranged to surround the plurality of first connection terminal groups (81), in which adjacent connection terminals (8) are arranged in a rectangular ring pattern with a second interval (G2). The adjacent connection terminals (8) between different first connection terminal groups (81) are configured with a first set of intervals (G11) having more than the first interval (G1) and the second interval (G2). The adjacent connection terminals (8) between the first connection terminal group (81) and the second connection terminal group (82) are configured with a second set of intervals (G12) having a wider than the first interval (G1) and the second interval (G2). In a top view viewed from a direction orthogonal to the module substrate (4), the power supply terminal of the first semiconductor element (2), namely the first power supply terminal (26) and... One of the plurality of first connection terminal groups (81), namely object terminal group (81A), overlaps, and the connection terminal (8) supplying power to the first semiconductor element (2) in the object terminal group (81A) is connected to the first power terminal (26). In the top view, the power terminal of the second semiconductor element (3), namely the second power terminal (36), overlaps with the second connection terminal group (82), and the connection terminal (8) supplying power to the second semiconductor element (3) in the second connection terminal group (82) is connected to the second power terminal (36).

[0069] According to this structure, in the target terminal group (81A), the connection terminal (8) that supplies power to the first semiconductor element (2) and the first power supply terminal (26) can be connected with a short wiring distance along a direction (Z) orthogonal to the module substrate (4). Additionally, in the second connection terminal group (82), the connection terminal (8) that supplies power to the second semiconductor element (3) and the second power supply terminal (36) can also be connected with a short wiring distance along a direction (Z) orthogonal to the module substrate (4). Here, a second set of intervals (G12) is provided between the target terminal group (81A) (the first connection terminal group (81)) and the second connection terminal group (82). Therefore, as explained below, using this gap, components can be mounted on the main substrate (5) near the first power supply terminal (26) and the second power supply terminal (36). For example, on the main substrate (5), there is a case where a through-hole (TH) is formed between the mounting surface (5a) on which the semiconductor module (1) is mounted and the opposite surface (5b) that electrically connects the opposite surface (5b) to the connection terminal (8). Therefore, on the opposite surface (5b), there is a case where an opening of the through-hole (TH) is formed according to the configuration of the connection terminal (8). On the opposite surface (5b) of the mounting surface (5a), it is not possible to mount a component in a position that overlaps with such an opening when viewed from above. However, since there is no connection terminal (8) in the area corresponding to the gap of the second set of intervals (G12), such an opening is not formed. Therefore, on the side (5b) of the main substrate (5) opposite to the mounting surface (5a), it is possible to mount a component in an area corresponding to the gap of the second set of intervals (G12) when viewed from above. That is, according to this structure, the driven parts (7, 7f) can be configured with a short wiring distance for the power supply terminals (26, 36) of the semiconductor elements (2, 3) mounted on the semiconductor module (1).

[0070] Preferably, the first semiconductor element (2) is a processor (2) and the second semiconductor element (3) is a memory (3). In other words, the semiconductor module (1) mounts the processor (2) and the memory (3) on a first surface (4a) of a rectangular module substrate (4), and sets a plurality of connection terminals (8) on a second surface (4b) opposite to the first surface (4a). The semiconductor module (1) is mounted on the main substrate (5) with the second surface (4b) facing the main substrate (5). Among the plurality of connection terminals (8) set on the second surface (4b), there are a plurality of regularly arranged connection terminal groups (80). The plurality of connection terminal groups (80) include: a first connection terminal group (81), in which adjacent connection terminals (80) are arranged in a grid pattern with a first interval (G1); and a second connection terminal group (82), arranged to surround the plurality of first connection terminal groups (81), in which adjacent connection terminals (8) are arranged in a rectangular ring pattern with a second interval (G2). Adjacent connection terminals (8) between different first connection terminal groups (81) are configured with a first set of intervals (G11) greater than the first interval (G1) and the second interval (G2), and adjacent connection terminals (8) between the first connection terminal group (81) and the second connection terminal group (82) are configured with a second set of intervals (G12) wider than the first interval (G1) and the second interval (G2). Viewed from above in a direction orthogonal to the module substrate (4), the power supply terminal of the processor (2) is the first power supply terminal. (26) overlaps with one of the first connection terminal groups (81), namely the object terminal group (81A), and the connection terminal (8) in the object terminal group (81A) that supplies power to the processor (2) is connected to the first power terminal (26). In the top view, the power terminal of the memory (3), namely the second power terminal (36), overlaps with the second connection terminal group (82), and the connection terminal (8) in the second connection terminal group (82) that supplies power to the memory (3) is connected to the second power terminal (36).

[0071] The processor (2) and memory (3) often work together, and there are many signal lines connecting only the processor (2) and memory (3). Therefore, this usually allows the semiconductor module (1) with the processor (2) and memory (3) to have fewer connection terminals (8) than the total number of connection terminals (28) of the processor (2) and connection terminals (38) of the memory (3). Therefore, the wiring efficiency and mounting efficiency are improved when the semiconductor module (1) is mounted on the main substrate (5) compared to when the processor (2) and memory (3) are mounted on the main substrate (5). The processor (2) consumes a lot of current and usually has a large number of power supply terminals (26). In addition, the bare die constituting the processor (2) is located in the center of the package, so, for example, when the connection terminal (28) of the processor (2) is a BGA, the power supply terminals (26) are usually located in the center. In addition, in memory (3) which is developing towards larger capacity, in order to supply power evenly to the memory cells inside the memory (3), the power supply terminals (36) are usually distributed. When the driven component (7) is connected to the power supply terminal (26) of the processor (2) and the power supply terminal (36) of the memory (3), the wiring distance becomes longer, which may limit the effect of the driven component (7). However, according to this structure, as described above, the driven component (7) can be installed on the side (5b) of the main substrate (5) opposite to the mounting surface (5a) in a region that corresponds to the gap of the second set of intervals (G12) when viewed from above. That is, the driven components (7, 7f) can be connected to the power supply terminal (26) of the processor (2) and the power supply terminal (36) of the memory (3) with a short wiring distance along a direction orthogonal to the module substrate (4) and the main substrate (5).

[0072] Preferably, the object terminal group (81A) is designated as the first object terminal group (81A), and at least one terminal in the plurality of first connection terminal groups (81) that is different from the first object terminal group (81A) is designated as the second object terminal group (81B). In the top view, the second power terminal (36) and the second object terminal group (82) overlap, and the connection terminal (8) in the second object terminal group (81B) that supplies power to the memory (3) is connected to the second power terminal (36).

[0073] A connection terminal (8) is formed between the first connection terminal group (81) and the second connection terminal group (82) without extending across the second set of intervals (G12). As described above, the power terminal (36) of the memory (3) overlaps with the second connection terminal group (82) in plan view. Moreover, when the power terminal (36) of the memory (3) overlaps with one of the first connection terminals (81), namely the second object terminal group (81B), in plan view, the power terminal (8) of the memory (3) is located on both sides of the area that overlaps with the gap of the second set of intervals (G12) in plan view. Therefore, the driven members (7, 7f) can be efficiently arranged in the area that overlaps with the gap of the second set of intervals (G12) in plan view.

[0074] In addition, preferably, the second power terminals (36) are distributed in a direction along the first surface (4a) of the module substrate (4), a portion of the second power terminals (36) is connected to the second connection terminal group (82), and the other portion of the second power terminals (36) is connected to the second object terminal group (81B).

[0075] According to this structure, since a portion and other parts of the second power terminal (36) are arranged in the area where the second set of intervals (G12) where the connecting terminal (8) is not formed, the driven parts (7, 7f) can be appropriately arranged in the area overlapping the gap of the second set of intervals (G12).

[0076] Additionally, preferably, the plurality of connection terminals (8) include: a third connection terminal group (83) configured to surround the second connection terminal group (82), wherein adjacent connection terminals (8) in the third connection terminal group (83) are arranged in a rectangular ring with a third interval (G3), and adjacent connection terminals (80) between the second connection terminal group (82) and the third connection terminal group (83) are configured to have a third interval (G13) wider than the first interval (G1), the second interval (G2) and the third interval (G3), wherein, in the top view, the second power terminal (36) and the third connection terminal group (83) overlap, and the connection terminal (8) in the third connection terminal group (83) that supplies power to the memory (3) is connected to the second power terminal (36).

[0077] According to this structure, by having a third connection terminal group (83), the semiconductor module (1) can be provided with a large number of connection terminals (8). Moreover, since a third set of intervals (G13) is provided between the second connection terminal group (82) and the third connection terminal group (83), even if the number of connection terminals (8) increases, an area is provided for mounting driven parts (7f) that are connected to the power supply terminals (26) of the processor (2) and the power supply terminals (36) of the memory (3).

[0078] Furthermore, in the case where the plurality of connection terminals (8) include a third connection terminal group (83) arranged in a rectangular ring around the second connection terminal group (82) and adjacent connection terminals (8) are arranged at a third interval (G3), it is preferable that the second power terminal (36) is distributed in a direction along the first surface (4a) of the module substrate (4), a portion of the second power terminal (36) is connected to the second connection terminal group (82), and the other portion of the second power terminal (36) is connected to the third connection terminal group (83).

[0079] According to this structure, since a portion of the second power terminal (36) and other portions are arranged to sandwich a region where a third set of intervals (G13) without a connecting terminal (8) is formed, the driven parts (7, 7f) can be appropriately arranged in the region that overlaps with the gap of the third set of intervals (G13).

[0080] Additionally, preferably, the second set of intervals (G12) is set to a size greater than or equal to that of at least one of the bypass capacitor (7) and filter (7f) of the memory (3), and in the case where the plurality of connection terminals (8) include the third connection terminal group (83), and the connection terminals (80) adjacent to the second connection terminal group (82) and the third connection terminal group (83) are configured to have the third set of intervals (G13), the third set of intervals (G13) is also set to a size greater than or equal to that of at least one of the bypass capacitor (7) and filter (7f) of the memory (3).

[0081] According to this structure, at least one of the driven elements of the bypass capacitor (7) and the filter (7f) can be appropriately installed in the region of the main substrate (5) that overlaps with the region between the first connection terminal group (81) and the second connection terminal group (82) and the region between the second connection terminal group (82) and the third connection terminal group (83) when viewed from above.

[0082] Preferably, in the top view, the signal terminal (27) of the processor (2) and the second connection terminal group (82) overlap, and the connection terminal (8) in the second connection terminal group (82) corresponding to the signal terminal (27) of the processor (2) is connected to the signal terminal (8).

[0083] For example, when the connection terminal (28) of the processor (2) is of the BGA type, considering the lead-out of signal wiring, the signal terminal (28) is usually arranged on the periphery side, which is closer to the center. As described above, the processor (2) is arranged on the module substrate (4) in such a way that the power terminal (26) overlaps with the target terminal group (81A) (the first connection terminal group (81)) in a top view. Moreover, when the signal terminal (27) of the processor (2) overlaps with the second connection terminal group (82) in a top view, the processor (2) is arranged on the module substrate (4) in such a way that the center of gravity (Q1) of the shape of the module substrate (4) in a top view does not overlap with the center of gravity (Q2) of the shape of the processor (2) in a top view. Therefore, it is possible to properly ensure the position of other semiconductor elements such as the memory (3) to form the semiconductor module (1).

[0084] In addition, preferably, in the top view, the center of gravity (Q1) of the shape of the module substrate (4) is used as the reference point for rotational symmetry, and the plurality of first connection terminal groups (81) and second connection terminal groups (82) are arranged in a four-fold symmetrical positional relationship.

[0085] Since the connection terminals (8) of the semiconductor module (1) can be flexibly configured according to the user's specifications, the area for mounting the driven components (7, 7f) can be set, for example, by appropriately reducing the number of connection terminals (8). However, since the area of ​​the semiconductor module (1), which has multiple semiconductor elements such as the processor (2) and memory (3), is relatively large, if the connection terminals (8) are reduced, the stress difference along the substrate surface of the module substrate (4) will increase when the semiconductor module (1) is mounted on the main substrate (5), resulting in a decrease in mechanical strength. According to this structure, when the multiple first connection terminal groups (81) and the second connection terminal groups (82) have a second set of intervals (G12) and are arranged in a four-fold symmetrical positional relationship, the mechanical strength when mounting the semiconductor module (1) can be maintained, and the area for mounting the driven components (7, 7f) can be ensured.

[0086] In addition, preferably, in the top view, one of the four corners of the module substrate (4) is designated as the target corner (TE), and the other three corners are designated as asymmetric corners (NE). In the top view, the processor (2) is positioned closer to the target corner (TE) than all of the asymmetric corners (NE). In the top view, the memory (3) is positioned on one side that does not pass through the edge (NS) of the target corner (TE). In the top view, the distribution range of each of the plurality of first connection terminal groups (81) is rectangular, the four first connection terminal groups (81) are arranged in a 2-row, 2-column configuration, and the second connection terminal group (82) is arranged surrounding the four first connection terminal groups (81).

[0087] According to this structure, the processor (2) is positioned near one corner (object corner (TE)) of the module substrate (4). Furthermore, one or more memories (3) can be positioned along either the longitudinal or transverse direction, or each direction, of the L-shaped region in the module substrate (4) where the processor (2) is not positioned. That is, the processor (2) and memories (3) can be efficiently mounted on the module substrate (4), and in top view, the first power terminal (26) and the first object terminal group (81A) of the processor (2) overlap, and in top view, the second power terminal (36) and the second terminal group (82) of the memory (3) overlap.

[0088] As one embodiment, a semiconductor device (10) is mounted on one side of the main substrate (5), namely the first surface (5a) of the main substrate, wherein the main substrate (5) has a through hole (TH) connecting the second surface (5b) of the main substrate (5a) to the opposite side of the first surface (5a) of the main substrate (5a) at a position overlapping with the connection terminal (8) connecting the second power terminal (36) in the top view. On the second surface (5b) of the main substrate, at a position overlapping with the area between the second connection terminal group (82) and other connection terminal groups (81, 83) adjacent to the second connection terminal group (82) in the top view, at least one of the bypass capacitor (7) and filter (7f) of the memory (3) is mounted.

[0089] According to this structure, as described above, a driven member (7) can be installed on the side (5b) of the main substrate (5) opposite to the mounting surface (5a), in a region corresponding to the gap of the second set of intervals (G12) when viewed from above. That is, the driven member (7) can be connected to the power supply terminal (26) of the processor (2) and the power supply terminal (36) of the memory (3) with a short wiring distance along a direction orthogonal to the module substrate (4) and the main substrate (5).

[0090] Explanation of reference numerals in the attached figures:

[0091] 1: Semiconductor Module

[0092] 2: System LSI (Processor, First Semiconductor Component)

[0093] 3: Memory (Second Semiconductor Component)

[0094] 4: Module baseboard

[0095] 4a: First surface of the module substrate (first surface of the module substrate)

[0096] 4b: Second side of the module substrate (second side of the module substrate)

[0097] 5: Main base board

[0098] 5a: First surface of the main substrate

[0099] 5b: Second side of the main substrate

[0100] 7: Bypass capacitor

[0101] 7f: Filter

[0102] 8: Connecting terminals

[0103] 10: Semiconductor devices

[0104] 26: Processor power terminals (processor power terminals, first power terminals)

[0105] 27: Processor signal terminals (processor signal terminals)

[0106] 31: First power supply terminal of the memory (power supply terminal of the memory, second power supply terminal)

[0107] 32: Second memory power supply terminal (power supply terminal of memory, second power supply terminal)

[0108] 33: Third memory power supply terminal (memory power supply terminal, second power supply terminal)

[0109] 36: Memory power supply terminals (memory power supply terminals, second power supply terminals)

[0110] 37: Memory signal terminal

[0111] 39: Grounding terminal

[0112] 80: Connecting terminal block

[0113] 81: First connection terminal group

[0114] 81A: First object terminal group (object terminal group)

[0115] 81B: Second object terminal group

[0116] 82: Second connection terminal group

[0117] 83: Third connection terminal group

[0118] G1: First Interval

[0119] G2: Second Interval

[0120] G3: Third Interval

[0121] G11: First interval

[0122] G12: Second interval

[0123] G13: Third Interval

[0124] NE: Asymmetrical corner

[0125] NS: Non-object edge (edge ​​that does not pass through the corner of the object)

[0126] Q1: Center of gravity (the center of gravity of the module substrate when viewed from above)

[0127] TE: Object corner

[0128] TH: Through hole

[0129] Z: Direction orthogonal to the module substrate

Claims

1. A semiconductor module, comprising mounting a first semiconductor element and a second semiconductor element on a first surface of a rectangular module substrate, disposing of a plurality of connection terminals on a second surface opposite to the first surface, and mounting the semiconductor module on the main substrate with the second surface facing the main substrate, wherein, The plurality of connection terminals disposed on the second surface include a plurality of connection terminal groups arranged in a regular manner. The plurality of said connection terminal groups include: Multiple first connection terminal groups, wherein adjacent connection terminals in the first connection terminal groups are arranged in a grid pattern with a first interval; The second connection terminal group is configured to surround a plurality of the first connection terminal groups, and in the second connection terminal group, adjacent connection terminals are arranged in a rectangular ring with a second interval. The adjacent connection terminals between different first connection terminal groups are configured to have a first group of intervals, the first group of intervals being an interval greater than or equal to the first interval and the second interval. The adjacent connection terminals between the first connection terminal group and the second connection terminal group are configured to have a second set of spacing that is wider than the first spacing and the second spacing. Viewed from a top angle orthogonal to the module substrate, the power supply terminal of the first semiconductor element, i.e., the first power terminal, overlaps with one of the plurality of first connection terminal groups, i.e., the target terminal group, and the connection terminal in the target terminal group that supplies power to the first semiconductor element is connected to the first power supply terminal. In the top view, the power supply terminal of the second semiconductor element, i.e., the second power supply terminal, overlaps with the second connection terminal group, and the connection terminal in the second connection terminal group that supplies power to the second semiconductor element is connected to the second power supply terminal.

2. The semiconductor module as described in claim 1, wherein, The first semiconductor element is a processor, and the second semiconductor element is a memory.

3. A semiconductor module, comprising mounting a processor and a memory on a first side of a rectangular module substrate, and disposing of a plurality of connection terminals on a second side opposite to the first side, wherein the semiconductor module is mounted on the main substrate with the second side facing the main substrate, wherein... The plurality of connection terminals disposed on the second surface include a plurality of connection terminal groups arranged in a regular manner. The plurality of said connection terminal groups include: Multiple first connection terminal groups, wherein adjacent connection terminals in the first connection terminal groups are arranged in a grid pattern with a first interval; The second connection terminal group is configured to surround a plurality of the first connection terminal groups, and in the second connection terminal group, adjacent connection terminals are arranged in a rectangular ring with a second interval. The adjacent connection terminals between different first connection terminal groups are configured to have a first group of intervals, wherein the first group of intervals is an interval greater than or equal to the first interval and the second interval. The adjacent connection terminals between the first connection terminal group and the second connection terminal group are configured to have a second set of spacing that is wider than the first spacing and the second spacing. Viewed from a top angle orthogonal to the module substrate, the processor's power supply terminal, i.e., the first power supply terminal, overlaps with one of the plurality of first connection terminal groups, i.e., the target terminal group, and the connection terminal in the target terminal group that supplies power to the processor is connected to the first power supply terminal. In the top view, the power supply terminals of the memory, namely the second power supply terminals and the second connection terminal group, overlap, and the connection terminals in the second connection terminal group that supply power to the memory are connected to the second power supply terminals.

4. The semiconductor module as described in claim 3, wherein, The object terminal group is designated as the first object terminal group, and at least one terminal group within the plurality of first connection terminal groups that is different from the first object terminal group is designated as the second object terminal group. In the top view, the second power terminal and the second object terminal group overlap, and the connection terminal in the second object terminal group that supplies power to the memory is connected to the second power terminal.

5. The semiconductor module as claimed in claim 4, wherein, The second power terminals are distributed in a direction along the first surface of the module substrate. A portion of the second power terminal is connected to the second connection terminal group. The other parts within the second power terminal are connected to the second object terminal group.

6. The semiconductor module as claimed in claim 4 or 5, wherein, The second set of intervals is set to a size greater than or equal to that of at least one of the bypass capacitors and filters that can be installed in the memory.

7. The semiconductor module as claimed in any one of claims 3 to 5, wherein, The plurality of connection terminals include: a third connection terminal group, configured to surround the second connection terminal group, wherein adjacent connection terminals in the third connection terminal group are arranged in a rectangular ring with a third interval. The adjacent connection terminals between the second connection terminal group and the third connection terminal group are configured to have a third set of spacing that is wider than the first spacing, the second spacing, and the third spacing. In the top view, the second power terminal and the third connection terminal group overlap, and the connection terminal in the third connection terminal group that supplies power to the memory is connected to the second power terminal.

8. The semiconductor module as claimed in claim 7, wherein, The second power terminals are distributed in a direction along the first surface of the module substrate. A portion of the second power terminal is connected to the second connection terminal group. The other parts within the second power terminal are connected to the third connection terminal group.

9. The semiconductor module as claimed in claim 7, wherein, The third set of intervals is set to a size greater than or equal to that of at least one of the bypass capacitor and filter that can be installed in the memory.

10. The semiconductor module of claim 8, wherein, The third set of intervals is set to a size greater than or equal to that of at least one of the bypass capacitor and filter that can be installed in the memory.

11. The semiconductor module as described in any one of claims 3 to 5, 8 to 10, wherein, In the top view, the signal terminals of the processor and the second connection terminal group overlap, and the connection terminals in the second connection terminal group corresponding to the signal terminals of the processor are connected to the signal terminals.

12. The semiconductor module as described in any one of claims 3 to 5, 8 to 10, wherein, In the top view, taking the center of gravity of the module substrate as the reference point for rotational symmetry, the plurality of first connection terminal groups and second connection terminal groups are arranged in a four-fold symmetrical positional relationship.

13. The semiconductor module as described in any one of claims 3 to 5, 8 to 10, wherein, In the top view, one of the four corners of the module substrate is designated as the object corner, and the other three corners are designated as asymmetrical corners. From this top-down view, the processor is positioned closer to the corner of the object than all of the asymmetrical corners. In the top view, the memory is positioned on one side that does not pass through the corner of the object. From the top view, each of the plurality of first connection terminal groups has a rectangular distribution area, and the four first connection terminal groups are arranged in a 2-row, 2-column configuration. The second connection terminal group is arranged to surround four of the first connection terminal groups.

14. A semiconductor device, wherein the semiconductor module according to any one of claims 3 to 13 is mounted on one side of the main substrate, i.e., a first side of the main substrate, wherein, The main substrate, in the top view, overlaps with the connection terminal connected to the second power terminal, and has a through hole connecting the second side of the main substrate (opposite to the first side) and the first side of the main substrate. On the second side of the main substrate, at a location overlapping the area between the second connection terminal group and other connection terminal groups adjacent to the second connection terminal group in the top view, at least one of the bypass capacitor and filter of the memory is mounted.

Images