Decoding device, decoding method, control circuit and storage medium

Abstract

The invention comprises: a hard decision decoding unit (10) for performing hard decision decoding of a polar code using an input signal to generate a first decoding result, and performing a first error detection process on the first decoding result to generate a first error detection result; a soft decision decoding unit (11) for performing successive decoding of a polar code on the input signal to generate a second decoding result obtained in each decoding in the successive decoding, and performing a second error detection process on a result obtained by updating the first decoding result using the second decoding result to generate a second error detection result; a data selection unit (13) for selecting and outputting the first decoding result or a result obtained by updating the first decoding result using the second decoding result; and a control unit (12) for stopping the soft decision decoding unit (11) when the data selection unit (13) outputs a final decoding result.

Description

Technical Field

[0001] The present invention relates to a decoding device, a decoding method, a control circuit and a storage medium for decoding a polarization-coded signal. Background Art

[0002] When performing communications, error correction techniques are usually applied to deal with errors caused by noise generated in the communication path. Polar codes, which are one form of error correction codes, can achieve characteristics that are asymptotic to the Shannon limit based on the idea of ​​polarization of the communication path (see the following non-patent document 1). In addition, polar codes can suppress the amount of computation required for encoding and decoding. Polar codes are block codes that perform polarization encoding on the blocks by repeatedly performing XOR operations and combinatorial changes on the bits in the blocks.

[0003] When decoding a polarization-coded signal, a successive elimination decoding method is generally used to determine bits one by one. In the successive elimination decoding method, if the code length becomes longer, the decoding process takes time. Patent document 1 discloses a technique in which a range to which successive decoding is applied is divided into a plurality of blocks, successive decoding is performed on the divided blocks, thereby obtaining a plurality of results, and further post-processing using exclusive OR or the like is applied to the plurality of results. In the technique described in patent document 1, the divided blocks can be successively decoded in parallel, and therefore the processing time required for the decoding process can be suppressed.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 6075812

[0007] Non-patent literature

[0008] Non-patent document 1: E. Arikan, "Channel Polarization: A Method for ConstructingCapacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," IEEE Transactions on Information Theory, vol.55, no.7, pp.3051-3073, Jul.2009. Summary of the invention

[0009] Problems to be solved by the invention

[0010] However, according to the technology described in the above-mentioned patent document 1, although the processing time required for the decoding process can be reduced by segmentation, the fundamental decoding method is still sequential decoding, so the total amount of decoding process calculations is still large. If the total amount of calculations is large, power consumption will increase due to constant processing, or power consumption will increase due to the use of a circuit with high processing power.

[0011] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to obtain a decoding device capable of suppressing the total amount of decoding process calculations.

[0012] Means for solving problems

[0013] In order to solve the above-mentioned problems and achieve the purpose, the decoding device of the present invention has a hard decision decoding unit, which uses an input signal to perform hard decision decoding of a polar code, thereby generating a first decoding result, and performs a first error detection process on the first decoding result, thereby generating a first error detection result. In addition, the decoding device has a soft decision decoding unit, which performs sequential decoding of a polar code on an input signal, thereby generating a second decoding result obtained in each decoding in the sequential decoding, and performs a second error detection process on a result obtained by updating the first decoding result using the second decoding result, thereby generating a second error detection result. In addition, the decoding device has: a data selection unit, which selects the first decoding result or the result obtained by updating the first decoding result using the second decoding result, and outputs it as a final decoding result; and a control unit, which stops the soft decision decoding unit when the data selection unit outputs the final decoding result.

[0014] Effects of the Invention

[0015] The decoding device of the present invention has an effect of being able to suppress the total amount of decoding processing calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram showing a configuration example of a decoding circuit according to the first embodiment.

[0017] Figure 2 This is a flowchart showing an example of a processing procedure in the decoding circuit according to the first embodiment.

[0018] Figure 3 This is a diagram showing the concept of the exclusive OR operation in the first embodiment.

[0019] Figure 4 This is a diagram showing a processing circuit as dedicated hardware according to the first embodiment.

[0020] Figure 5 This is a diagram showing an example of a control circuit according to the first embodiment.

[0021] Figure 6 This is a diagram showing a configuration example of a decoding circuit according to the second embodiment.

[0022] Figure 7 This is a flowchart showing an example of a processing procedure in the decoding circuit of the second embodiment.

[0023] Figure 8 This is a diagram showing a configuration example of a decoding circuit according to the third embodiment.

[0024] Fig. 9 This is a flowchart showing an example of a processing procedure in a decoding circuit according to the third embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, a decoding device and a decoding method according to an embodiment of the present invention will be described in detail based on the drawings. In addition, the present invention is not limited to this embodiment.

[0026] Implementation Method 1

[0027] Figure 1 This is a diagram showing a configuration example of a decoding circuit according to Embodiment 1 of the present invention. Figure 1 The decoding circuit 1 shown is an example of a decoding device of the present invention. The decoding circuit 1 decodes the input signal and outputs the result obtained by decoding to a subsequent circuit not shown. In addition, as described later, the decoding circuit 1 also calculates a decoding result as an intermediate result in the process of successive decoding. The decoding result as an intermediate result and the decoding result output to the subsequent circuit are both decoding results. Hereinafter, the decoding result output to the subsequent circuit is referred to as the final decoding result. For example, the subsequent circuit is a circuit for eliminating redundant bits when the decoding circuit 1 outputs the decoding result by adding redundant bits, a decoding circuit for outer codes when a concatenated code for error correction in cooperation with polar codes is applied, and a deinterleaving circuit when interleaving is performed between outer codes and polar codes. In addition, the subsequent circuit may be a deframing circuit or the like when the decoding device 1 replaces a signal from another transceiver with another frame and transmits it by the transceiver equipped with the decoding device 1, and may be an encoding circuit or the like if the decoding circuit 1 is a repeater that is assumed to be used until error correction decoding. In addition, when the decoding circuit 1 is the final circuit in the reception process of the received signal, the subsequent circuit is a circuit that executes an application that operates using the transmitted information, etc. The subsequent circuit is not limited to the above example.

[0028] The input signal input to the decoding circuit 1 is, for example, a received signal of a polarization-encoded signal received via a communication path, a log likelihood ratio (LLR), etc. The decoding circuit 1 is, for example, mounted on a receiving device. The receiving device receives a signal polarization-encoded in the transmitting device from a transmitting device. In addition, when the input signal input to the decoding circuit 1 is an LLR, a circuit preceding the decoding circuit 1 in the receiving device obtains the LLR and inputs it to the decoding circuit 1. When the input signal is a received signal, the circuit preceding the decoding circuit 1 is an A / D (Analog to Digital) conversion circuit, etc.

[0029] like Figure 1 As shown in FIG. 1 , the decoding circuit 1 includes a hard decision decoding unit 10, a soft decision decoding unit 11, a control unit 12, and a data selection unit 13. The hard decision decoding unit 10 performs hard decision decoding of the polar code using the input signal to generate a first decoding result, and performs error detection processing on the first decoding result to generate a first error detection result. The processing performed by the hard decision decoding unit 10 is also referred to as a first processing. The soft decision decoding unit 11 performs sequential decoding of the polar code on the input signal to generate a second decoding result obtained in each decoding in the sequential decoding, updates the first decoding result using the second decoding result, and performs error detection processing on the result obtained by the update to generate a second error detection result. The processing performed by the soft decision decoding unit 11 is also referred to as a second processing. The data selection unit 13 selects the first decoding result or the result obtained by updating the first decoding result using the second decoding result, and outputs it as a final decoding result. The control unit 12 starts the soft decision decoding unit 11 according to the first error detection result, and stops the soft decision decoding unit 11 when the data selection unit 13 outputs the final decoding result. Specifically, when the data selection unit 13 outputs the final decoding result, it notifies the control unit 12 of control information indicating that the decoding result has been determined, and when the control unit 12 receives the notification, it stops the soft decision decoding unit 11.

[0030] The hard decision decoding unit 10 includes a non-sequential decoding unit 100 and a first error detection unit 101. In addition, the soft decision decoding unit 11 includes a sequential decoding unit 110, data update units 111-1 to 111-n, and second error detection units 112-1 to 112-n. n is an integer representing the number of data update units and second error detection units, and as described later, is, for example, the number of lists in list-type sequential elimination decoding. Figure 1 In the example, it is assumed that n is 3 or more, but the present invention is not limited to this example, and n only needs to be 1 or more.

[0031] Here, polarization codes are explained. Polarization codes are an error correction code method proposed by Arikan in 2008. As described in non-patent document 1, polarization codes are based on the idea of ​​polarizing the communication path and achieve characteristics that are asymptotic to the Shannon limit. The encoding of polarization codes is performed by repeatedly combining the bits in the block with XOR. In addition, when using polarization codes, generally speaking, a fixed value known between the transceiver and the transmitting and receiving devices, which is called frozen bit, is added to the information bit before encoding, and the information bit to which the fixed value is added is encoded by polarization code. Hereinafter, the fixed value called frozen bit, frozen bit, etc. is also referred to as a fixed value. The insertion position of the fixed value is determined relative to the information bit that is the encoding object. In polarization codes, the bits in one block are separated by polarization of the communication path, and the communication path capacity varies depending on the communication path. Unless otherwise specified, the following method is generally used: when calculating the communication path capacity before encoding, a fixed value is inserted from the part with a small communication path capacity. In the calculation of the communication path capacity, there is a bit that uses the result of determining the bit value of one bit in the two bits combined by XOR to calculate the communication path capacity. Therefore, the polar code is a code that assumes that the two bits combined by XOR are decoded successively.

[0032] Therefore, as a method for decoding polar codes, the following method is envisioned: using the received signal and the bits determined in the middle of decoding, using soft decision information such as occurrence probability, likelihood, and LLR, the bits are determined one by one. Representative decoding methods include Successive Cancellation Decoding (SCD), Successive Cancellation List Decoding (SCLD), and List-based Successive Cancellation Decoding (CRC aided SCLD) that uses a cyclic redundancy check (CRC) for decoding result determination. In addition, the longer the code length of the communication path capacity before encoding, the more clearly the positions with good and poor communication path capacity are separated. Therefore, the longer the code length of the polar code, the more effectively it can be used. However, when decoding the polar code, successive decoding of the bits is performed one by one. Therefore, if the code length is long, the amount of calculation in the decoding process will increase. In this embodiment, as described below, the amount of calculation is reduced on average by combining successive decoding with non-sequential decoding with hard decision.

[0033] In this embodiment, it is assumed that in the transmitting device, frozen bits are added before encoding of the polarization code, and redundant bits for error detection are added by error detection coding processing. As the method of error detection coding processing, any method can be used, and methods such as parity check code (parity check) represented by forward error correction (FEC), vertical parity check (VRC), horizontal parity check (LRC) (parity check), checksum, cyclic redundancy check, etc. can be cited. In addition, the method of error detection coding processing is not limited to the above examples, and any method can be used as long as it can detect errors.

[0034] Back to Figure 1 Description. The non-sequential decoding unit 100 of the hard decision decoding unit 10 generates a hard decision value based on the soft decision value or LLR obtained from the received signal, uses the hard decision value to perform non-sequential decoding of the polarization code, thereby performing hard decision decoding, and outputs the decoding result to the first error detection unit 101, the data selection unit 13, and the data update unit 111-1~111-n. The method for generating the hard decision value can use a common method, and any method can be used. For the circuit that performs non-sequential decoding of the polarization code, it can be a circuit shared with the polarization encoding circuit that encodes the polarization code, or it can be a dedicated circuit that decodes the polarization code.

[0035] The first error detection unit 101 uses the decoding result output from the non-sequential decoding unit 100 to perform error detection processing using redundant bits for error detection added before encoding, and outputs the result of the error detection processing to the control unit 12 and the data selection unit 13 .

[0036] The soft decision decoding unit 11 performs successive polarization decoding on the input signal input to the decoding circuit 1. The successive decoding unit 110 of the soft decision decoding unit 11 is a decoding unit that performs decoding successively using the input signal and the decoding result obtained in the decoding process of the successive decoding unit 110. The decoding method in the successive decoding unit 110 can use the successive elimination decoding method, the list type successive elimination decoding method, etc. as representative decoding methods. Among them, the successive decoding unit 110 outputs the decoding result, which is the result of successive decoding in the decoding process of the successive elimination decoding method or the list type successive elimination decoding method, to the data updating units 111-1 to 111-n at the decoding timing. In addition, the successive decoding unit 110 outputs the information for selecting the maximum likelihood candidate obtained in the decoding of the list type successive elimination decoding method to the data selection unit 13. The information indicating the maximum likelihood candidate is information indicating the likelihood of each candidate, that is, the decoding result, and a path metric or the like can be cited.

[0037] In addition, the decoding method in the successive decoding unit 110 can be any method other than the successive elimination decoding method and the list-type successive elimination decoding method as long as it is a successive decoding method. When the input signal is a received signal, the successive decoding unit 110 can generate LLR using the input signal and perform successive decoding using LLR, or can perform successive decoding using likelihood or probability using the input signal. When the input signal is LLR, the successive decoding unit 110 can perform successive decoding using LLR.

[0038] In addition, as an example, Figure 1 An example of applying the list-type successive elimination decoding method is shown. Therefore, the soft decision decoding unit 11 has data updating units 111-1 to 111-n and second error detection units 112-1 to 112-n at the subsequent stage of the successive decoding unit 110, which is the number of the maximum number of lists. When the maximum number of lists is set to L, n=L. In addition, it is also possible to have data updating units 111-1 to 111-n and second error detection units 112-1 to 112-n in parallel, which assume that the maximum number of lists is variable. In this case, for example, it is set to n>L, and it can also cope with the change of the maximum number of lists L.

[0039] exist Figure 1 As an example, the figure shows an example in which the list-type successive elimination decoding method is applied and the number of lists is 3 or more, but when the list-type successive elimination decoding method is applied and the number of lists is 1, the soft decision decoding unit 11 only needs to have a data updating unit 111-1 and a second error detection unit 112-1. When the successive elimination decoding method is applied as the decoding method of the successive decoding unit 110, the soft decision decoding unit 11 only needs to have a data updating unit 111-1 and a second error detection unit 112-1, similar to the case in which the list-type successive elimination decoding method is applied and the number of lists is 1. Therefore, Figure 1 The structure shown can be applied to both the case where the list-type successive elimination decoding method is used and the case where the successive elimination decoding method is used. Figure 1 This is a diagram including two representative successive decoding methods. When other successive decoding methods are used, the configuration of the soft decision decoding unit 11 may be set to a configuration corresponding to the successive decoding method.

[0040] The data updating units 111-1 to 111-n hold the decoding results of the non-sequential decoding unit 100 of the hard decision decoding unit 10, and update the held decoding results by overwriting the held decoding results with the decoding results input from the sequential decoding unit 110, i.e., the decoding results sequentially generated by the sequential decoding unit 110 through sequential decoding. As described later, data updating by the data updating units 111-1 to 111-n is also performed before the sequential decoding of the sequential decoding unit 110 is performed on all bits of the code length, i.e., at the stage where the sequential decoding of the sequential decoding unit 110 is performed on a portion of all bits of the code length. Therefore, after the updating, the decoding results held by the data updating units 111-1 to 111-n are based on the decoding results of the non-sequential decoding unit 100 of the hard decision decoding unit 10 as the first decoding results and the decoding results of the sequential decoding unit 110 as the second decoding results. The data updating units 111-1 to 111-n output the updated decoding results to the corresponding second error detection units 112-1 to 112-n, respectively. In addition, the data updating units 111-1 to 111-n output the updated decoding results to the data selection unit 13. In addition, although the input signals are different, the data updating units 111-1 to 111-n perform the same operation and can use the same circuit. The data updating units 111-1 to 111-n correspond to the lists in the list-type successive elimination decoding method, respectively. Therefore, although the decoding results input from the successive decoding unit 110 are different, the same operation is performed as an operation.

[0041] The second error detection units 112-1 to 112-n perform the same error detection processing as the first error detection unit 101 on the decoding results updated by the data update units 111-1 to 111-n, respectively, and output the error detection results to the data selection unit 13. The same circuit can be used as the first error detection unit 101 and the second error detection units 112-1 to 112-n.

[0042] Through the above actions, the soft decision decoding unit 11 outputs to the data selection unit 13 the decoding result for selecting the number of lists updated by the data updating units 111-1 to 111-n, the error detection result of the second error detection unit 112-1 to 112-n, and the information for selecting the maximum likelihood candidate output from the sequential decoding unit 110.

[0043] The control unit 12 controls the soft decision decoding unit 11 based on the error detection result input from the first error detection unit 101 of the hard decision decoding unit 10 and the control information to be described later input from the data selection unit 13. Specifically, when the error detection result input from the first error detection unit 101 is a result indicating that an error has occurred, the control unit 12 starts the soft decision decoding unit 11. In addition, when information indicating that the decoding result has been determined is input from the data selection unit 13 as control information, the control unit 12 stops the soft decision decoding unit 11.

[0044] The data selection unit 13 generates control information based on the information input from the hard decision decoding unit 10 and the information input from the soft decision decoding unit 11, and outputs the control information to the control unit 12. In addition, the data selection unit 13 selects a decoding result as a final decoding result based on the information input from the hard decision decoding unit 10 and the information input from the soft decision decoding unit 11, and outputs the final decoding result to a circuit (not shown) at a subsequent stage of the decoding circuit 1.

[0045] Specifically, when the error detection result input from the first error detection unit 101 indicates that there is no error, the data selection unit 13 selects the decoding result output from the non-sequential decoding unit 100 of the hard decision decoding unit 10 as the final decoding result and outputs it. When the error detection result input from the first error detection unit 101 indicates that there is no error, the soft decision decoding unit 11 does not operate and determines the final decoding result. When the error detection result input from the first error detection unit 101 indicates that there is an error, the soft decision decoding unit 11 operates. When the error detection result input from the first error detection unit 101 indicates that there is an error, the data selection unit 13 uses the information input from the soft decision decoding unit 11 to select the decoding result as the final decoding result and output the final decoding result. At this time, information is also input from the soft decision decoding unit 11 to the data selection unit 13 at a stage before all bits of the sequential decoding are completed. If the data selection unit 13 obtains a decoding result without error, even if the sequential decoding of all bits is not completed, the decoding result is determined as the final decoding result. Specifically, the data selection unit 13 selects a decoding result in which the error detection result input from the second error detection unit 112-1 to 112-n indicates no error among the decoding results input from the data update units 111-1 to 111-n. The decoding results input from the data update units 111-1 to 111-n are the decoding results of updating the decoding results of non-sequential decoding using the decoding results of sequential decoding before all bits of the list number are completed, or the decoding results of non-sequential decoding are updated using the decoding results of sequential decoding when all bits are completed. For example, when the decoding result input from the second error detection unit 112-2 indicates no error, the data selection unit 13 selects the decoding result input from the data update unit 111-2 as the final decoding result for output.

[0046] On the other hand, when all the error detection results input from the second error detection units 112-1 to 112-n indicate errors even after the successive decoding of all bits is completed, the data selection unit 13 uses the information for selecting the maximum likelihood candidate input from the successive decoding unit 110 to select the maximum likelihood decoding result from the decoding results input from the data updating units 111-1 to 111-n and output it as the final decoding result. For example, when the information for selecting the maximum likelihood candidate is a path metric, the data selection unit 13 selects the decoding result with the smallest path metric. When there are multiple results indicating no errors among the error detection results input from the second error detection units 112-1 to 112-n, the data selection unit 13 may select the maximum likelihood decoding result using the information for selecting the maximum likelihood candidate input from the successive decoding unit 110.

[0047] Next, the operation of the decoding circuit 1 according to the present embodiment will be described using a flowchart. Figure 2 1 is a flowchart showing an example of the processing procedure in the decoding circuit 1 of the present embodiment. Here, the case where the list-type successive elimination decoding method is used as the successive decoding method is described as an example. In addition, the following assumes Figure 1 The decoding circuit 1 shown in the structure performs Figure 2 The processing shown is for illustration only, but as long as it can be implemented Figure 2 The processing shown in Figure 1 The processing is implemented by a decoding circuit having a structure other than the structure shown. Figure 2 The processing process shown is an example of the processing process in the decoding circuit 1. As long as it is a processing process that can obtain the same result, the processing process in the decoding circuit 1 is not limited to Figure 2 Example shown.

[0048] First, when an input signal is input to the decoding circuit 1, the non-sequential decoding unit 100 of the hard decision decoding unit 10 performs non-sequential decoding (step S101). As described above, the non-sequential decoding unit 100 outputs the decoding result to the first error detection unit 101, and the first error detection unit 101 performs error detection processing and outputs the error detection result to the data selection unit 13 and the control unit 12. The data selection unit 13 determines whether an error is detected based on the error detection result (step S102). When no error is detected (step S102: No), the data selection unit 13 selects the decoding result input from the non-sequential decoding unit 100, that is, the decoding result of the non-sequential decoding, as the final decoding result (step S113). Then, the data selection unit 13 outputs the final decoding result. When the data selection unit 13 has determined the decoding result, that is, outputted the final decoding result, it notifies the control unit 12 of information indicating that the decoding result has been determined as control information. When receiving the notification, the control unit 12 stops the soft decision decoding unit 11.

[0049] When the error detection result input from the first error detection unit 101 indicates that an error has been detected (step S102: Yes), the sequential decoding unit 110 performs sequential decoding (step S103). Specifically, the data selection unit 13 may notify the control unit 12 of the detection of an error as control information, and the control unit 12 may receive the notification and instruct the sequential decoding unit 110 of the soft decision decoding unit 11 to start processing, or the control unit 12 may make a judgment based on the error detection result input from the first error detection unit 101 and instruct the sequential decoding unit 110 to start processing. In addition, here, an example is described in which the soft decision decoding unit 11 is operated when the error detection result of the first error detection unit 101 indicates that an error has been detected, but the hard decision decoding unit 10 and the soft decision decoding unit 11 may be operated simultaneously and processed in parallel. In this case, the processing of the hard decision decoding unit 10 ends earlier than the processing of the soft decision decoding unit 11, and therefore, when no error is detected in the error detection of the first error detection unit 101, the soft decision decoding unit 11 may be stopped.

[0050] The successive decoding unit 110 generates the decoding results of the number of lists by successive decoding, and generates the information for selecting the maximum likelihood candidate of the number of lists. The successive decoding unit 110 outputs the decoding results of the number of lists to the corresponding data updating units 111-1 to 111-n, and outputs the information for selecting the maximum likelihood candidate of the number of lists to the data selection unit 13.

[0051] The sequential decoding unit 110 determines whether the decoding is completed, that is, whether the decoding corresponding to the code length has been performed (step S104). When the decoding is completed (step S104: Yes), the sequential decoding unit 110 instructs the data updating units 111-1 to 111-n to update the decoding results, and the data updating units 111-1 to 111-n update the decoding results (step S105). Specifically, the data updating units 111-1 to 111-n use the decoding results input from the sequential decoding unit 110 to overwrite the retained decoding results, thereby updating the decoding results. The data updating units 111-1 to 111-n output the updated decoding results to the corresponding second error detection units 112-1 to 112-n, respectively. The second error detection units 112-1 to 112-n perform error detection processing on the input decoding results, and output the error detection results to the data selection unit 13.

[0052] The data selection unit 13 determines whether there is a decoding result without error in the decoding result after the decoding result of the non-sequential decoding unit 100 is updated using the decoding result of the sequential decoding unit 110 based on the error detection results input from the second error detection units 112-1 to 112-n (step S106). If there is a decoding result without error (step S106: yes), the data selection unit 13 selects a candidate without error (i.e., the error detection result among the decoding results input from the data updating units 111-1 to 111-n is determined to be a decoding result without error) as the final decoding result (step S107), and outputs the final decoding result. That is, when the successive decoding performed by the soft decision decoding unit 11 is list-type successive elimination decoding, the soft decision decoding unit 11 generates a decoding result in which the first decoding result is updated using the second decoding result of each list and a second error detection result, and the data selection unit 13 selects, based on the second error detection result, a decoding result in which the first decoding result is updated using one second decoding result from the decoding results in which the first decoding result is updated using the second decoding result of each list and outputs it.

[0053] When there is no decoding result without error (step S106: No), the data selection unit 13 selects the candidate with the maximum likelihood as the final decoding result based on the information for selecting the candidate with the maximum likelihood input from the sequential decoding unit 110 (step S108), and outputs it as the final decoding result. As described above, for example, when the information for selecting the candidate with the maximum likelihood is the path metric, the candidate with the maximum likelihood is the decoding result with the smallest path metric. That is, when there is no result indicating no error in the second error detection result, the data selection unit 13 selects the decoding result obtained by updating the first decoding result using one second decoding result from the decoding results obtained by updating the first decoding result using the second decoding result of each list based on the information indicating the likelihood, and outputs it.

[0054] If the decoding is not completed in step S104 (step S104: No), the successive decoding unit 110 determines whether the decoding has been performed x times (step S109). The processing after the judgment of whether the decoding has been performed x times is one of the characteristics of the present embodiment. x is a predetermined natural number and is an arbitrary value less than the code length. In addition, in the successive decoding of the successive decoding unit 110, when the successive decoding process is not performed in units of bits, but the successive decoding process is performed in units of symbols or the decoding process of polarization decoding a plurality of bits at a time such as non-binary polarization decoding, when the code length is N and the number of bits processed at a time is s, x can be an arbitrary value less than N / s. The successive decoding unit 110 counts the number of times the decoding is performed in the successive decoding unit 110 for each codeword, that is, each input signal. Then, when the number of decoding times in the sequential decoding unit 110 is less than x times, that is, when the decoding is not performed x times (step S109: No), the sequential decoding unit 110 performs the processing from step S103 again.

[0055] On the other hand, when the decoding has been performed x times (step S109: Yes), the sequential decoding unit 110 instructs the data updating units 111-1 to 111-n to update the decoding results, and the data updating units 111-1 to 111-n perform the updating of the non-sequential decoding results (step S110). The data updating units 111-1 to 111-n output the updated decoding results to the corresponding second error detection units 112-1 to 112-n, respectively. The second error detection units 112-1 to 112-n perform error detection processing on the input decoding results, and output the error detection results to the data selection unit 13.

[0056] The data selection unit 13 determines whether there is a decoding result without error in the decoding results of the sequential decoding unit 110 based on the error detection results input from the second error detection units 112-1 to 112-n (step S111). If there is a decoding result without error (step S111: yes), the data selection unit 13 selects a candidate without error (i.e., the error detection result among the decoding results input from the data updating units 111-1 to 111-n is determined to be a decoding result without error) as the final decoding result (step S112), and outputs the final decoding result.

[0057] When there is no error-free decoding result (step S111 : No), the sequential decoding unit 110 resets the counter indicating the number of sequential decoding times, and performs the processing from step S103 again.

[0058] Thus, in this embodiment, before the successive decoding of the amount corresponding to the code length is completed, the decoding result is updated (S110) and the determination of whether there is a decoding result without error (S111) is performed at the x-time stage of the successive decoding, and the decoding process is terminated when a decoding result without error is obtained. Thus, the amount of calculation of the decoding process can be suppressed, and the operation rate of the decoding circuit 1 can be reduced. By reducing the operation rate of the decoding circuit 1, the power consumption can be suppressed.

[0059] In addition, in the present embodiment, the soft decision decoding unit 11 counts the number of decoding times in the successive decoding, and at the stage where the counted number of times is x, the soft decision decoding unit 11 performs the second error detection process based on the second error detection units 112-1 to 112-n. However, performing x decoding times is only an example of a judgment standard, and the second error detection process can be performed at any timing as long as it is an intermediate stage before the successive decoding of an amount corresponding to the code length is completed. That is, the soft decision decoding unit 11 performs the second error detection process before performing the successive decoding of an amount corresponding to the code length, and the data selection unit 13 determines whether the second error detection result is a result indicating that there is no error. If the second error detection result is a result indicating that there is no error, the first decoding result is updated by the second decoding result corresponding to the second error detection result, and the decoding result is selected and output. Then, when the data selection unit 13 selects and outputs the decoding result after the first decoding result is updated by the second decoding result, the control unit 12 receives control information indicating that the decoding result has been determined from the data selection unit 13, thereby stopping the soft decision decoding unit 11. In this way, in the middle of the successive decoding, the soft decision decoding unit 11 can be stopped based on the second error detection result. For example, as described above, a fixed value called frozen bit is added to the information before the encoding of the polarization code. In the case where redundant bits are added to the information bits in the error detection coding process before the encoding of the polarization code, the detection result of the error detection will not change even if the fixed value is decoded. Therefore, in this case, the number of decodings corresponding to the fixed value can be omitted and the count of x times can be counted. In addition, x can be changed to a variable value instead of a fixed value according to the transmission state. It is not limited to this example, and an arbitrary reference can be set in combination with the circuit structure as an intermediate stage before the end of the successive decoding of the amount corresponding to the code length. In addition, in the case where redundant bits for error detection are added to the value obtained by combining the information bit and the fixed value, and in the case where redundant bits for error detection are added to the fixed value, it can also be applied. Figure 2 The processing process shown.

[0060] In addition, in the non-sequential decoding of step S101, decoding using hard decision values ​​is performed. Therefore, although the correction performance is lower than that of the sequential decoding of soft decisions, it can be realized by a one-to-one operation corresponding to the hard decision values, and thus can be realized by a process simpler than the sequential decoding. For example, in the case of a communication state that is so good that sequential decoding is not necessary, the decoding circuit 1 can output the final decoding result through the processes of step S101, step S102, and step S113, so the operation rate of the decoding circuit 1 can be suppressed. In addition, in the case that there is an error in the determination of step S102, the sequential decoding of soft decisions having higher correction performance than the decoding process of hard decisions is applied, thereby enabling the decoding circuit 1 to cope with an environment in which the communication state is not good.

[0061] In a conventional polar code decoding method, it is necessary to continue processing until the sequential decoding of an amount corresponding to the code length is completed, and the operation rate of the decoding circuit cannot be reduced. In this embodiment, non-sequential decoding, which has low correction performance but low processing load, is first implemented, thereby enabling decoding to be completed by simple processing when sequential decoding is not required. In addition, the data update units 111-1 to 111-n overwrite the decoding results that also include the midway results of sequential decoding to the retained decoding results, and output them to the second error detection units 112-1 to 112-n, thereby enabling error detection processing to be performed even in the middle of sequential decoding. In addition, as described above, sequential decoding is terminated when it is determined that there is no error in step S111, thereby enabling the operation rate of the decoding circuit 1 to be reduced.

[0062] In addition, the present embodiment effectively reduces the amount of computation by utilizing the characteristics of polar codes. Here, a 2-bit exclusive OR (XOR: eXclusive OR) used in a part of encoding and decoding of polar codes will be described. Figure 3 : is a diagram showing the concept of the XOR operation of the present embodiment. In the encoding of the polar code, the bits before being encoded, that is, the pre-encoded bits 41 and 44 become the input of the XOR operation circuit 42, and the encoded bits 43 and 45 are the outputs of the XOR operation. Here, for the pre-encoded bit 41, the pre-encoded bit 41 is decoded using the LLR, likelihood, probability, etc. corresponding to the positions of the encoded bits 43 and the encoded bits 45. Then, the pre-encoded bit 44 is decoded using the decoding result of the pre-encoded bit 41 and the LLR, likelihood, probability, etc. corresponding to the positions of the encoded bits 43 and the encoded bits 45. Therefore, there is a tendency that the LLR, likelihood, probability, etc. of the later side (in this example, the pre-encoded bit 44) in the decoding order is higher.

[0063] In addition, as described above, fixed values ​​called frozen bits, frozen bits, etc. are usually arranged in sequence from the position where the communication path capacity before encoding is small. The order of the fixed values ​​is different, but the trend is to be fixed in the order from early to late in the decoding process. These are different from other error correction technologies that randomly generate errors, and show the following property: the earlier the polar code is decoded, the more likely it is to generate errors. This property is a principle support for the following trend: error correction can be completed in the middle of the above-mentioned sequential decoding. This embodiment uses such properties of polar codes to suppress the amount of calculation.

[0064] In addition, when the judgment in step S104 is "yes", the processing of steps S105 to S108 is the same as that of the usual list-based successive elimination decoding method. Therefore, in essence, this embodiment does not have the same degradation related to decoding performance as the usual list-based successive elimination decoding method. In addition, when the number of lists of the list-based successive elimination decoding method is set to 1, it is equivalent to the successive elimination decoding method, so Figure 2 The processing of can also be applied to the case of using the successive elimination decoding method. In addition, when the number of lists is set to 1, it can also be omitted Figure 2 The processing of steps S105 to S108 and S112.

[0065] Next, hardware for realizing the decoding circuit 1 of the present embodiment will be described. Each unit constituting the hard decision decoding unit 10 and the soft decision decoding unit 11 of the decoding circuit 1, the control unit 12, and the data selection unit 13 can be realized by a processing circuit as dedicated hardware. Figure 4 1 is a diagram showing a processing circuit as dedicated hardware according to the present embodiment. The hard decision decoding unit 10 and the soft decision decoding unit 11, the control unit 12 and the data selection unit 13, which constitute the decoding circuit 1, are respectively configured by, for example, Figure 4 The processing circuit 5 shown is used to implement it.

[0066] The processing circuit 5 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a circuit formed by combining them. The functions of the hard decision decoding unit 10 and the soft decision decoding unit 11, the control unit 12, and the data selection unit 13 that constitute the decoding circuit 1 may be implemented by different processing circuits, or all or part of the functions of these units may be integrated and implemented by one or more processing circuits.

[0067] The processing circuit that realizes the respective units of the hard decision decoding unit 10 and the soft decision decoding unit 11 , the control unit 12 , and the data selection unit 13 that constitute the decoding circuit 1 may be a control circuit having a processor. Figure 5 FIG. 1 is a diagram showing an example of a control circuit of the present embodiment. Figure 5 As shown in FIG. 1 , the control circuit includes a processor 61 and a memory 62. The functions of the hard decision decoding unit 10 and the soft decision decoding unit 11, the control unit 12, and the data selection unit 13 that constitute the decoding circuit 1 are as follows: Figure 5 When the control circuit shown in the figure is implemented, these functions can be implemented by software, firmware, or a combination of software and firmware. Software and firmware are recorded as programs and stored in the memory 62. The processor 61 reads the program from the memory 62 and executes it, thereby realizing the functions of the hard decision decoding unit 10 and the soft decision decoding unit 11, the control unit 12, and the data selection unit 13 that constitute the decoding circuit 1. These programs can also be said to be programs that cause the computer to execute the processes and methods executed by the hard decision decoding unit 10 and the soft decision decoding unit 11, the control unit 12, and the data selection unit 13 that constitute the decoding circuit 1. The program can be provided by a recording medium or a communication medium.

[0068] Here, the memory 62 is equivalent to, for example, non-volatile or volatile semiconductor memories such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory), magnetic disks, floppy disks, optical disks, compact disks, mini disks, DVDs (Digital Versatile Disks), etc.

[0069] When the functions of the hard decision decoding unit 10 and the soft decision decoding unit 11, the control unit 12, and the data selection unit 13 that constitute the decoding circuit 1 are realized by the control circuit, the program stored in the memory 62 is a program that executes the decoding method including the following steps 1 to 4. The first step is a step of performing the following first processing: using the input signal to perform hard decision decoding of the polar code, thereby generating a first decoding result, and performing error detection processing on the first decoding result, thereby generating a first error detection result. The second step is a step of performing the following second processing: sequentially decoding the polar code on the input signal, thereby generating a second decoding result obtained in each decoding in the sequential decoding, and performing error detection processing using the decoding result after updating the first decoding result using the second decoding result, thereby generating a second error detection result. The third step is a step of selecting the first decoding result or the decoding result after updating the first decoding result using the second decoding result, and outputting it as the final decoding result. The fourth step is a step of stopping the second processing when the final decoding result is output in the third step.

[0070] In addition, the functions of the hard decision decoding unit 10 and the soft decision decoding unit 11, the control unit 12, and the data selection unit 13, which constitute the decoding circuit 1, may be partially implemented by dedicated hardware and partially implemented by software or firmware. For example, the hard decision decoding unit 10, the sequential decoding unit 110, the second error detection units 112-1 to 112-n, and the control unit 12 may be implemented by dedicated hardware. Figure 4 The processing circuit 5 as a dedicated hardware realizes its functions, and the data updating units 111-1 to 111-n and the data selecting unit 13 are controlled by Figure 5 The control circuit shown in the figure realizes its functions. Thus, the decoding circuit 1 can be realized by dedicated hardware, software, firmware or a combination thereof.

[0071] Implementation Method 2

[0072] Figure 6 FIG. 2 is a diagram showing a configuration example of a decoding circuit according to Embodiment 2 of the present invention. Figure 6 As shown in the figure, the decoding circuit 2 is an example of the decoding device of the present invention. The decoding circuit 2 decodes the input signal similarly to the decoding circuit 1 of the embodiment 1, and outputs the result obtained by decoding to the subsequent circuit not shown. In addition, in the present embodiment, the decoding result output to the subsequent circuit is also referred to as the final decoding result. Hereinafter, for the same parts as the embodiment 1, repeated descriptions are omitted, and the parts different from the embodiment 1 are mainly described.

[0073] In this embodiment, encoding of a systematic polar code is implemented, and the systematic polar code is added with redundant bits for performing error detection in the transmitting device. The systematic polar code is a polar code that can separate information bits and redundant bits based on polarization coding. As in Embodiment 1, before encoding the systematic polar code, the transmitting device adds a fixed value known between the transmitting and receiving devices, such as a frozen bit, to the information bit. The input signal input to the decoding circuit 2 can be a soft decision value of a received signal sent from the transmitting device and received by the receiving device, or it can be an LLR generated based on the received signal.

[0074] like Figure 6 As shown, the decoding circuit 2 has a hard decision decoding unit 20, a soft decision decoding unit 21, a control unit 22 and a data selection unit 23. The hard decision decoding unit 20 has a first non-sequential decoding unit 200, a replacement unit 201, a second non-sequential decoding unit 202 and a first error detection unit 203. In addition, the soft decision decoding unit 21 has a sequential decoding unit 210, data update units 211-1 to 211-n, a third non-sequential decoding unit 212-1 to 212-n and a second error detection unit 213-1 to 213-n. n is an integer representing the number of data update units, third non-sequential decoding units and second error detection units, and as described later, is, for example, the number of lists in the list-type sequential elimination decoding method. In Figure 6 In the example, it is assumed that n is 3 or more, but the present invention is not limited to this example, and n only needs to be 1 or more.

[0075] Here, after generating a hard decision value using a method corresponding to the input signal, the first non-sequential decoding unit 200 of the hard decision decoding unit 20 performs non-sequential decoding of the polarization code as in Embodiment 1 on the hard decision value, and outputs the decoding result to the replacement unit 201. The replacement unit 201 replaces the bit position corresponding to the fixed value in the decoding result output from the first non-sequential decoding unit 200 with the fixed value, and outputs the replaced decoding result to the second non-sequential decoding unit 202. The second non-sequential decoding unit 202 performs non-sequential decoding of the polarization code on the decoding result output from the replacement unit 201, and outputs the decoding result to the data selection unit 23 and the first error detection unit 203.

[0076] That is, in this embodiment, the hard decision decoding unit 20 performs hard decision decoding of the polar code on the input signal to generate a third decoding result, replaces the bit position corresponding to the fixed value of the third decoding result with a fixed value, and performs hard decision decoding of the polar code on the decoding result replaced with the fixed value to generate a first decoding result. The first decoding result is input to the data selection unit 23 in the same manner as in the first embodiment.

[0077] The first error detection unit 203 performs error detection processing on the decoding result output from the second non-sequential decoding unit 202, and outputs the error detection result to the control unit 22 and the data selection unit 23. The processing of the first error detection unit 203 is the same as that of the first error detection unit 101 in the first embodiment.

[0078] The soft decision decoding unit 21 decodes the system polarization code successively for the input signal input to the decoding circuit 2. The successive decoding unit 210 of the soft decision decoding unit 21 uses the input signal and the decoding result obtained in the decoding process of the successive decoding unit 210 to perform decoding successively. The decoding method in the successive decoding unit 210 is the same as that in Implementation 1, and a successive elimination decoding method, a list-type successive elimination decoding method, etc. can be used, but it is not limited to these. At the timing of decoding, the successive decoding unit 210 outputs the results decoded successively in the decoding process to the data update units 211-1 to 211-n. In addition, the successive decoding unit 210 outputs the information representing the maximum likelihood candidate to the data selection unit 23, similarly to the successive decoding unit 110 in Implementation 1. In addition, Figure 6 As an example, an example using the list-type successive erasure decoding method is shown. However, as described in Embodiment 1, the structure when the number of lists is 1 is the same as that of the example using the successive erasure decoding method. Figure 6 The structure shown can also be applied to the case where the successive elimination decoding method is used.

[0079] The data updating units 211-1 to 211-n hold the decoding results input from the replacement unit 201 of the hard decision decoding unit 20, and update the decoding results by overwriting the held decoding results with the decoding results as the result of the decoding process input from the sequential decoding unit 210. The data updating units 211-1 to 211-n output the updated decoding results to the corresponding third non-sequential decoding units 212-1 to 212-n, respectively.

[0080] The third non-sequential decoding units 212-1 to 212-n perform non-sequential decoding on the decoding results input from the data updating units 211-1 to 211-n, and output the decoding results to the corresponding second error detection units 213-1 to 213-n, respectively. In addition, the third non-sequential decoding units 212-1 to 212-n output the decoding results to the data selection unit 23. The second error detection units 213-1 to 213-n perform error detection processing on the decoding results input from the third non-sequential decoding units 212-1 to 212-n, similarly to the first error detection unit 203, and output the error detection results to the data selection unit 23.

[0081] That is, in this embodiment, the soft decision decoding unit 21 performs hard decision decoding of the polar code on the decoding result obtained by updating the decoding result of the permutation unit 201 using the second decoding result, thereby generating a fourth decoding result, and the second error detection units 213-1 to 213-n perform error detection processing on the fourth decoding result, thereby generating a second error detection result.

[0082] The control unit 22 controls the soft decision decoding unit 21 based on the error detection result input from the first error detection unit 203 of the hard decision decoding unit 20 and the control information input from the data selection unit 23. Specifically, when the error detection result input from the first error detection unit 203 indicates that an error has occurred, the control unit 22 starts the soft decision decoding unit 21. On the other hand, when information indicating that the decoding result has been determined is input from the data selection unit 23 as control information, the soft decision decoding unit 21 is stopped. In addition, as described in Embodiment 1, the hard decision decoding unit 20 and the soft decision decoding unit 21 may be operated simultaneously to perform processing in parallel. In this case, the processing of the hard decision decoding unit 20 ends earlier than the processing of the soft decision decoding unit 21. Therefore, when no error is detected in the error detection of the first error detection unit 203, the soft decision decoding unit 21 may be stopped.

[0083] The data selection unit 23 generates control information based on the information input from the hard decision decoding unit 20 and the information input from the soft decision decoding unit 21, and outputs the control information to the control unit 22. In addition, the data selection unit 23 selects a decoding result as a final decoding result based on the information input from the hard decision decoding unit 20 and the information input from the soft decision decoding unit 21, and outputs the final decoding result to a circuit (not shown) at a subsequent stage of the decoding circuit 2.

[0084] Specifically, when the error detection result input from the first error detection unit 203 indicates that there is no error, the data selection unit 23 selects the decoding result output from the second non-sequential decoding unit 202 of the hard decision decoding unit 20 as the final decoding result and outputs it. When the error detection result input from the first error detection unit 203 indicates that an error has occurred, the data selection unit 23 selects the decoding result as the final decoding result using the information input from the soft decision decoding unit 21, and outputs the final decoding result. Specifically, the data selection unit 23 selects the decoding result whose error detection result input from the second error detection unit 213-1 to 213-n indicates that there is no error among the decoding results input from the third non-sequential decoding units 212-1 to 212-n.

[0085] On the other hand, when all the error detection results input from the second error detection units 213-1 to 213-n indicate errors, the data selection unit 23 uses the information for selecting the maximum likelihood candidate input from the sequential decoding unit 210 to select the maximum likelihood decoding result from the decoding results input from the third non-sequential decoding units 212-1 to 212-n and output it as the final decoding result.

[0086] Next, the operation of the decoding circuit 2 according to the present embodiment will be described using a flowchart. Figure 7 1 is a flowchart showing an example of a process procedure in the decoding circuit 2 of this embodiment. The description of the parts overlapping with those in Embodiment 1 is omitted. Here, the case where the list-type successive elimination decoding method is used as the successive decoding method is described as an example.

[0087] First, when an input signal is input to the decoding circuit 2, the first non-sequential decoding unit 200 of the hard decision decoding unit 20 performs non-sequential decoding (step S201). As described above, the first non-sequential decoding unit 200 outputs the decoding result to the replacement unit 201. The replacement unit 201 replaces the bit position corresponding to the fixed value in the decoding result input from the first non-sequential decoding unit 200 with a fixed value (step S202). The replacement unit 201 outputs the decoding result replaced with the fixed value to the second non-sequential decoding unit 202. The second non-sequential decoding unit 202 performs non-sequential decoding on the decoding result input from the replacement unit 201 (step S203). The second non-sequential decoding unit 202 outputs the decoding result to the data selection unit 23 and the first error detection unit 203. The first error detection unit 203 performs error detection processing and outputs the error detection result to the data selection unit 23 and the control unit 22.

[0088] The data selection unit 23 determines whether an error is detected based on the error detection result (step S204). If no error is detected (step S204: No), the data selection unit 23 selects the decoding result input from the second non-sequential decoding unit 202 as the final decoding result (step S217). Then, the data selection unit 23 outputs the final decoding result. When the data selection unit 23 has determined the decoding result, that is, when the final decoding result is output, the information indicating that the decoding result has been determined is notified to the control unit 22 as control information. When receiving the notification, the control unit 22 stops the soft decision decoding unit 21.

[0089] When the error detection result input from the first error detection unit 203 indicates that an error has been detected (step S204: Yes), the successive decoding unit 210 performs successive decoding (step S205). The successive decoding unit 210 generates a list number of decoding results through successive decoding, and generates a list number of information for selecting the maximum likelihood candidate. The successive decoding unit 210 outputs the list number of decoding results to the corresponding data updating units 211-1 to 211-n, and outputs the list number of information for selecting the maximum likelihood candidate to the data selection unit 23.

[0090] The sequential decoding unit 210 determines whether the decoding is completed, that is, whether the decoding corresponding to the code length is performed (step S206). When the decoding is completed (step S206: Yes), the sequential decoding unit 210 instructs the data updating units 211-1 to 211-n to update the decoding results, and the data updating units 211-1 to 211-n update the decoding results (step S207). Specifically, the data updating units 211-1 to 211-n use the decoding results input from the sequential decoding unit 210 to overwrite the retained decoding results, thereby updating the decoding results. The data updating units 211-1 to 211-n output the updated decoding results to the third non-sequential decoding units 212-1 to 212-n.

[0091] The third non-sequential decoding units 212-1 to 212-n perform non-sequential decoding on the decoding results input from the data updating units 211-1 to 211-n (step S208). The third non-sequential decoding units 212-1 to 212-n output the decoding results to the corresponding second error detection units 213-1 to 213-n and the data selection unit 23.

[0092] The data selection unit 23 determines whether there is a decoding result without error among the decoding results input from the third non-sequential decoding units 212-1 to 212-n based on the error detection results input from the second error detection units 213-1 to 213-n (step S209). If there is a decoding result without error (step S209: yes), the data selection unit 23 selects a candidate without error (i.e., the error detection result among the decoding results input from the third non-sequential decoding units 212-1 to 212-n is determined to be a decoding result without error) as the final decoding result (step S210), and outputs the final decoding result.

[0093] When there is no error-free decoding result (step S209: No), the data selection unit 23 selects the maximum likelihood candidate as the final decoding result based on the information for selecting the maximum likelihood candidate input from the sequential decoding unit 210 (step S211), and outputs it as the final decoding result.

[0094] If the decoding is not completed in step S206 (step S206: No), the successive decoding unit 210 determines whether the decoding has been performed x times (step S212). The x is the same as in Embodiment 1. If the number of decoding times in the successive decoding unit 210 is less than x times, that is, if the decoding has not been performed x times (step S212: No), the successive decoding unit 210 performs the processing from step S205 again.

[0095] On the other hand, when decoding has been performed x times (step S212: Yes), the sequential decoding unit 210 instructs the data updating units 211-1 to 211-n to update the decoding results, and performs steps S213, S214, and S215 in the same manner as steps S207, S208, and S209.

[0096] If there is a decoding result without error (step S215: Yes), the data selection unit 23 selects a candidate without error (i.e., a decoding result without error determined as a decoding result without error in the decoding results input from the third non-sequential decoding units 212-1 to 212-n) as the final decoding result (step S216), and outputs the final decoding result. If there is no decoding result without error (step S215: No), the sequential decoding unit 210 performs the processing from step S205 again.

[0097] As in the first embodiment, when the number of lists of the list-type successive erasure decoding method is set to 1, since it is equivalent to the successive erasure decoding method, Figure 7 The processing of can also be applied to the case of using the successive elimination decoding method. In addition, when the number of lists is set to 1, it can also be omitted Figure 7 Processing of steps S209, S210, S211, and S216.

[0098] In the decoding method of this embodiment, in the first step, hard decision decoding of the polar code is performed on the input signal to generate a third decoding result, and the bit position where the fixed value is configured in the encoding of the third decoding result is replaced with a fixed value, and hard decision decoding of the polar code is performed on the decoding result replaced with the fixed value, thereby generating the first decoding result. In addition, in the second step, hard decision decoding of the polar code is performed on the result obtained by updating the decoding result obtained by replacing the fixed value of the third decoding result with the second decoding result, thereby generating a fourth decoding result, and error detection processing is performed on the fourth decoding result, thereby generating a second error detection result.

[0099] Next, the hardware for realizing the decoding circuit 2 of this embodiment will be described. As with the components of the decoding circuit 1 of the first embodiment, the components of the hard decision decoding unit 20 and the soft decision decoding unit 21, the control unit 22, and the data selection unit 23 that constitute the decoding circuit 2 can be implemented by a dedicated hardware. Figure 4 In addition, similarly to the components of the decoding circuit 1 of the first embodiment, the components of the hard decision decoding unit 20 and the soft decision decoding unit 21, the control unit 22, and the data selection unit 23 that constitute the decoding circuit 2 can also be realized by Figure 5 The control circuit shown in the figure is used to achieve this. Figure 5 When the control circuit shown realizes each of the hard decision decoding unit 20 and the soft decision decoding unit 21, the control unit 22, and the data selection unit 23 that respectively constitute the decoding circuit 2, it can be realized by software, firmware, or a combination of software and firmware as in Embodiment 1. The specific implementation method of each function is the same as in Embodiment 1. As in Embodiment 1, the decoding circuit 2 can be realized by dedicated hardware, software, firmware, or a combination thereof.

[0100] As described above, in this embodiment, as in Embodiment 1, when there is no error in the stage until the decoding corresponding to the code length is not completed, the decoding process can be quickly ended. Therefore, redundant operations can be suppressed and the operation rate of the decoding circuit 2 can be reduced.

[0101] Implementation 3

[0102] Figure 8 1 is a diagram showing a configuration example of a decoding circuit according to Embodiment 3 of the present invention. This embodiment implements encoding of a systematic polar code, which is provided with redundant bits for performing error detection in a transmission signal. Figure 8 As shown in the figure, the decoding circuit 3 is an example of a decoding device of the present invention. The decoding circuit 3 decodes the input signal similarly to the decoding circuits 1 and 2 of the embodiments 1 and 2, and outputs the result obtained by decoding to a subsequent circuit not shown. In addition, in the present embodiment, the decoding result output to the subsequent circuit is also referred to as the final decoding result. The input signal of the present embodiment is the same as that of the embodiment 2. Hereinafter, for the same parts as those of the embodiment 2, repeated descriptions are omitted, and the parts different from the embodiment 2 are mainly described.

[0103] like Figure 8 As shown, the decoding circuit 3 includes a hard decision decoding unit 20, a soft decision decoding unit 21, a third error detection unit 31, a control unit 32, and a data selection unit 33. The hard decision decoding unit 20 and the soft decision decoding unit 21 are the same as those in the second embodiment, and thus their description is omitted.

[0104] The third error detection unit 31 performs hard decision on the input signal, performs error detection processing on the hard decision result, and outputs the error detection result as the third error detection result to the control unit 32 and the data selection unit 33. The control unit 32 has the same function as the control unit 22 of the second embodiment, and performs processing corresponding to the error detection result input from the third error detection unit 31. The data selection unit 33 has the same function as the data selection unit 23 of the second embodiment, and performs processing corresponding to the error detection result input from the third error detection unit 31.

[0105] When the control unit 32 determines that an error exists based on the error detection result input from the third error detection unit 31, the control unit 32 starts the hard decision decoding unit 20. When the control information from the data selection unit 33 indicates that the data selection unit 33 has determined the decoding result, the control unit 32 stops the hard decision decoding unit 20 and the soft decision decoding unit 21. The operation of the control unit 32 other than this is the same as that of the control unit 22 in the second embodiment.

[0106] When the data selection unit 33 determines that there is no error based on the error detection result input from the third error detection unit 31, it selects the result of hard decision on the input signal input to the decoding circuit 3 as the final decoding result and outputs it. When the data selection unit 33 determines that there is an error, it outputs control information indicating that there is an error to the control unit 32. In addition, when the data selection unit 33 selects and outputs the final decoding result, it outputs control information indicating that the decoding result has been determined to the control unit 32, similarly to the first and second embodiments. The other operations of the data selection unit 33 are the same as those of the data selection unit 23 of the second embodiment.

[0107] Next, the operation of the decoding circuit 3 according to the present embodiment will be described using a flowchart. Fig. 9 1 is a flowchart showing an example of a process in the decoding circuit 3 of this embodiment. The description of the parts overlapping with those in Embodiment 2 is omitted. Here, the case where the list type successive elimination decoding method is used as the successive decoding method is described as an example.

[0108] First, when an input signal is input to the decoding circuit 3, the third error detection unit 31 performs hard decision on the input signal and performs error detection processing on the result of the hard decision. The third error detection unit 31 outputs the error detection result to the control unit 32 and the data selection unit 33. The data selection unit 33 determines whether there is an error based on the error detection result input from the third error detection unit 31 (step S301). If there is no error (step S301: No), the data selection unit 33 selects the soft decision value or the hard decision result of the LLR of the received signal input to the decoding circuit 3 as the final decoding result (step S319), and outputs the final decoding result. When the data selection unit 33 has determined the decoding result, that is, when the final decoding result is output, the information indicating that the decoding result has been determined is notified to the control unit 32 as control information in the same manner as in the second embodiment. When receiving the notification, the control unit 32 stops the hard decision decoding unit 20 and the soft decision decoding unit 21.

[0109] When there is an error (step S301: Yes), hard decision decoding is performed in the same manner as in the second embodiment, and soft decision decoding is performed based on the result. Fig. 9 Steps S302 to S318 shown are the same as steps S201 to S217 in Embodiment 2, and thus description thereof will be omitted.

[0110] As described above, in the decoding circuit 3 of the present embodiment, the third error detection unit 31 performs hard decision on the input signal and performs error detection processing on the result of the hard decision. Furthermore, when the error detection result of the error detection processing performed by the third error detection unit 31 indicates that there is no error, the decoding circuit 3 of the present embodiment does not start the hard decision decoding unit 20 and the soft decision decoding unit 21, but outputs the hard decision result as the final decoding result. Therefore, in the present embodiment, the same effect as that of the second embodiment can be obtained, and compared with the second embodiment, the amount of calculation of the decoding circuit 3 can be further suppressed, and the operation rate of the decoding circuit 3 can be reduced.

[0111] The configuration described in the above embodiment is an example of the content of the present invention, and may be combined with other known techniques. Part of the configuration may be omitted or modified without departing from the gist of the present invention.

[0112] Description of symbols

[0113] 1, 2, 3: decoding circuit; 10, 20: hard decision decoding unit; 11, 21: soft decision decoding unit; 12, 22, 32: control unit; 13, 23, 33: data selection unit; 31: third error detection unit; 100: non-sequential decoding unit; 101, 203: first error detection unit; 110, 210: successive decoding unit; 111-1 to 111-n, 211-1 to 211-n: data update unit; 112-1 to 112-n, 213-1 to 213-n: second error detection unit; 200: first non-sequential decoding unit; 201: replacement unit; 202: second non-sequential decoding unit; 212-1 to 212-n: third non-sequential decoding unit.

Claims

1. A decoding device, characterized in that: The decoding device has: a hard decision decoding unit configured to perform hard decision decoding of the polar code using the input signal to generate a first decoding result, and to perform a first error detection process on the first decoding result to generate a first error detection result; a soft decision decoding unit configured to successively decode the polar code on the input signal to thereby generate a second decoding result obtained in each decoding in the successive decoding, update the first decoding result using the second decoding result, and perform a second error detection process on a result obtained by updating the first decoding result using the second decoding result to thereby generate a second error detection result; a data selection unit that selects the first decoding result or a result obtained by updating the first decoding result using the second decoding result, and outputs the result as a final decoding result; as well as A control unit that stops the soft decision decoding unit when the data selection unit outputs the final decoding result.

2. The decoding device according to claim 1, characterized in that When the first error detection result indicates that there is no error, the data selection unit selects and outputs the first decoding result.

3. The decoding device according to claim 1, characterized in that When the first error detection result indicates that an error exists, the control unit activates the soft decision decoding unit.

4. The decoding device according to claim 1, characterized in that The soft decision decoding unit performs the second error detection process before the sequential decoding is performed by an amount corresponding to the code length. The data selection unit determines whether the second error detection result is a result indicating no error, and if the second error detection result is a result indicating no error, selects a result obtained by updating the first decoding result using the second decoding result corresponding to the second error detection result, and outputs the result as the final decoding result, When the data selection unit outputs a result obtained by updating the first decoding result using the second decoding result as the final decoding result, the control unit stops the soft decision decoding unit.

5. The decoding device according to claim 4, characterized in that The soft decision decoding unit executes the second error detection process when the number of decoding times in the sequential decoding reaches a set number of times.

6. The decoding device according to claim 1, characterized in that: The successive decoding is a list-based successive elimination decoding. The soft decision decoding unit generates a result obtained by updating the first decoding result using the second decoding result of each list and the second error detection result, The data selection unit selects and outputs a result obtained by updating the first decoding result using one of the second decoding results from among the results obtained by updating the first decoding result using the second decoding result of each list based on the second error detection result.

7. The decoding device according to claim 6, characterized in that The soft decision decoding unit generates information indicating likelihoods corresponding to the second decoding results of each list, When there is no result indicating that there is no error in the second error detection result, the data selection unit selects and outputs a result obtained by updating the first decoding result using one of the second decoding results from the results obtained by updating the first decoding result using the second decoding result of each list based on the information indicating the likelihood.

8. The decoding device according to any one of claims 1 to 7, characterized in that: The polarization code is a system polarization code, the hard decision decoding unit performs hard decision decoding of the polar code on the input signal to generate a third decoding result, replaces a bit position where the fixed value is arranged in the encoding of the third decoding result with a fixed value, and performs hard decision decoding of the polar code on the decoding result replaced with the fixed value to generate the first decoding result, The soft decision decoding unit performs hard decision decoding of the polar code on a result obtained by updating a decoding result obtained by replacing a fixed value of the third decoding result using the second decoding result, thereby generating a fourth decoding result, and performs error detection processing on the fourth decoding result, thereby generating the second error detection result.

9. The decoding device according to any one of claims 1 to 7, characterized in that: The decoding device includes an error detection unit that performs hard decision on the input signal to generate a hard decision result, and performs error detection processing on the hard decision result to generate a third error detection result. The control unit activates the hard decision decoding unit based on the third error detection result.

10. The decoding device according to claim 9, characterized in that: When the third error detection result indicates that there is no error, the data selection unit selects and outputs the hard decision result.

11. A decoding method, wherein the decoding method is a decoding method in a decoding device for decoding polar codes, characterized in that: The decoding method comprises the following steps: In a first step, the following first processing is performed: hard decision decoding of the polar code is performed using the input signal to generate a first decoding result, and error detection processing is performed on the first decoding result to generate a first error detection result; The second step is to perform the following second processing: successively decoding the polar code on the input signal to thereby generate a second decoding result obtained in each decoding in the successive decoding, updating the first decoding result using the second decoding result, and performing error detection processing on a result obtained by updating the first decoding result using the second decoding result to thereby generate a second error detection result; Step 3, selecting the first decoding result or the decoding result obtained by updating the first decoding result using the second decoding result, and outputting it as the final decoding result; as well as In step 4, when the final decoding result is output in step 3, the second process is stopped.

12. The decoding method according to claim 11, characterized in that: The polarization code is a system polarization code, In the first step, hard decision decoding of the polar code is performed on the input signal to generate a third decoding result, a bit position at which the fixed value is configured in the encoding of the third decoding result is replaced with a fixed value, and hard decision decoding of the polar code is performed on the decoding result replaced with the fixed value to generate the first decoding result, In the second step, hard decision decoding of the polar code is performed on a result obtained by updating a decoding result obtained by replacing a fixed value of the third decoding result using the second decoding result, thereby generating a fourth decoding result, and error detection processing is performed on the fourth decoding result, thereby generating the second error detection result.

13. A control circuit for controlling a decoding device, characterized in that: The control circuit enables the decoding device to perform the following steps: In a first step, the following first processing is performed: hard decision decoding of the polar code is performed using the input signal to generate a first decoding result, and error detection processing is performed on the first decoding result to generate a first error detection result; The second step is to perform the following second processing: successively decoding the polar code on the input signal to thereby generate a second decoding result obtained in each decoding in the successive decoding, updating the first decoding result using the second decoding result, and performing error detection processing on a result obtained by updating the first decoding result using the second decoding result to thereby generate a second error detection result; Step 3, selecting the first decoding result or the decoding result obtained by updating the first decoding result using the second decoding result, and outputting it as the final decoding result; as well as In step 4, when the final decoding result is output in step 3, the second process is stopped.

14. A storage medium storing a program for controlling a decoding device, characterized in that: The program causes the decoding device to perform the following steps: In a first step, the following first processing is performed: hard decision decoding of the polar code is performed using the input signal to generate a first decoding result, and error detection processing is performed on the first decoding result to generate a first error detection result; The second step is to perform the following second processing: successively decoding the polar code on the input signal to thereby generate a second decoding result obtained in each decoding in the successive decoding, updating the first decoding result using the second decoding result, and performing error detection processing on a result obtained by updating the first decoding result using the second decoding result to thereby generate a second error detection result; Step 3, selecting the first decoding result or the decoding result obtained by updating the first decoding result using the second decoding result, and outputting it as the final decoding result; as well as In step 4, when the final decoding result is output in step 3, the second process is stopped.

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