Cell-aware defect characterization by considering inter-cell timing

Abstract

Cell-aware defect characterization is disclosed by considering inter-cell timing. Also disclosed is a method and apparatus to determine whether a defect can be detected in a standard library cell used to design integrated circuits. A defect detection table is generated that indicates whether a particular defect can be detected using a particular combination of input logic states and under different load conditions. The results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible outcomes for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can only be detected under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load condition.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to systems and methods for verifying operations of integrated circuit designs, and more particularly, to cell-aware defect characterization by considering inter-cell timing. BACKGROUND

[0002] Testing the operations of complex integrated circuits (ICs) is difficult due to the very large number of cells that exist within the design. The use of complex ICs has been growing and there are indications that it will continue to grow for the foreseeable future. There are currently many tools for assisting in testing such ICs, including tools for ensuring that such designs meet reliability and operational requirements. One important tool for assisting in testing complex ICs is a cell-aware defect model. Cell-aware defect models characterize defects within standard library cells to achieve better defect coverage and more accurate defect diagnosis. The industry has widely adopted cell-aware defect models for designs manufactured using the latest manufacturing technology. SUMMARY

[0003] A method is disclosed in which a cell of an integrated circuit design is modeled using a plurality of inputs, at least one output, and at least one modeled defect. The logic state of the at least one of the outputs of the model is determined based on a combination of logic states of at least one of the plurality of inputs and a first load condition imposed on at least one of the inputs on which the state of the at least one of the outputs is based. The logic state of the at least one of the outputs of the model is determined based on the logic state of at least one of the inputs and a second load condition imposed on at least one of the inputs on which the state of the at least one of the outputs is based. When at least one of the modeled defects exists in the model for the combination of input logic states, a processor determines whether the logic state of the at least one of the outputs is different with the first load condition imposed than with the second load condition imposed.

[0004] Additionally, a system is disclosed that includes a memory for storing whether a modeled defect in a cell of an integrated circuit is detectable under a predetermined combination of applied input logic states. The system further includes a processor coupled to the memory to: (1) store the determination of whether the modeled defect is detectable; (2) model a cell of an integrated circuit design using a plurality of inputs and at least one output; (3) model the cell using at least one modeled defect; (4) determine the logic state of at least one of the outputs of the model based on a first load condition imposed on at least one of the inputs based on a combination of logic states of at least one of the plurality of inputs and the state of the output; determine the logic state of at least one of the outputs of the model based on a second load condition imposed on at least one of the inputs based on the logic state of at least one of the inputs and the state of the output; and (5) when the combination of the at least one modeled defect for the input logic states is present in the model, determine whether the logic state of the output under the second load condition is different from the logic state of the output under the first load condition.

[0005] Additionally, a non-transitory computer-readable medium is disclosed, comprising stored instructions that, when executed by a processor, cause the processor to perform the following operations: (1) storing a determination regarding whether a modeled defect is detectable; (2) modeling a cell of an integrated circuit design using a plurality of inputs and at least one output; (3) modeling the cell using at least one modeled defect; (4) determining the logic state of at least one of the outputs of the model based on a combination of the logic states of at least one of the plurality of inputs and a first load condition imposed on at least one of the inputs upon which the state of the output is based; (5) determining the logic state of at least one of the outputs of the model based on a second load condition imposed on at least one of the inputs upon which the logic state of the output is based; and (6) when the combination of the input logic states for at least one of the modeled defects exists in the model, determining whether the logic state of the output under the second load condition is different from the logic state of the output under the first load condition. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings illustrating embodiments of this disclosure. The drawings are provided to give an understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0007] Figure 1 It is a simplified description of a standard library unit with four inputs and one output.

[0008] Figure 2 This is an illustration of an instance of a unit for which defects have been modeled.

[0009] Figure 3 This is an explanation of the static defect detection table.

[0010] Figure 4 Explain D-DDT, in which various combinations of input logic states applied to each of the inputs are recorded as defects and the output has the logic level shown.

[0011] Figure 5 This is based on the DDT description of the disclosed methods and equipment.

[0012] Figure 6 It is a description of dynamic defect detection records used to record the behavior of each combination of logical states and arcs.

[0013] Figure 7 This is a flowchart of one embodiment of the disclosed method.

[0014] Figure 8 This describes a set of example processes used to transform and verify the design data and instructions representing integrated circuits during the design, verification, and manufacturing processes of in-process (e.g., integrated circuits).

[0015] Figure 9 This describes an example machine of a computer system 900 in which a set of instructions for causing the machine to execute any or more of the methodologies discussed herein can be executed. Detailed Implementation

[0016] The disclosed method and apparatus provide an efficient and relatively accurate method and apparatus for modeling faults in cells of complex integrated circuits (ICs).

[0017] For designs with thousands of standard library cells, the signal applied to the pins of each cell is influenced by the signals of neighboring cells, resulting in a factor that must be considered when attempting to model the resistive / capacitive (RC) network connected to each pin. Furthermore, the amount of RC load at the cell pins can depend on the type of technology used to implement the cell. Different RC loads can result in different waveforms at each of the cell's input pins in the IC. These different waveforms can significantly influence behavior caused by specific types of defects within the cell.

[0018] One way to test standard library cells is to detect the appropriate output state for each specific combination of input states that can be applied to the cell.Figure 1 This is a simplified description of a standard library cell with four inputs A0, A1, B0, B1 and one output, each marked with a red cross to indicate it is a test point. The cell's functionality is confirmed by applying specific combinations of input logic states and observing the logic state at the output. This oversimplified test is sufficient for simple cells. However, as the complexity of standard library cells increases, this oversimplified method fails to detect faults effectively. Specifically, it is difficult to determine the source of faults in complex cells simply by applying known logic states to the inputs and detecting the logic state of the output.

[0019] To allow for more comprehensive analysis, a standard cell-aware defect model is used to model the behavior of the cells under specific defect conditions. This behavior is documented in a defect detection table. A cell-aware defect model for the library cells is generated using the Cell-Aware Test Model Generation Tool (CTMGT). CTMGT simulates many (if not all) possible input combinations of the input logic states at the input pins of a specific library cell for a given defect combination, and also simulates the logic states of the outputs under specific input and defect conditions to accurately capture the defective behavior of the cells.

[0020] Two types of defects are typically considered: static defects and dynamic defects. Static defects cause the signal to be stuck in either a logic 0 or a logic 1 state, regardless of the input value applied to the cell's input. Dynamic defects cause a delay in the transition of the signal from a logic 0 state to a logic 1 state (or from 1 to 0). Typically, defect detection tables (DDTs) include static defect detection tables (S-DDTs) and dynamic defect detection tables (D-DDTs).

[0021] Figure 2 This is an illustration of an example of a cell for which defects have been modeled. For example, the first defect D1 is an open circuit between the first field-effect transistor (FET) 204a and the second FET 204b. The second defect D2 is a resistive short circuit between the gate and source of the third FET 204c. The third defect D3 is a resistive short circuit between the gate and source of the fourth FET 204d. The fourth defect D4 is a resistive short circuit between the drain and source of the fifth FET 204e. A set of inputs A0, A1, B0, B1 is shown, as well as the output node 206. Additional defects 202f, 202g, and 202h are also shown. It should be noted that when an element shown in the figure is associated with a reference designation having a numerical part followed by a letter (e.g., FET 204a), all elements having the same numerical part can be commonly referenced by the numerical part, e.g., FET 204.

[0022] Figure 3This is a description of the S-DDT 300. The first four columns of the S-DDT 300 indicate combinations of input logic states. A "1" in the first column, labeled "A0", indicates that a signal with logic state "1" is applied to input A0. Note that several nodes in cell 200 can be connected to input A0, as in the example shown in cell 200. Similarly, a "0" in the second column, labeled "A1", indicates that a signal with logic state "0" is applied to input A1. This also applies to the columns labeled "B0" and "B1".

[0023] A "1" or "0" in the column labeled "Output" indicates the output caused by a specific combination of input signal states in the absence of any defects in the cell. The last five columns indicate whether each specific defect can be detected using a specific combination of input logic states (i.e., what would cause a change in the resulting output). A "1" in the column labeled "Dx" indicates that an associated defect can be detected, where x equals 1, 3, 5, or 7. For example, a "1" in the columns labeled "D5" and "D7" indicates that if defect D5 or defect D7 is present in the circuit and input logic states 0, 0, 0, 1 are applied to inputs "A0", "A1", "B0", and "B1" respectively, then the output will be "1" (opposite to the "0" indicated in the output column of row 1). Furthermore, defects D1, D3, and D4 will not affect the output state (i.e., such defects cannot be detected from this combination of input logic states). Note that defects D2, D6, and D8 are not modeled for combinations of input and output logic states in this table. Therefore, this table does not indicate whether such defects are detectable. It should also be noted that a particular logical state is not necessarily logically related to the specific defect mentioned in this example; rather, the input state is unrelated to the location of the defect to actually enable detection of these specific defects in the manner described in the DDT presented herein. These DDT values ​​were arbitrarily selected merely for the purpose of illustrating the expected operation of the DDT according to the disclosed methods and apparatus.

[0024] Figure 4 The D-DDT 400 describes various combinations of input logic states applied to each of inputs A0, A1, B0, and B1, including defects D2, D6, and D8, wherein the output has the logic states shown in the D-DDT 400. In the D-DDT 400, a "0" in one of the input columns indicates that the signal applied to that input is in a logic "0" state. An "R" in one of the input columns indicates that the signal applied to the corresponding input rises from a logic "0" state to a logic "1" state. An "F" in the input column indicates that the signal applied to the associated input falls from a logic "1" state to a logic "0" state.

[0025] Therefore, when a defect is detected by a given input vector (i.e., the set of input logic states applied to the cell input node), a "1" is recorded in the detection table, and when a defect is not detected by a given input vector, a "0" is recorded in the detection table.

[0026] Furthermore, the demand for low power consumption has driven down chip operating voltages, which in turn has led to a significant increase in analog effects and process-dependent timing variations. These effects result in an increase in the length of timing arcs (i.e., the rise and / or fall times of a signal at a specific node in the IC, attributed to the propagation through a specific portion of the circuit). This increase makes it more difficult to accurately detect dynamic faults, as some dynamic faults are dependent on specific timing along the circuitry of the IC.

[0027] Therefore, it would be advantageous to provide a system that can efficiently and more accurately model the conditions under which failures will occur.

[0028] The disclosed methods and apparatus presented herein provide a cell-aware fault model that takes into account different timings (i.e., the resulting waveforms) caused by inter-cell capacitance or load capacitance. By considering different examples of RC loads when modeling fault conditions, a more realistic model of defect behavior can be used. This model can then be applied to an IC design. In the modeling of the IC design, a range of RC values ​​are used depending on the specific manufacturing technology used to manufacture the IC. Therefore, it is possible to determine whether a defect exhibits different "detection states" for different timing arcs (i.e., detectable under some RC load conditions but not under different RC load conditions). In cases where it is determined that the defect is sensitive to the timing of the waveform applied to the input (e.g., caused by different inter-cell capacitances), a flexible detection state "x" is placed in the column of the S-DDT to indicate that the cell-aware test model has determined that the state of the defect is nondeterministic (i.e., it can vary with different RC loads on various input pins).

[0029] Unit-aware defect models calibrate defects within standard library cells, enabling more efficient defect modeling and therefore more accurate defect diagnosis. Unit-aware defect modeling captures defect behavior from a Defect Detection Table (DDT). Similar to previously used DDTs (e.g....), Figure 4 As shown in the diagram, the DDT used in the currently disclosed methods and apparatus has several rows, each of which is associated with a specific combination of logical states of the inputs, an output, and indicates the effect of each defect within a group of defects being modeled. In some embodiments, a determination about whether a defect is detectable can be made by determining whether the logical state of the unit's output differs in the presence of a defect from that in the absence of a defect.

[0030] However, according to currently disclosed methods and devices, a cell-aware defect model is generated using an advanced CTMGT library cell. Several possible combinations of input pins are modeled. For each combination of input signals, a specific timing arc (i.e., the signal rise or fall time based on the load condition on the signal) is assumed to be applied at each input. The same combination of input signal logic states (i.e., input rising, falling, or in a steady state) is applied, but different timing arcs are applied at each of the inputs. Applying signals with different timing arcs to those inputs that are rising or falling allows for more accurate capture of defect behavior under different conditions. This process is then repeated for each combination of input signal logic states. Similarly, the load condition at the output is changed. For each combination, the logic state of the output is determined. In the illustrated example, only one output exists, but other embodiments may have multiple outputs. By determining whether the logic state of the output differs under different load conditions, the behavior of the cell for each combination of input logic states and load conditions can be determined. Therefore, in some embodiments, the processor determines the logic state of at least one of the outputs of the cell model based on a predetermined combination of logic states at the inputs and a first load condition imposed on at least one of the inputs upon which the output state is based. Next, the processor determines the logic state of the output of the cell model based on the logic state of at least one of the inputs and a second load condition imposed on the inputs upon which the output state is based. Then, when at least one of the defects exists in the combination of input logic states in the cell model, the processor determines whether the logic state of at least one of the outputs differs under the first load condition compared to under the second load condition.

[0031] Similarly, the logic state of the output is determined for combinations of input logic states and different load conditions applied to the output. That is, the processor of the control process determines the logic state of at least one of the outputs of the unit model based on a predetermined combination of logic states and specific load conditions imposed on one or more of the outputs. Next, the processor determines the logic state of the unit model's output based on the predetermined combination of logic states and different load conditions imposed on the output. Then, when at least one of the defects exists in the model for a combination of input logic states, the processor determines whether the logic state of the output differs under the initial load conditions compared to under subsequent load conditions.

[0032] For each defect being modeled, the model can have one of three different outcomes for each combination of input logic states. The first outcome is that the modeled defect is detectable in all cases of a specific combination of logic states, regardless of the timing arcs applied to the inputs for all output load conditions. In this case, the defect is marked with a "1" in the DDT. The second outcome is that the defect is not detectable using this combination of logic states, regardless of the timing arcs applied to each input and the load conditions on the outputs. In this case, the defect is assigned a "0" in the row associated with this combination of input logic states in the DDT. The third outcome is that defects can be detected for some timing arcs and / or sets of output load conditions, but not for others. In this case, an "x" is placed in the column associated with that defect for the row associated with this combination of input signal states. This will be made clearer with the following example.

[0033] By indicating in the DDT whether a defect is detectable under all load conditions, undetectable under any load conditions, or detectable only under some load conditions, defects that might otherwise be difficult to detect or characterize can be identified.

[0034] Figure 5 This is based on the disclosed methods and equipment described in DDT 500. (As per the description for...) Figure 4 In the DDT400 example shown, each input is indicated at the header of its corresponding entry in column 502 of the DDT 500. Additionally, each output (only one output exists in the illustrated example) is indicated at the header of its corresponding entry in column 504 of the DDT 500. Furthermore, each defect being modeled is indicated at the header of its corresponding entry in column 506 of the DDT 500. The inputs, outputs, and defects indicated at the header of each column in the DDT 500 are... Figure 4 The DDT 400 shown and about Figure 4 The inputs, outputs, and defects described in DDT 400 are the same.

[0035] However, with Figure 4 Compared to DDT 400, each column of DDT 500 is a "merged result" from a series of modeled behaviors. The merged result is the result of merging several results, each with the same input but different time series arcs and / or output load condition sets, as will be seen in the examples described below.

[0036] Figure 6This is a description of a dynamic defect detection record 600 used to record the behavior of each combination and arc of logic states. The recorded defect behavior of the dynamic defect detection record 600 is used to create the merged results shown in DDT 500. For each defect 606, a defect entry 608 is created in association with each unique combination of input logic states 602 and input load condition 609. In some embodiments, the dynamic defect detection record also has a unique defect entry 608 associated with each of a plurality of output load conditions 604. That is, for inputs 602 and input load conditions 609, there are unique defect entries 608 associated with all the same values, but for output load conditions 604, there are unique defect entries 608 associated with different values.

[0037] Observing the first six rows of the dynamic defect detection record 600, the logic states of the inputs and outputs remain the same. That is, for each of the first six rows 607, the logic state of input A0 is "0", the logic state of input A1 is "0", the logic state of input B0 is "0", and the logic state of input B1 is "R" (rising). The output of each of the first six rows is "0". In addition to columns indicating the specific logic state of each input, output, and defect state, there are columns 609 associated with each input and 605 associated with the output, indicating the load (i.e., arc) associated with each specific input and output. Figure 6 In the example shown, the load is indicated by an integer from 1 to 3 to indicate one of three distinct loads for which defects D2, D6, and D8 will be modeled. It should be noted that load conditions can include a different number of unique load conditions for each of the inputs and outputs. For example, there can be three unique load conditions 609a associated with input A0 and five different unique load conditions 609b associated with input A1. Additionally, it should be noted that... Figure 6 The record 600 shown only shows some combinations of input logic states, the resulting output logic states, and the load conditions for each, because the number of combinations is too large to describe all possible combinations.

[0038] As shown in row 607a, for a specific combination of logic states applied to the inputs, when load condition 1 (row 607a, column 609a) is applied to input A0, load condition 1 (row 607a, column 609b) is applied to input A1, load condition 1 (row 607a, column 609c) is applied to input B0, load condition 1 (row 607a, column 609d) is applied to input B1, and output load condition 1 (row 607a, column 605) is present at the output, the output (row 607a, column 604) will be 0 and none of the three defects D2, D6, and D8 will be detected. However, when the load condition on input A0 (row 607b, column 609a) changes to load condition 2, as shown in row 607b of record 600, defect D8 is detected, as indicated by the "1" in column 617 of column D8 in row 607b. Therefore, all other things being equal, changing the load condition applied to the input signal at input A0 will alter whether defect D8 is detected. Similarly, when load condition 3 is applied to the signal at input A0 (row 607c, column 609a), defect D8 is detected, as recorded by the "1" in row 607c and column 617 of D8. It should be noted that in the illustrated example dynamic defect detection record 600, the value in the output load condition column 605 remains constant for all rows shown. However, the output load condition will typically be variable, similar to the input load condition on each input, and will be changed to test the ability to detect defects under different output load conditions.

[0039] As can be seen, the same logic state is applied to each of the inputs in the first six rows 607 of record 600, but the loads 609a and 609b of the first two inputs A0 and A1 change in each of these rows 607. Furthermore, as the loads 609a and 609b of these two inputs change, the detectable specific defects 606a, 606b, and 606c also change. Since each of the first six rows 607 has the same logic state, it will be "merged" into row 508 of DDT 500 with the same logic state shown in the first row 508 of DDT 500 (i.e., 0, 0, 0, and R for the four inputs A0, A1, B0, and B1, respectively). Defect D2 was not detected for all the tested input and output load conditions imposed on the first six rows 607 of the dynamic defect detection record 600. Therefore, the defect entry with the value "0" is placed in column D2 506a of the first row 508 of DDT 500. Since the combined defects D6 and D8 for the logic states at the input can be detected under some load conditions but not under others, the defect entries with the value "x" are placed in columns D6 506b and D8 506c in the first row 508 (i.e., the row associated with a specific combination of input logic states 0, 0, 0, R).

[0040] Next, observe row 611 of record 600. The input has a combination of logical states R, 0, 0, R. In the advanced CTMGT defect generation model, the load condition for input A0 in column 609a is set to load condition 1 in row 7 611a, load condition 2 in row 8 611b, and so on. The load condition 609b for input A1 remains load condition 1 for rows 7, 8, and 9 611a to 611c, but is set to load condition 2 for rows 10 611d and 11 611e. Defect D8 is not detected in rows 7 through 11 611. However, both defects D2 and D6 are detected in some of these rows, but not in others. Therefore, after merging the model for the combination of input states R, 0, 0, R, the defects D2 and D6 in columns 506a and 506b are marked with "x" in row 510 of DDT 500, and the defect D8 in column 506c is marked with "0" in row 510, thus indicating that defects D2 and D6 are detected under some, but not other, load conditions for the combination of input logic states shown in the second row of DDT. However, defect D8 is not detected for this particular combination of input logic states under any load condition.

[0041] Now observe the combination of input logic states shown in column 502 as 0, 0, R, R in the third row 512 of DDT 500. It can be seen that defects D2 and D6 are never detected under any load conditions, while defect D8 is always detected under any load conditions, as indicated by the "0" in column 506a and column 506b of D2 in the third row 512 of DDT 500 and the "1" in column 506c of D8 in the third row 512 of DDT 500.

[0042] In some embodiments, record 600 is maintained. However, in other embodiments, record 600 is not explicitly created, but the result is compiled to make DDT 500 complete. That is, the description of generating record 600 is merely illustrative in some embodiments, but may be explicitly generated in other embodiments.

[0043] In some embodiments, the specific load conditions for determining the arcs at the inputs and outputs can be determined based on the results of static timing analysis (STA) and dynamic timing analysis (DTA). Methods for performing this timing analysis are well known in the art. Specifically, the specific load conditions for which the advanced CTMGT generates the combined values ​​in the DDT can be modeled by characterizing the specific properties of the input signal likely to be applied to the input or appear as an output signal in the design under test using a series of slew rates caused by the potential capacitive load. Alternatively, a model indicating the range of reactive loads (e.g., capacitive loads) can be used to determine a series of slew rates that the advanced CTMGT should use to generate a series of models for each combination of input logic states.

[0044] Figure 7 This is a flowchart of an embodiment of the disclosed method. Initially, a cell of an integrated circuit design is modeled using multiple inputs, at least one output, and at least one modeled defect (step 702). A logic state for at least one of the outputs is determined based on a combination of logic states of at least one of the inputs and a first load condition imposed on the inputs to determine the state of the output (step 704). Next, a logic state for at least one of the outputs is determined based on the logic states of at least one of the inputs and a second load condition imposed on the inputs (step 706). Finally, when a combination of logic states for the inputs with at least one modeled defect exists in the model, the processor determines whether the logic state of the at least one output differs when the first load condition is imposed on the inputs compared to when the second load condition is imposed (step 708).

[0045] Apparatus for carrying out the disclosed method

[0046] Figure 8This describes a set of example processes 800 used during the design, verification, and manufacturing of an integrated circuit (e.g., an electronically manufactured integrated circuit) to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be constructed and implemented as multiple modules or operations. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with the creation of a product concept 810 using information provided by the designer. This information is transformed to create an article of manufacture using a set of EDA processes 812. Upon completion, the design goes offline 834, and the original pattern (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing facility to create a mask set. The mask set is then used to manufacture the integrated circuit. After going offline, semiconductor dies are manufactured 836, and packaging and assembly processes 838 are performed to produce the final integrated circuit 840.

[0047] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. Higher levels of abstraction can be used to design circuits and systems using hardware description languages ​​('HDL'), such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be transformed into logic-level register-transfer-level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction, which is less abstract, adds more useful details to the design description, such as more details about the modules described. Lower levels of abstraction can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language at a lower level of abstraction for specifying more detailed descriptions is SPICE, used to describe circuits with many analog components. Descriptions at each level of abstraction are enabled to be used by the corresponding tools at that level (e.g., formal verification tools). The design process can use... Figure 7 The sequence described herein. The described process can be enabled through EDA products (or tools).

[0048] During system design phase 814, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics, such as power consumption, performance, area (physical and / or lines of code), and cost reduction. Dividing the design into different types of modules or components can occur at this stage.

[0049] During logic design and functional verification 816, modules or components in the circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of the circuit can be verified to generate outputs that match the requirements of the specifications for the designed circuit or system. Functional verification can be performed using simulators and other programs (e.g., testbed generators, static HDL checkers, and formal verifiers). In some embodiments, a special component system, referred to as a 'simulator' or 'prototype system', is used to accelerate functional verification.

[0050] During the synthesis and design process 818 for testing, HDL code is transformed into a netlist. In some embodiments, the netlist may be a graphical structure, wherein the edges of the graphical structure represent components of the circuit and the nodes of the graphical structure represent the interconnections of the components. Both HDL code and netlist are layered artifacts that can be used by EDA products to verify that the integrated circuit functions according to a specified design when it is manufactured. The netlist may be optimized for a target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that it meets specification requirements.

[0051] During netlist verification (820), the compliance of the netlist with timing constraints and its correspondence with HDL code are checked. During design planning (822), the overall planar diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0052] During layout or physical implementation 824, physical placement (e.g., the positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components via multiple conductors) occur, and a cell can be selected from a library to enable a specific logic function. As used throughout this disclosure, the term "cell" refers to a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit "block" may refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled as physical structures and during simulation. Parameters of the selected cell (based on a 'standard cell'), such as size, are specified to make it accessible in a database for use in EDA products.

[0053] During analysis and extraction (826), circuit functionality is verified at the layout level, allowing for improvements to the layout design. During physical verification (828), the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and that the circuit system functionality matches the HDL design specification. During resolution enhancement (830), the geometry of the layout is transformed to improve the fabrication method of the circuit design.

[0054] During the offline phase, data is created for producing photomasks (where appropriate, after the application of lithographic enhancement). During mask data preparation 830, the 'offline' data is used to produce photomasks for the finished integrated circuits.

[0055] Computer systems (e.g.) Figure 9 The storage subsystem of the computer system (900) can be used to store some or all of the EDA products described herein, as well as programs and data structures for developing units for the physical and logical design of libraries and the use of said libraries.

[0056] Figure 9 This describes an example machine of a computer system 900 in which a set of instructions for causing the machine to perform any or more of the methodologies discussed herein can be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0057] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0058] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)), static memory 906 (e.g., flash memory, static random access memory (SRAM) and the like) and a data storage system 918, which communicate with each other via a bus 930.

[0059] Processing device 902 represents one or more processors, such as microprocessors, central processing units, or the like. More specifically, processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 902 may be configured to execute instructions 926 for performing the operations and steps described herein.

[0060] The computer system 900 may further include a network interface device 908 for communication via a network 920. The computer system 900 may also include a video display component 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing component 922, a signal generation device 916 (e.g., a speaker), a video processing component 928, and an audio processing component 932.

[0061] The data storage device 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) on which one or more sets of instructions 926 or software embodying any or more of the methodologies or functions described herein are stored. The instructions 926 may also reside wholly or at least partially in main memory 904 and / or processing device 902 during execution by computer system 900, which also constitute machine-readable storage media.

[0062] In some embodiments, instruction 926 includes instructions for implementing functionality corresponding to this disclosure. While machine-readable storage medium 924 is shown as a single medium in exemplary embodiments, the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions (e.g., a centralized or distributed database and / or associated caches and servers). The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine and processing device 902 to perform any or more of the methodologies of this disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0063] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. An operation is an operation that requires physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be called bits, values, elements, symbols, characters, items, numbers, or the like.

[0064] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise expressly indicated as is clearly stated in this disclosure, it should be understood that throughout the description, specific terms refer to the operation and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the registers and memories of the computer system and converts said data into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage devices.

[0065] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0066] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various other systems may be used in conjunction with the programs taught herein, or it may be proven convenient to construct more specialized devices to implement the methods. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that a variety of programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0067] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a form readable by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0068] In the foregoing disclosure, embodiments thereof have been described with reference to specific example embodiments of this disclosure. It will be apparent that various modifications may be made to the embodiments without departing from the broader spirit and scope of the embodiments of this disclosure as set forth in the following claims. Where elements are referenced in a singular form in this disclosure, more than one element may be depicted in the drawings, and similar elements are labeled with similar numbers. This disclosure and the drawings should be regarded accordingly in an illustrative rather than restrictive sense.

Claims

1. A method comprising: Model the cells of the integrated circuit design using multiple inputs, at least one output, and at least one modeled defect; The logic state of at least one of the model's outputs is determined based on a first load condition imposed on at least one of the plurality of inputs, on which the logic state of at least one output is based. The logic state of the at least one of the outputs of the model is determined based on the logic state of at least one of the plurality of inputs and the logic state of the at least one output, which is based on a second load condition imposed on at least one of the plurality of inputs. and When at least one of the modeled defects exists in the combination of input logic states, the processor determines whether the logic state of the at least one of the outputs of the model is different under the first load condition than under the second load condition.

2. The method according to claim 1, further comprising: The logical state of at least one of the outputs of the model is determined based on the combination of logical states and a third load condition imposed on the at least one output; The logical state of at least one of the outputs of the model is determined based on the combination of logical states and a fourth load condition imposed on the at least one output; and When at least one of the modeled defects exists in the combination of input logic states, determine whether the logic state of at least one of the outputs of the model is different under the third load condition than under the fourth load condition.

3. The method of claim 1, wherein the modeled defect is determined from the logic state of the at least one output.

4. The method of claim 3, wherein the modeled defect is determined to be detectable from the logic states of the plurality of inputs and the logic states of the at least one output.

5. The method of claim 4, further comprising: The unit is modeled using the plurality of inputs and the at least one output, without the at least one modeled defect; For the model having the modeled defects, the logical state of at least one of the outputs of the model is determined based on a predetermined combination of the logical states of at least one of the plurality of inputs; For a model that does not have the modeled defects, the logical state of at least one of the outputs of the model is determined based on the predetermined combination of the logical states of at least one of the plurality of inputs; and Whether the modeled defect is detectable is determined based on whether the logic state for at least one output of the model having the modeled defect is the same as the logic state for at least one output of the model not having the modeled defect.

6. The method of claim 1, further comprising indicating in a defect detection table whether the modeled defect: It can be detected under all input load conditions; It is detectable under some input load conditions, but not under other load conditions; or It is not detectable under any of the input load conditions.

7. The method of claim 6, further comprising indicating in a dynamic defect detection record whether the modeled defect is detectable, the dynamic defect detection record having defect entries for each unique combination of input logic states, input load conditions, and output load conditions.

8. A system comprising: A memory used to store whether a modeled defect in a cell of an integrated circuit can be detected under a predetermined combination of applied input logic states; Processor, which is coupled to the memory to: Store the determination of whether the modeled defect can be detected; Modeling a cell in an integrated circuit design using multiple inputs and at least one output; The unit is modeled using at least one modeled defect; The logic state of at least one of the model's outputs is determined based on a first load condition imposed on at least one of the plurality of inputs, on which the logic state of at least one output is based. The logic state of at least one of the outputs of the model is determined based on the logic state of at least one of the plurality of inputs and the logic state of the at least one output, which is based on a second load condition imposed on at least one of the plurality of inputs. When at least one of the modeled defects exists in the combination of input logic states, determine whether the logic state of at least one of the outputs of the model under the second load condition is different from the logic state of at least one of the outputs of the model under the first load condition.

9. The system of claim 8, wherein the processor is further configured to: The logical state of at least one of the outputs of the model is determined based on the combination of logical states and a third load condition imposed on the at least one output; The logical state of at least one of the outputs of the model is determined based on the combination of logical states and a fourth load condition imposed on the at least one output; and When the combination of at least one of the modeled defects with respect to the input logic state exists in the model, determine whether the logic state of at least one of the outputs of the model is different under the third load condition than under the fourth load condition.

10. The system of claim 8, wherein the processor is further configured to determine from the logic state of the at least one output whether the modeled defect is detectable.

11. The system of claim 10, wherein the processor is further configured to determine whether the modeled defect is detectable from the logic states of the plurality of inputs and the logic states of the at least one output.

12. The system of claim 11, wherein the processor is further configured to: The unit is modeled using the plurality of inputs and the at least one output, without the at least one modeled defect; For the model having the modeled defects, the logical state of at least one of the outputs of the model is determined based on the predetermined combination of the logical states of at least one of the plurality of inputs; For a model that does not have the modeled defects, the logical state of at least one of the outputs of the model is determined based on the predetermined combination of the logical states of at least one of the plurality of inputs; and Whether the modeled defect is detectable is determined based on whether the logic state for at least one output of the model having the modeled defect is the same as the logic state for at least one output of the model not having the modeled defect.

13. The system of claim 8, wherein the processor is further configured to indicate in a defect detection table whether the modeled defect: It can be detected under all input load conditions; It is detectable under some input load conditions, but not under other load conditions; or It is not detectable under any of the input load conditions.

14. The system of claim 13, wherein the processor is further configured to indicate in a dynamic defect detection record whether the modeled defect is detectable, the dynamic defect detection record having defect entries for each unique combination of input logic states, input load conditions, and output load conditions.

15. A non-transitory computer-readable medium comprising stored instructions that, when executed by a processor, cause the processor to perform the following operations: Store the determination of whether the modeled defect can be detected; Modeling a cell in an integrated circuit design using multiple inputs and at least one output; The unit is modeled using at least one modeled defect; The logic state of at least one of the model's outputs is determined based on a first load condition imposed on at least one of the plurality of inputs, on which the logic state of at least one output is based. The logic state of at least one of the outputs of the model is determined based on the logic state of at least one of the plurality of inputs and the logic state of the at least one output, which is based on a second load condition imposed on at least one of the plurality of inputs. When at least one of the modeled defects exists in the combination of input logic states, determine whether the logic state of at least one of the outputs of the model under the second load condition is different from the logic state of at least one of the outputs of the model under the first load condition.

16. The non-transitory computer-readable medium of claim 15, further causing the processor to: The logical state of at least one of the outputs of the model is determined based on the combination of logical states and a third load condition imposed on the at least one output; The logical state of at least one of the outputs of the model is determined based on the combination of logical states and a fourth load condition imposed on the at least one output; and When the combination of at least one of the modeled defects with respect to the input logic state exists in the model, determine whether the logic state of at least one of the outputs of the model is different under the third load condition than under the fourth load condition.

17. The non-transitory computer-readable medium of claim 15, further causing the processor to determine from the logic state of the at least one output whether the modeled defect is detectable.

18. The non-transitory computer-readable medium of claim 17, further causing the processor to determine whether the modeled defect is detectable from the logical states of the plurality of inputs and the logical states of the at least one output.

19. The non-transitory computer-readable medium of claim 18, further causing the processor to: The unit is modeled using the plurality of inputs and the at least one output, without the at least one modeled defect; For the model having the modeled defects, the logical state of at least one of the outputs of the model is determined based on a predetermined combination of the logical states of at least one of the plurality of inputs; For a model that does not have the modeled defects, the logical state of at least one of the outputs of the model is determined based on the predetermined combination of the logical states of at least one of the plurality of inputs; and Whether the modeled defect is detectable is determined based on whether the logic state for at least one output of the model having the modeled defect is the same as the logic state for at least one output of the model not having the modeled defect.

20. The non-transitory computer-readable medium of claim 19, further causing the processor to indicate in a defect detection table whether the modeled defect: It can be detected under all input load conditions; It is detectable under some input load conditions, but not under other load conditions; or It is not detectable under any of the input load conditions.

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