A layout reinforcement method for SET effect

Abstract

The present invention discloses a layout reinforcement method for SET effect, which includes forming a layout structure with SET reinforcement effect by at least one of seamless well / substrate contact and split active area on the basis of the layout design of standard cells after adding well contact and substrate contact reinforcement, wherein seamless well / substrate contact refers to canceling the shallow trench isolation STI between the well / substrate contact and the active area, and splitting the active area refers to splitting a wider transistor into several narrower transistors. The present invention aims to solve the problem that the SET effect of global signals such as clock trees and reset networks will have a serious impact on the whole chip, and to reinforce such global signals.

Description

Technical Field

[0001] The present invention relates to integrated circuit design technology, and in particular to a layout reinforcement method for SET (single event transient pulse) effect. Background Art

[0002] During the manufacturing process of integrated circuits, heavy ions from space, alpha particles, and neutrons bombarding sensitive nodes of integrated circuits will directly or indirectly cause soft errors in integrated circuits. With the continuous reduction of processes, the increasing complexity of integrated circuits, the continuous reduction of power supply voltages, and the continuous increase in operating frequencies, soft errors have gradually become the most important reliability issue in deep submicron processes. When the process is reduced to the deep submicron stage, single event upsets (SEU), single event transient pulses (SET), and multiple bit upsets (MBU) become the main sources of soft errors. As the integrated circuit manufacturing process continues to shrink to the nanometer scale, SET has become more and more serious and has become the first source of soft errors.

[0003] Charged particles bombarding sensitive nodes of a circuit will generate a transient pulse. If a transient pulse occurs at a sensitive node of a sequential circuit such as a storage unit, latch, or trigger and collects enough charge, an SEU will occur, and the transient pulse will evolve into a "persistent" error. The erroneous data may not be restored until the data is rewritten. If a transient pulse occurs at a combinatorial logic node and collects enough charge, it will propagate downward along the data path and may be latched by the next level sequential unit, becoming a "persistent" error. This type of transient pulse occurring at a combinatorial logic node is called a SET.

[0004] For SET to be captured by the next-level sequential unit, at least four conditions must be met: (1) Particle bombardment must generate a pulse that can propagate along the circuit, that is, the generated pulse has sufficient width and height; (2) There must be a sensitization path from the bombarded node to the next-level sequential unit; (3) When SET propagates to the next-level sequential unit, it must have sufficient width and height to change the state of the sequential unit, that is, meet the setup and hold time requirements of the sequential unit; (4) In synchronous circuits, SET must arrive at the valid clock edge. When the SET pulse width generated at the bombarded node is small, the width continues to decrease during the propagation process until it eventually disappears. Therefore, how to reduce the SET pulse width and achieve the final effect of layout reinforcement has become a key technical issue that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is as follows: In view of the above-mentioned problems existing in the prior art, a layout reinforcement method for the SET effect is provided, aiming to solve the problem that the SET effect of global signals such as clock trees and reset networks will have a serious impact on the entire chip, and to reinforce such global signals.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A layout reinforcement method for SET effect includes: on the basis of the layout design of a standard unit after adding well contact and substrate contact reinforcement, forming a layout structure with SET reinforcement effect by at least one of seamless well / substrate contact and segmented active area.

[0008] Optionally, the seamless well / substrate contact refers to eliminating the shallow trench isolation STI between the well / substrate contact and the active region, so that the well / substrate contact is close to the active region to increase the control capability of the well / substrate contact over the potential of the body region.

[0009] Optionally, after the shallow trench isolation STI between the well / substrate contact and the active area is removed, the well contact and the substrate contact are extended toward the middle of the layout design at the same time, and are directly connected to the source of the PMOS transistor and the NMOS transistor of the standard cell respectively.

[0010] Optionally, the split active area refers to splitting a wider transistor into several narrower transistors, and the split transistors are connected in parallel and replace the original wider transistor, so as not to affect the function of the circuit. The transistor refers to a PMOS transistor or an NMOS transistor.

[0011] Optionally, when the wider transistor is split into a plurality of narrower transistors, the split transistors are isolated by shallow trench isolation (STI).

[0012] Optionally, when the wider transistor is split into a plurality of narrower transistors, the split transistors share a common gate.

[0013] Optionally, when the wider transistor is split into a plurality of narrower transistors, the split transistors are distributed in an abacus shape in the layout with a common gate as the center.

[0014] In addition, the present invention also provides an integrated circuit, wherein the integrated circuit comprises a standard cell, and the standard cell is a standard cell reinforced by the layout reinforcement method for the SET effect.

[0015] Optionally, the standard cell is an INV_8 cell.

[0016] Optionally, the INV_8 unit includes a PMOS transistor and an NMOS transistor connected in parallel to each other.

[0017] Compared with the prior art, the present invention has the following advantages: the present invention includes, on the basis of the layout design of the standard unit after adding well contacts and substrate contacts for reinforcement, forming a layout structure with SET reinforcement effect by at least one of seamless well / substrate contacts and splitting the active area. Through the above means, the SET pulse width can be effectively reduced, and the problem that the SET effect of global signals such as clock trees and reset networks will have a serious impact on the entire chip can be solved, and such global signals can be reinforced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of conventional well contact and radiation resistance of NMOS (P+ and STI should be adjacent in the figure).

[0019] Figure 2 Schematic diagram of the radiation resistance of the NMOS seamless well / substrate contact in this embodiment.

[0020] Figure 3 FIG. 4 is a schematic diagram of dividing the active area of ​​the MOS tube in this embodiment.

[0021] Figure 4 is a circuit diagram of the INV_8 unit in this embodiment.

[0022] Figure 5 Physical layout of the INV_8 cell with added well contact and substrate contact reinforcement.

[0023] Figure 6 Physical layout of the INV_8 cell designed with only seamless well / substrate contact reinforcement.

[0024] Figure 7 The physical layout of the INV_8 unit with only split active area reinforcement design.

[0025] Figure 8 The physical layout of the INV_8 cell after combining seamless well / substrate contact and segmented active area reinforcement.

[0026] Fig. 9 This is the experimental simulation process in this embodiment. DETAILED DESCRIPTION

[0027] This embodiment provides a layout reinforcement method for SET effect, including: on the basis of the layout design of the standard unit after adding well contact and substrate contact reinforcement, by at least one of seamless well / substrate contact and splitting the active area, forming a layout structure with SET reinforcement effect.

[0028] In this embodiment, seamless well / substrate contact refers to canceling the shallow trench isolation STI (Shallow trench isolation) between the well / substrate contact and the active area. In the standard cell, the well contact (PMOS device) and the substrate contact (NMOS device) are isolated from the active area using shallow trench isolation technology STI (Shallow trench isolation), which can make the well / substrate contact close to the active area to increase the control capability of the well / substrate contact over the bulk potential.

[0029] In this embodiment, after the shallow trench isolation STI between the well / substrate contact and the active area is removed, the well contact and the substrate contact are extended toward the middle of the layout design at the same time, and are directly connected to the source of the PMOS transistor and the NMOS transistor of the standard cell respectively.

[0030] Figure 1 Shown is a cross-sectional view of the conventional connection method of an NMOS tube for comparison. Studies have shown that charge collection caused by particle bombardment of sensitive nodes will cause single-particle effects, and the amount of charge collection will directly affect the pulse width and peak value of the single-particle transient. The greater the charge collection amount of the device, the wider the pulse width of the single-particle transient, the higher the peak value, and the easier it is to cause soft errors. Under traditional bulk silicon processes, device charge collection mechanisms include drift, diffusion, and bipolar amplification effects, among which bipolar amplification effects dominate. In this embodiment, seamless well / substrate contact is used to reduce the bipolar amplification effect, thereby reducing the SET pulse width, such as Figure 2 As shown. The seamless well / substrate contact method may result in the length of the transistor not being able to use the minimum gate length. Under S40LL, the minimum gate length is 40nm. If the method of this embodiment is used, the length of the transistor close to seamless must be more than 60nm to pass the design rule check (DRC).

[0031] In this embodiment, splitting the active area refers to splitting a wider transistor into several narrower transistors, and the split transistors are connected in parallel and replace the original wider transistors, so as not to affect the function of the circuit. The transistors refer to PMOS transistors or NMOS transistors.

[0032] In this embodiment, when a wider transistor is split into a plurality of narrower transistors, the split transistors are isolated by shallow trench isolation (STI).

[0033] In this embodiment, when a wider transistor is split into a plurality of narrower transistors, the split transistors share a common gate.

[0034] In this embodiment, when a wider transistor is split into several narrower transistors, the split transistors are arranged in an abacus shape with a common gate as the center in the layout. Based on the layout design of the standard unit after adding well contacts and substrate contacts for reinforcement, a layout structure with a certain SET reinforcement effect is formed by seamless well / substrate contacts and segmented active areas, and the layout shape is like an abacus.

[0035] Many studies have shown that due to the charge collection mechanism of the "funnel effect" and the parasitic bipolar amplification effect of bulk silicon devices, the device drain region has always been the most sensitive area to SET. When heavy ions bombard the center of the device drain region, the charge collection amount is the largest. And the size of the device charge collection amount is positively correlated with the drain area. Therefore, reducing the device drain area can effectively reduce the device charge collection amount, thereby suppressing the width and peak value of the single-particle transient pulse. Based on this, the present invention splits the transistor in width. When the MOSFET width is large, resulting in an excessively large sensitive area, the wider transistor can be split into several narrower transistors by dividing the active area. The split transistors are connected in parallel to replace the original wider transistors, thereby not affecting the function of the circuit. The split transistors are isolated by STI. When heavy ions bombard sensitive nodes, because the drain area of ​​the transistor is reduced and the transistors are isolated from each other, only a small part of the charge deposited by a single particle will be collected by the drain of the transistor. This will reduce the collection of charge, thereby achieving the purpose of reducing the SET pulse width. Such as Figure 3 Zhong (1) and Figure 3 The transistor shown in (2) has the same W and L. By dividing the active area, Figure 3 The layout shown in (2) effectively reduces the charge collection area when bombarded, thereby achieving the purpose of reducing the pulse width when bombarded.

[0036] In addition, this embodiment further provides an integrated circuit, wherein the integrated circuit includes a standard cell, and the standard cell is a standard cell reinforced by the above-mentioned layout reinforcement method for the SET effect.

[0037] In this embodiment, the standard unit is the INV_8 unit. Figure 4 As shown, in this embodiment, the INV_8 unit includes a PMOS transistor and an NMOS transistor connected in parallel with each other.

[0038] Table 1 shows the reinforcement methods used for the four comparative units in this embodiment. INV_8_A, INV_8_B, INV_8_C and INV_8_D are bombarded with heavy ions with a bombardment energy of LET=37MeV·cm2 / mg respectively. The simulation conditions are shown in Table 2.

[0039] Table 1: Description of reinforcement methods.

[0040] unit Reinforcement method INV_8_A No reinforcement bombardment INV_8_B Only seamless well / substrate contact reinforcement INV_8_C Only split active area reinforcement INV_8_D Seamless well / substrate contact reinforcement + split active area reinforcement

[0041] Table 2: Heavy ion bombardment simulation conditions.

[0042] Technology SMIC40LL Craft Corner TT Voltage 1.1V temperature 25℃

[0043] Table 3 shows the pulse widths of the four units after heavy ion bombardment. By comparing the results of INV_8_B and INV_8_A, it can be concluded that the seamless contact reinforcement design reduces the pulse width to a certain extent, and the reinforcement effect of PMOS is more obvious than that of NMOS; by comparing the results of INV_8_C and INV_8_A, it can be concluded that the abacus-shaped reinforcement design reduces the pulse width to a certain extent, and the reinforcement effect of NMOS is more obvious than that of PMOS; by comparing the results of INV_8_D and INV_8_A, it can be concluded that the combination of seamless contact and abacus-shaped reinforcement design can greatly reduce the pulse width of PMOS and NMOS at the same time, thereby obtaining a good SET reinforcement effect.

[0044] Table 3: Pulse width (in ps).

[0045] unit Bombarding PMOS Bombarding NMOS INV_8_A 200.5 224.7 INV_8_B 105.7 184.5 INV_8_C 121.9 68.3 INV_8_D 70.4 61.3

[0046] Figure 5 The physical layout of the INV_8 unit without seamless well / substrate contact reinforcement and split active area reinforcement, only adding well contact and substrate contact reinforcement. As can be seen from the figure, the well contact and substrate contact are located at the top and bottom of the layout respectively, and are actively connected to the source of PMOS and NMOS respectively through the metal layer.

[0047] Figure 6 The physical layout of the INV_8 unit with only seamless well / substrate contact reinforcement design. As can be seen from the figure, the well contact and substrate contact extend to the middle of the layout at the same time, and are directly connected to the source of PMOS and NMOS respectively. This setting can make the well / substrate contact better control the body potential, thereby effectively suppressing the bipolar amplification effect.

[0048] Figure 7 The physical layout of the INV_8 unit, which is designed for split active area reinforcement only, shows that the active width of a single MOS is small, and multiple MOS tubes share the same gate. Looking at the entire unit layout, its shape is similar to an abacus. A large number of research results show that when the drain area is reduced, the collected charge will also be reduced when a single particle bombards, and the pulse width generated will also be reduced.

[0049] Figure 8The physical layout of the INV_8 cell after the seamless well / substrate contact and split active area reinforcement. This reinforcement design fully combines the advantages of seamless contact and abacus-shaped reinforcement.

[0050] Fig. 9 This is the experimental simulation process. The Sentaurus TCAD tool released by Synopsys, a well-known IC design software developer, is used to construct a 3D device model and perform single-particle simulation. In order to simulate and analyze the single-particle effect of the INV_8 unit under the 40nm process, Figure 4 As shown in the figure, the deficiencies of the experimental simulation include: (1) the layout of INV_8_A, INV_8_B and INV_8_C units was drawn using Virtuoso software; (2) based on the connection relationship and spacing between units given in the layout, the drawn layout was converted into a 3D TCAD model; (3) the LET was 37 MeV cm 2 / mg heavy ions bombarded the drain centers of the PMOS transistor and NMOS transistor of the standard cell respectively; (4) the observed LET was 37MeV·cm 2 / mg, the pulse width of the node produced by heavy ion bombardment changes. The results obtained in this embodiment are as follows:

[0051] (1) In 40nm process, bombardment energy LET = 37 MeV cm 2 / mg heavy ions bombarded the drain center of the unreinforced INV_8 cell and the cell reinforced with seamless well / substrate contact. Compared with the unreinforced cell, the SET pulse width generated by the cell reinforced with seamless well / substrate contact was reduced to a certain extent. The SET pulse of the PMOS device was reduced by 47.3%, and the SET pulse of the NMOS device was reduced by 17.9%.

[0052] (2) In 40nm process, bombardment energy LET = 37 MeV cm 2 / mg heavy ions bombarded the drain center of the unreinforced and split active area reinforced INV_8 cells respectively. Compared with the unreinforced cells, the SET pulse width generated by the split active area reinforced cells was reduced. The SET pulse of the PMOS device was reduced by 39.2%, and the SET pulse of the NMOS device was reduced by 69.6%.

[0053] (3) At 40nm process, bombardment energy LET = 37 MeV cm 2 / mg heavy ions bombarded the drain center of the unreinforced INV_8 cell and the cell reinforced with a combined split active region and seamless well / substrate contact. Compared with the unreinforced cell, the cell reinforced with a combined split active region and seamless well / substrate contact produced a narrower SET pulse width. The SET pulse of the PMOS device was reduced by 64.9%, and the SET pulse of the NMOS device was reduced by 72.7%.

[0054] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0055] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A layout reinforcement method for SET effect, characterized in that: include: Based on the layout design of the standard cell after adding well contact and substrate contact reinforcement, a layout structure with SET reinforcement effect is formed by at least one of seamless well / substrate contact and segmented active area; The seamless well / substrate contact refers to cancelling the shallow trench isolation STI between the well / substrate contact and the active area, so that the well / substrate contact is close to the active area to increase the control capability of the well / substrate contact over the body area potential. After cancelling the shallow trench isolation STI between the well / substrate contact and the active area, the well contact and the substrate contact are extended toward the middle of the layout design at the same time, and are directly connected to the source of the PMOS transistor and the NMOS transistor of the standard cell respectively. The splitting of the active area refers to splitting a wider transistor into several narrower transistors, and the split transistors are connected in parallel and replace the original wider transistor, so as not to affect the function of the circuit. The transistor refers to a PMOS transistor or an NMOS transistor. When the wider transistor is split into several narrower transistors, the split transistors are isolated by shallow trench isolation STI. When the wider transistor is split into several narrower transistors, the split transistors share a gate. When the wider transistor is split into several narrower transistors, the split transistors are distributed in an abacus shape in the layout with a common gate as the center.

2. An integrated circuit comprising a standard cell, characterized in that: The standard cell is a standard cell reinforced by the layout reinforcement method for SET effect as described in claim 1.

3. The integrated circuit according to claim 2, characterized in that The standard cell is an INV_8 cell.

4. The integrated circuit according to claim 3, characterized in that The INV_8 unit includes a PMOS transistor and an NMOS transistor connected in parallel to each other.

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