Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device has a source region and a drain region, a gate structure and a metal line located in a substrate. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metal line is located above the source region and the drain region and the gate structure and is electrically connected to the drain region or the source region. The source region includes a doped region, the doped region having a disconnection region located between two opposite ends of the doped region. The metal line extends from the drain region, crosses the gate structure, crosses the disconnection region and exceeds the source region.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Metal-oxide-semiconductor (MOS) field effect transistor (MOSFET) is an important semiconductor device used in very large integrated circuits such as microprocessors. MOSFET is a device composed of four terminals, usually identified as source, base (bulk), gate and drain, where the voltage on the gate controls the current flowing from the drain to the source. Summary of the invention

[0003] According to some embodiments, a semiconductor device includes a drain region and a source region, a gate structure, and a metal line in a substrate. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metal line is located above the source region and the drain region and the gate structure and is electrically connected to the drain region or the source region. The source region includes a doped region having a disconnection region between two opposite ends of the doped region. The metal line extends from the drain region, crosses the gate structure, crosses the disconnection region, and exceeds the source region.

[0004] According to some embodiments, a semiconductor device includes a substrate having a first conductivity type doped well in the substrate, a second conductivity type doped well in the first conductivity type doped well, and an isolation structure on the substrate, the isolation structure defining a first region and a second region of the substrate. A first conductivity type doped drain region is located in the first conductivity type doped well and in the first region of the substrate. A first conductivity type doped source region is located in the second conductivity type doped well and in the second region of the substrate, and surrounds the first conductivity type doped drain region. A gate structure is partially disposed on the substrate and partially disposed on one of the isolation structures. The gate structure is disposed between the first conductivity type doped source region and the first conductivity type doped drain region, and the first conductivity type doped source region surrounds the gate structure. A channel region is located below the gate structure and in the second conductivity type doped well. A metal line is located above the first conductivity type doped source region and the first conductivity type doped drain region and the gate structure. The metal line is electrically connected to the first conductivity type doped drain region. The first conductivity type doped source region has a split loop-shaped top view divided by a disconnection region. The metal line extends across the gate structure and across the disconnect region and beyond the first conductivity type doped source region.

[0005] According to some embodiments, a method for manufacturing a semiconductor device includes at least the following steps. A first conductive type doped well is formed in a substrate. A second conductive type doped well is formed in the first conductive type doped well in the substrate. An isolation structure is formed on the substrate to define a first region and a second region of the substrate. A gate structure and a conductive semiconductor pattern are formed on the isolation structure and on the substrate. A first conductive type doped region and a second conductive type doped region are formed in the first region and the second region of the substrate. At least one metal line is formed above the gate structure and across the gate structure. The at least one metal line extends across the first conductive type doped region and the second conductive type doped region in the second region and is electrically connected to at least one of the first conductive type doped region and the second conductive type doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced to make the discussion clear.

[0007] Figures 1 to 8 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 1A , Figure 2A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A is a schematic, exemplary top view of a portion of the structure of a semiconductor device.

[0009] Fig. 9 is a schematic top view showing a portion of a structure including a high voltage semiconductor device according to some embodiments of the present disclosure.

[0010] Fig.10 is a schematic enlarged top view showing a doped ring portion of a structure according to some embodiments of the present disclosure.

[0011] Fig.11 is a schematic top view showing the relative positions and shapes of the doped ring region and the gate structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are also considered. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] In addition, for ease of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe similar or different elements or features shown in the figures, and may be used interchangeably depending on the order of existence or the context of description.

[0015] It should be understood that the following embodiments of the present disclosure provide applicable concepts that can be implemented in a variety of specific contexts. The specific embodiments discussed herein are merely illustrative and relate to integrated structures that include more than one type of semiconductor device, and are not intended to limit the scope of the present disclosure. The embodiments of the present disclosure will describe exemplary manufacturing processes for integrated structures formed using one or more MOS devices and integrated structures made according to the manufacturing processes. Certain embodiments of the present disclosure relate to structures including semiconductor MOS devices such as laterally diffused MOS (LDMOS) and other semiconductor devices. The substrate and / or wafer may include one or more types of integrated circuits or electronic components in the integrated circuits. The semiconductor device may be formed on a bulk semiconductor substrate or a silicon / germanium on insulator substrate. The embodiments are intended to provide further explanation, but are not intended to limit the scope of the present disclosure.

[0016] Figures 1 to 8 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0017] Reference Figure 1 In some embodiments, a substrate 100 is provided. Figure 1 As shown, in some embodiments, the substrate 100 includes a device region DR, and the device region DR may be defined by an isolation structure or isolation region that separates and isolates the active region. In some embodiments, the substrate 100 may further include other active components such as transistors, diodes, optoelectronic devices, or the like, and / or passive components such as capacitors.

[0018] In some embodiments, substrate 100 is a semiconductor substrate. In one embodiment, substrate 100 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 100 may include a doped semiconductor substrate. In one embodiment, substrate 100 includes a P-type semiconductor substrate. In one embodiment, substrate 100 includes an N-type semiconductor substrate. For N-type doping, arsenic or phosphorus is added to a semiconductor material such as silicon. For P-type doping, boron or gallium is used as a dopant added to a semiconductor material such as silicon.

[0019] In some alternative embodiments, the substrate 100 is made of: other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

[0020] exist Figure 1 In some embodiments, the substrate 100 includes a first conductivity type semiconductor substrate, and the substrate 100 includes a deep second conductivity type doped well 102 and a second conductivity type doped well 104 formed therein. In one embodiment, the first conductivity type is P type, and the second conductivity type is N type. In another embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0021] In some embodiments, substrate 100 is a P-type silicon substrate, and deep second conductivity type doped well 102 is a deep N-type well and second conductivity type doped well 104 is an N-type well.

[0022] In some embodiments, an ion implantation process is performed through a mask pattern (not shown) covering the substrate 100 to dope the second conductivity type dopant into the substrate 100 to form the deep second conductivity type doped well 102 and the second conductivity type doped well 104. In one embodiment, an ion implantation process is performed to dope the N-type dopant into the substrate 100 to sequentially form an N-type well (the second conductivity type doped well 104) and a deep N-type well (the deep second conductivity type doped well 102). In some embodiments, the deep second conductivity type doped well 102 (e.g., the deep N-type well) is formed at a deeper depth than the depth of the second conductivity type doped well 104 (e.g., the N-type well), but the second conductivity type doped well 104 (e.g., the N-type well) is formed at a larger span than the span of the deep second conductivity type doped well 102 (e.g., the deep N-type well). For example, the N-type dopant is phosphorus or arsenic.

[0023] Reference Figure 1 , after forming the deep second conductivity type doped well 102 and the second conductivity type doped well 104, a first conductivity type body well 106 is formed and a first conductivity type doped well 108 is formed. In some embodiments, the first conductivity type body well 106 is a P-type body well and the first conductivity type doped well 108 is a P-type doped region. In one embodiment, an ion implantation process is performed to dope a P-type dopant into the substrate 100 to form the P-type body well 106 and the P-type well (the first conductivity type doped well 108). For example, the P-type dopant is boron or gallium.

[0024] Figure 1A yes Figure 1 A schematic top view of an exemplary embodiment of the structure shown. Figure 1A From the schematic top view, the deep second conductivity type doped well 102 is formed as a circular doped region with a deeper depth but a smaller span, and the second conductivity type doped well 104 is formed as a circular doped region with a shallower depth and a larger span at a position overlapping the deep second conductivity type doped well 102. From the schematic top view, the deep second conductivity type doped well 102 and the second conductivity type doped well 104 may be shaped like concentric circles.

[0025] In some embodiments, reference Figure 1A, the first conductive type body well 106 is formed into a ring shape having a hoop body portion 106U and an inner extended brim portion 106E extending toward the center of the ring. In some embodiments, the first conductive type body well 106 is located in the deep second conductive type doped well 102 and the second conductive type doped well 104. In some embodiments, the first conductive type body well 106 is located at the bottom of the second conductive type doped well 104, and the hoop body portion 106U extending from the bottom of the second conductive type doped well 104 to the substrate surface 100T has an extension depth greater than the extension depth of the brim portion 106E. In one embodiment, referring to Figure 1 , the outer side surface 106S of the first conductivity type body well 106 is substantially aligned with the side surface 102S of the deep second conductivity type doped well 102. In one embodiment, the bottom surface 106B of the first conductivity type body well 106 is flush with the bottom surface 104B of the second conductivity type doped well 104. In some embodiments, the depth of the hoop body portion 106U of the first conductivity type body well 106 is about the same as the depth of the second conductivity type doped well 104.

[0026] In some embodiments, reference Figure 1 and Figure 1A , the first conductivity type doped well 108 is formed in a ring shape located within the second conductivity type doped well 104, and is located within the span of the first conductivity type body well 106, but is separated from the first conductivity type body well 106. In some embodiments, the first conductivity type doped well 108 is located at the center of the first conductivity type body well 106 and between the extended ring portions 106E. In one embodiment, the depth of the first conductivity type doped well 108 is shallower than the depths of the first conductivity type body well 106 and the second conductivity type doped well 104. After forming the first conductivity type body well 106 and the first conductivity type doped well 108, the second conductivity type doped well 104 is defined as an outer portion 1040 located outside the first conductivity type body well 106, an inner portion 1041 located inside the first conductivity type body well 106, and a central portion 1042 located inside the first conductivity type doped well 108.

[0027] like Figure 2As shown, in some embodiments, more than one isolation structure 109, 110 is formed in the substrate 100. In some embodiments, the isolation structures 109, 110 are oxide isolation structures. The formation of the oxide isolation structure includes, for example, performing a thermal oxidation process to oxidize the uncovered surface of the substrate 100. In one embodiment, the thermal oxidation process is, for example, a local oxidation of silicon (LOCOS) process or a shallow trench isolation (STI) process. In some embodiments, the formation of the isolation structures 109, 110 includes using a mask pattern (not shown) formed on the substrate 100 to expose a portion of the substrate surface to define an area in which the isolation structure is subsequently formed, and then performing a thermal oxidation process. In one embodiment, the mask pattern may include a pad oxide layer (not shown) and a silicon nitride layer (not shown), and after the thermal oxidation process, the two layers are removed sequentially.

[0028] exist Figure 2 In the embodiment, at least one isolation structure 110 is formed in a closed region (i.e., inner portion 1041) surrounded by a first conductive type body well 106 and located between the first conductive type body well 106 and the first conductive type doped well 108. In one embodiment, one end of the isolation structure 110 physically contacts the outer edge of the first conductive type doped well 108, while the other end of the isolation structure 110 is located at a position close to the first conductive type body well 106 but spaced apart from the first conductive type body well 106. In addition, another isolation structure 109 is located above the second conductive type doped well 104 or directly above the outer portion 1040 outside the first conductive type body well 106.

[0029] Figure 2 The number of isolation structures 109 and 110 shown in the figure is for illustration only. In some alternative embodiments, more or fewer isolation structures may be formed according to actual design requirements. In some embodiments, the isolation structures 109 and 110 are shaped like rings, strips, or blocks, and are arranged next to or in parallel with the active area. It should be understood that the shape and size of the isolation structures are not limited by the embodiments described herein. In some embodiments, as shown in FIG. Figure 2 As shown, top surfaces 109T, 110T of the isolation structures 109, 110 are higher than the top surface of the substrate 100 (substrate surface 100T).

[0030] Figure 2A yes Figure 2 Schematic top view of an exemplary embodiment of the structure shown. Figure 2A and Figure 2 , active areas AR1 and AR2 are defined by isolation structures 109 and 110, and an uncovered portion (not covered by isolation structures 109 and 110) or an exposed portion of the substrate surface is defined as active area AR1 (defined by isolation structure 110) and active area AR2 (sandwiched between isolation structures 109 and 110 and defined by isolation structures 109 and 110). In some embodiments, the active area AR1 defined by isolation structure 110 is circular, and the active area AR2 sandwiched between isolation structures 109 and 110 and defined by isolation structures 109 and 110 is ring-shaped.

[0031] Reference Figure 3 In some embodiments, an oxide layer 111 is formed on the exposed substrate surface 100T. The formation of the oxide layer 111 may include performing a thermal oxidation process on the substrate 100. It should be understood that the thickness of the oxide layer can be adjusted by the temperature, duration and other conditions of the thermal oxidation process, and the thermal process for forming the oxide layer 111 may utilize conditions different from those used in the thermal oxidation process for forming the isolation structure 110. In some embodiments, the oxide layer 111 is formed not only on the active regions AR1 and AR2 (i.e., the exposed substrate surface 100T), but also on the isolation structure 110 or the non-active region with a smaller thickness. Thereafter, a conductive semiconductor material layer 113 is formed on the substrate 100 to cover the isolation structure 110 and the oxide layer 111. In some embodiments, the conductive semiconductor material layer 113 includes a polysilicon layer. In some embodiments, the polysilicon layer is an undoped polysilicon layer formed by, for example, chemical vapor deposition (CVD). In some embodiments, the polysilicon layer is a doped polysilicon layer formed by, for example, CVD and in-situ doping.

[0032] Reference Figure 4 A patterning process is performed to pattern the conductive semiconductor material layer 113 into conductive blocks 114, 116 and 118 and to pattern the oxide layer 111 into a gate oxide layer 112. In some embodiments, the conductive block 114 is located on the isolation structure 109 above the outer portion 1040 of the second conductivity type doped well 104.

[0033] Figure 4A yes Figure 4 Schematic top view of an exemplary embodiment of the structure shown. FIG. 4A to FIG. 44A , and may function as a field plate. During the patterning process, most of the oxide layer 111 located on the active regions AR1 and AR2 is removed, except that the portion of the oxide layer 111 located on the active regions AR2 is retained and becomes the gate oxide layer 112. In some embodiments, the conductive blocks 114 and 118 are in direct contact with the underlying isolation structures 109 and 110. In some embodiments, the conductive blocks 114 and 118 are located on the underlying isolation structures 109 and 110 with an oxide layer between them and the underlying isolation structures 109 and 110. In some embodiments, after patterning, a stack (gate structure 115) of a gate oxide layer 112 and a conductive block 116 located on the patterned gate oxide layer 112 is formed, and such a stack is located on the isolation structure 110, extends over the inner portion 1041 of the second conductive type doped well 104, and reaches the first conductive type body well 106. In one embodiment, the stack (gate structure 115) of the gate oxide layer 112 and the conductive block 116 is formed as follows: Figure 4A The ring shape shown is formed and can function as a gate structure. That is, the conductive block 116 and the gate oxide layer 112 function as the gate electrode and gate dielectric layer of the gate stack. Since the conductive blocks 114, 116 and 118 are formed from the same layer (conductive semiconductor material layer 113) and can therefore be regarded as the first group of conductive blocks 120. When forming the active area AR2 (see Figure 2 ) of the stack (gate structure 115), as Figure 4 and Figure 4A As shown, a portion of the first conductivity type body well 106 is exposed as a ring and is defined as an active area AR3.

[0034] Figure 5A yes Figure 5 Schematic top view of an exemplary embodiment of the structure shown. In some embodiments, reference Figure 5 and Figure 5A , a semiconductor pattern 125 is formed on the isolation structure 110, and the semiconductor pattern 125 is located between the conductive block 118 and the conductive block 116 of the stack (gate structure 115). In some embodiments, referring to Figure 5A, the semiconductor pattern 125 can be formed in a spiral shape or a coil shape and plays the role of a passive element such as a resistor or an inductor. In some embodiments, the formation of the semiconductor pattern 125 includes forming a conductive semiconductor material (not shown) covering the conductive block 120 and the isolation structure 110 on the substrate 100, and then patterning the conductive semiconductor material into the semiconductor pattern 125. In some embodiments, the formation of the semiconductor pattern 125 further includes performing an implantation process to dope the conductive semiconductor material. In some embodiments, the conductive semiconductor material includes polysilicon formed by CVD. In some embodiments, the conductive semiconductor material includes amorphous silicon formed by a furnace. In some embodiments, the conductive semiconductor material includes doped polysilicon formed by, for example, CVD and in-situ doping. In some embodiments, the patterning of the conductive semiconductor material may include performing one or more etching processes to etch the conductive semiconductor material using the same mask pattern simultaneously or sequentially.

[0035] Fig. 6A yes Figure 6 Schematic top view of an exemplary embodiment of the structure shown. Figure 6 In the active area AR3, a second conductive type doping region 132 is formed in the substrate 100 next to the stack (gate structure 115), and a second conductive type doping region 133 is formed in the substrate 100 in the active area AR1 surrounded by the isolation structure 110 and the conductive block 118. Figure 6 and Fig. 6A The second conductive type doping region 133 may be a circular doping region, which is located in the annular first conductive type doping well 108 and surrounded by the annular first conductive type doping well 108 and located in the annular conductive block 118. In some embodiments, the doping region 133 functions as a drain region. Fig. 6A From the schematic top view shown, it can be seen that the second conductive type doping region 132 is formed as a C-shaped ring or in an open ring shape. Fig. 6A and Fig.10From the schematic top view shown, the second conductive type doping region 132 may be shaped like a ring having a break portion (break) BK (unprocessed area of ​​the first conductive type body well 106) located between the two ends 132E of the second conductive type doping region 132. That is, during the formation of the second conductive type doping region 132, no or very little second conductive type dopant is implanted into the break region. In some embodiments, the position of the break portion BK corresponds to the crossing location of the high voltage interconnection (HVI) metal line formed subsequently. In some embodiments, the doping region 132 acts as a source region.

[0036] exist Figure 6 In some embodiments, first conductivity type doping regions 134 and 136 are formed in the substrate 100 in the active regions AR1 and AR3, respectively. Figure 6 and Fig. 6A , the first conductive type doping region 134 is formed in a ring shape positioned next to the second conductive type doping region 132 and between the conductive block 114 and the second conductive type doping region 132. In some embodiments, the first conductive type doping region 136 is formed just beside the second conductive type doping region 133 and between the conductive block 118 and the second conductive type doping region 133. Fig. 9 As can be seen in FIG. 1 , in some embodiments, the first conductive type doping region 134 is formed in a ring shape that encloses a C-shaped ring region of the second conductive type doping region 132 . Fig. 9 It can also be seen in FIG. 1 that the first conductive type doping region 136 is formed in a ring shape of a circular doping region enclosing the second conductive type doping region 133 .

[0037] Reference Figure 6, doping regions 132, 133, 134 and 136 are formed in the active regions AR1 and AR3 in the substrate 100. The doping regions may be doped with dopants of different conductivity types. In some embodiments, the second conductivity type doping regions 132 and 133 are N-type doping regions, and the first conductivity type doping regions 134 and 136 are P-type doping regions. In one embodiment, phosphorus is used to dope the N-type doping regions, and boron is used to dope the P-type doping regions, for example, according to a complementary metal oxide semiconductor (CMOS) process. In some embodiments, the second conductivity type doping region 132 is an N-type doping region and acts as a source of an N-channel metal oxide semiconductor (NMOS). In some embodiments, the second conductivity type doping region 132 is a P-type doping region and acts as a source of a P-channel metal oxide semiconductor (PMOS).

[0038] In some embodiments, the second conductive type doping regions 132, 133 are formed before forming the first conductive type doping regions 134, 136. For example, by using a photoresist pattern (not shown) partially covering the substrate 100 as a mask to perform ion implantation on the exposed substrate 100 to form the doping regions of the same conductive type, and a thermal process may be performed to further drive the dopant into the substrate with a desired profile, and sequentially or individually formed as doping regions of different conductive types. In some embodiments, the doping regions 132, 133, 134, and 136 are formed in the substrate 100 at substantially the same depth. In one embodiment, the doping regions 132, 133, 134, and 136 are formed in the region exposed by the photoresist pattern, and the doping regions 132, 133, 134, and 136 are formed only in the active regions AR1 and AR3. In some embodiments, the doping regions 132, 133, 134, and 136 are shallower than the first conductive type doping well 108 and the isolation structure 110. That is, the depth of the doped regions 132, 133, 134, and 136 is less than the depth of the first conductive type doped well 108 (measured from the top surface of the substrate 100 (substrate surface 100T)). In some embodiments, the location of the ring-shaped doped region 136 substantially overlaps the location of the first conductive type doped well 108, but the ring-shaped doped region 136 has a shallower depth. In some embodiments, the second conductive type doped regions 132 and 133 are formed with a higher doping concentration than the deep second conductive type doped well 102 and the second conductive type doped well 104. In some embodiments, the first conductive type doped regions 134 and 136 are formed with a higher doping concentration than the first conductive type body well 106 and the first conductive type doped well 108.

[0039] In some embodiments, a laterally diffused metal oxide semiconductor (LDMOS) transistor structure is formed, the LDMOS transistor structure including a source region (a second conductive type doping region 132), a drain region (a second conductive type doping region 133), a gate structure 115, and a channel region CR located directly below the gate structure 115 in a first conductive type body well 106. In some embodiments, the transistor structure includes an inner portion 1041 located below the isolation structure 110, and the inner portion 1041 functions as a drift region or a lightly doped drain extension. In addition, for the transistor structure, the gate oxide layer 112 is thin over the entire channel region CR and over a portion of the drift region, but the oxide of the isolation structure 110 (e.g., LOCOS) located under the gate structure 115 has a greater thickness. Such a transistor structure can be used for electrostatic discharge (ESD) protection of high voltage devices. In the ESD protection design of high voltage applications, the LDMOS transistor structure can be used as an ESD protection device.

[0040] In some embodiments, Figure 7 In the present invention, a first interlayer dielectric layer 130 covering the conductive block 120, the semiconductor pattern 125, and the doped regions 132, 133, 134, and 136 is formed over the substrate 100 and the isolation structures 109 and 110. In some embodiments, the first interlayer dielectric layer 130 includes through-hole openings O1 and O2 formed by etching the first interlayer dielectric layer 130 using a resist pattern (not shown) as a mask. In some embodiments, the formation of the first interlayer dielectric layer 130 includes forming a dielectric material in a blanket form over the substrate 100 and patterning the dielectric material by performing one or more etching processes including anisotropic etching, reactive ion etching (RIE), isotropic etching processes, or a combination thereof, to form through-hole openings O1 and O2 in the first interlayer dielectric layer 130. In some embodiments, the through hole opening O1 exposes the doped regions 133, 132, 134 and the through hole opening O2 exposes the conductive blocks 114, 116, 118 and the semiconductor pattern 125. For example, the through hole opening O1 or O2 may be formed with an inclined sidewall profile or a substantially vertical sidewall profile. In some embodiments, the first interlayer dielectric layer 130 includes at least one dielectric material selected from silicon oxide, silicon nitride, SiC, silicon carbonitride (SiCN), or a low-k dielectric material. The low-k dielectric material has a k value lower than about 4.0 and includes, for example, carbon-containing oxides or silicate glass. In some embodiments, the first interlayer dielectric layer 130 is formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and spin-on methods. In one embodiment, the first interlayer dielectric layer 130 may include a plurality of layers composed of different dielectric materials or include an etch stop layer so that different materials are selected to achieve a suitable etching selectivity.

[0041] In some embodiments, reference Figure 7After forming the first interlayer dielectric layer 130, a first metallization pattern 140 is formed, and the metallization pattern 140 includes via portions 1402 and 1404 filling the via openings O1 and O2, and a connection trace 1406 disposed on the first interlayer dielectric layer 130. In some embodiments, the via portion 1402 is electrically connected and in contact with the doped regions 132, 133, and 134, respectively, and the via portion 1404 is electrically connected and in contact with the conductive blocks 114, 116, 118, and the semiconductor pattern 125. In an embodiment, the connection trace 1406 is electrically and physically connected to the via portions 1402 and 1404. In some embodiments, the formation of the first metallization pattern 140 includes forming a masking pattern (not shown) on the first interlayer dielectric layer 130 and forming a metal material (not shown) filling the via openings O1 and O2 on the first interlayer dielectric layer 130, removing the additional metal material, and then removing the masking pattern. For example, the via portions 1402, 1404 and the connection trace 1406 may be formed separately or in a single process, and the metal material filled into the via openings O1, O2 may be the same as or different from the metal material used to form the connection trace 1406. For example, the metal material includes copper, tungsten, cobalt, nitride or alloys thereof. In some embodiments, the metal material is formed by CVD, physical vapor deposition (PVD) or electroplating. It should be understood that the formation of the first metallization pattern 140 may include forming a barrier layer and / or an adhesion layer and / or a seed layer as part of the pattern.

[0042] Fig. 7A yes Figure 7 Schematic top view of an exemplary embodiment of the structure shown. Fig. 7A In the schematic top view shown, the connection traces 1406 of the first metallization pattern 140 include traces 1406-1, 1406-2, and 1406-3, wherein the trace 1406-1 is located at a position overlapping with and covering the active area AR1 and the conductive block 118, the trace 1406-2 is located at a position overlapping with and covering the conductive block 116, and the trace 1406-3 is located at a position overlapping with and covering the active area AR3 and the conductive block 114. It should be understood that more metal patterns such as extended metal lines or pads may be formed during the formation of the first metallization pattern 140 to achieve further external electrical connections.

[0043] In some embodiments, Figure 8In the embodiment of the present invention, a second interlayer dielectric layer 150 is formed over the first interlayer dielectric layer 130 and the substrate 100, covering the first metallization pattern 140. In some embodiments, the second interlayer dielectric layer 150 is formed with a through hole opening O3. In some embodiments, the formation of the second interlayer dielectric layer 150 includes forming a dielectric material in a blanket form over the substrate 100 using a resist pattern (not shown) as a mask, and patterning the dielectric material by performing one or more etching processes to form a through hole opening O3 in the second interlayer dielectric layer 150. In some embodiments, the through hole opening O3 exposes the underlying first metallization pattern 140, especially the connecting trace 1406. For example, the through hole opening O3 may be formed with an inclined sidewall profile or a substantially vertical sidewall profile. In some embodiments, the second interlayer dielectric layer 150 includes at least one dielectric material selected from silicon oxide, silicon nitride, SiC, silicon carbonitride (SiCN), or a low-k dielectric material such as a carbon-containing oxide or silicate glass. In some embodiments, the second interlayer dielectric layer 150 is formed by, for example, LPCVD, PECVD, and spin coating methods. In one embodiment, the second interlayer dielectric layer 150 may include multiple layers composed of different dielectric materials or include an etch stop layer so that different materials are selected to achieve appropriate etching selectivity. In one embodiment, the material of the second interlayer dielectric layer 150 may be different from the material of the first interlayer dielectric layer 130. In one embodiment, the material of the second interlayer dielectric layer 150 may be the same as the material of the first interlayer dielectric layer 130.

[0044] In some embodiments, reference Figure 8 , after forming the second interlayer dielectric layer 150, a second metallization pattern 160 is formed, and the metallization pattern 160 includes a through hole portion 1602 filled inside the through hole opening O3 and a connection trace 1606 disposed on the second interlayer dielectric layer 150 and extending on the second interlayer dielectric layer 150. In some embodiments, the through hole portion 1602 is electrically connected and in contact with the connection trace 1406, respectively, and is further electrically connected to the conductive blocks 114, 116, 118 and the doped regions 132, 133, 134. In an embodiment, the connection trace 1606 is electrically and physically connected to the through hole portion 1602. In some embodiments, the material and formation method of the second metallization pattern 160 are similar to the materials and methods used to form the first metallization pattern, and will not be repeated herein. It should be understood that the formation of the second metallization pattern 160 may include forming a barrier layer and / or an adhesion layer and / or a seed layer as part of the pattern.

[0045] Fig. 8A yes Figure 8 Schematic top view of an exemplary embodiment of the structure shown. Fig. 8A and Figure 8As shown in the schematic top view, the connecting traces 1606 of the second metallization pattern 160 include traces 1606-1, 1606-2 and 1603-3. Trace 1606-1 is located at a position overlapping with the active area AR1, the conductive block 118 and the trace 1406-1 and covering the active area AR1, the conductive block 118 and the trace 1406-1. Trace 1606-2 is located at a position overlapping with the conductive block 116 and the trace 1406-2 and covering the conductive block 116 and the trace 1406-2. Trace 1603-3 is located at a position overlapping with the active area AR3, the conductive block 114 and the trace 1406-3 and covering the active area AR3, the conductive block 114 and the trace 1406-3. In addition, the connection trace 1606 includes a trace 1606-4 extending from the trace 1606-1 toward the outer region and connected to an input / output (I / O) pad 1606-5 located outside the conductive block 114, and the trace 1606-4 is a high voltage interconnect (HVI) metal line. Fig. 7A and Fig. 8A , circular trace 1606-1 is located above and covers doped regions 133, 136 and is adjacent to trace 1606-4. Figure 8 and Fig. 8A In some embodiments, the doped region 133 functioning as a drain region is electrically connected to the traces 1606-1, 1606-4, and the pad 1606-5 through the via portion 1602, the trace 1406-1, and the via portions 1402 and 1404. It should be understood that more metal patterns such as extended metal lines or pads may be formed during the formation of the second metallization pattern 160 to achieve further external electrical connections.

[0046] Fig. 9 is a schematic top view showing a portion of a structure including a high voltage semiconductor device according to some embodiments of the present disclosure. Fig.10 is a schematic enlarged top view showing a doped ring portion of a structure according to some embodiments of the present disclosure. Fig. 9 or Fig.10 Some elements including the semiconductor pattern and the first metallization pattern are omitted.

[0047] exist Fig. 9 and Fig.10 In the embodiment, the first conductive type doping region 134 is formed as a ring-shaped doping region located adjacent to the second conductive type doping region 132 and between the conductive block 114 and the second conductive type doping region 132. Fig. 9As can be seen in FIG. 1 , in some embodiments, the first conductive type doping region 136 is formed in a ring shape that encloses the circular doping region of the second conductive type doping region 133. In some embodiments, the trace 1606-1 is located above the doping regions 133, 136 and overlaps with and covers the doping regions 133, 136. Fig. 9 In FIG. 1 , trace 1606-4, a high voltage interconnect (HVI) metal line, extends from trace 1606-1 to pad 1606-5 to electrically connect the drain region (doped region 133) to pad 1606-5. Fig. 9 , trace 1606-4 extends from trace 1606-1, across conductive block 116 of the gate structure and across break BK and beyond doped regions 132, 134 and connects to pad 1606-5. In some embodiments, trace 1606-4 has a width Wm ranging from about 0.1 microns to about 100 microns. In some embodiments, trace 1606-4 has a width Wm ranging from about 0.1 microns to about 30 microns.

[0048] from Fig. 9 and Fig.10 From the schematic top view shown, the second conductive type doping region 132 is shaped like a split ring (open ring) or a C-shaped ring having a break portion BK located between two ends 132E of the second conductive type doping region 132. Fig.10 As can be seen in FIG. 1 , the vertical projection (along the thickness direction) of the metal trace 1606-4 falls within the span of the disconnection portion BK, and does not touch or overlap with the doped region 132. That is, the overpass location or intersection location of the trace 1606-4 overlaps with the location of the disconnection portion BK. Fig.10 In the embodiment, the two ends 132E are separated from the trace 1606-4 by spacings S1 and S2, respectively, and the spacing S1 or S2 is in the range of about 0.05 microns to about 20 microns. In some embodiments, the spacing S1 is the same as the spacing S2. In some embodiments, the spacing S1 is different from the spacing S2. In some embodiments, the extension length L of the break portion BK is BK Greater than the width Wm of the trace 1606-4. In some embodiments, the second conductive type doping region 132 is shaped like an open ring and has a width Wd (in the radial direction) ranging from about 0.05 microns to about 8.0 microns. In some embodiments, the spacing S3 between the second conductive type doping region 132 and the conductive block 116 may be less than 5 microns. In one embodiment, the spacing S3 between the second conductive type doping region 132 and the conductive block 116 may be zero. In some embodiments, the extension length L of the disconnection portion BK is BKIn some embodiments, the ratio of the spacing S1 / S2 to the width Wm of the trace 1606-4 is in the range of about 5E-4 to about 500. It should be understood that dimensions such as length, width, spacing, etc. are provided as exemplary possible ranges and can be modified with pattern and layout design, and other ranges are also included in the scope of the present disclosure.

[0049] Since the disconnection area is an unprocessed area of ​​the first conductive type body well 106 that exists between the two ends 132E of the second conductive type doping area 132, the second conductive type doping area 132 is not formed as a continuous closed ring-shaped doping area (doping ring area). In some embodiments, the position of the disconnection portion BK is located directly below the high voltage metal trace 1606-4 of the second metallization pattern 160, and the disconnection portion position corresponds to the crossing position of the high voltage metal trace 1606-4 crossing over the doping area 132 (i.e., the intersection position of the metal trace 1606-4 and the extension of the end 132E of the doping area 132). That is, the C-shaped doping ring area 132 is formed with a disconnection portion BK at a position directly below the traversing high voltage internal connection metal line. Compared with the O-shaped ring doping area that forms a continuous path, there is a gap or disconnection in the C-shaped ring doping area 132, and the hot carrier path located below the high voltage internal connection metal line is cut off.

[0050] Since the hot carrier effect is minimized, the gate oxide layer (or gate dielectric layer) of the gate structure located below the high voltage interconnect (HVI) metal line will not be damaged. With this configuration, the human body mode (HBM) protection level can be significantly improved. For example, compared with the configuration with the O-ring doping region, the configuration designed with the C-ring doping region increases the HBM protection level from 500V (including 500V) to 2500V (including 2500V) and reduces the HBM endurance deviation from 2000V to 500V (down by ~78%).

[0051] Fig.11 is a schematic top view of an exemplary embodiment showing the relative positions and shapes of doping regions and gate structures according to some embodiments of the present disclosure.

[0052] from Fig.11From the top view shown, the source region 1110 includes portions 1110-1 and 1110-2 extending in the X direction connected by a portion 1110-4 extending in the Y direction, and X extension portions 1110-2 and 1110-3 connected by a Y extension portion 1110-5. From the schematic top view, the source region 1110 is shaped like a folded loop in which portion 1110-1 is folded inward and extended, and there is a disconnection portion BK located between two end portions 1110E (located between end portion 1110E of portion 1110-1 and end portion 1110E of portion 1110-3). That is, the source region 1110 is a doped region shaped like two connected fingers. In some embodiments, the gate structure 1120 is arranged adjacent to the source region 1110 and is also shaped like a folded loop or like two connected fingers. From the top view, the gate structure 1120 is a continuous structure without a disconnection portion. Fig.11 In the embodiment, the drain region 1130 is enclosed by the gate structure 1120 and the source region 1110 and is shaped like a "C" or a hairpin. In some embodiments, the drain region 1130 is spaced apart from the gate structure 1120 and spaced apart from the source region 1110. Fig.11 In the embodiment, HVI trace 1140 is located above and overlaps a portion of drain region 1130 and extends along drain region 1130 in the X direction over drain region 1130, crosses gate structure 1120 and disconnection portion BK, and exceeds gate structure 1120 and source region 1110 or is located outside gate structure 1120 and source region 1110. Since HVI trace 1140 crosses over gate structure 1120 and source region 1110, the location of disconnection portion BK is located below the crossing location of HVI trace 1140 crossing over source region 1110. Fig.11 From the top view shown, the extension length L of the break portion BK BK Greater than the width Wm of the HVI trace 1140.

[0053] In the above embodiments, the configuration of the source region of the transistor structure is designed to have a disconnection or gap in the continuous path at a position below the HVI metal line or trace, and due to the presence of the disconnection or gap, the continuous path is interrupted and the hot carrier path is interrupted. With the hot carrier effect minimized, the gate oxide layer (or gate dielectric layer) next to the disconnection and located below the HVI metal line will not be damaged. With this configuration, the HBM protection level is increased several times and significantly improved, and the HBM durability deviation is reduced by 78%.

[0054] According to some embodiments, a semiconductor device includes a drain region and a source region, a gate structure, and a metal line in a substrate. The source region surrounds the drain region in the substrate. The gate structure is disposed on the substrate and disposed between the source region and the drain region. The gate structure surrounds the drain region. The metal line is located above the source region and the drain region and the gate structure and is electrically connected to the drain region or the source region. The source region includes a doped region having a disconnection region between two opposite ends of the doped region. The metal line extends from the drain region, crosses the gate structure, crosses the disconnection region, and exceeds the source region.

[0055] In some embodiments, the source region has a top view that is a C-shaped ring. In some embodiments, the vertical projection of the metal line falls within the span of the disconnected region and overlaps with the span of the disconnected region. In some embodiments, the two opposite ends of the doped region are spaced apart from the vertical projection of the metal line by a first spacing and a first spacing, respectively, and the first spacing is the same as the second spacing. In some embodiments, the two opposite ends of the doped region are spaced apart from the vertical projection of the metal line by a first spacing and a first spacing, respectively, and the first spacing is different from the second spacing. In some embodiments, further comprising an isolation structure located on the substrate and between the source region and the drain region, and the gate structure is partially disposed on the substrate and partially disposed on the insulating structure. In some embodiments, further comprising a doped body well located below the source region and the gate structure, and a channel region located below the gate structure and within the doped body well.

[0056] According to some embodiments, a semiconductor device includes a substrate having a first conductivity type doped well in the substrate, a second conductivity type doped well in the first conductivity type doped well, and an isolation structure on the substrate, the isolation structure defining a first region and a second region of the substrate. A first conductivity type doped drain region is located in the first conductivity type doped well and in the first region of the substrate. A first conductivity type doped source region is located in the second conductivity type doped well and in the second region of the substrate, and surrounds the first conductivity type doped drain region. A gate structure is partially disposed on the substrate and partially disposed on one of the isolation structures. The gate structure is disposed between the first conductivity type doped source region and the first conductivity type doped drain region, and the first conductivity type doped source region surrounds the gate structure. A channel region is located below the gate structure and in the second conductivity type doped well. A metal line is located above the first conductivity type doped source region and the first conductivity type doped drain region and the gate structure. The metal line is electrically connected to the first conductivity type doped drain region. The first conductivity type doped source region has a split loop-shaped top view divided by a disconnection region. The metal line extends across the gate structure and across the disconnect region and beyond the first conductivity type doped source region.

[0057] In some embodiments, the extension length of the disconnected region is greater than the width of the metal line at the intersection of the metal line crossing the first conductive type doped source region. In some embodiments, the extension length of the disconnected region is in a range of about 0.2 microns to about 70 microns. In some embodiments, the first conductive type is N-type and the second conductive type is P-type. In some embodiments, the first conductive type is P-type and the second conductive type is N-type. In some embodiments, the first conductive type doped well has a doping concentration lower than the doping concentration of the first conductive type doped drain region and the first conductive type doped source region. In some embodiments, further comprising a second conductive type doped region located in the first region of the substrate and surrounding the first conductive type doped drain region. In some embodiments, further comprising a second conductive type doped region located in the second region of the substrate and surrounding the first conductive type doped source region. In some embodiments, the second conductive type doped region has a closed loop shaped top view.

[0058] According to some embodiments, a method for manufacturing a semiconductor device includes at least the following steps. A first conductive type doped well is formed in a substrate. A second conductive type doped well is formed in the first conductive type doped well in the substrate. An isolation structure is formed on the substrate to define a first region and a second region of the substrate. A gate structure and a conductive semiconductor pattern are formed on the isolation structure and on the substrate. A first conductive type doped region and a second conductive type doped region are formed in the first region and the second region of the substrate. At least one metal line is formed above the gate structure and across the gate structure. The at least one metal line extends across the first conductive type doped region and the second conductive type doped region in the second region and is electrically connected to at least one of the first conductive type doped region and the second conductive type doped region.

[0059] In some embodiments, forming a first conductivity type doped region and a second conductivity type doped region in the first region and the second region of the substrate includes: forming the first conductivity type doped region in the first region and the second region of the substrate by performing a first ion implantation process; and later forming the second conductivity type doped region in the first region and the second region of the substrate by performing a second ion implantation process, and the first ion implantation process is different from the second ion implantation process. In some embodiments, forming the first conductivity type doped region in the first region and the second region of the substrate includes forming a first conductivity type doped drain region in the first region and forming a first conductivity type doped source region in the second region, and the first conductivity type doped source region and the first conductivity type doped drain region are formed in the same implantation process. In some embodiments, forming the first conductivity type doped source region in the second region includes implanting a first conductivity type dopant into the substrate to form a split ring region, the split ring region having a disconnected portion in which the first conductivity type dopant is not implanted.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a drain region, located in the substrate; a source region, located in the substrate and surrounding the drain region; A gate structure, disposed on the substrate, disposed between the source region and the drain region and surrounding the drain region; as well as a metal line located above the source region, the drain region and the gate structure and electrically connected to the drain region or the source region, wherein the source region comprises a doped region having a disconnection region between two opposite ends of the doped region; and The metal line extends from the drain region, crosses the gate structure, crosses the disconnected region and exceeds the source region. 2 . The semiconductor device according to claim 1 , wherein the source region has a top view that is a C-shaped ring. 3 . The semiconductor device according to claim 1 , wherein a vertical projection of the metal line falls within a span of the disconnection region and overlaps the span of the disconnection region. 4 . The semiconductor device according to claim 3 , wherein the two opposite ends of the doped region are spaced apart from the vertical projection of the metal line by a first spacing and a second spacing, respectively, and the first spacing is the same as the second spacing. 5 . The semiconductor device according to claim 3 , wherein the two opposite ends of the doping region are spaced apart from the vertical projection of the metal line by a first interval and a second interval, respectively, and the first interval is different from the second interval. 6 . The semiconductor device according to claim 1 , further comprising an isolation structure located on the substrate and between the source region and the drain region, and the gate structure is partially disposed on the substrate and partially disposed on the isolation structure. 7 . The semiconductor device of claim 6 , further comprising a doped body well located below the source region and the gate structure, and a channel region located below the gate structure and within the doped body well.

8. A semiconductor device comprising: A substrate having a first conductivity type doped well located in the substrate, a second conductivity type doped well located in the first conductivity type doped well, and an isolation structure located on the substrate, the isolation structure defining a first region and a second region of the substrate; a first conductivity type doped drain region located in the first conductivity type doped well and in the first region of the substrate; a first conductivity type doped source region located in the second conductivity type doped well and in the second region of the substrate, surrounding the first conductivity type doped drain region; a gate structure, partially disposed on the substrate and partially disposed on one of the isolation structures, wherein the gate structure is disposed between the first conductivity type doped source region and the first conductivity type doped drain region, and the first conductivity type doped source region surrounds the gate structure; a channel region located below the gate structure and within the second conductivity type doped well, and a metal line located above the first conductivity type doped source region, the first conductivity type doped drain region and the gate structure, wherein the metal line is electrically connected to the first conductivity type doped drain region, The first conductive type doped source region has a split loop-shaped top view divided by a disconnected region, and the metal line extends across the gate structure and across the disconnected region and exceeds the first conductive type doped source region. 9 . The semiconductor device according to claim 8 , wherein an extension length of the disconnected region is greater than a width of the metal line at an intersection position where the metal line crosses over the first conductive type doped source region. 10 . The semiconductor device according to claim 9 , wherein the extension length of the disconnected region is in a range from 0.2 μm to 70 μm. 11 . The semiconductor device according to claim 8 , wherein the first conductivity type is an N type, and the second conductivity type is a P type. 12 . The semiconductor device according to claim 8 , wherein the first conductivity type is a P type, and the second conductivity type is an N type. 13 . The semiconductor device according to claim 8 , wherein the first conductivity type doped well has a doping concentration lower than the doping concentrations of the first conductivity type doped drain region and the first conductivity type doped source region. 14 . The semiconductor device according to claim 8 , further comprising a second conductivity type doped region located in the first region of the substrate and surrounding the first conductivity type doped drain region. 15 . The semiconductor device according to claim 8 , further comprising a second conductivity type doped region located in the second region of the substrate and surrounding the first conductivity type doped source region. The semiconductor device according to claim 15 , wherein the second conductive type doping region has a closed loop shape in a top view.

17. A method for manufacturing a semiconductor device, comprising: forming a first conductivity type doped well in the substrate; forming a second conductivity type doped well in the first conductivity type doped well in the substrate; forming an isolation structure on the substrate to define a first region and a second region of the substrate; forming a first conductivity type doped drain region within the first conductivity type doped well in the first region of the substrate; forming a first conductivity type doped source region in the second conductivity type doped well in the second region of the substrate, wherein the first conductivity type doped source region surrounds the first conductivity type doped drain region; forming a gate structure on the isolation structure and on the substrate, wherein the gate structure is disposed between the first conductivity type doped source region and the first conductivity type doped drain region, and the first conductivity type doped source region surrounds the gate structure; and forming at least one metal line above and across the gate structure, wherein the at least one metal line is located above the first conductivity type doped source region and the first conductivity type doped drain region, wherein the metal line is electrically connected to the first conductivity type doped drain region, The first conductive type doped source region has a split loop-shaped top view divided by a disconnected region, and the metal line extends across the gate structure and across the disconnected region and exceeds the first conductive type doped source region. 18 . The method for manufacturing a semiconductor device according to claim 17 , wherein the first conductivity type is an N type, and the second conductivity type is a P type. 19 . The method for manufacturing a semiconductor device according to claim 17 , wherein the first conductivity type doped source region and the first conductivity type doped drain region are formed in a same implantation process. 20 . The method for manufacturing a semiconductor device according to claim 17 , wherein the first conductivity type is a P type, and the second conductivity type is an N type.

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