Microprocessor and method thereof

Abstract

This application provides a microprocessor and a method thereof. In one embodiment, a microprocessor includes: an instruction cache configured to receive instruction fetches including a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion other than the first byte portion based on a hit in the side cache tag array; and a side cache data array configured to store instruction data of the second byte portion.

Description

Technical Field

[0001] This invention generally relates to microprocessors, and more particularly to instruction fetch bandwidth in microprocessors. Background Technology

[0002] A microprocessor comprises one or more execution units that actually execute instructions. A superscalar processor includes the ability to issue multiple instructions to various execution units each clock cycle to improve the processor's throughput or the processor's average instructions per clock cycle. The instruction fetch and decode functions at the top of the microprocessor pipeline should provide an instruction flow to the execution units at a sufficient rate to utilize the additional execution units and actually improve throughput.

[0003] Because the instructions in the instruction set are not fixed-length, but rather can vary in length, the x86 architecture makes this task more challenging. Therefore, x86 microprocessors need to include a significant amount of logic to process the incoming instruction byte stream to determine the start and end points of each instruction. Modern microprocessors typically fetch sixteen (16) bytes of data per cycle, as fetching lengths greater than sixteen imposes considerable timing constraints on instruction formatting, such as determining instruction boundaries and prefix information, especially as clock speeds increase. Furthermore, the need to fetch more than 16 bytes per cycle has not traditionally been a common requirement. However, the increasing popularity of multimedia in many types of digital devices has led to a seemingly annual increase in multimedia instructions, and consequently, some chip manufacturers have adopted different approaches to handle fetching longer than 16 bytes (e.g., 32-byte fetching). Unfortunately, these solutions often result in the need for large-scale error recovery mechanisms in the event of self-modifying code or certain aliasing situations, or large and extremely complex caches with lower-than-expected performance. Therefore, there is a need to handle fetching longer than 16 bytes without sacrificing performance. Summary of the Invention

[0004] In one embodiment, a microprocessor includes: an instruction cache configured to receive instruction fetches including a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion other than the first byte portion based on a hit in the side cache tag array; and a side cache data array configured to store instruction data of the second byte portion.

[0005] Other systems, methods, features, and advantages of the present invention will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of the invention, and protected by the appended claims. Attached Figure Description

[0006] The various aspects of the invention can be better understood by referring to the following accompanying drawings. The components in the drawings are not necessarily drawn to scale, but rather the emphasis is on clearly illustrating the principles of the invention. Furthermore, in the drawings, the same reference numerals refer to corresponding parts in all the figures.

[0007] Figure 1A This is a block diagram illustrating an embodiment of an example side cache array system used in a microprocessor pipeline.

[0008] Figure 1B It is shown Figure 1A The diagram shows an example front end of a microprocessor pipeline.

[0009] Figure 2 This is a schematic diagram illustrating an embodiment of example extended logic used in an edge cache array system.

[0010] Figure 3 This is a flowchart illustrating an embodiment of an example edge cache array method. Detailed Implementation

[0011] Certain embodiments of a side cache array system and method are disclosed, enabling efficient processing of instruction sets (such as those found in multimedia code) with a total length greater than sixteen (16) bytes by a microprocessor. In one embodiment, a side cache is implemented that stores only the second byte portion (e.g., the second half) of a thirty-two (32) byte pick-up of instruction information or data (e.g., instruction boundaries, prefix information, etc.), while allowing regular logic to process the first byte portion (e.g., the first half) of the 32 byte pick-up. The tag and data arrays of the side cache are located in different pipeline stages, where the side cache tag array is read earlier. A hit in the side cache tag array yields a 32-byte increment in the sequential pick-up address of the instruction cache (I cache) and this data is tiered into the XIB queue. Subsequently, a hit in the side cache tag array also causes the instruction information to be written to the XIB queue using the computed first byte portion. By using the side cache, 32-byte pick-ups can be processed without the errors or large cache sizes found in other methods for processing 32-byte pick-ups. Typically, certain embodiments of edge cache array systems provide better throughput in the presence of long instructions (e.g., AVX type instructions, which can be 6 to 11 bytes long) that typically result in 4 instruction groups exceeding 16 bytes.

[0012] Furthermore, while other mechanisms for handling 32-byte fetches have been established, these methods have drawbacks. For example, one approach performs a slow scan of 16 bytes at a time, then accumulates the instructions and instruction boundaries determined by these scans in the same cache. However, this approach is vulnerable to attacks involving self-modified code or aliases, which can cause start and end marker errors, requiring slow and potentially error-prone recovery processing. In some approaches, micro-op caches have been created to achieve higher throughput. For example, micro-op caches serve as a front-end replacement for standalone (e.g., I-cache) caches with higher bandwidth (e.g., up to 4 micro-ops / cycle, or 6 micro-ops / cycle). However, caches are very large and complex, and merging such solutions would essentially require redesigning much of the pipeline for many microprocessors. Conversely, some embodiments of the side cache array system address the need for 16-byte retrievals by widening the I cache retrieval and using the side cache array to store start / end / prefix information for the second part of the 32-byte retrieval, while allowing regular (e.g., L-level and M-level) logic to process the first part. This provides a simple approach using space-saving techniques while achieving higher throughput (e.g., being able to issue four x86 instructions / cycles for critical loops, even for instructions with an average length of eight (8) bytes).

[0013] Having summarized certain features of the edge cache array system of the present invention, detailed reference will now be made to the description of the edge cache array system as illustrated in the accompanying drawings. While the edge cache array system will be described in conjunction with these drawings, it is not intended to limit it to the one or more embodiments disclosed herein. That is, while the invention permits modifications and alternatives, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein in a manner sufficient for those skilled in the art to understand. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to the specific forms disclosed. Rather, the invention will cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. As used throughout this application, the word “may” is used in a permissive sense (i.e., implying potential) rather than a mandatory sense (i.e., implying necessity). Similarly, the word “comprising” means including, but not limited to, the specific embodiments disclosed herein.

[0014] Various units, modules, circuits, logic, or other components can be described as being "configured" to perform one or more tasks. In this context, "configured" is a broad description of a structure, which generally means "having a circuit or other physical structure" that performs or is capable of performing one or more tasks during operation. A circuit can be a special-purpose circuit or a more general-purpose processing circuit operating under the control of coded instructions. That is, in describing certain aspects or features of various implementations of the invention, terms such as "unit," "module," "circuit," "logic," and "component" may be used herein. Those skilled in the art will understand that the corresponding features are implemented using circuits, whether those circuits are special-purpose circuits or more general-purpose circuits operating under the control of microcoded instructions.

[0015] Furthermore, units / modules / circuits / logic / components can be configured to perform tasks even when the unit / module / circuit / logic / component is not currently in operation. The description of units / modules / circuits / logic / components configured to perform one or more tasks explicitly aims to avoid functional limitations on those units / modules / circuits / logic / components. Those skilled in the art will understand that the specific structure or interconnection of circuit elements will typically be determined by the compiler of design automation tools (such as register-transfer language (RTL) compilers). RTL compilers operate on scripts that are very similar to assembly language code to compile the scripts into a form for the layout or fabrication of the final circuit.

[0016] That is, more advanced software tools are used to design integrated circuits (such as the integrated circuits of this invention) to model the desired functional operation of the circuit. As is well known, "Electronic Design Automation" (or EDA) is a category of software tools used to design electronic systems (such as integrated circuits). EDA tools are also used to program design functions into field-programmable gate arrays (FPGAs). Hardware description languages ​​(HDLs) such as Verilog and Very High Speed ​​Integrated Circuit Hardware Description Language (VHDL) are used to create a high-level representation of the circuit from which a low-level representation and the final actual wiring can be derived. In practice, since modern semiconductor chips can have billions of components, EDA tools are considered essential for their design. In practice, circuit designers use programming languages ​​such as C / C++ to specify operational functions. EDA software tools translate this specified function into RTL. The hardware description language (e.g., Verilog) then translates the RTL into a discrete gate netlist. This netlist defines the actual circuit produced, for example, by a foundry. In practice, these tools are well known and understood for their role and use in facilitating the design process of electronic and digital systems, and therefore need not be described further herein.

[0017] Figure 1AAn exemplary embodiment of a pipeline for a microprocessor 10 is shown. It should be understood that, for brevity and ease of explanation and illustration, certain known components of the microprocessor 10 are omitted herein. As is known, pipelined architectures provide multiple instructions that overlap during execution, where each stage is called a pipeline level. The blocks shown in the pipeline can each be implemented according to one or more levels, which are shown on the left side of the blocks and, in the depicted embodiment, are represented by the uppercase letters C, I, B, U, L, M, F, G, W, X, E, S, W, Y, and Z, which proceed sequentially from top to bottom and are redirected (as indicated by arrows). Those skilled in the art will understand that... Figure 1A The number and / or arrangement of stages depicted herein are merely illustrative of one exemplary embodiment, and in some embodiments, different numbers and / or arrangements of stages may be implemented, and are therefore contemplated within the scope of the invention. Those skilled in the art will also understand that the blocks provide a general description of the functionality of the pipeline, and for brevity, associated logic or circuitry known to those skilled in the art has been omitted herein. For example, those skilled in the art will understand that, as is known, each stage of a pipeline may be separated by a clock pipeline register or latch.

[0018] In one embodiment, the microprocessor 10 includes an I-cache tag array 12, an I-cache data array 14, a side cache tag array 16, and a side cache data array 18. The microprocessor 10 also includes length / prefix (L / PF) scan logic 20, expansion logic 22, an instruction multiplexer (M) queue 24, and a XIB multiplexer (M) queue 26. In one embodiment, the I-cache tag array 12, I-cache data array 14, side cache tag array 16, side cache data array 18, L / PF scan logic 20, expansion logic 22, instruction M queue 24, and XIB M queue 26 constitute a side cache array system; however, in some embodiments, fewer or more logic components may constitute a side cache array system. The microprocessor 10 also includes an instruction formatter 28, a formatted instruction queue (FIQ) / circular queue 30, translation logic 32, a register alias table / reservation station (RAT / RS) 34, an execution unit 36, and exit logic 38.

[0019] In one embodiment, the I-cache tag array 12 and the edge cache tag array 16 are implemented at level C. (See reference...) Figure 1B The image shown is for... Figure 1AThe example source used at the front end 40 of the pipeline shown in the microprocessor 10. The front end 40 includes a pickup unit 42 (e.g., including a multiplexer and a clock register), a side cache tag array 16, a translation back buffer (TLB) 44, an I cache data array 14, an I cache tag array 12, and a branch target access cache (BTAC) 46 (i.e., a portion of the pipeline, but...). Figure 1A (not shown in the image), fast predictor 48 (i.e., part of the pipeline, but also in...) Figure 1A (Not shown in the diagram), and a multiplexer (MUX) 50. The pickup unit 42 receives multiple cached instruction address sources, including sequential instruction addresses, (e.g., from S-level) correction instruction addresses, (e.g., from G-level) decode time instruction addresses, and addresses from BTAC 46 and the fast predictor 48. The output of the pickup unit 42 is provided as input to the side cache tag array 16, TLB 44, I-cache data array 14, I-cache tag array 12, BTAC 46, and fast predictor 48 for accessing the cached address of the next instruction in the I-cache data array 14.

[0020] Additionally, the fast predictor 48 includes a single-cycle branch predictor that provides single-cycle prediction (e.g., taking one cycle to generate the target address, a prediction provided at level I in one embodiment). In one embodiment, the fast predictor 48 includes a table (also referred to herein as an array or target array) storing the branch target addresses of previously executed branch instructions, which enables branch prediction when the stored branch instructions are subsequently encountered. In one embodiment, the table includes 128 entries, but in some embodiments other sizes (e.g., 64 entries, 32 entries, etc.) may be used. The table is organized as an n-way (e.g., n is an integer greater than 1) set-associative cache. Generally, an n-way set-associative cache is also referred to herein as a multi-set-associative cache. In one embodiment, each entry stores eight (8) 3-bit counters and the current local branch mode, which is selected by the 3-bit local branch mode. The fast predictor 48 also includes a conditional branch predictor that is accessed in parallel with the table and provides take / not take direction for conditional branches. The fast predictor 48 also includes a return stack that can provide targets instead of the table. In one embodiment, the return stack comprises four (4) entries and provides a target for the return instruction. Note that the specifications listed above are for illustrative purposes only, and some embodiments may be implemented under different specifications, and are therefore contemplated within the scope of the invention. The fast predictor 48 is configured to deliver the predicted branch target immediately (within a single cycle) without employing branch penalties. In some embodiments, the fast predictor 48 may operate according to other specifications of its prediction mechanism and / or table configuration, or in some embodiments, the fast predictor 48 may be omitted. Most branches are correctly predicted by the fast predictor 48. In some embodiments, where the fast predictor 48 provides a branch prediction that differs from the branch prediction of BTAC 46 (e.g., different in direction and / or target) based on the same acquired branch instruction, BTAC 46 utilizes the branch prediction information provided by BTAC 46 (e.g., direction, target address, branch prediction type) to rewrite the branch prediction of the fast predictor 48 and update the fast predictor table within a set of levels of BTAC 46 (e.g., at level U).

[0021] Level I and / or Level B correspond to various tables in the access pipeline, and in some embodiments include (e.g., tag-based) multiplexing directions or paths from the table, as well as reading instructions.

[0022] BTAC 46 maintains information about previously executed branch instructions used to predict the target address, direction, and type during subsequent execution. BTAC 46 includes one or more tables much larger than the tables of the fast predictor 48. In one embodiment, BTAC 46 includes a 4k-entry, m-way set association table (also referred to herein as an array or target array), where m is an integer greater than 1. Similar to an n-way set association table, an m-way set association table may also be referred to herein as a multi-set association table. Each entry in BTAC 46 includes a valid bit, a branch target address prediction, a direction prediction, and a branch type. The branch type specifies whether the branch instruction is a call / return, an indirect branch, a conditional relative branch, or an unconditional relative branch. In one embodiment, BTAC 46 includes or cooperates with a conditional relative branch predictor (or simply a conditional branch predictor), wherein the conditional branch predictor has a multi-entry (e.g., 12k) tag geometry (TAGE)-based conditional branch predictor, multiple tables, multiple bits (e.g., 3 bits), a take / not take (T / NT) counter, and a multi-bit global branch history. That is, as is known, a TAGE conditional branch predictor includes a label table with geometrically increasing branch history length. As another example, indirect prediction includes a multi-entry (e.g., 1.5k) TAGE predictor, and table entries are used for static indirect branching. In one embodiment, two TAGE conditional branch predictors are used, one for edge A in the predictor array and one for edge B in the predictor array. The TAGE conditional branch predictor may be part of or used in conjunction with BTAC 46.

[0023] TLB 44, under the management of the memory management unit (not shown), provides the known virtual-to-physical page address translation. Specifically, TLB 44 stores the physical address of the most recently used virtual address. TLB 44 receives the linear address from the segmentation unit (which translates logical addresses from the program into linear addresses) and compares a portion of that linear address with entries in TLB 44 to find a match. If a match is found, the physical address is calculated based on the TLB entry. If no match is found, a page table entry from memory is fetched and placed into TLB 44.

[0024] The I cache data array 14 includes a level-1 cache containing instructions that have been fetched or pre-fetched from L2, L3, or main memory. The I cache data array 14 includes multiple timer registers.

[0025] The I cache tag array 12 includes an array of tags corresponding to instructions in the I cache data array 14, and includes multiple timer registers for determining a match between information associated with a picked-up cache instruction (e.g., a tag or portion of a cache address) and the I cache data array 14 and BTAC 46.

[0026] More relevant to the edge cache array system is that, in some embodiments (e.g., at level C), the I-cache tag array 12 and the edge cache tag array 16 are implemented in parallel, along with other processes including sending addresses to the I-cache data array 14, TLB 44, fast predictor 48, and BTAC 46. Note that the edge cache tag array 16 is separate from the edge cache data array 18, which is implemented in a different level (e.g., level U). The I-cache data array 14 is configured to provide 32 bytes of data, but for most processes, it is fetched at 16 bytes / cycle. A hit at the edge cache tag array 16 signals the multiplexer 50 to select 32 bytes (instead of 16 bytes), and the sequential address is incremented by 32 bytes instead of 16 bytes. A miss at the edge cache tag array 16 signals the multiplexer 50 to increment the address by 16 bytes. In other words, the multiplexer 50 is configured to select 32 bytes or 16 bytes based on whether there is a hit in the side cache tag array 16, where the sequential address is increased accordingly to the pickup unit 42.

[0027] Refer again Figure 1A Before proceeding with a further description of the side cache array system, the logic for processing the first 16 bytes is briefly described (followed by the remainder of the pipeline). For the first 16 bytes of data picked up from the 32-byte fetch, L / PF scan logic 20, XIB M queue 26, and instruction formatter 28 provide XIB and decoding functions associated with the L-stage (length), M-stage (multiplexing), and F-stage (formatting) of the pipeline. L / PF scan logic 20 identifies and marks the start and end bytes (L-stage) of each instruction within the stream, thereby segmenting the byte stream into an x86 instruction stream, which is hierarchically defined at XIB M queue 26 (M-stage) before providing decoding functions at the F-stage of instruction formatter 28. Note that additional information regarding XIB functionality and the L, M, and F stages can be found in U.S. Patent No. 8,612,727, which is incorporated herein by reference in its entirety to the extent consistent with the present disclosure.

[0028] The FIQ / circular queue 30 receives and buffers formatting instructions until they can be translated into microinstructions. The FIQ / circular queue 30 also provides preliminary decoding and fast looping functionality (e.g., on a BTAC loop branch, the loop queue is activated and the loop instructions are repeatedly sent).

[0029] The W class offers an optional additional timing clock.

[0030] At level X, instruction translator 32 (in level X or translation level) translates the formatting instructions stored in FIQ / circular queue 30 into microinstructions.

[0031] Instructions are provided in program order to Register Alias ​​Table / Reservation Station (RAT / RS) table 34. The RAT function of RAT / RS 34 maintains and generates dependency information for each instruction. The RAT function of RAT / RS 34 renames the source and destination of instructions to internal registers and dispatches instructions to the reservation station of RAT / RS 34, which (possibly out of program order) issues instructions to the function unit or execution unit (EU) 36. The execution unit 36, including integer units, executes branch instructions at the E (execution) level. Execution unit, branch unit, and integer unit are terms used interchangeably herein. In one embodiment, execution unit 36 ​​(e.g., two execution units) executes two branches in a single clock cycle. Execution unit 36 ​​also indicates whether the BTAC 46 has correctly predicted the branch instruction.

[0032] The execution result is provided to exit logic 38. In one embodiment, exit logic 38 includes a reordering cache (not shown) that contains information related to the instructions that have been executed. It is well known that reordering caches maintain the original program order of instructions after they are issued and allow serialization of results during the exit stage. In one embodiment, some information from the reordering cache may be stored elsewhere in the pipeline, such as at instruction formatter 28. The information stored in the reordering cache may include branch information, such as the type of branch, branch mode, target, tables used in the prediction, and cache replacement policy information (e.g., Least Recently Used or LRU). Exit logic 28 may also include branch table updates, which include S, W, Y, and Z levels and are configured to update various tables (e.g., BTAC) at the front end (e.g., at S level) with information related to the fully decoded and executed branch instructions (e.g., the final result of the branch). At S, W, Y, and Z levels, updates may involve table reads, target address writes, and counter increments or decrements, which may involve some latency. In one embodiment, the branch table update provides an indication of the error prediction for a given conditional branch instruction and the edge (e.g., A, B, or C) that is cached for that conditional branch instruction.

[0033] Referring again to the relevant functionality of the edge cache array system, in one embodiment, the edge cache data array 18 includes a two-way 64-entry table or array, with each entry comprising 2KB of instruction data. The edge cache data array 18 stores instruction boundaries (e.g., start, end), cumulative prefixes, branch information (e.g., the position of the BTAC branch during fetching), and breakpoint markers. The instruction data stored in the edge cache data array 18 is stored in a compressed form by storing the second half of the 16-byte markers at approximately half their original size (e.g., if stored in the format of XIB M queue 26). In response to a hit in the edge cache tag array 16, instruction information or data (e.g., instruction boundaries, prefix information, etc.) associated with the latter half of the 32-byte fetch is hierarchically assigned to the edge cache data array 18, processed by the extension logic 22, and written to the XIB M queue 26. The first 16 bytes of data from the 32-byte fetch are processed by the L / PF scan logic 20 and then written to the XIB M queue 26, while the raw data from the I cache data array 14 (e.g., which is not stored in the edge cache data array 18) is hierarchically assigned to the instruction data M queue 24. Note that the processing of I cache data (e.g., for the first 16 bytes) follows the non-edge cache branches (in... Figure 1A The left side of the instruction is scanned in a standard manner. L / PF scan logic 20 determines the instruction length and accumulates prefixes, which can total 10 to 15 different types in an x86-based instruction. For example, based on the scan of the instruction, prefixes are identified (e.g., in hexadecimal 66, 67, 2E, 3E, etc.), and prefixes may include OS, AS, REX, and their variants, as described in U.S. Patent No. 8,612,727, which is incorporated herein by reference in its entirety. L / PF scan logic 20, in conjunction with XIB M queue 26, accumulates one or more of these prefixes and appends them to or associates them with the opcode byte. Thus, the scan enables the determination of the instruction length (e.g., starting from the opcode byte) and all prefixes affecting the instruction. L / PF scan logic 20 uses standard or common L-level logic (as explained in the aforementioned referenced patent, which is incorporated by reference) to process the first half or first portion (i.e., the first 16 bytes) of the 32-byte pick-up. That is, L / PF scan logic 20 scans the information from I cache data array 14, generates appropriate tags, and writes the information to another entry in XIB M queue 26. In other words, L / PF scan logic 20 and expansion logic 22 write the corresponding entry to XIB M queue 26.

[0034] Based on certain conditions (e.g., a side cache miss, an odd 16-byte address representing the second half of a 32-byte fetch, and not being the target of a branch), a side cache entry is written based on a previous scan. Generally, since prefix information and branch information (e.g., whether a branch exists, whether it is taken, or not) can significantly increase the size of each instruction (e.g., 15 bits per byte), the total number of possible bits can be 20 bits × 16 bytes. While some embodiments may store all these bits in the side cache data array 18, in some embodiments, only a portion of the information is stored. The side cache data array 18 stores a compressed instruction-by-instruction version of this instruction information and also limits the number of instructions utilizing the side cache data array 18 (e.g., 5 or fewer instructions, programmable in some embodiments). In other words, one purpose of the side cache array system is to handle long instructions (where a typical 16-byte fetch bandwidth is insufficient to handle groups of these types of instructions). To preserve side cache entries when needed (e.g., for instructions 8 to 10 bytes long fetched from instruction cache data array 14), side cache data array 18 is configured to store a finite number of instructions with sufficient bit capacity in each entry to represent various markers (start, end, prefix) for each instruction byte via bit representation. The compressed format enables the storage of only five 15-bit groups instead of sixteen 15-bit groups, as combined below. Figure 2 Further described. Specifically, in one embodiment, the edge cache data array 18 only needs to store 5 possible start bits, 5 possible end bits, 5 possible breakpoint markers, and 5 possible prefix markers. Only 75 bits exist, instead of the 240 bits with all prefixes. Therefore, certain embodiments of the edge cache array system are designed to process a predetermined number of instructions or a programmable number of instructions, and for illustrative purposes, the number of five instructions is used as a maximum limit for processing in the edge cache data array 18, while it is understood that other limits may be used in some embodiments. Typically, the edge cache data array 18 stores markers (e.g., bit representations) for the start and end, breakpoint, branch, and prefix information of instructions. Note that the edge cache data array 18 with marker storage relative to the I cache data is smaller than an instruction cache with prefix information and various markers embedded therein.

[0035] The compressed instruction information from the side cache data array 18 is then expanded by extension logic 22 into a format suitable for use by the XIB M queue 26. For example, before writing to the XIB M queue 26, extension logic 22 knows to append start and / or end bits and other instruction information to each instruction byte. In practice, the output of extension logic 22 includes the result of a length scan (each byte is marked with a start or end byte), a marker indicating whether a BTAC branch exists, the presence of breakpoints, and an identifier of one or more prefixes associated with the instruction byte. For example, if the first instruction begins at byte 2 (in hexadecimal shorthand), prefix data is appended before proceeding to the next instruction to determine if certain bits need to be appended, etc. The result is an entry to the XIB M queue 26 based on this extension information for the second half or second portion of the 32-byte fetch.

[0036] Instruction M queue 24 is tracked together with XIB M queue 26, and in one embodiment, instruction M queue 24 includes a portion of XIB M queue 26. Instruction M queue 24 receives raw, unmodified data from instruction cache data array 14. Instruction M queue 24 contains instruction bytes for hierarchical processing to the decoder of instruction formatter 28. For a 16-byte fetch scenario, there is a single write entry to instruction M queue 24. For a 32-byte fetch scenario, there are two entries written to instruction M queue 24.

[0037] In XIB M queue 26, each byte has an associated extended marker, which comprises 19 bits for each entry (16 bytes) and corresponds to start, end, whether it is a branch, data breakpoint, and prefix type (e.g., OS, AS, 2E, 3E, segment overwrite prefix, etc.). For example, 15 bits correspond to the prefix, and 4 bits are used for start, end, branch, and breakpoint. In some embodiments, XIB M queue 26 also includes approximately 6 to 12 entries. XIB M queue 26 is read to feed to the M level, where instructions are effectively multiplexed and the entire level is consumed for formatting at the F level.

[0038] Control logic in certain embodiments of the edge cache array system provides certain checks for updates to the edge cache array system. For example, when there is an edge cache tag array miss, a write to a new edge cache entry is implemented, picking up an odd 16-byte address (e.g., representing the second half of a 32-byte pick) that is not the target of a branch (e.g., excluding the target of the branch because in this case, all start / end / prefix tags will be unavailable since the entire pick is not scanned (only a portion after the branch target)). For example, when the branch reaches the middle point of a 16-byte pick, a full scan of the instruction boundary will not occur, and therefore the entire set of start, end, and prefix data will not be available for writing to the edge cache data array 18. Therefore, if the edge cache entry involves the target of a branch, it is excluded from the edge cache entries. Additionally, certain embodiments of the edge cache array system may (e.g., by using feature control registers, scans, fuses, etc.) limit the use of the edge cache data array 18 to a predetermined or programmable number of instruction code regions per 16 bytes. For example, in cases where there are more than 5 instructions per 16 bytes, to avoid exceeding the per-clock bandwidth byte fetch (e.g., 16 bytes per clock cycle fetch), the side cache array entries can be limited to a predetermined or configurable number (e.g., 3 to 5) of instructions. Furthermore, side cache array entries, or in some embodiments, the entire side cache array 18, may be invalidated in the following situations: I cache array cast out (e.g., in the case of evicting data from I cache array 14, a corresponding invalid entry in side cache array 18 is required to avoid inappropriate aliases), snoop invalidation (e.g., via a signal sent from I cache array 14), TLB invalidation, or OS / AS prefix default change (e.g., affecting instruction length). Note that because the side cache array system operates in parallel with the instruction cache, the U-level knows when a cache hit occurs and whether an eviction or invalidation event has occurred.

[0039] Now for reference Figure 2 A schematic diagram is shown, such as the side cache entry expansion performed by extension logic 22. Specifically, a schematic diagram is shown of the side cache data array 18, a prefix bus 51 corresponding to five instructions with start and prefix information, a demultiplexer 52 for the instructions, a XIB M queue 26, and decode OR logic 54. Note that the use of five instructions is used as a condition for implementing an embodiment of the side cache array system in the illustration, and other limitations may be imposed in some embodiments. The data stored in the side cache data array 18 adopts... Figure 2The format is representatively shown on the left side below the edge cache data array 18, and includes end markers (end[15:0]) for bytes 15 to 0, branch markers (branch[15:0]) for bytes 15 to 0, and breakpoint markers (bpoint[15:0]) for bytes 15 to 0. These markers are in the form used by the XIB M queue 26 and are therefore also directly stored in the XIB queue entry 56 shown. Extension logic 22 decodes and performs a logical OR operation to extend the encoded start points of each of the five instructions into the XIB M queue format, as shown by decoding OR logic 54 and Ins1start[3:0], Ins2start[3:0], ... Ins5start[3:0]. For example, the start bits of the five instructions are decoded from a 4-bit version to a 16-bit version. These 16-bit versions are then ORed together to create the Start[15:0] format in the XIB M queue entry. Note that maintaining the start bits of each instruction in this format in the side cache data array 18 does not save space, but it enables the prefix bus to be extended to a format suitable for the XIB M queue 26.

[0040] Notice Figure 2 At the center of the cache data array 18 are five instructions, each consisting of a 4-bit start[3:0] and a 15-bit prefix[14:0], and shown is the use of demultiplexer 52 to bootstrap the prefix bus 51 to create a format suitable for use in the XIB M queue 26 (e.g., prefixes attached to the individual instructions, including Ins1Prefix[14:0], Ins2Prefix[14:0], ...Ins5Prefix[14:0]). For instruction 1, the value of the start1 field is between 0 and 15. Based on this value, the ins1 prefix (PF1) is bootstrap to one of the 16 segments of the XIB M queue entry 56 being written. For example, if Start1[3:0] == 1100, then PF1[14:0] is bootstrap to the 12th byte segment of the XIB M queue entry 56 being written. The same operation is performed for each of the five instructions. The data from the individual instructions are ORed together to create the M queue entry write data. In other words, each demultiplexer (demux) 52 feeds the input to the XIB M queue 26 (e.g., the 16 segments of the XIB M queue 26 are inputs, and the Ins1 demux feed is also fed by the demuxes of Ins2, Ins3, etc., which are together ORed (e.g., in RTL)).

[0041] Note that only a single entry of XIB M queue 26 is shown. In a real implementation, there may be six (6) or more entries in this queue. Each byte requires 1 bit for start, end, branch, and breakpoint, plus 15 bits for prefix. In one embodiment, each entry is 16×19 or 304 bits wide, and may also include some other data unrelated to this description.

[0042] In view of the above description, those skilled in the art should understand that Figure 3 The side cache array method, denoted as method 58 and implemented by a microprocessor in one embodiment, includes: receiving instruction fetch (60) at an instruction cache including a first byte portion and a second byte portion; signaling further processing of the second byte portion other than the first byte portion by the side cache tag array based on a hit of the side cache tag array (62); and storing instruction data of the second byte portion at a side cache data array (64).

[0043] Any processing description or box in the flowchart should be understood as representing a module, segment, logic, or part of code (which includes one or more executable instructions for implementing a particular logical function or step in the process), and alternative implementations are included within the scope of the embodiments, wherein, as those skilled in the art will understand, functions may be performed in a different order than shown or discussed (including substantially concurrent execution or execution in a different order), depending on the functions involved.

[0044] While the invention has been shown and described in detail in the accompanying drawings and the foregoing description, such showing and description should be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

[0045] Note that different combinations of the disclosed embodiments may be used, therefore referring to an embodiment or one embodiment does not imply that features from that embodiment are excluded from being used with features from other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.

Claims

1. A microprocessor, comprising: An instruction cache, configured to receive instruction fetches including a first byte portion and a second byte portion; An edge cache tag array is configured to signal further processing of the second byte portion in addition to the first byte portion based on a hit in the edge cache tag array. as well as A high-speed cache data array, configured to store instruction data in the second byte portion, The edge cache data array is configured to store the instruction data in compressed form. The compressed instruction data includes indications of instruction boundaries, cumulative prefixes, branches, and breakpoint markers. The further processing includes, in response to a hit in the edge cache tag array, the instruction data associated with the second byte portion being hierarchically assigned to the edge cache data array, processed by extended logic, and written to the XIB multiplexer queue.

2. The microprocessor of claim 1, further comprising the extension logic configured to extend the instruction data from compressed form to extended form.

3. The microprocessor according to claim 2, wherein, The extended form includes instruction data in a format suitable for storage in the XIB multiplexer queue.

4. The microprocessor of claim 3, further comprising the XIB multiplexer queue, the XIB multiplexer queue being configured to receive extended instruction data corresponding to the second byte portion from the extended logic.

5. The microprocessor according to claim 1, wherein, The processing of the edge cache data occurs at a later stage than the processing of the edge cache tag array.

6. The microprocessor of claim 1 further includes length and prefix scan logic, the length and prefix scan logic being configured to process instruction cache data corresponding to the first byte portion by performing length determination and prefix scan of instruction cache data corresponding to the first byte portion, the instruction cache data including more information bits than the side cache data.

7. The microprocessor of claim 6 further includes an XIB multiplexer queue configured to receive processed instruction cache data.

8. The microprocessor of claim 1 further includes a multiplexer queue configured to receive raw instruction data from an instruction cache corresponding to the first byte portion and the second byte portion.

9. The microprocessor according to claim 1, wherein, The first byte portion and the second byte portion each consist of 16 bytes and 32 bytes, respectively.

10. The microprocessor according to claim 1, wherein, The fetching of the first byte portion and the second byte portion corresponds to the instructions used for multimedia processing.

11. A method implemented by a microprocessor, the method comprising: The instruction is fetched at the instruction cache, including the first byte portion and the second byte portion. Based on the hit of the edge cache tag array, the edge cache tag array signals the second byte portion in addition to the first byte portion for further processing; as well as The instruction data for the second byte is stored in the edge cache data array. This also includes storing the instruction data in compressed form in the side cache data array. The compressed instruction data includes indications of instruction boundaries, cumulative prefixes, branches, and breakpoint markers. The further processing includes, in response to a hit in the edge cache tag array, the instruction data associated with the second byte portion being hierarchically assigned to the edge cache data array, processed by extended logic, and written to the XIB multiplexer queue.

12. The method of claim 11, further comprising expanding the instruction data from a compressed form to an extended form.

13. The method according to claim 12, wherein, The extension includes formatting the instruction data in a format suitable for storage in the XIB multiplexer queue, and also includes receiving the extended instruction data corresponding to the second byte portion at the XIB multiplexer queue.

14. The method according to claim 11, wherein, The processing of the edge cache data occurs at a later stage than the processing at the edge cache tag array.

15. The method according to claim 11 further includes determining the length and performing a prefix scan on the instruction cache data corresponding to the first byte portion, wherein the instruction cache data includes more information bits than the side cache data.

16. The method of claim 15, further comprising: The processed instruction cache data is received at the XIB multiplexer queue; as well as The raw instruction data is received from the instruction cache corresponding to the first byte portion and the second byte portion at the multiplexer queue.

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