Input Circuit

Abstract

The present invention discloses an input circuit. The input circuit (1) includes an input buffer circuit (12), an N-type transistor (N1) and a pull-up circuit (21). The input buffer circuit (12) uses a first node (a) as an input and a second node (b) as an output. The source of the N-type transistor (N1) is connected to an input terminal (PAD), the drain is connected to the first node (a), and the gate is connected to a power supply (VDD). The pull-up circuit (21) is arranged between the first node (a) and the power supply (VDD). When the input signal changes from low to high, the pull-up circuit (21) makes the power supply (VDD) and the first node (a) conductive within a specified period. On the other hand, when the input signal changes from high to low, the power supply (VDD) and the first node (a) are not conductive. In the input circuit, the delay time in the input buffer circuit can be shortened, and the error of the pulse width of the output signal can be suppressed.

Description

Technical Field

[0001] The present disclosure relates to an input circuit for a semiconductor integrated circuit device. Background Art

[0002] In a semiconductor integrated circuit device, when it is connected to other electronic devices, a signal with a voltage higher than the power supply voltage of the semiconductor integrated circuit device may be input. In such a case, in order to protect the internal circuit, a circuit for reducing the voltage of the input signal is provided in the input circuit of the semiconductor integrated circuit device. For example, in a commonly used input circuit, a voltage-reducing N-type transistor is provided in the front stage of the input buffer circuit, and the gate of the N-type transistor is connected to the power supply. As a result, the voltage of the input signal is reduced to a voltage equivalent to the difference between the power supply voltage and the threshold voltage of the N-type transistor. Therefore, the internal circuit of the semiconductor integrated circuit device can be protected.

[0003] In Patent Document 1, the following structure is disclosed for an input circuit: it includes an inverter as an input buffer circuit, an N-type transistor for step-down provided in the front stage of the inverter, and a P-type transistor connected between the input node of the inverter and the power supply. The gate of the P-type transistor is connected to the output node of the inverter. When the input signal rises, if the output signal of the inverter is reversed from high to low, the P-type transistor is turned on, and the voltage of the input node of the inverter rises to the power supply voltage. As a result, the reversal of the output signal is accelerated, so the delay time of the inverter can be suppressed to a shorter level.

[0004] Patent Document 1: Japanese Patent No. 3092636 Summary of the invention

[0005] -Technical problem to be solved by the invention-

[0006] However, in the input circuit disclosed in Patent Document 1, the following problem occurs. That is, when the input signal starts to fall, the P-type transistor is in the on state. Therefore, during the period until the output signal of the inverter is inverted to high and the P-type transistor is turned off, the power supply and the low drive element of the transmission side output circuit are in a short-circuit state. In this state, the transition of the input signal from high to low becomes slow, and the inversion of the output signal of the inverter is greatly delayed. Therefore, the delay time of the inverter will increase. As a result, the delay time of the inverter will have a large difference in the rise and fall of the input signal, thereby causing an error in the pulse width of the output signal of the input circuit.

[0007] An object of the present disclosure is to shorten the delay time in an input buffer circuit and suppress an error in the pulse width of an output signal in an input circuit.

[0008] -Technical solutions to technical problems-

[0009] In a first aspect of the present disclosure, an input circuit that receives an input signal at an input terminal includes an input buffer circuit, an N-type transistor, and a pull-up circuit. The input buffer circuit uses a first node as an input and a second node as an output. The source of the N-type transistor is connected to the input terminal, the drain is connected to the first node, and the gate is connected to a power supply. The pull-up circuit is arranged between the first node and the power supply. The pull-up circuit is configured to: when the input signal changes from low to high, the power supply and the first node are turned on within a specified period. On the other hand, when the input signal changes from high to low, the power supply and the first node are not turned on.

[0010] According to this aspect, the input circuit includes an input buffer circuit, an N-type transistor, and a pull-up circuit, the input buffer circuit uses the first node as input and the second node as output, the source of the N-type transistor is connected to the input terminal, the drain is connected to the first node, and the gate is connected to the power supply, and the pull-up circuit is arranged between the first node and the power supply. When the input signal changes from low to high, the pull-up circuit makes the power supply and the first node conductive within a specified period. Therefore, the voltage of the first node increases, the signal inversion of the second node is accelerated, and the delay time in the input buffer circuit is shortened. On the other hand, when the input signal changes from high to low, the pull-up circuit does not make the power supply and the first node conductive. Therefore, no short circuit occurs between the power supply and the low drive element of the transmission side output circuit, and the input signal changes from high to low quickly, so the signal inversion of the second node does not cause delay. Therefore, the difference in the delay time in the input buffer circuit can be suppressed in the rise and fall of the input signal, so the error generated in the pulse width of the output signal can be suppressed.

[0011] In a second aspect of the present disclosure, an input circuit that receives an input signal at an input terminal includes an input buffer circuit, an N-type transistor, and a pull-up circuit. The input buffer circuit uses a first node as an input and a second node as an output. The source of the N-type transistor is connected to the input terminal, the drain is connected to the first node, and the gate is connected to a power supply. The pull-up circuit is arranged between the first node and the power supply. The pull-up circuit includes a first P-type transistor and a second P-type transistor. The first P-type transistor and the second P-type transistor are connected in series between the power supply and the first node. The first P-type transistor receives an inversion signal of the signal of the first node at the gate. The second P-type transistor receives the signal of the second node at the gate when the input buffer circuit is a buffer that does not invert the logic of the signal, and receives the inversion signal of the signal of the second node at the gate when the input buffer circuit is an inverter.

[0012] According to this aspect, the input circuit includes an input buffer circuit, an N-type transistor, and a pull-up circuit. The input buffer circuit uses a first node as an input and a second node as an output. The source of the N-type transistor is connected to the input terminal, the drain is connected to the first node, and the gate is connected to the power supply. The pull-up circuit is arranged between the first node and the power supply. The pull-up circuit includes a first P-type transistor and a second P-type transistor, and the first P-type transistor and the second P-type transistor are connected in series between the power supply and the first node. The first P-type transistor receives an inversion signal of a signal of the first node at the gate. When the input buffer circuit is a buffer that does not invert the logic of the signal, the second P-type transistor receives a signal of the second node at the gate, and when the input buffer circuit is an inverter, the second P-type transistor receives an inversion signal of the signal of the second node at the gate. When the input signal is a low signal, the second P-type transistor receives a low signal at the gate, and is therefore in a conducting state. When the input signal changes from low to high, the first P-type transistor becomes in a conducting state when the inversion signal of the signal of the first node is lower than a threshold. Therefore, the voltage of the first node increases, the signal inversion of the second node is accelerated, and thus the delay time in the input buffer circuit is shortened. On the other hand, when the input signal is a high signal, the second P-type transistor receives the high signal at the gate and is in a cut-off state. Therefore, when the input signal changes from high to low, there is no short circuit between the power supply and the low drive element of the transmission side output circuit, and the input signal changes from high to low quickly, so that the signal inversion of the second node does not cause delay. Therefore, the difference in delay time in the input buffer circuit can be suppressed in the rise and fall of the input signal, and the error generated in the pulse width of the output signal can be suppressed.

[0013] -Effects of the Invention-

[0014] According to the present disclosure, in an input circuit, the delay time in the input buffer circuit can be shortened, and an error generated in the pulse width of an output signal can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a diagram showing a circuit configuration example of an input circuit according to the first embodiment.

[0016] Figure 2 It is shown Figure 1 The signal waveform diagram of the input circuit operation.

[0017] Figure 3 It is a diagram showing a circuit configuration example of an input circuit according to the second embodiment.

[0018] Figure 4 It is shown Figure 3 The signal waveform diagram of the input circuit operation.

[0019] Figure 5It is a diagram showing another circuit configuration example of the input circuit according to the second embodiment.

[0020] Figure 6 It is a diagram showing a circuit configuration example of an input circuit according to the third embodiment.

[0021] Figure 7 It is a diagram showing a circuit configuration example of an input circuit according to a fourth embodiment.

[0022] Figure 8 It is shown Figure 7 The signal waveform diagram of the input circuit operation.

[0023] Fig. 9 It is a diagram showing another circuit configuration example of the input circuit according to the fourth embodiment.

[0024] Fig.10 It is a diagram showing another circuit configuration example of the input circuit according to the fourth embodiment.

[0025] Fig.11 It is a diagram showing a circuit configuration example of an input circuit according to a fifth embodiment.

[0026] Fig.12 It is a diagram showing another circuit configuration example of the input circuit according to the fifth embodiment.

[0027] Fig.13 It is a diagram showing a circuit configuration example of an input circuit according to the sixth embodiment.

[0028] FIG. 14( a ) shows Fig.13 FIG14( b ) is a diagram showing an example of the circuit structure of the voltage conversion circuit in FIG14( a ), and FIG14( b ) is a diagram showing an example of the input and output voltages of the circuit of FIG14( a ).

[0029] Fig.15 It is a diagram showing a circuit configuration example of an input circuit according to the seventh embodiment.

[0030] -Explanation of symbols-

[0031] 1, 2, 2A, 3, 4, 4A, 4B, 5, 5A, 6, 7-input circuit; 11-inverter (input buffer circuit); 12-buffer (input buffer circuit); 13-dual-input NAND circuit (input buffer circuit); 14-dual-input AND circuit (input buffer circuit); 21, 22, 22A, 23, 24, 24A, 24B, 26, 27-pull-up circuit; 31-NAND circuit; 32, 33, 34-inverter; 61-voltage conversion circuit; N1, N2-N-type transistor; P1, P2, P5-P-type transistor; PAD-input terminal; SW-transmission gate switch; a-first node; b-second node; d-third node; VDD-power supply, power supply voltage. DETAILED DESCRIPTION

[0032] The following describes the implementation mode with reference to the accompanying drawings. It should be noted that in the circuit structure diagram shown below, the components related to the present disclosure are mainly simplified. Therefore, for example, there is a situation where the components illustrated in a directly connected manner are indirectly connected because other components are arranged between them in the actual circuit structure.

[0033] In the following description, "VDD" is used as a symbol to represent both the power supply itself and the power supply voltage. In addition, "high" and "low" of a signal refer to the logic levels of the high potential side and the low potential side of the signal. In addition, "on" and "off" of a transistor refer to whether the transistor is in a conducting state or a non-conducting state.

[0034] In the following embodiments, it is assumed that the power supply voltage VDD is 1.8 V and the voltage of the input signal is 3.3 V or 1.8 V. The circuit operation is described with respect to the case where the voltage of the input signal is 3.3 V.

[0035] (First Embodiment)

[0036] Figure 1 The circuit configuration of the input circuit according to the first embodiment is shown. Figure 1 The input circuit 1 shown is provided in the semiconductor integrated circuit, and receives an input signal sent from other electronic devices to the semiconductor integrated circuit through an input terminal PAD. When the voltage of the input signal is higher than the power supply voltage VDD, the input circuit 1 reduces the voltage of the input signal in order to protect the internal circuit of the semiconductor integrated circuit.

[0037] The input circuit 1 includes an inverter 11 as an example of an input buffer circuit, a voltage-dropping N-type transistor N1 provided between an input terminal PAD and the inverter 11, and a pull-up circuit 21. The inverter 11 takes node a as input and node b as output, and inverts the signal of node a and outputs it to node b. The source of the N-type transistor N1 is connected to the input terminal PAD, the drain is connected to the node a, and the gate is connected to the power supply VDD.

[0038] The pull-up circuit 21 includes a P-type transistor P1 and a dual-input NAND circuit 31. The source of the P-type transistor P1 is connected to the power supply VDD, and the drain is connected to the node a. The dual-input NAND circuit 31 takes the signal of the node a and the signal of the node b as inputs, and the output node, that is, the node c, is connected to the gate of the P-type transistor P1. That is, when the signals of the nodes a and b are both high and the signal of the node c is low, the P-type transistor P1 is turned on. Otherwise, the P-type transistor P1 is turned off.

[0039] Reference Figure 2 The signal waveform of Figure 1 The operation of the input circuit 1 will be described.

[0040] (1) When the input signal rises (the input signal changes from low to high)

[0041] When the input signal provided to the input terminal PAD is low, the signal at the node a is low, and the signal at the node b is high. At this time, the signal at the node c is high, and the P-type transistor P1 is turned off.

[0042] When the input signal changes from low to high, the voltage of node a rises as the voltage of the input signal rises. When the voltage of node a exceeds the threshold of NAND circuit 31, the signal of node c becomes low, thereby turning on P-type transistor P1. By turning on P-type transistor P1, the voltage of node a rises, and the inversion of the signal of node b is accelerated. Therefore, the delay time in inverter 11 becomes shorter (t1).

[0043] Here, by designing the delay time in the NAND circuit 31 to be shorter than the delay time in the inverter 11 , the P-type transistor P1 can be turned on earlier than in the example of Patent Document 1.

[0044] When the signal at the node b changes from high to low, the signal at the node c becomes high, and the P-type transistor P1 becomes cut-off again.

[0045] (2) When the input signal drops (the input signal changes from high to low)

[0046] When the input signal changes from high to low, the signal at node c remains high, and the P-type transistor P1 remains cut off. Therefore, there is no short circuit between the power supply VDD and the low drive element of the transmission side output circuit, and the input signal changes from high to low quickly, and the signal waveform is not blunted. Therefore, the inversion of the signal at node b is not delayed, and the delay time in the inverter 11 is not increased (t2).

[0047] As a result of the above operation, there is no error in the pulse width of the signal at the node b with respect to the pulse width of the input signal supplied to the input terminal PAD (tH_b=tL_PAD, tL_b=tH_PAD).

[0048] That is, in this embodiment, the pull-up circuit 21 is configured to conduct power supply VDD and node a for a predetermined period when the input signal changes from low to high, and not conduct power supply VDD and node a when the input signal changes from high to low.

[0049] As described above, according to the present embodiment, the input circuit 1 includes an inverter 11, an N-type transistor N1, and a pull-up circuit 21. The inverter 11 has a node a as an input and a node b as an output. The source of the N-type transistor N1 is connected to the input terminal PAD, the drain is connected to the node a, and the gate is connected to the power supply VDD. The pull-up circuit 21 is provided between the node a and the power supply VDD. When the input signal changes from low to high, in the pull-up circuit 21, the output node c of the NAND circuit 31 becomes low within a prescribed period, and the P-type transistor P1 conducts the power supply VDD and the node a. Therefore, the voltage of the node a increases, and the signal inversion of the node b is accelerated, so the delay time in the inverter 11 becomes shorter. On the other hand, when the input signal changes from high to low, in the pull-up circuit 21, the output node c of the NAND circuit 31 does not become low, and the P-type transistor P1 does not conduct the power supply VDD and the node a. Therefore, there is no short circuit between the power supply VDD and the low drive element of the transmission side output circuit, and the input signal quickly changes from high to low, so there is no delay in the signal inversion of the node b. Therefore, the difference in the delay time in the inverter 11 can be suppressed in the rise and fall of the input signal, so that the error generated in the pulse width of the output signal can be suppressed.

[0050] It should be noted that, as an input buffer circuit, a buffer that does not invert the logic of the signal may be used instead of the inverter 11. In this case, for example, an inverter may be provided between the node b and the NAND circuit 31. That is, the signal of the node a is provided as the first input to the NAND circuit 31, and when the input buffer circuit is an inverter, the signal of the node b is provided as the second input to the NAND circuit 31, and when the input buffer circuit is a buffer that does not invert the logic of the signal, the inverted signal of the signal of the node b is provided as the second input to the NAND circuit 31.

[0051] (Second Embodiment)

[0052] Figure 3 A circuit configuration of an input circuit according to a second embodiment is shown. Figure 3 The basic structure of the input circuit 2 shown is similar to Figure 1 As an example of an input buffer circuit, the input circuit 2 includes a buffer 12 that does not invert the signal, and also includes a structure similar to Figure 1 The pull-up circuit 21 shown is different from the pull-up circuit 22 .

[0053] The pull-up circuit 22 includes P-type transistors P1 and P2 connected in series between the power supply VDD and the node a, and an inverter 32. The inverter 32 receives the signal of the node a, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1. The P-type transistor P2 receives the signal of the output node of the buffer 12, i.e., the node b, at the gate.

[0054] Reference Figure 4 The signal waveform of Figure 3 The operation of the input circuit 2 will be described.

[0055] (1) When the input signal rises (the input signal changes from low to high)

[0056] When the input signal provided to the input terminal PAD is low, the signal at the node a is low, and the signal at the node b is low. At this time, the signal at the node c becomes high, and the P-type transistor P1 is turned off. In addition, the P-type transistor P2 is turned on.

[0057] When the input signal changes from low to high, the voltage of node a rises as the voltage of the input signal rises. When the voltage of node a exceeds the threshold of inverter 32, the signal of node c becomes low, thereby turning on P-type transistor P1. Since P-type transistor P2 is turned on, the voltage of node a rises by turning on P-type transistor P1, and the inversion of the signal of node b is accelerated. Therefore, the delay time in buffer 12 is shortened (t1).

[0058] Here, by designing the delay time in the inverter 32 to be shorter than the delay time in the buffer 12 , the P-type transistor P1 can be turned on earlier than in the example of Patent Document 1.

[0059] When the signal at the node b changes from low to high, the P-type transistor P2 becomes cut off.

[0060] (2) When the input signal drops (the input signal changes from high to low)

[0061] When the input signal changes from high to low, the signal at node b remains high, and the P-type transistor P2 remains cut off. Therefore, there is no short circuit between the power supply VDD and the low drive element of the transmission side output circuit, and the input signal changes from high to low quickly, and the signal waveform is not blunted. Therefore, the inversion of the signal at node b is not delayed, and the delay time in the buffer 12 is not increased (t2).

[0062] Next, when the voltage of node a drops and becomes lower than the threshold of inverter 32, the signal of node c becomes high, and P-type transistor P1 becomes off again. After that, after the delay time in buffer 12, the signal of node b becomes low, so P-type transistor P2 is turned on again. However, P-type transistor P1 is turned off earlier than P-type transistor P2 is turned on, so when a falling signal is input, power supply VDD and node a are not turned on.

[0063] As a result of the above operation, there is no error in the pulse width of the signal at the node b relative to the pulse width of the input signal supplied to the input terminal PAD (tH_b=tH_PAD, tL_b=tL_PAD).

[0064] That is, the pull-up circuit 22 is configured to conduct power supply VDD and node a for a predetermined period when the input signal changes from low to high, and not conduct power supply VDD and node a when the input signal changes from high to low.

[0065] As described above, according to the present embodiment, the input circuit 2 includes a buffer 12, an N-type transistor N1, and a pull-up circuit 22. The buffer 12 uses node a as input and node b as output. The source of the N-type transistor N1 is connected to the input terminal PAD, the drain is connected to the node a, and the gate is connected to the power supply VDD. The pull-up circuit 22 is provided between the node a and the power supply VDD. The pull-up circuit 22 includes P-type transistors P1 and P2 connected in series between the power supply VDD and the node a. The P-type transistor P1 receives the inversion signal of the signal of the node a at the gate, and the P-type transistor P2 receives the signal of the node b at the gate. When the input signal is low, the P-type transistor P1 receives a high signal at the gate, and is therefore in an off state. When the input signal changes from low to high, the P-type transistor P1 becomes conductive when the inversion signal of the signal of the node a is lower than the threshold. Therefore, the voltage of the node a increases, the signal inversion of the node b is accelerated, and thus the delay time in the buffer 12 is shortened. On the other hand, when the input signal is high, the P-type transistor P2 receives a high signal at the gate, and is therefore in an off state. Therefore, when the input signal changes from high to low, there is no short circuit between the power supply VDD and the low drive element of the transmission side output circuit, and the input signal changes from high to low quickly, so there is no delay in the signal inversion of the node b. Therefore, the difference in the delay time in the buffer 12 can be suppressed in the rise and fall of the input signal, and the error generated in the pulse width of the output signal can be suppressed.

[0066] Figure 5 Another circuit configuration example of the input circuit according to this embodiment is shown. Figure 5 In this case, for example, in the pull-up circuit 22A, an inverter 33 is provided between the node b and the gate of the P-type transistor P2 to provide an inverted signal of the signal at the node b to the gate of the P-type transistor P2.

[0067] (Third Embodiment)

[0068] Figure 6 A circuit configuration of an input circuit according to a third embodiment is shown. Figure 6 The basic structure of the input circuit 3 shown is similar to Figure 3 The input circuit 3 includes a structure similar to that of Figure 3 The pull-up circuit 22 shown is different from the pull-up circuit 23 .

[0069] The pull-up circuit 23 includes P-type transistors P1 and P2 connected in series between the power supply VDD and the node a, and inverters 32 and 34. The inverter 32 receives the signal of the node a, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1. The inverter 34 receives the signal of the node c, and the output node is connected to the gate of the P-type transistor P2.

[0070] That is, in Figure 3 In the input circuit 2 shown in FIG. 1 , a signal at node b is provided to the gate of the P-type transistor P2. Figure 6 In the input circuit 3 shown, a signal obtained by delaying a signal at a node a by inverters 32 and 34 is supplied to the gate of a P-type transistor P2.

[0071] Figure 6 The input circuit 3 operates with Figure 3 That is, the pull-up circuit 23 is configured to conduct the power supply VDD and the node a for a predetermined period when the input signal changes from low to high, and not conduct the power supply VDD and the node a when the input signal changes from high to low. Figure 6 In the input circuit 3, the control of the P-type transistor P2 is performed without depending on the characteristics of the buffer 12 as an example of the input buffer circuit and without affecting the characteristics of the buffer 12.

[0072] Therefore, according to the present embodiment, similarly to the second embodiment, the difference in delay time in the buffer 12 can be suppressed between the rising and falling edges of the input signal, and thus the error generated in the pulse width of the output signal can be suppressed.

[0073] (Fourth Embodiment)

[0074] Figure 7 A circuit configuration of an input circuit according to a fourth embodiment is shown. Figure 7 The input circuit 4 shown is configured to receive an enable signal EN and control the pass / fail of the input signal according to the enable signal EN. Here, the input circuit 4 is configured to pass the input signal (enable) when the enable signal EN is "1" (high), and not pass the input signal (disable) when the enable signal EN is "0" (low).

[0075] As an input buffer circuit, the input circuit 4 includes a dual-input NAND circuit 13. The dual-input NAND circuit 13 receives the signal of node a and the enable signal EN as inputs and outputs node b. When the enable signal EN is "1", the inverted signal of the signal of node a is output to node b, and when the enable signal EN is "0", node b is fixed to high. That is, the dual-input NAND circuit 13 functions as an inverter that allows the signal to pass when the enable signal EN is "1", and does not allow the signal to pass when the enable signal EN is "0".

[0076] The pull-up circuit 24 includes P-type transistors P1 and P2 connected in series between the power supply VDD and the node a, and a NAND circuit 31. The NAND circuit 31 receives the signal of the node a and the signal of the node b as inputs, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1. The gate of the P-type transistor P2 is connected to the output node, i.e., the node d, of the inverter 41 that receives the enable signal EN as input. The pull-up circuit 24 has a Figure 1 The structure is obtained by adding a P-type transistor P2 to the pull-up circuit 21.

[0077] Figure 7 When the enable signal EN is "1", the dual-input NAND circuit 13 acts as an inverter, and the P-type transistor P2 is turned on, so that the first embodiment is the same as the first embodiment. Figure 1 The input circuit 1 operates in the same manner.

[0078] Figure 8 is a signal waveform showing the action when the enable signal EN is "0". Figure 8 As shown, when the enable signal EN is "0", the node b is fixed to high. As a result, the signal of the node c provided to the gate of the P-type transistor P1 changes according to the transition of the input signal. However, since the signal of the node d provided to the gate of the P-type transistor P2 is fixed to high, the P-type transistor P2 is turned off. Therefore, there is no short circuit between the power supply VDD and the low drive element of the transmission side output circuit, and the waveform of the input signal is not blunted.

[0079] Here, assuming that the P-type transistor P2 is not added to the pull-up circuit 24, the pull-up circuit 24 has the same Figure 1 The structure of the pull-up circuit 21 is the same as that of the pull-up circuit 21. In this case, when the signal at the node c becomes low, a short circuit occurs between the power supply VDD and the low drive element of the transmission side output circuit, and the waveform of the input signal is blunted. In this embodiment, this problem is solved. That is, according to this embodiment, the pass / fail of the input signal can be controlled by the enable signal EN, and when the enable signal EN is "0", the waveform of the input signal can be prevented from being blunted.

[0080] Fig. 9 Another circuit configuration example of the input circuit according to this embodiment is shown. As an input buffer circuit, Fig. 9 The input circuit 4A shown includes a dual-input AND circuit 14. The dual-input AND circuit 14 receives the signal of node a and the enable signal EN as inputs and outputs node b. When the enable signal EN is "1", the signal of node a is output to node b, and when the enable signal EN is "0", node b is fixed to low. That is, the dual-input AND circuit 14 functions as a buffer that allows the signal to pass when the enable signal EN is "1", and does not allow the signal to pass when the enable signal EN is "0".

[0081] The pull-up circuit 24A includes P-type transistors P1, P2, P3, and an inverter 32 connected in series between the power supply VDD and the node a. The inverter 32 receives the signal of the node a, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1. The P-type transistor P2 receives the output of the dual-input AND circuit 14, i.e., the signal of the node b, at the gate. The gate of the P-type transistor P3 is connected to the output node, i.e., the node d, of the inverter 41 that takes the enable signal EN as an input. The pull-up circuit 24A has a Figure 3 The structure is obtained by adding a P-type transistor P3 to the pull-up circuit 22.

[0082] Fig. 9 When the enable signal EN is "1", the dual-input AND circuit 14 acts as a buffer, and the P-type transistor P3 is turned on, so that the input circuit 4A is connected to the second embodiment. Figure 3 On the other hand, when the enable signal EN is "0", the node b is fixed to low, and the P-type transistor P2 is turned on. However, since the signal at the node d provided to the gate of the P-type transistor P3 is fixed to high, the P-type transistor P3 is turned off. Therefore, there is no short circuit between the power supply VDD and the low drive element of the transmission side output circuit, and the waveform of the input signal is not blunted. Therefore, the same as Figure 7 The input circuit 4 has the same function and effect.

[0083] Fig.10 Another circuit configuration example of the input circuit according to this embodiment is shown. As an input buffer circuit, Fig.10 The input circuit 4B shown includes a dual-input NAND circuit 13. Figure 7 The input circuit 4 is the same as shown, and the dual-input NAND circuit 13 receives the signal of the node a and the enable signal EN as inputs and outputs the node b.

[0084] The pull-up circuit 24B includes a P-type transistor P1 and a three-input NAND circuit 35. The source of the P-type transistor P1 is connected to the power supply VDD, and the drain is connected to the node a. The three-input NAND circuit 35 takes the signal of the node a, the signal of the node b and the enable signal EN as inputs, and the output node, i.e., the node c, is connected to the gate of the P-type transistor P1.

[0085] Fig.10 When the enable signal EN is "1", the two-input NAND circuit 13 functions as an inverter and the three-input NAND circuit 35 functions as a two-input NAND circuit, so that the same as the first embodiment is used. Figure 1 On the other hand, when the enable signal EN is "0", the node b is fixed to high, but since the enable signal EN is included in the input of the three-input NAND circuit 35, the node c is fixed to high. Therefore, the P-type transistor P1 is turned off. Therefore, there is no short circuit between the power supply VDD and the low drive element of the transmission side output circuit, and the waveform of the input signal is not blunted. Therefore, it is possible to obtain the same Figure 7 The input circuit 4 has the same function and effect.

[0086] Fig.10 The structure is that only one stage of P-type transistors is arranged between the power supply VDD and the node a. From the viewpoint of area efficiency, this structure is effective when it is desired to avoid a multi-stage structure of transistors.

[0087] It should be noted that this embodiment can also be applied when the logic of the enable signal EN is opposite, that is, when the enable signal EN is "0", the input signal is passed (enabled) and when the enable signal EN is "1", the input signal is not allowed to pass (disabled). Figure 7 In the structure, an enable signal EN is provided to the gate of the P-type transistor P2, and an inversion signal of the enable signal EN is provided to the dual-input NAND circuit 13.

[0088] (Fifth Embodiment)

[0089] Fig.11 A circuit configuration of an input circuit according to a fifth embodiment is shown. Fig.11 The input circuit 5 shown includes the first embodiment in addition to Figure 1 In addition to the structure of the input circuit 1 shown, it also includes an N-type transistor N2 provided between the power supply VDD and the node a. That is, the N-type transistor N2 is provided in parallel with the P-type transistor P1 of the pull-up circuit 21. The drain of the N-type transistor N2 is connected to the power supply VDD, the source is connected to the node a, and the gate is connected to the input terminal PAD.

[0090] Fig.11 The input circuit 5 operates with Figure 1 The operation of the input circuit 1 is the same as that of the input circuit 1. However, when a rising signal having a voltage higher than the power supply voltage VDD is input to the input terminal PAD (when the input signal changes from low to high), the N-type transistor N2 is turned on. Thus, the voltage of the node a can be assisted to rise.

[0091] Fig.12 Another circuit configuration example of the input circuit according to the fifth embodiment is shown. Fig.12 The input circuit 5A shown in the figure includes the fourth embodiment in addition to Fig. 9 In addition to the structure of the input circuit 4A shown in the figure, it also includes an N-type transistor N2 provided between the power supply VDD and the node a. That is, the N-type transistor N2 is provided in parallel with the P-type transistors P1, P2, and P3 of the pull-up circuit 24A. The drain of the N-type transistor N2 is connected to the power supply VDD, the source is connected to the node a, and the gate is connected to the input terminal PAD.

[0092] Fig.12 The operation of the input circuit 5A is Fig. 9 However, when a rising signal having a voltage higher than the power supply voltage VDD is input to the input terminal PAD (when the input signal changes from low to high), the N-type transistor N2 is turned on. This assists the voltage rise of the node a.

[0093] It should be noted that in the configurations of the other input circuits shown in the first to fourth embodiments, Fig.11 and Fig.12 The structure of FIG. 1 is similarly modified by adding an N-type transistor N2.

[0094] (Sixth Embodiment)

[0095] With the recent demand for power saving, a system for turning on / off the power supply of a semiconductor integrated circuit as needed is generally adopted. Figure 1 In the input circuit 1 shown, when the power supply is turned off, that is, when VDD is 0 V, it is not allowed to receive a high voltage signal at the input terminal PAD. That is, if the drain-gate withstand voltage of the N-type transistor N1 is 1.8 V, when the input terminal PAD receives an input signal of 3.3 V when VDD is 0 V, the drain-gate voltage of the N-type transistor N1 becomes 3.3 V, which exceeds the drain-gate withstand voltage.

[0096] In contrast, in this embodiment, an input circuit is provided that can turn off the power supply, that is, make VDD 0 V, without depending on a signal received by the input terminal PAD.

[0097] Fig.13A circuit configuration of an input circuit according to the sixth embodiment is shown. Fig.13 The basic structure of the input circuit 6 shown is similar to Figure 1 The input circuit 1 shown in FIG. 2 is the same as that shown in FIG. However, the gate of the N-type transistor N1 and the drain of the P-type transistor P1 in the pull-up circuit 26 are not connected to the power supply VDD, but are connected to the node d. The node d is connected to the input terminal PAD via the voltage conversion circuit 61. When the power supply VDD is turned on, the voltage conversion circuit 61 outputs the power supply voltage VDD to the node d, and when the power supply VDD is turned off, the voltage of the input terminal PAD is divided and output to the node d.

[0098] FIG. 14(a) shows an example of a circuit structure of a voltage conversion circuit 61, and FIG. 14(b) shows the relationship between the input and output voltages of the voltage conversion circuit 61. In the voltage conversion circuit 61, when the power supply is turned on (VDD=1.8V), the N-type transistor N61 is turned on, so that the gate voltage of the P-type transistor P63 becomes 0V, and thus the P-type transistor P63 is turned on. As a result, regardless of the signal received by the input terminal PAD, the voltage VDD is output to the node d. On the other hand, it is assumed that when the power supply is disconnected (VDD=0V), a high signal (3.3V) is provided to the input terminal PAD. Since the gate voltage is 0V, the P-type transistors P61 and P62 are both turned on. Therefore, the voltage divided by the series-connected resistor R, that is, 3.3 / 2V, is output to the node d via the transistors P61 and P62. It should be noted that the structure of the voltage conversion circuit 61 shown in FIG. 14(a) is an example and is not limited to this.

[0099] Fig.13 The input circuit 6 operates as follows. When the power is turned on (VDD = 1.8V), the power supply voltage VDD is output to the node d through the operation of the voltage conversion circuit 61. Therefore, Fig.13 The input circuit 6 is connected with Figure 1 The same action as the input circuit 1.

[0100] On the other hand, when the power supply is disconnected (VDD=0V), if a high signal (3.3V) is provided to the input terminal PAD, the voltage of the node d becomes 3.3 / 2V through the action of the voltage conversion circuit 61. At this time, the N-type transistor N1 is turned on. The voltage of the node a drops from the voltage of the input terminal PAD 3.3V due to the pinch-off characteristic of the N-type transistor N1, and does not exceed the voltage of the node d. In addition, according to VDD=0V, the voltage of the node c becomes almost 0V, the P-type transistor P1 is turned on, and the node a and the node d are connected. As a result, the voltage of the node a becomes 3.3 / 2V.

[0101] Thus, since the gate of the N-type transistor N1 is connected to the node d instead of the power supply VDD, the drain-gate voltage of the N-type transistor N1 does not exceed the drain-gate withstand voltage even if a high signal is supplied to the input terminal PAD when the power supply is off.

[0102] In addition, since the drain of the P-type transistor P1 is not connected to VDD but to the node d, even if a high signal is provided to the input terminal PAD when the power is off, no unnecessary inflow current is generated from the input terminal PAD. That is, if the drain of the P-type transistor P1 is connected to the power supply VDD, when a high signal is provided to the input terminal PAD when the power is off, current will flow from the input terminal PAD along the path of the N-type transistor N1→node a→P-type transistor P1→VDD. In this embodiment, this problem is avoided.

[0103] Furthermore, since the reduced voltage is supplied to the node a, the voltage does not exceed the withstand voltage of the previous transistor.

[0104] Therefore, according to the present embodiment, in the input circuit 6 , the power supply can be turned off without causing degradation or damage to the transistor and without causing unnecessary inflow of current.

[0105] It should be noted that, here, the present embodiment is described by taking the case where the present embodiment is applied to the first embodiment as an example, but it can also be applied to the other embodiments mentioned above. That is, the gate of the N-type transistor N1 and the drain of the P-type transistor P1 in the pull-up circuit 22 and the like are connected to the node d, and the node d is connected to the input terminal PAD via the voltage conversion circuit 61. Fig.11 The input circuit 5 and Fig.12 In the input circuit 5A shown, the drain of the N-type transistor N2 may also be connected to the node d.

[0106] (Seventh Embodiment)

[0107] Fig.15 A circuit configuration of an input circuit according to the seventh embodiment is shown. Fig.15 The basic structure of the input circuit 7 shown is similar to Fig.13 The input circuit 6 is the same as shown. However, in the pull-up circuit 27, a P-type transistor P5 and a transmission gate switch SW composed of a P-type transistor and an N-type transistor connected in parallel are added.

[0108] The P-type transistor P5 is connected between a node c which is the gate of the P-type transistor P1 and a node a which is the source of the P-type transistor P1. The gate of the P-type transistor P5 is connected to the power supply VDD. The transmission gate switch SW is connected between the node c and the output node of the NAND gate 31. The gate of the N-type transistor constituting the transmission gate switch SW is connected to the power supply VDD, and the gate of the P-type transistor constituting the transmission gate switch SW is connected to the node a.

[0109] Fig.15 The input circuit 7 shown in the figure operates as follows. When the power supply is turned on (VDD=1.8V), the P-type transistor P5 is turned off, and the transmission gate switch SW is turned on because its N-type transistor is turned on. Therefore, Fig.15 The input circuit 7 is connected with Fig.13 The same action as the input circuit 6.

[0110] On the other hand, when the power supply is turned off (VDD=0V), if a high signal (3.3V) is provided to the input terminal PAD, the P-type transistor P5 is turned on, thereby connecting the node a and the node c, and the voltages of the nodes a and c are the same as the node d. Therefore, the P-type transistor P1 is turned off. In addition, in the transmission gate switch SW, the N-type transistor is turned off because the gate voltage is 0V, and the P-type transistor is turned off because the voltage of the drain (node ​​c) is equal to the voltage of the gate (node ​​a), so the transmission gate switch SW is turned off. As a result, the node c is cut off from the output node of the NAND gate 31, so that unnecessary inflow current from the P-type transistor P5 through the NAND gate 31 can be prevented.

[0111] Therefore, according to the present embodiment, in the input circuit 7 , the power supply can be turned off without causing degradation or damage to the transistor and without causing unnecessary inflow of current.

[0112] It should be noted that, here, the present embodiment is described by taking the case where the circuit structure of the first embodiment is applied as an example, but it can also be applied to the circuit structures of the above-mentioned other embodiments. That is, in the pull-up circuit, a P-type transistor P5 is connected between the gate of any one of the P-type transistors P1, P2, and P3 and the node a, and a transmission gate switch SW is provided between the gate and the node of the previous stage circuit to which the signal is sent.

[0113] For example, for Figure 3For the input circuit 2, a P-type transistor P5 is connected between the gate of the P-type transistor P1 and the node a, and a transmission gate switch SW is provided between the gate of the P-type transistor P1 and the output node of the inverter 32. Alternatively, a P-type transistor P5 is connected between the gate of the P-type transistor P2 and the node a, and a transmission gate switch SW is provided between the gate of the P-type transistor P2 and the input buffer 12.

[0114] It should be noted that the present disclosure is not limited to the structures shown in the above-mentioned embodiments, and those skilled in the art can make many changes under the technical ideas of the present disclosure. In addition, the various constituent elements in the multiple embodiments can be arbitrarily combined within the scope of the present disclosure.

[0115] -Industrial Applicability-

[0116] In the present disclosure, in the input circuit, the delay time in the input buffer circuit can be shortened and the error generated in the pulse width of the output signal can be suppressed, which is effective in achieving, for example, speeding up LSI and improving performance.

Claims

1. An input circuit, which is an input circuit that receives an input signal at an input terminal, characterized in that: The input circuit includes an input buffer circuit, an N-type transistor and a pull-up circuit. The input buffer circuit has the first node as input and the second node as output, The source of the N-type transistor is connected to the input terminal, the drain of the N-type transistor is connected to the first node, and the gate of the N-type transistor is connected to a power supply. The pull-up circuit is arranged between the first node and the power supply, The pull-up circuit is configured to conduct the power supply and the first node for a predetermined period when the input signal changes from low to high, and not conduct the power supply and the first node when the input signal changes from high to low. The pull-up circuit includes a NAND circuit and a P-type transistor. The NAND circuit uses the signal of the first node as a first input, and when the input buffer circuit is an inverter, uses the signal of the second node as a second input, and when the input buffer circuit is a buffer that does not invert the logic of the signal, uses the inverted signal of the signal of the second node as the second input, The source of the P-type transistor is connected to the power supply, the drain of the P-type transistor is connected to the first node, and the gate of the P-type transistor receives the output of the NAND circuit.

2. The input circuit according to claim 1, characterized in that: The input buffer circuit receives an enable signal, allows the signal of the first node to pass when the enable signal is at a first logic level, and does not allow the signal of the first node to pass when the enable signal is at a second logic level. The pull-up circuit is configured to prevent conduction between the power supply and the first node when the enable signal is at the second logic level.

3. The input circuit according to claim 1, characterized in that: The input circuit includes a second N-type transistor, a drain of the second N-type transistor is connected to the power supply, a source of the second N-type transistor is connected to the first node, and a gate of the second N-type transistor is connected to the input terminal.

4. An input circuit, which is an input circuit that receives an input signal at an input terminal, characterized in that: The input circuit includes an input buffer circuit, an N-type transistor and a pull-up circuit. The input buffer circuit has the first node as input and the second node as output, The source of the N-type transistor is connected to the input terminal, the drain of the N-type transistor is connected to the first node, and the gate of the N-type transistor is connected to a power supply. The pull-up circuit is arranged between the first node and the power supply, The pull-up circuit is configured to conduct the power supply and the first node for a predetermined period when the input signal changes from low to high, and not conduct the power supply and the first node when the input signal changes from high to low. The pull-up circuit includes a first P-type transistor and a second P-type transistor, The first P-type transistor and the second P-type transistor are connected in series between the power supply and the first node, The first P-type transistor receives an inversion signal of the signal at the first node at a gate. The second P-type transistor receives the signal of the second node at a gate when the input buffer circuit is a buffer that does not invert the logic of a signal, and receives an inverted signal of the signal of the second node at a gate when the input buffer circuit is an inverter.

5. The input circuit according to claim 4, characterized in that: The input buffer circuit receives an enable signal, allows the signal of the first node to pass when the enable signal is at a first logic level, and does not allow the signal of the first node to pass when the enable signal is at a second logic level. The pull-up circuit is configured to prevent conduction between the power supply and the first node when the enable signal is at the second logic level.

6. The input circuit according to claim 4, characterized in that: The input circuit includes a second N-type transistor, a drain of the second N-type transistor is connected to the power supply, a source of the second N-type transistor is connected to the first node, and a gate of the second N-type transistor is connected to the input terminal.

7. An input circuit, which is an input circuit that receives an input signal at an input terminal, characterized in that: The input circuit includes an input buffer circuit, an N-type transistor and a pull-up circuit. The input buffer circuit has the first node as input and the second node as output, The source of the N-type transistor is connected to the input terminal, the drain of the N-type transistor is connected to the first node, and the gate of the N-type transistor is connected to a power supply. The pull-up circuit is arranged between the first node and the power supply, The pull-up circuit is configured to conduct the power supply and the first node for a predetermined period when the input signal changes from low to high, and not conduct the power supply and the first node when the input signal changes from high to low. The pull-up circuit includes a first P-type transistor and a second P-type transistor, The first P-type transistor and the second P-type transistor are connected in series between the power supply and the first node, The first P-type transistor receives an inversion signal of the signal at the first node at a gate. The second P-type transistor receives at a gate an inversion signal of a signal received by a gate of the first P-type transistor.

8. The input circuit according to claim 7, characterized in that: The input buffer circuit receives an enable signal, allows the signal of the first node to pass when the enable signal is at a first logic level, and does not allow the signal of the first node to pass when the enable signal is at a second logic level. The pull-up circuit is configured to prevent conduction between the power supply and the first node when the enable signal is at the second logic level.

9. The input circuit according to claim 7, characterized in that: The input circuit includes a second N-type transistor, a drain of the second N-type transistor is connected to the power supply, a source of the second N-type transistor is connected to the first node, and a gate of the second N-type transistor is connected to the input terminal.

10. An input circuit, which is an input circuit that receives an input signal at an input terminal, characterized in that: The input circuit includes an input buffer circuit, an N-type transistor and a pull-up circuit. The input buffer circuit has the first node as input and the second node as output, The source of the N-type transistor is connected to the input terminal, the drain of the N-type transistor is connected to the first node, and the gate of the N-type transistor is connected to a power supply. The pull-up circuit is arranged between the first node and the power supply, The pull-up circuit includes a first P-type transistor and a second P-type transistor, The first P-type transistor and the second P-type transistor are connected in series between the power supply and the first node, The first P-type transistor receives an inversion signal of the signal at the first node at a gate. The second P-type transistor receives the signal of the second node at a gate when the input buffer circuit is a buffer that does not invert the logic of a signal, and receives an inverted signal of the signal of the second node at a gate when the input buffer circuit is an inverter.

11. The input circuit according to claim 10, characterized in that: The input buffer circuit receives an enable signal, allows the signal of the first node to pass when the enable signal is at a first logic level, and does not allow the signal of the first node to pass when the enable signal is at a second logic level. The pull-up circuit includes a third P-type transistor, The third P-type transistor is connected in series with the first P-type transistor and the second P-type transistor, The third P-type transistor receives a low signal at a gate when the enable signal is at the first logic level, and receives a high signal at a gate when the enable signal is at the second logic level.

12. The input circuit according to claim 10, characterized in that: The input circuit includes a second N-type transistor, a drain of the second N-type transistor is connected to the power supply, a source of the second N-type transistor is connected to the first node, and a gate of the second N-type transistor is connected to the input terminal.

13. An input circuit, which is an input circuit that receives an input signal at an input terminal, characterized in that: The input circuit includes an input buffer circuit, an N-type transistor, a pull-up circuit and a voltage conversion circuit. The input buffer circuit has the first node as input and the second node as output, The source of the N-type transistor is connected to the input terminal, the drain of the N-type transistor is connected to the first node, and the gate of the N-type transistor is connected to the third node. The pull-up circuit is arranged between the first node and the third node, The voltage conversion circuit is configured to output the voltage of the power supply to the third node when the power supply is turned on, and to divide the voltage of the input terminal and output it to the third node when the power supply is turned off. The pull-up circuit is configured such that, when the power supply is turned on, when the input signal changes from low to high, the third node and the first node are conducted within a specified period, and on the other hand, when the input signal changes from high to low, the third node and the first node are not conducted.

14. The input circuit according to claim 13, characterized in that: The pull-up circuit includes a NAND circuit, a first P-type transistor, a second P-type transistor and a transmission gate switch. The NAND circuit uses the signal of the first node as a first input, and when the input buffer circuit is an inverter, uses the signal of the second node as a second input, and when the input buffer circuit is a buffer that does not invert the logic of the signal, uses the inverted signal of the signal of the second node as the second input, The source of the first P-type transistor is connected to the third node, the drain of the first P-type transistor is connected to the first node, and the gate of the first P-type transistor receives the output of the NAND circuit. The source of the second P-type transistor is connected to the gate of the first P-type transistor, the drain of the second P-type transistor is connected to the first node, and the gate of the second P-type transistor is connected to the power supply. The transmission gate switch is composed of a P-type transistor and an N-type transistor connected in parallel, and is arranged between the gate of the first P-type transistor and the output node of the NAND circuit, the gate of the P-type transistor is connected to the first node, and the gate of the N-type transistor is connected to the power supply.

15. An input circuit, which is an input circuit that receives an input signal at an input terminal, characterized in that: The input circuit includes an input buffer circuit, an N-type transistor, a pull-up circuit and a voltage conversion circuit. The input buffer circuit has the first node as input and the second node as output, The source of the N-type transistor is connected to the input terminal, the drain of the N-type transistor is connected to the first node, and the gate of the N-type transistor is connected to the third node. The pull-up circuit is arranged between the first node and the third node, The voltage conversion circuit is configured to output the voltage of the power supply to the third node when the power supply is turned on, and to divide the voltage of the input terminal and output it to the third node when the power supply is turned off. The pull-up circuit includes a first P-type transistor and a second P-type transistor, The first P-type transistor and the second P-type transistor are connected in series between the third node and the first node, The first P-type transistor receives an inversion signal of the signal at the first node at a gate. The second P-type transistor receives the signal of the second node at a gate when the input buffer circuit is a buffer that does not invert the logic of the signal, and receives an inversion signal of the signal of the second node at a gate when the input buffer circuit is an inverter.

16. The input circuit according to claim 15, characterized in that: The pull-up circuit includes a third P-type transistor and a transmission gate switch, The source of the third P-type transistor is connected to the gate of the first P-type transistor or the second P-type transistor, the drain of the third P-type transistor is connected to the first node, and the gate of the third P-type transistor is connected to the power supply. The transmission gate switch is composed of a P-type transistor and an N-type transistor connected in parallel, and is arranged between the gate of the first P-type transistor or the second P-type transistor and a node that sends a signal to the gate, the gate of the P-type transistor is connected to the first node, and the gate of the N-type transistor is connected to the power supply.

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