System-on-chip device, spread spectrum clock generator and method thereof

Abstract

The present application provides a system-on-chip device, a spread spectrum clock generator, and a method thereof. In one embodiment, a spread spectrum clock generator includes a digital deltasigma modulator coupled to a fractional-N phase-locked loop (PLL), wherein the PLL includes a discrete-time capacitor multiplier loop filter.

Description

Technical Field

[0001] The present invention relates generally to spread spectrum clock generators, and in particular to spread spectrum clock generators for use in a system on a chip (SoC). Background Art

[0002] Spread spectrum clock generators (SSCGs) are ubiquitous in modern system-on-chip (SoC) devices and microprocessors. SSCGs are required to reduce electromagnetic interference (EMI), which can cause systems to interfere with each other. SSCGs are typically implemented as fractional-N phase-locked loops (PLLs) using digital delta sigma (delta-sigma) modulators (DDSMs), which require low PLL bandwidth to filter quantization noise. Low loop bandwidth requires large on-chip capacitors, which can result in excessive area consumption. In addition to capacitors, loop filters are typically implemented using resistors. Together, the resistors and capacitors form the poles and zeros necessary to stabilize the PLL's control loop. Because die-cast resistors and capacitors cannot be matched in process, the PLL's control loop can be degraded, resulting in reduced EMI suppression and increased jitter. Summary of the Invention

[0003] In one embodiment, a spread spectrum clock generator includes a digital delta sigma modulator coupled to a fractional-N phase-locked loop (PLL) including a discrete-time capacitor multiplier loop filter.

[0004] Other systems, methods, features and advantages of the present invention will be or become apparent to those skilled in the art by examining the following drawings and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present invention, and be protected by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present invention may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on clearly illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals throughout the various figures refer to corresponding parts.

[0006] Figure 1A is a block diagram illustrating an example environment in which embodiments of a process-independent spread spectrum clock generator (SSCG) may be used.

[0007] Figure 1B is a schematic diagram illustrating an exemplary embodiment of a process-independent SSCG.

[0008] Figures 2A-2C is a schematic diagram illustrating the continuous-time to discrete-time conversion of the capacitance multiplier loop filter of the process-independent SSCG.

[0009] Figure 2D is a schematic diagram illustrating example non-overlapping clocks used in a switched capacitor resistor of a discrete-time capacitance multiplier loop filter of an embodiment of a process-independent SSCG.

[0010] Figure 3 is a schematic diagram illustrating a small-signal phase-domain model of a phase-locked loop, from which the open-loop transfer function of an embodiment of a process-independent SSCG is derived.

[0011] Figure 4 is a flow chart illustrating an embodiment of an example discrete-time loop filtering method. DETAILED DESCRIPTION

[0012] Certain embodiments of a process-independent spread spectrum clock generator (SSCG) and associated methods are disclosed that utilize a combination of switched capacitor resistors for the capacitance multiplier loop filter and a calibrated voltage-controlled oscillator (VCO) in combination with a scaled current reference to provide a process-independent SSCG.

[0013] Additionally, SSCGs are typically implemented as fractional-N phase-locked loops (PLLs) using digital delta sigma modulators. The fabrication of SSCGs involves different processes for resistors and capacitors, and therefore one process may not work well with another, which can result in reduced PLL performance. In contrast, certain embodiments of process-independent SSCGs use a discrete-time capacitor multiplier filter in combination with a switched-capacitor (programmable) charge pump current reference that is dynamically selected (i.e., dynamically adjusted) based on the VCO gain. This maintains the PLL control loop gain constant, achieving process-independent operation that improves the performance of the PLL and, therefore, the SSCG (e.g., smaller area consumption, improved EMI suppression, and / or reduced jitter).

[0014] Having summarized certain features of the process-independent SSCG of the present invention, reference will now be made in detail to the description of the process-independent SSCG as shown in the accompanying drawings. Although the process-independent SSCG will be described in conjunction with these drawings, it is not intended to limit it to one or more embodiments disclosed herein. That is, although the present invention is susceptible to modifications and alternative forms, its specific embodiments are shown by way of example in the drawings and will be described herein in detail enough for those skilled in the art to understand. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to the specific form disclosed. On the contrary, the present invention will cover all modifications, equivalents and alternatives that fall within the spirit and scope of the invention as defined by the appended claims. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning potentially) rather than a mandatory sense (i.e., meaning must). Similarly, the word "include" means including but not limited to.

[0015] Now refer to Figure 1A , shows an example environment 10 in which an embodiment of a process-independent spread spectrum clock generator (SSCG) can be used. The environment includes a crystal oscillator 12 that provides a reference clock to a system on a chip (SoC) 14. The SoC 14 includes a process-independent SSCG 16 that is configured to control a plurality of phase-locked loops (PLLs) 18. Each of the PLLs 18 is configured to provide clock signals to different functional areas or logic on the SoC 14 (e.g., the SoC 14). Figure 1A 1, 2, . . . N). For example, PLL0 18 can be configured to drive multiple processor cores of a multi-core processor on SoC 14 (e.g., clock the cores) based on the output of SSCG 16. As another example, PLL118 can be configured to generate a double data rate (DDR) reference clock based on the output of the SSCG. As will be appreciated by those skilled in the art, additional and / or other logic may be present as a recipient of the output of PLL 18, and further discussion thereof is omitted herein for the sake of brevity as it is not germane to the present invention.

[0016] Figure 1B is a schematic diagram illustrating an exemplary embodiment of a process-independent SSCG. Specifically, Figure 1B Shown in more detail Figure 1ASSCG 16. As is well known, a frequency reference (such as a crystal oscillator 12) can be a major source of electromagnetic interference (EMI) on a SoC (in addition to other sources of EMI). A spread spectrum clock generator implements a technique in which the clock frequency is slightly modulated to reduce the peak energy generated by the clock. Spread spectrum clocking reduces clock-generated EMI from both the fundamental frequency and subsequent harmonics, thereby reducing overall system EMI. In other words, the spread spectrum clock generator is configured to spread the energy over a larger portion of a given frequency spectrum. As described above, the SSCG 16 includes a fractional-N PLL that, in addition to the innovations described herein, uses a digital delta sigma modulator (DDSM), a configuration commonly used in the industry. The crystal oscillator 12 provides a reference frequency to the PLL of the SSCG 16, which in turn implements the function of a frequency synthesizer that provides a spread spectrum clock to multiple PLLs 18. The SSCG 16 includes a phase frequency detector (PFD) 20, a charge pump current reference generator 22, a charge pump (CP) 24, a discrete time capacitor loop filter 26, a voltage controlled oscillator (VCO) 28, a 1 / M frequency divider 30, a multi-mode divider (N / N+P) 32, a DDSM 34, and a ramp generator 36. The functions of components 20, 22, 24, 28, 30, 32, 34, and 36 are well known in the industry, and therefore, a discussion thereof is omitted here for the sake of brevity. Additional information regarding the SSCG can be found in published literature such as Texas Instruments. TM ) Technical Brief SWRA029, "Fractional / Integer-N PLL Basics". Instead, for the purposes of this invention, the focus will be on loop filter 26 (hereinafter in conjunction with Figures 2A-2D Further described) and the configurable operation between the charge pump current reference generator 22 and the VCO 28 and its effect on the corresponding gain coefficient to ensure that it is not dependent on the process (hereinafter combined with Figure 3 further described).

[0017] First focus Figures 2A-2C , shows a schematic diagram illustrating continuous-time to discrete-time conversion of a capacitance multiplier loop filter. Figure 2ASpecifically shown is a continuous-time capacitance multiplier loop filter 38 that receives current Ip from charge pump 24 (e.g., as generated by charge pump current reference generator 22). Continuous-time capacitance multiplier loop filter 38 includes a continuous-time capacitance multiplier 40, a capacitor C2 42 in the circuit in addition to capacitance multiplier 40, a resistor R3 44, and another capacitor C3 46. Continuous-time capacitance multiplier 40 includes an amplifier 48 having an output connected to the inverting input (-); a resistor Rx 50 and a capacitor C1 52 arranged in series at the non-inverting input (+); and another resistor Ry 54 at the output of amplifier 48. Certain embodiments of a process-independent SCCG use an equivalent switched-capacitor loop filter to efficiently implement the functionality of continuous-time capacitance multiplier loop filter 38, which reduces chip area, among other benefits. To illustrate this implementation, an illustration of the conversion from continuous time to discrete time is provided below.

[0018] Figure 2B A version 38A of the continuous-time capacitance multiplier loop filter 38 is shown, wherein capacitance multiplier 40 is shown replaced by capacitance multiplier 40A having an effective impedance, ie, 1 / 2 of C 1eff R arranged in series 1eff The following equations 1-5 can be obtained from Figures 2A-2B The test is derived as follows:

[0019]

[0020] C 1eff =C1(1+n r ) (Equation 2)

[0021] n r =R x / R y (Equation 3)

[0022] ix=I p / (1+n r ) (Equation 4)

[0023] R y =R x / n r (Equation 5)

[0024] Figure 2C The discrete time capacitance multiplier filter 26 resulting from the above conversion is shown. Specifically, Figure 2AResistors Rx 50, Ry 54, and R3 44 have been replaced by switched-capacitor resistors 56, 58, and 60, while amplifier 48 and capacitors C1 52, C2 42, and C3 46 remain. Thus, discrete-time capacitance multiplier filter 26 includes a parallel arrangement of switched-capacitor resistor Rx 56 and capacitor C1 52 at the non-inverting input of amplifier 48, and at the output of amplifier 48, within the loop, is switched-capacitor resistor Ry 58, the output of which is fed back to the input of switched-capacitor resistor Rx 56, which also receives the charge pump current Ip. Outside the loop, at the output (Vc) of loop filter 26, there is a parallel arrangement of capacitor C2 42, switched-capacitor resistor R3 60, and capacitor C3 46.

[0025] With specific reference to switched capacitor resistors 56, 58, and 60, switched capacitor resistors Rx 56 and R360 are similarly configured, while switched capacitor resistor Ry 58 comprises a bilinear switched capacitor resistor. Referring to switched capacitor resistor Rx 56, switched capacitor resistor Rx 56 comprises a first switch driven by a first clock Φ1 and a second switch driven by a second clock Φ2 on each side of the Cx branch node (including capacitor Cx (in this branch). The first clock Φ1 and the second clock Φ2 comprise non-overlapping clocks 62 and 64, as shown in FIG. Figure 2D , which is generated using known clock generation techniques for switched capacitor circuits, and therefore, for the sake of brevity, its discussion is omitted here. Note that these switches can be implemented according to any known transistor and / or switching logic consistent with the manufacturing method for SSCG 16. Similarly, switched capacitor resistor R3 60 includes a first switch driven by a first clock Φ1 and a second switch driven by a second clock Φ2 on each side of the CR3 branch node (including capacitor CR3 (in this branch)).

[0026] As indicated above, the switched capacitor resistor Ry 58 comprises a bilinear switched capacitor resistor. The switched capacitor resistor Ry 58 comprises a set of switches on each side of the opposite side node of the branch (including the capacitor Cy). Figure 2C At the top node depicted in , on either side of the node are a first switch driven by a first clock Φ1 and a second switch driven by a second clock Φ2. Figure 2CAt the bottom node depicted in FIG, on either side of the node is a third switch driven by the second clock Φ2 and a fourth switch driven by the first clock Φ1. Further explaining, since amplifier 48 is used to drive load Cy with a single set of switches, amplifier 48 becomes unloaded for one of the clock states (e.g., Φ2), which may cause amplifier 48 (e.g., a buffer) to become unstable. By using a dual linear switched capacitor configuration, this unloaded state is avoided because amplifier 48 is always exposed to the same load.

[0027] like Figures 2A-2C As shown in FIG, the continuous time capacitance multiplier filter 38 uses actual resistors Rx 50, Ry 54 and R3 44, as shown in FIG. Figure 2C As shown in , the actual resistors Rx 50, Ry 54 and R3 44 are converted into discrete time by being implemented as switched capacitor resistors Rx 56, Ry 58 and R3 60, respectively. Therefore, the following equations 6-8 can be described:

[0028] Rx = T / Cx = 1 / fCx (Equation 6)

[0029] Ry = T / 4Cy = 1 / 4Cy (Equation 7)

[0030] R3=T / CR3=1 / fCR3 (Equation 8)

[0031] In equations 6-8, T = the period of clocks Φ1, Φ2, and f = the frequency of clocks Φ1, Φ2. Note that in the portion of the continuous-time capacitance multiplier loop filter 38 that performs capacitance multiplication (e.g., the continuous-time capacitance multiplier), the effective capacitance C 1eff is given by Equation 2, and Ry is given by Equation 5. Checking Equations 2 and 5, when increasing n r When the effective capacitance increases, Ry decreases. Therefore, n r Doubling Ry reduces Ry by a factor of 2. Since for a standard switched capacitor resistor Cy = T / Ry, reducing Ry by a factor of 2 will double Cy. As shown in equation 7 above, using a bilinear switched capacitor resistor Ry58 increases n r The area loss is reduced by a factor of 4. In addition, due to Figure 2C The poles and zeros of the PLL control loop are functions of the ratio of the capacitors (the resistors replaced by capacitors), and further because the switched capacitor resistors are based on the reference frequency of the current reference (which depends on the off-chip crystal oscillator 12), the discrete-time multiplier loop filter 26 is independent of the process.

[0032] The analysis of the SSCG transfer function is discussed below, in particular its independence from process, which can be assessed by looking at the gain coefficient of the open-loop transfer function (and similarly, the closed-loop transfer function with the same parameters). Figure 3 is a schematic diagram illustrating a small-signal phase-domain model 66 of a phase-locked loop, from which the open-loop transfer function of an embodiment of a process-independent SSCG is derived. Examination of the small-signal phase-domain model 66 reveals the following equations 9-15 (where a = 1, and R 1e =R 1eff And C 1e =C 1eff ):

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040] The open-loop gain (or loop gain) LG(s) is given by the following equations 16-17:

[0041]

[0042]

[0043] Substituting z(s) yields the following equation 18:

[0044]

[0045] This can be achieved by grouping the first dividend and divisor of Equation 18 into one term, as shown in Equation 19 below:

[0046]

[0047] Specifically, LG(s) can be rewritten as follows:

[0048]

[0049]

[0050]

[0051] For ω p1 、ω p2 and the equations for b and c are shown in Equations 12 - 15 (a still equals 1). Examination of LG(s) shows that in a conventional system, K, ω z 、ω p1 、ω p2 are functions of the absolute values of resistors, capacitors, I p and K VCO Therefore, LG(s) is not independent of the process. However, as shown in Figure 2C , independence from the process can be achieved by implementing the resistors in the capacitance multiplier filter 38 of ( Figure 2A ) as switched-capacitor resistors. When converting the filter from the continuous-time version to the discrete-time version, note that as described above, for Rx and R3, R = T / C, and for Ry, R = T / 4C. These approximations are valid as long as the bandwidth of the PLL of the SSCG 16 is much less than the reference clock frequency (e.g., BW << Fref). Reviewing LG(s), referring to Equation 20, and noting that if K, ω z 、ω p1 、ω p2 are process-independent, then LG(s) is process-independent. Through simple algebraic manipulation of the above equations, the following Equation 23 can be shown:

[0052]

[0053] In other words, ω z is a function of the ratio of the stable frequency f and the capacitor (and is process-independent since it has a similar effect between increases or decreases in capacitance due to being fabricated by the same process). For ω p1 、ω p2 , noting from Equations 12 and 13 that if b and c are process-independent (and referring to a = 1), then ω p1 and ω p2 are process-independent. Through simple algebraic manipulation of the equations described herein, the following Equations 24 and 25 can be shown:

[0054]

[0055]

[0056] That is, b is a function of the sum of the ratio of the stable reference clock frequency f and the capacitor. N r= 4Cy / Cx and is therefore the ratio of the capacitors. c is also a function of the stable reference frequency f and the ratio of the capacitors. Since a, b, and c are independent of the process, ω p1 and ω p2 It is not dependent on the process.

[0057] Now note the gain factor K, and remember Equation 21, I p is generated by the switched capacitor current reference generator 22 ( Figure 1B ) generated. p The equation for is as follows (Equation 26):

[0058]

[0059] Where T 1 =2Tref, where Tref is the reference clock period, and f 1 = fref / 2, where fref is the reference clock frequency as described above. Note that C I Corresponding to the main capacitor for generating the charge pump current reference. That is, the charge pump current reference includes the generation of I p The switched capacitor circuit of FIG. 1 and the capacitors within this block are used to generate the above equation 26. Using algebraic manipulation of the above equation, equation 27 can be shown:

[0060]

[0061] In other words, by calibrating I p and K VCO The product of the voltages K and VCO is kept constant. Additionally, the VCO provides a control voltage from which a clock is generated. When the control voltage changes, the frequency changes. The VCO consists of a programmable switching circuit or device (e.g., a programmable transistor) that converts a voltage into a current, where the current drives a current controlled oscillator. During the calibration process, the control voltage is kept constant and the transistor is switched to a multiple of the current used to control the current controlled oscillator. By keeping the control voltage constant, the frequency can be fine-tuned to the desired value. Additionally, the gain can be measured, where adjusting the control voltage results in a gain determined by the change in frequency caused by the change in the control voltage. Once K is determined, the gain is measured. VCO , then determine the charge pump current value. Usually, the calibration goal is to determine the VCO gain (K VCO ), so that once determined, the charge pump current can be varied to keep K (eg, the open loop transfer function K) constant and thus achieve independence from the process. Thus, the measured gain K VCO , then I p Scaling (note that K in Equation 18 VCO and I pThe inverse relationship between them can therefore be kept constant). p Process drift may occur across C1. However, for K, given that Vref is process-independent, the second dividend and divisor in Equation 27 cancel out any variations, making K process-independent. Vref is derived from the bandgap voltage, which is process-independent. In practice, implementing a switched-capacitor programmable charge pump current reference generator with dynamic VCO gain selection (i.e., dynamic adjustment) allows the PLL control loop gain to remain constant.

[0062] While the above description is for the open-loop path transfer function, since the closed-loop function uses the same parameters, a similar derivation of independence with respect to the process can be shown, but is omitted here for brevity and clarity.

[0063] Having described certain embodiments of a process-independent SSCG, it should be understood that one embodiment of an exemplary discrete-time loop filtering method implemented in a SSCG (in Figure 4 68 ), the method includes receiving a signal from a charge pump ( 70 ); and filtering the signal using a discrete-time capacitance multiplier loop filter ( 72 ).

[0064] Any processing description or block in the flowchart should be understood to represent a module, segment, logic or portion of code (which includes one or more executable instructions for implementing specific logical functions or steps in the process), and alternative implementations are included within the scope of the embodiments, where, as those skilled in the art will understand, functions may be performed out of the order shown or discussed (including substantially concurrently or in a different order), depending on the functionality involved.

[0065] Although the present invention has been shown and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention from a study of the drawings, the disclosure, and the appended claims.

[0066] Note that different combinations of the disclosed embodiments may be used, and therefore reference to an embodiment or one embodiment does not exclude the use of features from that embodiment with features from other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.

Claims

1. A spread spectrum clock generator comprising a digital delta sigma modulator coupled to a fractional-N phase-locked loop (PLL), wherein: The PLL comprises a discrete-time capacitance multiplier loop filter comprising: An amplifier including a non-inverting input and an inverting input; a first switched capacitor resistor and a capacitor coupled to the non-inverting input, the capacitor coupled between the first switched capacitor resistor and the non-inverting input; and A second switched capacitor resistor is coupled to the inverting input, the input of the second switched capacitor resistor being coupled to the output of the amplifier, and the input of the first switched capacitor resistor being coupled to the output of the second switched capacitor resistor.

2. The spread spectrum clock generator according to claim 1, wherein: Each of the first switched capacitor resistor and the second switched capacitor resistor includes a capacitor and at least two switches driven by non-overlapping clocks.

3. The spread spectrum clock generator according to claim 1, wherein: The second switched capacitor resistor includes a bilinear switched capacitor resistor.

4. The spread spectrum clock generator according to claim 1, wherein: The discrete-time capacitance multiplier loop filter is process independent.

5. The spread spectrum clock generator according to claim 1, wherein: The PLL also includes a voltage controlled oscillator (VCO) configured to be calibrated, and a switched capacitor charge pump current reference generator reference, which is configured to be dynamically adjusted based on the gain of the VCO, wherein the resulting gain factor is process independent.

6. A system-on-chip (SoC) device, comprising: A spread spectrum clock generator comprising a digital delta sigma modulator coupled to a fractional-N phase locked loop (PLL), the PLL including a discrete time capacitor multiplier loop filter comprising: An amplifier including a non-inverting input and an inverting input; a first switched capacitor resistor and a capacitor coupled to the non-inverting input, the capacitor coupled between the first switched capacitor resistor and the non-inverting input; and a second switched capacitor resistor coupled to the inverting input, the input of the second switched capacitor resistor coupled to the output of the amplifier, and the input of the first switched capacitor resistor coupled to the output of the second switched capacitor resistor; and A plurality of PLLs are coupled to the spread spectrum clock generator, each of the plurality of PLLs being configured to serve different logic on the SoC device.

7. The SoC device according to claim 6, wherein: Each of the first switched capacitor resistor and the second switched capacitor resistor includes a capacitor and at least two switches driven by non-overlapping clocks.

8. The SoC device according to claim 6, wherein: The second switched capacitor resistor includes a bilinear switched capacitor resistor.

9. The SoC device according to claim 6, wherein: The discrete-time capacitance multiplier loop filter is process independent.

10. The SoC device according to claim 6, wherein: The fractional-N PLL also includes a voltage-controlled oscillator (VCO) configured to be calibrated, and a switched capacitor charge pump current reference generator reference, which is configured to be dynamically adjusted based on the gain of the VCO, wherein the resulting gain factor is process-independent.

11. The SoC device according to claim 6, wherein: At least one of the plurality of PLLs is configured to drive a plurality of processor cores on the SoC device based on an output of the spread spectrum clock generator.

12. The SoC device according to claim 6, wherein: At least one of the plurality of PLLs is configured to generate a double data rate reference clock (DDR reference clock) based on an output of the spread spectrum clock generator.

13. A discrete-time loop filtering method implemented in a spread spectrum clock generator, the method comprising: receiving a signal from a charge pump; as well as The signal is filtered using a discrete-time capacitance multiplier loop filter, the discrete-time capacitance multiplier loop filter comprising: An amplifier including a non-inverting input and an inverting input; a first switched capacitor resistor and a capacitor coupled to the non-inverting input, the capacitor coupled between the first switched capacitor resistor and the non-inverting input; and A second switched capacitor resistor is coupled to the inverting input, the input of the second switched capacitor resistor being coupled to the output of the amplifier, and the input of the first switched capacitor resistor being coupled to the output of the second switched capacitor resistor.

14. The method according to claim 13, wherein Each of the first switched capacitor resistor and the second switched capacitor resistor includes a capacitor and at least two switches driven by non-overlapping clocks.

15. The method according to claim 13, wherein The second switched capacitor resistor includes a bilinear switched capacitor resistor.

16. The method according to claim 13, wherein The discrete-time capacitance multiplier loop filter is process independent.

17. The method of claim 13, further comprising calibrating a voltage controlled oscillator (VCO) and scaling a current reference to maintain a process independent gain factor.

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