Memory Components and Their Manufacturing Methods

Abstract

A semiconductor memory structure and a method for manufacturing the same. In one aspect, an intermediate stack of dielectric layers is formed on a first stack of dielectric layers in a first step. Then, the intermediate stack of dielectric layers is partially or completely etched, and an adhesive pad layer is deposited thereon. In response to planarizing the adhesive pad layer to expose the top surface of the intermediate stack of dielectric layers, a second stack of dielectric layers is deposited over the planarized adhesive pad layer. A step is formed by etching the second stack of dielectric layers, the intermediate stack of dielectric layers, and the first stack of dielectric layers in a step region of the memory element. The step is located near one end of a central adhesive pad, wherein the steps of the step are formed within the thickness of the central adhesive pad.

Description

Technical Field

[0001] This disclosure pertains to the fields of semiconductor and memory technology, and relates to a memory element and a method for manufacturing the same. Background Technology

[0002] In recent years, the storage capacity of semiconductor memory devices has been increasing, and the structure of these memory devices has also been constantly evolving. The demand for memory devices focuses on small size and large storage capacity. To meet this demand, three-dimensional (3D) memory devices, such as 3D NAND flash memory devices, have been extensively explored to achieve increased cell density at a competitive cost. To manufacture 3D NAND flash memory devices, advanced word line patterning is currently used, and steps are created for the word line contacts in the memory device through repeated staircase etching and hard mask finishing processes. Summary of the Invention

[0003] This disclosure describes a method for manufacturing a memory element. The memory element includes a peripheral region, a stepped region, and a plurality of memory cells located in a first step of a memory array region. A method for manufacturing a memory element begins by forming an intermediate stack of dielectric layers on a first stack of dielectric layers in the aforementioned regions of the memory element. Subsequently, one or more dielectric layers of the intermediate stack of dielectric layers are etched (on which an adhesive pad layer is deposited). The adhesive pad layer is located above the etched intermediate stack of dielectric layers and in the peripheral region, stepped region, and memory array region of the memory element. In a subsequent step, the deposited adhesive pad layer is planarized to expose the top surface of the intermediate stack of dielectric layers and form a central adhesive pad. The method further includes forming a second stack of dielectric layers over the central adhesive pad and etching through the second stack of dielectric layers, the intermediate stack of dielectric layers, and the first stack of dielectric layers to form a step in the stepped region of the memory element. As described in the detailed description, the first stack of dielectric layers, the second stack of dielectric layers, and the intermediate stack of dielectric layers comprise alternating dielectric layers of different compositions.

[0004] Additionally, this disclosure describes a memory element comprising a memory array region, a central bonding pad, a stepped region, and a peripheral region. In an exemplary memory element, the memory array region includes a plurality of vertically arranged steps. Each of the plurality of steps includes a plurality of memory cells and a plurality of word lines respectively coupled to the plurality of memory cells. A central bonding pad is located between two adjacent steps of the plurality of steps. Furthermore, the stepped region of the memory element includes a step adjacent to one end of the central bonding pad and a plurality of conductive posts connected to the step. Specifically, one or more steps of the step are formed within the thickness range of the central bonding pad. The peripheral region of the memory element includes a stack of multiple dielectric layers and via contacts extending downward through the stack of multiple dielectric layers.

[0005] Furthermore, this disclosure describes a memory element comprising a peripheral region and a memory bank array region. The peripheral region comprises a stack of multiple dielectric layers. The memory bank array region comprises multiple vertically arranged steps. The memory bank array region comprises multiple memory cells and multiple word lines respectively coupled to the multiple memory cells. The memory element also includes a step region in which steps are fabricated. The steps include portions of the multiple word lines extending from the memory bank array region of the memory element. In particular, the memory element includes a central bonding pad located between the steps in the memory bank array region. In this architecture, the top and bottom surfaces of the central bonding pad are coplanar with two corresponding transition interfaces between the dielectric layers in the peripheral region of the memory element.

[0006] Another aspect of this disclosure is that the dielectric layer comprises a pair of silicon oxide layers and silicon nitride layers, a pair of silicon oxide layers and polysilicon layers, a pair of silicon nitride layers and polysilicon layers, a pair of silicon oxide layers and tungsten layers, or a group of silicon oxide layers, silicon nitride layers and polysilicon layers.

[0007] In some cases, the thickness of the central bonding pad of a memory element is equal to the sum of the thicknesses of one or more consecutive dielectric layers in the peripheral region of the memory element.

[0008] For illustrative purposes, the following description relates to steps for 3D memory devices and related manufacturing methods. This disclosure can be applied to 3D NAND memory devices having a floating gate (FG) or a charge-trapping (CT) gate. Furthermore, 3D memory devices can have various architectures, including CMOS under the memory array (CUA) and CMOS near the memory array (CNA).

[0009] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other aspects, features, and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0010] Figure 1 This is an example memory element.

[0011] Figure 2a A schematic cross-sectional side view of a portion of an exemplary semiconductor memory element.

[0012] Figure 2b for Figure 2a A schematic cross-sectional side view of the magnified memory array region of the memory elements.

[0013] Figures 3 to 17 To illustrate Figure 1 A schematic cross-sectional side view of an exemplary process for an exemplary semiconductor memory.

[0014] [Symbol Explanation]

[0015] 10, 100: Memory elements

[0016] 12: Memory controller

[0017] 13: Line decoder

[0018] 14: Memory cell array

[0019] 15: Column decoder

[0020] 16: Temporary storage

[0021] 17: Voltage source

[0022] 101: Stepped structure

[0023] 105: Array circuit

[0024] 106: Internal Connection

[0025] 110: Surrounding Area

[0026] 115: First Stage

[0027] 116, 118, 911, 912: Steps

[0028] 120: Memory Array Area

[0029] 125: Second stage

[0030] 130: Alternating layers

[0031] 131, 132, 811, 812, 820: Dielectric layers

[0032] 140: Through-hole contact

[0033] 145: Contact pad

[0034] 150: Central padding

[0035] 155: Common source line

[0036] 160: Control gate

[0037] 161: Word Line

[0038] 170: Inter-electrode dielectric

[0039] 171: Charge trapping layer

[0040] 174: Barrier Layer

[0041] 173: Tunneling Layer

[0042] 175: Channel Layer

[0043] 180: Plug

[0044] 210: First stack

[0045] 220: Dielectric rod

[0046] 230: Cell pore

[0047] 310: Intermediate layer

[0048] 410: Photoresist

[0049] 610: Next, the subbase layer

[0050] 810: Second stack

[0051] 830: Hard mask layer

[0052] 910: Stepped structure

[0053] 1010: Dielectric materials

[0054] 1110: Storage cell hole

[0055] 1210: Dielectric materials

[0056] 1310: Slot channel

[0057] 1510: Conductive slit

[0058] 2000: Stepped Area

[0059] 2001: Conductive Post

[0060] T1, T2: Thickness Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0062] In the various figures, the same reference numerals and names indicate the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale.

[0063] 3D memory devices increase memory density without reducing the size of individual memory cells through vertically stacked multilayer memory arrays. In 3D memory devices, the edges of the word lines of the memory array are processed by repeatedly etching and resist trimming the multilayer stack to form steps. These steps provide the connection points between the memory cells and the vertical interconnects in the 3D memory device and are configured to connect the memory cells to circuitry beneath the array for data reading, writing, and erasing.

[0064] To connect bitline circuitry and memory cells, vertical memory channels are formed through layer stacking. Specifically, memory cell vias are etched and filled to form the memory channels. However, with a sufficiently large number of layers, it becomes difficult to etch the memory cell vias that penetrate the layer stack. To address this issue, one or more center landing pads can be provided between different levels of the layers in a 3D memory device. Such pads act as etch stop layers between levels during the etching of the memory cell vias. Unfortunately, introducing multi-level memory array layers and center landing pads during the fabrication of 3D memory devices presents further challenges. In particular, it is difficult to precisely control step formation due to the non-uniform etching selectivity introduced by the center landing pad material and other materials in the 3D memory device.

[0065] This disclosure presents a method and structure in which steps can be fabricated across multiple levels of 3D memory elements in a single sequence of etching and trimming steps. Specifically, this disclosure defines the location and thickness of a central bonding pad by depositing one or more pairs of dielectric stacks on top of a first level of a layer of a memory array. The deposited pairs of dielectric stacks are patterned, filled, and planarized. Thus, the etched portions of the pairs of dielectric stacks are filled to define the central bonding pad. Then, a second level of the memory array layer, having memory cells similar to the first level of the memory array layer, is fabricated on the planarized central bonding pad.

[0066] In this disclosure, steps can be formed by traversing multiple layers using a single-segment process. The single-segment process includes multiple cycles of trimming and etching the open stepped regions of the multi-layer memory element. The position and thickness of the central adhesive pad can be precisely controlled so that the central adhesive pad is embedded in the dielectric stack and is not exposed in the single-segment stepped process. That is, the stepped etching process etches only the dielectric stack of the multi-layer memory element. Therefore, uniform steps can be generated at the edges of word lines to form contacts in the 3D memory element.

[0067] In addition, this disclosure provides a simplified integration process for generating multi-level memory elements formed using a single-segment ladder, which can reduce the cost of memory elements.

[0068] Figure 1 This is an exemplary memory element 10. Memory element 10 includes a memory controller 12 and a memory cell array 14. The memory controller 12 includes hardware and software logic for performing various operations, including programming the memory cell array 14, such as writing to, reading from, or erasing the memory cell array 14. In some embodiments, the memory controller 12 includes one or more processors to program the memory cells in the memory cell array 14. For example, the memory controller 12 can perform operations to program the memory cell array 14. These operations can be stored in memory accessible to the memory controller 12. In some embodiments, the operations can be stored at flash memory or a hard disk. In some embodiments, the operations can be stored at temporary memory. In some embodiments, the operations can be stored in a dedicated portion of the memory cell array 14, different from the memory cells to be programmed.

[0069] The storage cell array 14 includes one or more storage blocks. In some embodiments, each storage block may include multiple strings of storage cells. A string may include multiple storage cells. Storage cells may be single-level or multi-level storage cells. In some embodiments, the storage cell array 14 includes non-volatile storage cells, such as flash memory cells. However, the storage cell array 14 may include any type of 3D storage cells, including but not limited to 3D NAND flash memory cells comprising U-shaped strings and 3D NAND flash memory cells comprising non-U-shaped strings. In some embodiments, each storage block may include a single string.

[0070] Memory element 10 includes a row decoder 13 and a column decoder 15. In some embodiments, the row decoder is coupled to a plurality of word lines arranged in a first direction in the memory cell array 14, and the column decoder 15 is coupled to a plurality of bit lines arranged in a second direction in the memory cell array 14. In some other embodiments, the row decoder is coupled to a plurality of bit lines arranged in the first direction in the memory cell array 14, and the column decoder 15 is coupled to a plurality of word lines arranged in the second direction in the memory cell array 14.

[0071] The memory controller 12 can use the row decoder 13 or the column decoder 15 to control read or program operations on one or more memory cells in the memory cell array 14. In some embodiments, the memory controller 12 provides addresses to the row decoder 13 and the column decoder 15 to perform read or program operations on one or more specific memory cells in the memory cell array 14. In some other embodiments, addresses can be provided to the row decoder 13 and the column decoder 15 from external devices or external circuitry to perform read or program operations on one or more specific memory cells in the memory cell array 14.

[0072] In some embodiments, memory element 10 includes a voltage source 17. Memory controller 12 controls voltage source 17 to provide power to memory cell array 14. Memory controller 12 can use the power provided by voltage source 17 to perform read and program operations.

[0073] In some embodiments, memory element 10 may further include temporary memory 16 to store information for programming memory cells in memory cell array 14. This information may include different voltage levels and timing data to define the timing at which different voltage levels are applied to the memory cell array. Various formats can be used for the timing data of applying different voltage levels to the memory cell array, such as the start and end times of a specific voltage level or the start and duration of a specific voltage. Temporary memory 16 can be any suitable type of memory. For example, temporary memory 16 may be static random access memory (SRAM), NAND flash memory, or a set of temporary registers. In some embodiments, temporary memory 16 may be implemented as part of memory cell array 14 and may be different from the memory cells to be programmed.

[0074] Please refer to the attached diagram for more details. Figure 2a A schematic cross-sectional side view of an example of a memory element 100. The memory element 100 may provide... Figure 1 The memory cell array 14. In this example, memory element 100 includes a peripheral region 110, a stepped region 2000, and a memory array region 120. In this example, memory element 100 includes sub-array circuitry, such as under-array circuitry 105, disposed on a substrate in the peripheral region 110, stepped region 2000, and memory array region 120. Memory element 100 also includes interconnects 106, which include bit lines located above the substrate in the peripheral region 110, stepped region 2000, and memory array region 120. In this example, a plurality of contact pads 145 are located on the top surface of under-array circuitry 105. Interconnects 106 can be connected to the contact pads 145 of under-array circuitry 105 via via contacts 140, wherein via contacts 140 extend through alternating stacks 130 in the stacked film portion of peripheral region 110. In another example, the sub-array circuitry is not below the memory array but is located near the memory array.

[0075] like Figure 2a As shown, the memory array region 120 includes a plurality of word lines 161, which are arranged parallel to and spaced apart along the memory stack direction. The word lines 161 contact memory cells that serve as control gates 160 in the memory array region 120. In the memory element 100, the word line direction and the bit line direction are orthogonal.

[0076] In the example described, memory array region 120 includes vertical channel memory cells for better electrostatic control and greater on-current provided by a larger effective gate width. As described later in this disclosure, memory cells are fabricated by depositing a stack of alternating dielectric films and then forming pores through the film stack. The stack of alternating dielectric films may include multiple pairs of films, for example, each pair may include a dielectric layer and a sacrificial layer for displacing the gate. Pores may be formed by high aspect ratio etching to make room for the formation of inter-electrode dielectric 170 and channel layer 175 therein.

[0077] Figure 2a A two-tier memory array is shown, comprising a central bonding pad 150 disposed between a first tier 115 and a second tier 125 of the memory layers. The central bonding pad 150 serves as an etch stop layer for forming memory cell vias in the second tier 125. The central bonding pad 150 can be formed of various materials, such as polysilicon, tungsten, silicon nitride, silicon oxide, silicon oxynitride, high-k dielectric materials, silicides (e.g., CoSi, TiSi, or NiSi), and others. In some embodiments, the memory array region 120 may include horizontal channel memory cells, providing a smaller effective memory cell area.

[0078] Memory element 100 includes word lines 161, which are presented as a plurality of gate layers for memory cells in memory array region 120. Word lines 161 are separated by an interlayer dielectric material (e.g., silicon oxide) and electrically connect each memory cell in memory array region 120 to under-array circuitry 105 and interconnects 106.

[0079] For 3D NAND memory operations, memory cells are accessed via word lines 161 and bit lines. Adjacent to memory array region 120, memory element 100 includes a peripheral region 110, which includes electrical connections for reading from and writing to memory cells in memory element 100. For example... Figure 2a As shown, a stepped structure 101 is formed at one end of the word line 161. Conductive posts 2001 extend from the interconnect 106 to the end of the word line 161. The interconnect 106 is located at the top of the memory element 100. In this example, a plurality of interconnects 106 connect to contact openings (e.g., via contacts 140) that extend through and are electrically insulated within alternating stacks 130, and are configured to provide interconnection between the memory cells of the memory element 100 and the under-array circuitry 105. Figure 2aAs shown, the via contact 140 extends through multiple dielectric layers in the peripheral region 110 and connects the interconnect 106 to the contact pad 145. The via contact 140 may be formed of metal, metal silicide, or other materials. The interconnect 106 may be formed of a conductive material, such as metal.

[0080] like Figure 2b As shown in the enlarged view of the memory array region, the gate electrode of each memory cell includes an inter-electrode dielectric 170, which is fabricated by inserting a charge trapping layer 171 between two electrode layers (control gate 160 and channel layer 175). In this example, a barrier layer 174, such as a high-k material layer, is inserted between the control gate 160 and the charge trapping layer 171 to prevent electrons from being injected from the control gate 160 into the charge trapping layer 171 during erase operations. The charge retention and durability characteristics of the memory cell can be maintained in good condition. Simultaneously, a tunneling layer 173, such as an oxide layer, is inserted between the charge trapping layer 171 and the channel layer 175 to act as a tunneling barrier for charge carriers.

[0081] In the example, such as Figure 2a As shown, the stepped structure 101 of the memory element 100 includes one or more steps located near one end of the central bonding pad 150. Figure 1 As shown, two steps 116 and 118 are formed within the thickness of the central adhesive pad 150, specifically between the top and bottom surfaces of the central adhesive pad 150. The thickness of the central adhesive pad 150 is equal to the sum of the thicknesses of one or more consecutive dielectric layers in the peripheral region 110. For example, the thickness of the central adhesive pad 150 is equal to the sum of the thicknesses of an integer number of consecutive pairs of alternating dielectric layers 131 and 132 plus the thickness of an additional dielectric layer 132. For instance, the thickness of the central adhesive pad 150 is equal to the sum of the thicknesses of three consecutive dielectric layers in the intermediate stack 310 of the dielectric layers. Steps 116 and 118 are isolated by dielectric layer 131 (e.g., a silicon oxide layer). These two steps are not electrically connected to the vertically aligned via contacts 140 because they do not contact any conductive posts 2001 to interconnects 106 in the stepped region 2000.

[0082] The memory element 100 includes under-array circuitry 105 at its bottom. The under-array circuitry 105 performs functions including memory cell row and column decoding, bit line precharge logic reads, sense amplifiers, and timing control. The under-array circuitry 105 can be fabricated on a substrate (not shown here) using a front-end (FEOL) CMOS process. Figure 2a As shown, the through-hole contact 140 connects the array lower circuit 105 to the internal interconnect 106.

[0083] The memory element 100 also includes a common source line 155 located below and connected to the plurality of memory cells. The common source line 155 can be connected to the plurality of memory cells to couple their control gates 160 to a plurality of word lines 161, thereby reducing the size of the memory element 100. The common source line 155 can be provided of one or more conductive materials, such as polysilicon, tungsten, aluminum, copper, and other materials.

[0084] The fabrication of memory element 100 involves significant challenges, such as controlling the multi-step patterning process for etching steps and etching memory cell holes on the small steps with extremely high aspect ratios. Figures 3 to 17 yes Figure 2a and Figure 2b The exemplary memory element 100 shown is a cross-sectional side view to illustrate the manufacturing process for producing the memory element.

[0085] Figure 3 This is a schematic diagram showing a cross-sectional side view of a portion of an exemplary memory element 100 according to the present disclosure. The memory element 100 includes a memory array region 120, a stepped region 2000, and a peripheral region 110. Cross-sectional views of the array cut along the word line direction and the array cut along the bit line direction are shown in the memory array region 120. The memory element 100 includes a plurality of common source lines 155 located above a lower array circuitry 105. The common source lines 155 extend laterally in parallel and are spaced apart by a dielectric layer 131 (e.g., silicon oxide) for electrical isolation.

[0086] A first stack 210 of dielectric layers is deposited on the array lower circuitry 105. The first stack 210 of dielectric layers includes pairs of alternating dielectric layers 131 and 132 with different compositions, such as alternating oxide and nitride layers, or alternating silicon oxide and silicon nitride films. The pairs of dielectric layers 131, 132 (e.g., silicon oxide and silicon nitride films) can be repeatedly deposited, for example, 96 times, to create 96 pairs of layers in the first dielectric layer stack. One layer in a pair (e.g., the lower dielectric layer 131 (e.g., silicon oxide film)) provides mechanical support and dielectric isolation for the composition of memory elements. The other layer in the pair (e.g., the upper dielectric layer 132 (e.g., silicon nitride film)) serves as a sacrificial layer, which is subsequently removed to form a displacement gate.

[0087] In this example, the thickness of the alternating dielectric film determines the gate length of the memory cell in memory element 100 and can range from 5 nm to 50 nm. Any defects or small variations in the film thickness can lead to significant deviations in the memory array, resulting in poor device performance. Therefore, highly uniform and smooth deposition, interlayer precision, and adhesion may be required. Furthermore, as the number of stacked layers increases, stress management of the alternative dielectric film becomes critical and more challenging. In some embodiments, the first stack 210 of the dielectric layer may include a silicon oxide layer and a polysilicon layer, a silicon nitride layer and a polysilicon layer, a silicon oxide layer and a tungsten layer, and a silicon oxide layer, a silicon nitride layer and a polysilicon layer, as well as other layers.

[0088] In the memory array region 120 of memory element 100, vertical vias 230 are etched through a first stack 210 of dielectric layers to create space for memory cell formation and vertical electrical connections between memory layers. Vertical vias can be formed by high aspect ratio directional etching (e.g., RIE etching). Once the vias are etched, an inter-electrode dielectric 170 (e.g., a silicon oxide-silicon nitride-silicon oxide multilayer) is conformally deposited on the sidewalls and bottom surface of the vias. With this configuration, conductive vertical channel layers 175 (e.g., formed of polysilicon) are deposited along the inner surface of the inter-electrode dielectric 170. Gaps remaining between the vertical channel layers 175 can be filled with dielectric bars 220, for example, silicon oxide. Plugs 180 (e.g., polysilicon) are formed on the upper surface of each via. The plugs 180 are conductive and cover the top of the polysilicon channel layers 175 to provide electrical connections between lower first-order and higher second-order memory cells. Additionally, during the fabrication of the second-stage memory cell, the plug 180 serves as an etch stop layer to protect the first stage of the memory cell from vertical aperture etching.

[0089] Figure 4 This is a schematic cross-sectional side view of a portion of an exemplary memory element 100 after an intermediate stack 310 of dielectric layers is formed on a first stack 210 of dielectric layers in a peripheral region 110, a step region 2000, and a memory array region 120. In this example, an intermediate stack 310 of dielectric layers can be deposited, and the memory array region 120 includes a plurality of memory cells in a first step 115. The intermediate stack 310 of dielectric layers includes one or more pairs of dielectric layers 131 and 132. Each pair of dielectric layers in the intermediate stack 310 of dielectric layers includes alternating layers, such as an upper dielectric layer 132 and a lower dielectric layer 131, which constitute different layers. The intermediate stack 310 of dielectric layers may include two pairs of silicon oxide layers and silicon nitride layers, which are deposited alternately on the dielectric layers. Figure 3The intermediate stack 310 of the dielectric layer is deposited on top of the structures in the memory array region 120, the stepped region 2000, and the peripheral region 110. In other embodiments, various pairs of stacks having an alternating structure similar to the alternating structure of the intermediate stack 310 of the dielectric layer can be deposited, including a pair of silicon nitride and silicon oxide layers and a silicon oxide layer on top; two pairs of silicon nitride and silicon oxide stacks; two pairs of silicon nitride and silicon oxide stacks and a silicon nitride layer on top; and two pairs of silicon nitride and silicon oxide stacks and a polysilicon layer between the two pairs of stacks. The total thickness of the intermediate stack 310 of the dielectric layer will vary depending on the number of dielectric layer pairs and the thickness of each layer. The intermediate stack 310 of the dielectric layer will define the thickness of the subsequently fabricated adhesive pad.

[0090] The intermediate stack 310 of the dielectric layer can be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques to achieve a film stack including alternating layers of different compositions similar to the first stack 210 of the dielectric layer and a second stack 810 of the dielectric layer formed subsequently.

[0091] Figure 5 A schematic diagram illustrating a cross-sectional side view of a portion of an exemplary memory element 100 after photolithography. Photoresist 410 is deposited and patterned on the top surface of an intermediate stack 310 of the dielectric layer of the memory element 100. After exposure to UV light, the photoresist 410 is baked and developed, and used as a mask during etching to transfer the pattern from the photolithographic mask to the intermediate stack 310 of the dielectric layer. Specifically, a portion of the photoresist 410 is removed to expose the intermediate stack 310 of the dielectric layer in the memory array region 120 and the stepped region 2000, defining a space for a central bonding pad. A portion of the photoresist 410 may remain above the stepped region 2000 and certain areas of the memory array region 120 to allow for the formation of subsequent slits.

[0092] Figure 6 A schematic diagram illustrating a cross-sectional side view of a portion of an exemplary memory element 100 after etching is shown. In this step, patterned photoresist 410 is used as a mask to etch the intermediate stack 310 of the dielectric layer. Figure 6 As shown, one or more dielectric layers of the intermediate stack 310 of dielectric layers not covered by photoresist 410 are etched away, and the pattern of the photomask is transferred to the intermediate stack 310 of dielectric layers. After etching, the photoresist 410 is stripped off.

[0093] Specifically, the exposed portions of the intermediate stack 310 of the dielectric layer can be etched, for example, using anisotropic etching (e.g., reactive ion etching (RIE)). In this example, a pair of dielectric layers 131 and 132 and a second dielectric layer (e.g., a silicon nitride layer) are etched. Additionally, the etching depth on the intermediate stack 310 of the dielectric layer can be controlled by selectively etching the dielectric stack pair to stop at specific layers of the dielectric layer. Etching stop can be achieved through time-based etching or endpoint detection control during etching. After the etching step, portions of the intermediate stack 310 of the dielectric layer may remain above the step region 2000. Portions of the intermediate stack 310 of the dielectric layer (shown in an array along the bit line direction) may remain on some regions of the memory array region 120 to enable the formation of subsequent slots.

[0094] Figure 7 A cross-sectional side view of a portion of an exemplary memory element 100 after the deposition of the bonding pad 610 is illustrated. In this step, the bonding pad 610 (e.g., a polysilicon layer) is deposited over an etched dielectric intermediate stack 310 and within peripheral regions 110, step regions 2000, and memory array regions 120. The deposited bonding pad 610 has a thickness greater than that of the dielectric intermediate stack 310, thereby conformally covering the edge depth of the etched dielectric intermediate stack 310. The material of the bonding pad 610 may include, for example, polysilicon, tungsten, silicon nitride, silicon oxide, silicon oxynitride, high-k dielectric materials, and silicides (e.g., CoSi, TiSi, or NiSi), as well as other materials.

[0095] Following the deposition of the adhesive pad 610 is a planarization step to planarize the deposited adhesive pad 610 until the top surface of the underlying dielectric intermediate stack 310 is exposed. This planarization can be performed using a polishing process (e.g., chemical mechanical polishing). Figure 8 As shown, a portion of the adhesive pad 610 retained in the channel of the intermediate stack 310 of the dielectric layer provides a central adhesive pad 150.

[0096] After forming the central adhesive pad 150, a second layer 125 of the memory array is fabricated over the substrate, and the second layer 125 is perpendicularly aligned with the first layer 115. In some examples, the central adhesive pad 150 is located between two adjacent layers of multiple layers, such as between the first layer 115 and the second layer 125. Figure 9A cross-sectional side view of a portion of an exemplary memory element 100 is illustrated after the formation of a second stack 810 of dielectric layers. In this example, a second stack 810 is deposited comprising alternating dielectric layers 811 and 812 of different compositions (e.g., alternating layers of nitride and oxide materials). Specifically, the alternating dielectric layers 811 and 812 include an upper dielectric layer 812 with the same composition as the upper dielectric layer 132 in the first stack 115 and a lower dielectric layer 811 with the same composition as the dielectric layer 131 in the first stack 115. For example, the alternating dielectric layers 811 and 812 may be a silicon oxide layer and a silicon nitride layer, respectively, similar to the first stack 210 of dielectric layers.

[0097] The deposition conditions and thicknesses of the alternating dielectric layers in the first stack 210 and the second stack 810 may be identical. In some other embodiments, the second stack 810 of the dielectric layers may include different pairs of dielectric layers compared to the first stack 210.

[0098] Above the second stack 810 of dielectric layers, a dielectric layer 820, such as a silicon oxide layer, and a hard mask layer 830, such as a polysilicon layer, are deposited. The dielectric layer 820 covers the top dielectric layer 812 (e.g., a top silicon nitride layer), which is then converted into a conductive gate layer on top of the memory array region 120. In the following steps, the hard mask layer 830 will serve as a hard mask layer for step formation. In this example, the peripheral region 110 includes a first stack 210 of dielectric layers, an intermediate stack 310 of dielectric layers, and a second stack 810 of dielectric layers.

[0099] In some examples, the alternating dielectric layers in the first stack, intermediate stack, and second stack of dielectric layers include one of a pair of silicon oxide and silicon nitride layers, a pair of silicon oxide and polysilicon layers, a pair of silicon nitride and polysilicon layers, a pair of silicon oxide and tungsten layers, or a set of silicon oxide, silicon nitride, and polysilicon layers.

[0100] Figure 10 A cross-sectional side view of a portion of an exemplary memory element 100 after the formation of the steps is illustrated. In this example, in the step region 2000, the steps are etched through the second stack 810, intermediate stack 310, and first stack 210 of the dielectric layers. The formation of this step exposes the ends of each upper dielectric layer 132 and 812 for subsequent formation of vertical contacts. The steps are fabricated by etching multiple cycles of alternating dielectric layers using patterned photoresist and two-dimensional (2D) trimming of the patterned photoresist. This step requires precise etching step profiles, trimming etching uniformity, and pullback threshold size control of the word line contacts.

[0101] like Figure 10As shown, the hard mask layer 830 is first patterned to create openings for etching the stepped region 2000. The steps in the stepped region are created by repeatedly etching on the dielectric stack and trimming the patterned photoresist, ultimately approaching the common source line 155. In this example, directional etching can be performed along the trimmed photoresist and through the second, intermediate, and first stacks of dielectric layers in the stepped region 2000. Etching steps can be performed on a pair of stacked dielectric layers (e.g., a pair of silicon nitride and silicon oxide layers) using anisotropic directional etching techniques (e.g., RIE). The etching does not react with other exposed materials in the stepped region 2000, thus forming a uniform stepped structure. Trimming steps can be performed using 2D trimming techniques (e.g., dry etching) to trim the patterned photoresist in the horizontal direction. Trimming steps can also be performed by trimming the patterned photoresist above the stepped region 2000 using minimal incremental layer cost. In some other embodiments, step etching is performed by photoresist 2D trimming and vertical etching of multiple pairs of stacked dielectric layers.

[0102] During the formation of the staircase, the central adhesive pad 150 is horizontally embedded within one or more pairs of dielectric layers in the intermediate stack 310 of the dielectric layers. Therefore, the central adhesive pad 150 is not exposed to trimming and etching processes. In this respect, only the alternating dielectric stacks are exposed to the cyclic trimming / etching steps, and thus, the steps of the staircase formed for the paired dielectric stacks can be very uniform. Furthermore, during staircase formation, the stacked regions in the peripheral region 110 and the memory array region 120 remain covered by the hard mask layer 830 and are therefore unaffected by its trimming and etching processes. In this example, the staircase can be formed as a continuous staircase structure 910, i.e., the staircase has an uninterrupted series of steps. In the staircase region 2000, the steps of the staircase can be uniformly spaced laterally. Similarly, in the staircase region 2000, the steps of the staircase can be uniformly spaced vertically.

[0103] In this example, the staircase consists of two steps located near one end of the central pad 150. Specifically, as... Figure 10As shown, two steps 911 and 912 are located near one end of the central bonding pad 150. Each step includes a pair of dielectric layers 131 and 132, and one of the dielectric layers will be selectively removed and filled with a conductive gate material, such as sacrificial dielectric layer 132, during subsequent processing. In this example, steps 911 and 912 are formed within the thickness of the central bonding pad 150. As previously mentioned, the thickness of the central bonding pad 150 is related to the thickness of the intermediate stack 310 of the dielectric layers and the etched steps thereon. In some embodiments, there may be more than two steps located near one end of the central bonding pad 150. In some other embodiments, multiple central bonding pads may exist between multiple steps in the memory array region 120.

[0104] In this example, the top and bottom surfaces of the central adhesive pad 150 are coplanar with the two corresponding transition interfaces between the dielectric layer in the peripheral region 110. For example, as Figure 10 As shown, the top and bottom surfaces of the central pad 150 are coplanar with the transition interfaces between the intermediate stack 310 and the second stack 810 of the dielectric layer, and the transition interfaces between the first stack 210 and the intermediate stack 310 of the dielectric layer are coplanar.

[0105] Figure 11 A cross-sectional side view of a portion of an exemplary memory element 100 after interlayer dielectric filling in the stepped region 2000 is illustrated. In this step, a dielectric material 1010 (e.g., silicon oxide) is deposited on the memory element 100 to fill the open space above the etched steps. The dielectric material 1010 can be deposited using a chemical vapor deposition (CVD) technique and can subsequently be planarized to form a planarized silicon oxide surface on the memory element 100. Other materials can be used instead of silicon oxide, such as flowable oxides, spin-coated dielectrics, or other porous films. The planarization process can be performed using a CMP process to grind away the overfilled silicon oxide above the polysilicon hard mask layer 830 and stop the planarization on the polysilicon hard mask layer 830. After planarization, the polysilicon hard mask layer 830 is removed, for example, by a wet etching process.

[0106] Figures 12 to 17 yes Figure 1 A cross-sectional side view of an exemplary memory element 100 is shown to illustrate the process used to fabricate a second-order memory array and a conductive gate layer.

[0107] like Figure 12As shown, the memory cell via 1110 is etched downwards through the second stack 810 of the dielectric layer using a high aspect ratio etching technique. Generally, via etching involves the high aspect ratio structure of the vias and the different materials involved in the word line stack. The aspect ratio of vias in multi-level 3D NAND memory may be greater than 40:1, while the aspect ratio of planar NAND memory elements is 10:1. In this example, vertical via etching is performed on a single level (e.g., the second level 125) of a memory cell via with a limited memory layer and a low aspect ratio.

[0108] The memory cell vias 1110 are etched through the second stack 810 of the dielectric layer in the second layer 125 and the central bonding pad 150, stopping at the plug 180 in the first layer 115. In this example, the plurality of memory cell vias 1110 are substantially aligned with the memory cell vias in the first layer 115 of the memory array region 120. The etching of the vertical memory cell vias 1110 includes multiple steps, such as a first etching step and a second etching step. In this example, the first etching step etches through the second stack 810 of the dielectric layer and stops at the central bonding pad 150. The second etching step etches through the central bonding pad 150 and stops at the plug 180 in the first layer 115. The first and second etching steps may involve different etching chemicals with different etching selectivity between the dielectric stack material and the plug material. In this example, the etching of the memory cell vias can be performed using advanced plasma etching techniques, such as RIE etching. The stacked multi-level memory array structure is fabricated by sequentially etching the cells of each memory level, which has a finite number of memory cell layers and a low etching aspect ratio, and then stacking the memory levels and inserting a central bonding pad between them as a cell etching stop layer.

[0109] Figure 13 A cross-sectional side view of a portion of an exemplary memory element 100 after memory cell processing in a second memory stage is illustrated. In this example, multiple memory cells are fabricated in a second stage 125 of a memory array region 120. In this step, a second stack 810 through the dielectric layer is first etched into a vertical cylindrical memory aperture, and then an inter-electrode dielectric 170 and a conductive channel layer 175 are formed. The inter-electrode dielectric 170 may comprise a multilayer film (e.g., a silicon oxide-silicon nitride-silicon oxide (ONO) multilayer) and is deposited on the inner sidewalls and bottom surface of the memory cell aperture 1110. In this example, the first silicon oxide layer and the second silicon oxide layer in the inter-electrode dielectric 170 act as a tunneling oxide and a blocking oxide, respectively, while the silicon nitride layer in the inter-electrode dielectric 170 acts as a charge trapping (CT) material. A portion of the inter-electrode dielectric 170 is deposited on the bottom surface of the aperture and then removed, for example, by directional repair etching (e.g., RIE). A conductive vertical channel layer 175, for example, formed of polysilicon, is deposited along the inner surface of the inter-electrode dielectric 170. like Figure 13As shown, each memory cell aperture includes a dielectric rod 220, such as a silicon oxide rod, which serves as a core filler inside a polysilicon channel layer 175 and is covered by a plug 180 formed above it. Once the memory cells of the second stage 125 have been processed, a dielectric material 1210 (e.g., silicon oxide) is deposited on top of the memory element 100, followed by a CMP process to planarize the surface of the memory element 100.

[0110] Figure 14 A cross-sectional side view of a portion of an exemplary memory element 100 after etching the slot channels 1310 is illustrated. To minimize interference, the blocks of memory cell apertures are separated from each other by creating a plurality of slot channels 1310. The etching forming the plurality of slot channels 1310 extends through the second and first stages in the memory array region 120 and terminates at the common source line 155. Figure 14 As shown, the slot channels 1310 are spaced apart along the bit line direction. As previously described, the slots 1310 penetrate the remainder of the intermediate stack 310 of the dielectric layer (shown in an array along the bit line direction) over certain regions of the memory array region 120. Each slot channel extends along the word line direction and passes through multiple memory cells of multiple steps. The slots 1310 provide openings for forming the replacement gate layer and slots for electrical interconnects. Considering that the slot channels provide more space in the word line direction for the inflow of etching chemicals and the outflow of residual material, the etching of the slots can be performed using anisotropic etching techniques (e.g., RIE) and is less challenging compared to vertical via etching.

[0111] Figure 15 A cross-sectional side view of a portion of an exemplary memory element 100 after the replacement gate has been formed is illustrated. In this example, a conductive gate layer is formed by selectively removing one type of dielectric layer from the first stack, intermediate stack, and second stack of dielectric layers in the memory array region 120 and the step region 2000. Specifically, as Figure 15 As shown, dielectric layers 132 and 812 (e.g., silicon nitride layers in a dielectric layer stack) are removed, and the space is then refilled with multiple gate layers. Once the slit channel 1310 is opened, dielectric layers 132 and 812 (e.g., silicon nitride layers) on the sidewalls of the slit channel 1310 are exposed and then subjected to an etching process (e.g., dry etching) that is highly selective for dielectric layers 131 and 811, such as silicon oxide, and for pad layer 610, such as polysilicon. As a result, a very small portion of the central pad 150 and the common source line 155 is removed during the etching process. In this step, the etching process removes one type of dielectric layer from the first stack, intermediate stack, and second stack of dielectric layers in the memory array region 120 and the step region 2000 to form an opening, and continues until the sacrificial material in the step region 2000 and the memory array region 120 is completely removed.

[0112] Then, multiple gate layers are filled through exposed openings in the sidewalls of the slot channel using a deposition technique with good filling capability in small features (e.g., low-fluorine tungsten ALD process) to deliver conductive gate material to the multiple gate layers. In this example, multiple gapless gate layers fill the lateral space of the dielectric stack and exert minimal stress on the memory array region 120. Furthermore, the gate layer material must differ from the alternating dielectric stack materials and can be selected from metals, doped polysilicon, and other materials.

[0113] In this disclosure, the laterally filled gate layer serves as word line 161 and is configured to select and activate memory cells in memory array region 120. Figure 15 As shown, in the stepped region 2000, the gate layer replaces the sacrificial layer. Specifically, there are two steps in the gate step formed near one end of the central bonding pad 150. Depending on the thickness of the dielectric stack and the thickness of the central bonding pad 150, there may be more than two gate steps formed near the end of the central bonding pad 150. In this example, the stepped structure 101 includes a portion of the plurality of word lines 161 extending from the memory array region 120. Furthermore, in contrast, in the peripheral region 110, the alternating dielectric stack bodies maintain an alternating dielectric stack structure and are unaffected by the formation of the gate layer.

[0114] It has been determined that, in some embodiments, it is advantageous to construct the memory elements described herein (particularly, the steps of memory elements) such that certain features have dimensions falling within a specific range. For example, when a replacement gate layer is formed with steps, the thickness T1 of the central bonding pad 150 should be equal to the total thickness T2 of the dielectric stack. For example, the dielectric stack includes a silicon oxide layer and a silicon nitride layer, and the thickness T1 of the central bonding pad is equal to the total thickness of the two pairs of dielectric stacks.

[0115] In some other embodiments, the thickness T1 of the central bonding pad 150 may be equal to the total thickness T2 of the dielectric stack and other layers. For example, the dielectric stack includes a silicon nitride layer and a silicon oxide layer, and the central bonding pad thickness T1 is equal to the total thickness of a pair of stacks and one or more silicon nitride layers. In another example, the dielectric stack includes a silicon nitride layer and a silicon oxide layer, and the central bonding pad thickness T1 is equal to the total thickness of two pairs of stacks and one or more silicon nitride layers. In yet another example, the dielectric stack includes a silicon nitride layer and a silicon oxide layer, and the central bonding pad thickness T1 is equal to the total thickness of two pairs of stacks and one or more polysilicon layers.

[0116] Figure 16 and Figure 17A side cross-sectional view of an exemplary memory element 100 after slot deposition and interconnect formation is shown. The conductive slots 1510 are formed by depositing conductive material onto the plurality of slot channels 1310 and then planarizing the top surface of the memory array region 120. Subsequently, the plurality of via contacts 140 are formed in the peripheral region 110 and penetrate downwards through the plurality of dielectric layer stacks in the peripheral region 110, such as... Figure 17 As shown. Multiple patterning steps can be used to create vias in different regions of the memory element, and the vias are filled with a conductive material to form via contacts 140. In the stepped region 2000, the plurality of conductive posts 2001 are connected to the stepped structure 101 via interconnects 106 extending to one end of the plurality of word lines 161, wherein the stepped structure serves as one end of the word lines 161. On top of the second step 125, the plurality of interconnects 106, including bit lines, are fabricated using a BEOL process. The interconnects 106 include contact plugs (not shown) at the same or different levels, metal wires (not shown), and bit lines (not shown). The interconnects 106 can connect different components in the peripheral region 110, the stepped region 2000, and the memory array region 120. In this example, the plurality of interconnects 106 are connected to the plurality of memory cells in the memory array region 120 via the plurality of conductive posts 2001 and the plurality of word lines 161 in the stepped region 2000. The bit line is orthogonal to the word line 161. In this example, each memory cell string is electrically connected to a bit line, and the bottom of the memory cell string is connected to a common source line 155 formed below the first step 115 of the memory array. In one embodiment, at least one conductive post (not shown) in the step region 2000 extends downward and contacts a central bonding pad 150 comprising a conductive material. The conductive material includes polysilicon, tungsten, silicide, or other suitable materials. The conductive central bonding pad 150 surrounds a portion of the memory cell aperture 1110 (e.g., Figure 12 (As shown), and overlaps with a portion of the inter-electrode dielectric 170 and channel layer 175 in each cell. The conductive central adhesive pad 150 acts as a control gate for a portion of the channel layer 175 in each cell. When current is transmitted through the at least one conductive post to the conductive central adhesive pad 150 and turns on the control gate of each cell, the ability of current to flow through the channel layer 175 in each cell is enhanced.

[0117] While numerous details may be described herein, these details should not be construed as limiting the scope of the claimed invention or the scope that may be claimed, but rather as descriptions of specific features of particular embodiments. Certain features described herein in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Moreover, although features may be described above as operating in certain combinations and even initially claimed to be so, in some cases, one or more features from the claimed combination may be removed from said combination, and the claimed combination may be for sub-combinations or variations thereof. Similarly, although operations are depicted in a specific order in the drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in a sequential order, or to perform all the operations shown to obtain the desired result.

[0118] Only some examples and implementations are disclosed. Variations, modifications, and enhancements can be made to the described examples and implementations, as well as other implementations, based on what is disclosed.

[0119] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a memory element, characterized in that, include: An intermediate stack of dielectric layers is formed on multiple memory cells in the first stack of dielectric layers in the peripheral region, the step region, and the first step of the memory array region; Etch one or more dielectric layers in the intermediate stack of the dielectric layers in the stepped region and the memory array region; An adhesion pad is deposited on the intermediate stack of the etched dielectric layer in the peripheral region, the stepped region, and the memory array region; The adhesive pad layer is planarized to expose the top surface of the intermediate stack of the dielectric layer, thereby forming a central adhesive pad through the planarized adhesive pad layer; The second stack forming the dielectric layer; and Etching is performed through the second stack of the dielectric layer, the intermediate stack of the dielectric layer, and the first stack of the dielectric layer to form steps in the stepped region. The dielectric layers of the second stack of dielectric layers, the intermediate stack of dielectric layers, and the first stack of dielectric layers comprise alternating layers with different compositions.

2. The method for manufacturing a memory element as claimed in claim 1, further comprising: The depressions on the steps are filled with dielectric material; Multiple memory cell vias are etched downward through the second stack of the dielectric layer and the central bonding pad in the second stage of the memory array region, and the multiple memory cell vias are substantially aligned with the memory cell vias in the first stage of the memory array region; Multiple memory cells are manufactured in the second stage of the memory array region; Multiple slit channels extending through the second and first order of the memory array region are etched out; By etching the plurality of slit channels, a type of dielectric layer is removed from the first stack of dielectric layers, the intermediate stack of dielectric layers, and the second stack of dielectric layers in the memory array region and the step region; Multiple gate layers are formed in the space left by the removal of the dielectric layer of the aforementioned type; as well as Conductive material is deposited onto the plurality of slot channels to form conductive slots in the memory array region.

3. The method of manufacturing a memory element as claimed in claim 2, wherein forming the plurality of gate layers comprises: Through the sidewalls of the slit channel, selectively etch the first stack of dielectric layers, the intermediate stack of dielectric layers, and the second stack of dielectric layers in the memory array region and the step region; as well as Gate material is filled into the space created by the etched dielectric layer of the aforementioned type to form the plurality of gate layers, wherein the plurality of gate layers serve as word lines.

4. The method of manufacturing a memory element as claimed in claim 2, wherein manufacturing the plurality of memory cells comprises: Etching through the second stack of the dielectric layer and the central bonding pad located below the second stack of the dielectric layer forms the downward-facing memory cell via; An inter-electrode dielectric is formed on the inner sidewall of the storage cell hole; A conductive channel is deposited within the dielectric material between the electrodes; as well as A dielectric rod is deposited at the center of each of the storage cell holes.

5. The method of manufacturing a memory element as claimed in claim 1, wherein during the formation of the step, the central adhesive pad remains horizontally embedded in the intermediate stack of the dielectric layer, and The etching through the second stack of the dielectric layer, the intermediate stack of the dielectric layer, and the first stack of the dielectric layer to form the step includes repeatedly performing the following steps: On the patterned photoresist located above the stepped region, at least one of two maintenance adjustments or minimum incremental layer cost adjustments is performed; and The photoresist is oriented and etched through the second stack of the dielectric layer, the intermediate stack of the dielectric layer, and the first stack of the dielectric layer in the stepped region.

6. A memory element, characterized in that, include: The memory array region comprises multiple vertically arranged columns, each of which includes: Multiple storage units; and Multiple word lines are respectively coupled to the plurality of memory cells; The central bonding pad is located between two adjacent steps of the plurality of steps; The stepped area includes: A step, wherein the step is located near one end of the central adhesive pad, and wherein the steps of the step are formed within the thickness of the central adhesive pad; and Multiple conductive pillars are connected to the ladder; and The surrounding area includes multiple stacks of dielectric layers and via contacts that pass downward through the multiple stacks of dielectric layers.

7. The memory element of claim 6, further comprising circuitry located below or adjacent to the memory array region, wherein the circuitry is configured to control the operation of the memory element.

8. The memory element of claim 6, further comprising a plurality of interconnects located on top of the memory element, wherein the plurality of interconnects are respectively connected to the plurality of memory cells in the memory array region via the plurality of conductive posts and the plurality of word lines in the stepped region.

9. The memory element of claim 6, wherein at least one of the conductive pillars extends downward and contacts the central bonding pad comprising a conductive material.

10. The memory element of claim 6, wherein the dielectric layer comprises one of a pair of silicon oxide layers and silicon nitride layers, a pair of silicon oxide layers and polysilicon layers, a pair of silicon nitride layers and polysilicon layers, a pair of silicon oxide layers and tungsten layers, and a set of silicon oxide layers, silicon nitride layers, and polysilicon layers.

11. A memory element, comprising: The surrounding area includes multiple stacks of dielectric layers; The memory array region comprises multiple vertically arranged columns, each of which includes: Multiple storage units; and Multiple word lines are respectively coupled to the plurality of memory cells; A stepped area, including a step, wherein the step includes a portion of the plurality of word lines extending from the memory array area; and A central bonding pad is located between the plurality of steps in the memory array region. The top and bottom surfaces of the central adhesive pad are coplanar with the two corresponding transition interfaces between the dielectric layer in the peripheral region; The step is located near one end of the central adhesive pad, and the steps of the step are formed within the thickness of the central adhesive pad.

12. The memory element of claim 11, wherein the thickness of the central bonding pad is equal to the sum of the thicknesses of one or more consecutive dielectric layers in the peripheral region.

13. The memory element of claim 11, wherein one end of the central bonding pad is adjacent to one or more steps of the gate layer including the steps in the stepped region.

14. The memory element of claim 11, further comprising circuitry located below or adjacent to the memory array region, and configured to perform functions including memory cell row and column decoding, bit line precharge logic readout, sense amplifier, or timing control.

15. The memory element of claim 14, further comprising: Multiple contact pads located on the top surface of the circuit; The internal interconnect is located above the peripheral area, the stepped area, and the memory array area; as well as Multiple via contacts pass through the multiple stacks of the dielectric layer in the peripheral region and connect the interconnects and the contact pads.

16. The memory element of claim 15, further comprising a conductive post extending from the interconnect to one end of the plurality of word lines in the stepped area.

17. The memory element of claim 11, wherein the plurality of word lines are arranged in parallel and spaced apart along the memory stack direction, and wherein the plurality of word lines are configured as control gates for the plurality of memory cells.

18. The memory element of claim 17, further comprising a common source line located below the plurality of memory cells, wherein the common source line is configured to couple the control gate to the plurality of word lines, and wherein the common source line is made of polysilicon and is separated by a dielectric layer.

19. The memory element of claim 11, wherein the central bonding pad is made of polysilicon, tungsten, silicon nitride, silicon oxide, silicon oxynitride, a high dielectric constant dielectric material, or a silicide.

20. The memory element of claim 13, wherein one or more steps of the gate layer of the staircase do not contact any conductive pillar in the staircase region.

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