General purpose registers and slot allocation in graphics processing

Abstract

Example techniques are described for generating graphics content by obtaining a texture operation instruction corresponding to a texture operation, generating an indication that the texture operation corresponds to a delayed wave in response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation, performing the texture operation, sending an initial texture sampling instruction corresponding to the performed texture operation to a texture processor, and receiving texture mapping data corresponding to the initial texture sampling instruction.

Description

[0001] This patent application claims priority to U.S. non-provisional application No. 16 / 364,829, filed on March 26, 2019, entitled “GENERAL PURPOSE REGISTERAND WAVE SLOT ALLOCATION IN GRAPHICS PROCESSING,” which has been assigned to the assignee of this application and is hereby expressly incorporated herein by reference. Background Art

[0002] Graphics processing units (GPUs) are increasingly being used in different types of devices, including mobile devices such as smartphones, virtual reality (VR) devices, augmented reality (AR) devices, tablet computers, smart watches, and the like. Many GPUs utilize stream processors (SPs) that can be built into the GPU. The stream processors in the GPU can handle most traditional graphics rendering tasks, and / or can be programmed for more general digital processing. Stream processors are well suited for traditional GPU-centric tasks (e.g., graphics, image, video, and signal processing), as well as ray tracing, computational fluid dynamics, weather modeling, and the like.

[0003] As part of generating graphics content, GPUs and / or stream processors can perform texture mapping, which can be a process for defining high-frequency details, surface texture, or color information on graphics or three-dimensional (3D) models rendered in a scene. In particular, stream processors can be well suited for texture mapping tasks. However, a constraint associated with stream processors, as well as many other hardware components, is the total amount of memory, registers, slots for execution units, and the like available for use. Summary of the invention

[0004] The systems, methods, and devices described herein all have several aspects, no single one of which is solely responsible for its desirable attributes.Without limiting the scope of the present disclosure, some non-limiting features will now be briefly described.

[0005] Methods, devices, apparatus, and computer-readable media for generating graphics content are described herein. A method may include: obtaining a texture operation instruction corresponding to a texture operation; in response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation, generating an indication that the texture operation corresponds to a delayed wave; performing the texture operation; sending an initial texture sampling instruction corresponding to the texture operation being performed to a texture processor; and receiving texture mapped data corresponding to the initial texture sampling instruction.

[0006] In some embodiments, the method may further include: generating a virtual wave slot corresponding to the texture operation.

[0007] In another embodiment, the method may further include: after determining at least one of insufficient general register space available for the texture operation or insufficient slots available for the texture operation, determining that sufficient general register space is available for the texture operation and sufficient slots are available for the texture operation; converting the virtual slots into slots; and storing texture attributes corresponding to the texture operation in the general registers.

[0008] In further embodiments, the method may include, after converting the virtual sink and storing the texture attributes, performing post-processing on the texture mapping data using the sink and the texture attributes.

[0009] In some embodiments, the method may include using a pixel interpolation unit to perform the texture operation.

[0010] In further embodiments, the method may include sending data corresponding to the texture mapping data to a downstream component of the processor, wherein the data further corresponds to a frame of content output to a display.

[0011] In another embodiment, the method may include: repeatedly determining whether sufficient general register space and slots are available for the texture operation; and upon determining that sufficient general register space is available for the texture operation and sufficient slots are available for the texture operation, performing the following operations: converting the virtual slot into a slot; and storing a texture attribute corresponding to the texture operation in the general register.

[0012] In some embodiments, the method may include: obtaining a second texture operation instruction corresponding to a second texture operation; determining at least one of insufficient general register space available for the second texture operation or insufficient slots available for the second texture operation; determining that the second texture operation requires buffer storage space and slots; storing a virtual slot corresponding to the second texture operation in the texture buffer; and storing a texture attribute corresponding to the second texture operation in the texture buffer.

[0013] A device may include a memory and a processor coupled to the memory, which is configured to cause the device to perform a method including the following operations: obtaining a texture operation instruction corresponding to a texture operation; in response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation, generating an indication that the texture operation corresponds to a delayed wave; performing the texture operation; sending an initial texture sampling instruction corresponding to the texture operation being performed to a texture processor; and receiving texture mapped data corresponding to the initial texture sampling instruction.

[0014] In some embodiments, the device may include a display and / or the memory may include a texture buffer.

[0015] In further embodiments, the device may be a wireless communication device.

[0016] A computer-readable medium may be a non-transitory computer-readable medium storing a program containing instructions which, when executed by a processor of a device, cause the device to perform a method comprising: obtaining a texture operation instruction corresponding to a texture operation; in response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation, generating an indication that the texture operation corresponds to a delayed wave; performing the texture operation; sending an initial texture sampling instruction corresponding to the texture operation being performed to a texture processor; and receiving texture mapped data corresponding to the initial texture sampling instruction.

[0017] An apparatus may include: means for obtaining a texture operation instruction corresponding to a texture operation; means for generating an indication that the texture operation corresponds to a delayed wave in response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation; means for performing the texture operation; means for sending an initial texture sampling instruction corresponding to the texture operation being performed to a texture processor; and means for receiving texture mapped data corresponding to the initial texture sampling instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following drawings and related descriptions are provided to illustrate embodiments of the present disclosure and do not limit the scope of protection of the claims. When considered in conjunction with the drawings, various aspects of the present disclosure and its many attendant advantages will be readily understood as the various aspects of the present disclosure are better understood with reference to the following detailed description, wherein:

[0019] Figure 1An example device including a stream processor and a texture processor consistent with the disclosed embodiments is shown.

[0020] Figure 2 An example device including a stream processor and a texture processor consistent with the disclosed embodiments is shown.

[0021] Figure 3 is a flow chart of an example process for allocating general register space and wave slots on a streaming processor consistent with the disclosed embodiments.

[0022] Figure 4 is a flow chart of an example process for allocating general register space and wave slots on a streaming processor consistent with the disclosed embodiments.

[0023] Figure 5 is a flow chart of an example process for asynchronously converting a virtual slot to a physical slot consistent with the disclosed embodiments.

[0024] Figure 6 is a block diagram illustrating an example device having a graphics processor including at least one stream processor consistent with the disclosed embodiments. DETAILED DESCRIPTION

[0025] Although particular embodiments are described herein, other embodiments will be apparent to those of ordinary skill in the art, including embodiments that do not provide all of the benefits and features set forth herein.

[0026] This specification describes a multithreaded stream processor (e.g., also referred to as a stream processor), which may be a graphics processor, or may be included in a graphics processor (e.g., a GPU). This specification further describes the efficient allocation of general registers (a set of general registers, hereinafter referred to as GPR) and physical slots of execution units to threads being executed by the stream processor. In this specification, the stream processor may be configured to obtain and schedule the execution of instructions associated with a thread, and may include or access a set of registers (e.g., GPR). The GPR may include one or more registers (e.g., general register blocks, general register spaces, general register imprints, etc.) capable of storing (e.g., temporarily storing) data associated with the execution of instructions, and the GPR may be a volatile or non-volatile memory. In addition, the stream processor may include one or more execution units (e.g., arithmetic logic units (ALUs)) for performing calculations, one or more units associated with memory operations, and the like.

[0027] The stream processor can execute multiple threads. In some cases, these threads can be combined according to a specific code (e.g., instructions), and the combined threads can be executed in parallel. For example, a group of threads (e.g., warp, wavefront, wave, etc., hereinafter referred to as wave) can include a specific number of threads, each thread repeatedly executing the same code portion, such as a shader (e.g., instructions associated with rendering an image in a specific, unique manner) or a kernel (e.g., a computing kernel). The stream processor can execute (1) multiple threads and / or (2) multiple thread groups in parallel, and the techniques described herein can be applied in any case. For example, the stream processor can execute multiple groups of threads, each group of threads corresponding to the execution of a corresponding portion of the code. For example, the stream processor can alternate between thread groups so that each group can be executed. For another example, the stream processor can execute multiple threads, each thread corresponding to the execution of a corresponding code portion. For convenience, this specification refers to a thread as a specific thread or a group of threads, both of which are associated with the execution of a specific code portion.

[0028] In a stream processor, texture operations may have relatively long delays. Delay may be an important aspect of graphics processor performance. This delay can be alleviated by executing more threads on the GPU, so that some threads can perform ALU operations while other threads are waiting for texture operations to complete. This can be called "delay hiding". For example, in order to increase delay hiding, more memory can be included on the graphics processor. However, including additional memory (e.g., increasing the size of the memory) usually increases costs. For example, GPR can store data for different threads executed in parallel. The GPR size can be increased to improve the delay hiding ability of the execution thread. However, GPR can be a multi-port random access memory (RAM), which is more expensive than a single-port RAM and uses more physical space (e.g., three to four times the bit area of ​​a single-port RAM). Therefore, the cost of increasing the GPR size may be high.

[0029] In addition, a wave slot can be a physical storage used by a stream processor to schedule work for an execution unit (e.g., an ALU). A "wave" can represent the smallest scheduled work unit for an execution unit and can include multiple threads (e.g., 64 threads). Similar to the GPR size, the number of physical wave slots can be increased to improve latency hiding when executing threads. However, the cost of increasing the number of physical wave slots is also high. Therefore, GPU technology can be improved by more efficiently utilizing the available physical wave slots and GPRs.

[0030] Aspects of the present disclosure relate to efficient allocation of GPR space and physical slots.

[0031] Typically, a stream processor processes texture operations by allocating physical wave slots so that an execution unit executes a wave corresponding to a texture operation; and allocating GPR space to store texture attributes. The execution unit may process the physical wave slots in sequence, and / or pause a wave while waiting for a memory operation to complete. When an execution unit is scheduled, the execution unit may access the stored texture attributes to process a texture operation wave, the execution unit may determine texture coordinates, which may then be stored in a GPR, and the execution unit may determine a texture request, which may be sent to a texture loading unit. Based on the texture request, the texture loading unit may retrieve the texture coordinates from the GPR and send a texture sampling instruction to a texture processor. Based on the texture sampling instruction, the texture processor may perform, for example, texture mapping and texture filtering, and output the texture mapped data to the texture loading unit. The texture loading unit may then write the texture mapped data to the GPR, which may then be used for post-processing.

[0032] As described above, the stream processor allocates physical slots and GPR space before sending a texture sampling instruction to the texture processor. However, for some texture operations, the stream processor may be able to operate without using an execution unit before sending a texture sampling instruction to the texture processor.

[0033] For example, for some texture operations, the stream processor (and / or pixel interpolation unit (PI)) can generate an initial texture sampling instruction and send it to the texture processor without using the execution unit. Because the execution unit is not used at this stage, the stream processor can perform texture operations without initially allocating physical slots and / or GPR space. At a subsequent time (e.g., after receiving filtered and texture-mapped data from the texture processor), the stream processor can allocate physical slots and GPR space for storing return data (e.g., for post-processing operations). Therefore, by not initially allocating physical slots and GPR space for such texture operations, more physical slots and GPR space can be used for other operations, and the stream processor does not have to wait until there is space available to perform texture operations. Therefore, the throughput of the stream processor can be increased.

[0034] In another embodiment, a texture buffer can be used to increase the amount of texture processing latency hiding even for more complex texture operations. The texture buffer can be a type of memory (e.g., a single-port RAM) that is less expensive to add to a stream processor than additional physical slots and / or GPR space. For example, in more complex texture operations, when the physical slots and / or GPR space are full, the stream processor can use virtual slots stored in the texture buffer instead of physical slots, and further use the texture buffer to store texture attributes until physical slots and GPR space become available. By storing virtual slots and texture attributes in the texture buffer, the stream processor can continue to issue initial texture sampling instructions (e.g., for simple operations that do not use execution units) instead of waiting for physical slots and GPR space to become available for more complex texture operations.

[0035] It should be understood that in some cases, a texture operation may correspond to more than one wave and, therefore, be associated with more than one physical or virtual wave slot. However, for simplicity, the following description may refer to a physical or virtual wave slot (i.e., in the singular), but where appropriate, the same or similar processes may be applied to more than one physical or virtual wave slot consistent with the disclosed embodiments. Therefore, references to a single physical or virtual wave slot are not intended to be limiting.

[0036] The embodiments described herein are described with respect to texture operations, however, in other embodiments, the techniques described herein may also be used for other operations, such as retrieving color information or performing general computing tasks. Therefore, the following description related to texture mapping operations is for illustrative purposes only and is not intended to be limiting.

[0037] Figure 1 An example device 100 including a stream processor 110 and a texture processor 170 is shown consistent with the disclosed embodiments. Figure 1 As shown in FIG. 1 , the stream processor 110 includes a sequencer 130, a wave queue 140, an execution unit 145, a GPR 150, a pixel interpolation unit 160, a multiplexer 165, and a texture load unit 180. The stream processor 110 may receive input 120 and may send output 190. The stream processor 110 may also send to and receive from a texture processor 170.

[0038] Figure 1 The components depicted in the device 100 are for illustration purposes only and are not intended to be limiting. For example, the device 100, the stream processor 110, and / or the texture processor 170 may include fewer components or Figure 1100 may include other components not shown. For example, device 100 may include other components of a GPU pipeline, as well as other processors, memories, and other types of computer components. Stream processor 110 may include other components such as instruction caches, context registers, local memory, clock components, power components, schedulers, high-level task managers, etc., and may communicate with other components such as high-level sequencers, memories, other GPU components, other processors, etc.

[0039] In some embodiments, the input 120 of the stream processor 110 may include attributes of an operation and / or a packet describing an operation (e.g., a texture operation). For example, the input 120 may be received from a high-level sequencer, a high-level task manager of the stream processor 110, another GPU component, and / or another stream processor 110 component, and may be instructions and / or texture attributes (including, for example, i / j center-of-gravity coefficient data).

[0040] In further embodiments, sequencer 130 may be any type of component capable of receiving input 120, allocating slots, allocating GPR space, and utilizing pixel interpolation unit 160. For example, sequencer 130 may receive input 120, may generate virtual slots, may allocate physical slots, may allocate GPR space, and / or may defer allocating GPR space for certain operations, as described in further detail below.

[0041] In another embodiment, the wave queue 140 may be a storage component having a plurality of slots for scheduling work of the execution unit 145. In some implementations, the wave queue 140 may have a set of available physical wave slots for scheduling operations of the stream processor 110. Therefore, if all physical wave slots are allocated, other operations requiring physical wave slots cannot be continued until the physical wave slots become available.

[0042] In further embodiments, execution unit 145 may be any type of one or more processing components and circuits. For example, execution unit 145 may include one or more ALUs, floating point units, address generation units, load store units, branch execution units, registers, and the like. Execution unit 145 may sequentially execute operations corresponding to physical wave slots of wave queue 140, and / or pause a wave while waiting for one or more prerequisite operations (e.g., memory operations, loading texture data, and the like) to complete for the wave. In some implementations, execution unit 145 may read data from and write data to GPR 150. In further implementations, execution unit 145 may send texture requests to texture load unit 180.

[0043] In some embodiments, GPR 150 may be a storage component that can be used to store data for stream processor 110, such as texture attributes (e.g., u / v coordinates or i / j coefficient data). In some implementations, GPR 150 may receive texture attributes (e.g., i / j coefficient data) from sequencer 130, receive texture attributes (e.g., u / v coordinates) from execution unit 145, and / or receive texture attributes from texture load unit 180. In other implementations, GPR 150 may provide texture attributes to execution unit 145 and / or texture load unit 180.

[0044] In further embodiments, the pixel interpolation unit 160 may be any type of component capable of issuing initial texture sampling instructions to the texture processor 170. In some implementations, the pixel interpolation unit 160 may be part of the sequencer 130, while in other implementations, the pixel interpolation unit 160 may be a separate component. As used herein, in some examples, initial texture sampling instructions may refer to instructions generated by the pixel interpolation unit (e.g., simple shader operations) and / or instructions generated without using an execution unit of a stream processor. The initial texture sampling instructions may include instructions that cause the texture processor to perform, for example, texture mapping and filtering.

[0045] In further embodiments, multiplexer 165 may be any type of component capable of combining two signals into one signal (eg, combining texture sampling instructions from pixel interpolation unit 160 and texture load 180 into one signal to texture processor 170).

[0046] In some embodiments, the texture processor 170 may be a component that receives initial texture sampling instructions and texture sampling instructions, performs texture mapping, performs texture filtering, and / or returns texture mapping data to the texture loading unit 180 .

[0047] In further embodiments, texture load unit 180 may be a component that receives a texture request from execution unit 145, retrieves texture attributes from GPR 150, determines a texture sampling instruction (e.g., based on the texture request and the texture attributes), sends a texture sampling instruction to texture processor 170, receives texture mapped data from texture processor 170, and outputs (e.g., outputs 190) the texture mapped data (e.g., to another component, to GPR 150, etc.). As used herein, in some examples, texture sampling instructions may refer to instructions generated using data processed by an execution unit of a stream processor. Texture sampling instructions may include instructions that cause a texture processor to perform, for example, texture mapping and filtering.

[0048] In further embodiments, output 190 may be an output from stream processor 110, texture load unit 180, GPR 150, and / or another component of stream processor 110. For example, output 190 may include texture mapped data. In some embodiments, output 190 may be texture mapped data for post-processing operations. In further embodiments, post-processing operations may be performed within stream processor 110, and output 190 may be post-processed texture mapped data that is pushed to downstream components in the GPU pipeline.

[0049] Figure 2 An example device 200 including a stream processor 210 and a texture processor 270 is shown consistent with the disclosed embodiments. Figure 2 As shown in , stream processor 210 includes sequencer 230, wave queue 240, execution unit 245, GPR 250, pixel interpolation unit 260, multiplexer 265, texture load unit 280, and texture buffer 285. Stream processor 210 can receive input 220 and can send output 290. Stream processor 210 can also send to and receive from texture processor 270.

[0050] Figure 2 The components of the device 200 described in the figure are for illustration purposes only and are not intended to be limiting. For example, the device 200, the stream processor 210 and / or the texture processor 270 may include fewer components or Figure 2 2. The device 200 may include other components not shown in the figure. For example, the device 200 may include other components of the GPU pipeline, as well as other processors, memories, and other types of computer components. The stream processor 210 may include other components (e.g., instruction caches, context registers, local memory, clock components, power components, schedulers, high-level task managers, etc.) and may be able to communicate with other components (e.g., high-level sequencers, memories, other GPU components, other processors, etc.).

[0051] In some embodiments, the input 220 of the stream processor 210 may include attributes of an operation and / or a packet describing an operation (e.g., a texture operation). For example, the input 220 may be received from a high-level sequencer, a high-level task manager of the stream processor 210, another GPU component, and / or another stream processor 210 component, and may be instructions and / or texture attributes (including, for example, i / j center-of-gravity coefficient data).

[0052] In further embodiments, the sequencer 230 may be any type of component capable of receiving the input 220, allocating slots, allocating GPR space, utilizing the pixel interpolation unit 260, and storing data (e.g., virtual slot data) to the texture buffer 285. For example, the sequencer 230 may receive the input 220, may generate virtual slots, may store data for the virtual slots in the texture buffer 285 (e.g., if no physical slots are available), may allocate physical slots, may allocate GPR space, and / or may defer allocating GPR space and physical slots for certain operations, as described in further detail below.

[0053] In another embodiment, the wave queue 240 may be a storage component having a plurality of slots for scheduling the work of the execution unit 245 .

[0054] In further embodiments, execution unit 245 may be any type of one or more processing components and circuits. For example, execution unit 245 may include one or more ALUs, floating point units, address generation units, load store units, branch execution units, registers, and the like. Execution unit 245 may sequentially execute operations corresponding to physical wave slots of wave queue 240, and / or pause a wave while waiting for one or more prerequisite operations (e.g., memory operations, loading texture data, and the like) to complete for the wave. In some implementations, execution unit 245 may read data from and write data to GPR 250. In further implementations, execution unit 245 may send texture requests to texture load unit 280.

[0055] In some embodiments, GPR 250 may be a storage component that can be used to store data, such as texture attributes (e.g., u / v coordinates or i / j coefficient data) for stream processor 210. In some implementations, GPR 250 may receive texture attributes from sequencer 230, execution unit 245, and / or from texture load unit 280. In other implementations, GPR 250 may provide texture attributes to execution unit 245 and / or texture load unit 280.

[0056] In further embodiments, the pixel interpolation unit 260 may be any type of component capable of issuing initial texture samples to the texture processor 179. In some implementations, the pixel interpolation unit 260 may be part of the sequencer 230, while in other implementations, the pixel interpolation unit 260 may be a separate component.

[0057] In further embodiments, multiplexer 265 may be any type of component capable of combining two signals into one signal (eg, combining texture sampling instructions from pixel interpolation unit 260 and texture load 280 into one signal to texture processor 270).

[0058] In some embodiments, the texture processor 270 may be a component that receives initial texture sampling instructions and texture sampling instructions, performs texture mapping, performs texture filtering, and / or returns texture mapped data to the texture load unit 280 .

[0059] In further embodiments, texture load unit 280 may be a component that receives a texture request from execution unit 245, retrieves texture attributes from GPR 250 and texture buffer 285, determines a texture sampling instruction (e.g., based on the texture request and the texture attributes), sends a texture sampling instruction to texture processor 270, receives texture mapped data from texture processor 270, and outputs (e.g., outputs 290) the texture mapped data (e.g., to another component, to GPR 250, etc.).

[0060] In further embodiments, the texture buffer 285 may be a storage component that can be used to store data for the stream processor 210, such as texture attributes (e.g., u / v coordinates or i / j coefficient data), virtual slot data, texture mapped data, etc. In some implementations, the texture buffer 285 may receive texture attributes and / or virtual slot data from the sequencer 230 and / or the texture load unit 280. In further implementations, the texture buffer 285 may receive texture mapped data from the texture processor 270 and / or the texture load unit 280. For example, if the virtual slots have not been converted to physical slots, as discussed in further detail below, the texture mapping data received from the texture processor 270 may be stored in the texture buffer 285 until the physical slots are available. In further implementations, once the physical slots become available and the virtual slots can be converted to physical slots, the texture buffer 285 may provide the texture attributes and / or virtual slot data to, for example, the sequencer 230. In some implementations, the texture buffer may provide texture attributes, virtual slot data, and / or texture mapped data to the texture load unit 280, for example, when a physical slot becomes available after receiving texture mapped data from the texture processor 270.

[0061] In further embodiments, the output 290 may be an output from the stream processor 210, the texture loading unit 280, and / or another component of the stream processor 210. For example, the output 290 may include texture mapped data. In some embodiments, the output 290 may be texture mapped data for a post-processing operation. In further embodiments, the post-processing operation may be performed within the stream processor 210, and the output 290 may be post-processed texture mapped data that is pushed to a downstream component in the GPU pipeline.

[0062] Figure 3is a flow chart of an example process 300 for allocating general register space and wave slots on a stream processor consistent with the disclosed embodiments. In some embodiments, the process 300 can be performed using any type of computing device (e.g., a personal computer, a wireless communication device, a video game console, an augmented reality head mounted device, a virtual reality head mounted device, a mixed reality head mounted device, etc.). In other embodiments, the process 300 can be performed by a GPU of a computing device. In further embodiments, the process 300 can be performed using a stream processor and a texture processor of a GPU of a computing device. For example, the process 300 can be performed using a stream processor 110 and a texture processor 170 or a stream processor 210 and a texture processor 270.

[0063] When a computing device (e.g., a stream processor of a GPU of the computing device) obtains a texture operation instruction, process 300 may begin in block 310. In some embodiments, the texture operation instruction may correspond to and / or include texture attributes. In other embodiments, the texture operation instruction may be processed to determine texture attributes (e.g., i / j for two-dimensional (2D), or i / j / k for 3D, center-of-gravity coefficient data). In further embodiments, the texture operation instruction may be processed by a compiler to generate an execution thread for the computing device, generate an execution wave (of multiple threads) for the texture operation, and include a sampling instruction end indicator in the thread to indicate when the texture sampling of the wave is completed. In other embodiments, the texture operation instruction may include: a packet describing the texture operation to be performed.

[0064] In block 315, the computing device may generate a virtual wave slot for an execution wave of a texture operation of the texture operation instruction. In some embodiments, the virtual wave slot may control information associated with the wave. For example, the virtual wave slot may hold a current instruction pointer to a shader program associated with the wave, an execution mask for determining active threads in the wave, and / or a pointer to a storage base associated with the wave (whether currently available or not), etc.

[0065] In block 320, the computing device may determine whether there is GPR space and / or physical wave slots available for the texture operation. For example, the computing device may perform this determination based on the amount of available GPR space, the amount of available physical wave slots, the size / amount of texture attributes associated with the texture operation, the number of execution threads associated with the texture operation, the number of execution waves associated with the texture operation, and the like.

[0066] If, in block 320, the computing device determines that there is not enough available GPR space and / or physical wave slots (block 320 - No), the process may proceed to block 325. In block 325, the computing device may determine whether the execution wave of the texture operation requires GPR space and / or physical wave slots. For example, because the execution wave corresponds to a simple shader operation (e.g., the operation is a 2D operation and includes i / j coefficient data), the computing device may determine that GPR space and physical wave slots are not required. As another example, the computing device may determine that GPR space and physical wave slots are required because the texture operation corresponds to a more complex operation (e.g., the operation is a 3D operation and includes i / j / k coefficient data, calculates bias (e.g., based on input k), performs color synthesis, requires determining w coordinates, etc.).

[0067] If, in box 325, the computing device determines that the first wave does not require GPR space and / or physical slots (box 325-no), process 300 can proceed to box 330. In box 330, the computing device can perform the texture operation without initially allocating or using GPR space and / or physical slots. For example, the texture operation can be a simple 2D shader operation that uses i / j coefficient data (texture attributes) and data from local memory to determine the u / v coordinates. In some implementations, a pixel interpolation unit can be used instead of an execution unit of the computing device to perform the simple 2D shader operation. Therefore, since the pixel interpolation unit can be used to perform the texture operation, it may not be necessary to allocate physical slots and GPR space for the execution unit at the current stage, although the physical slots and / or GPR space may be required for the texture operation at a later stage (e.g., for a post-processing operation).

[0068] In block 335, the computing device may mark the execution wave for the texture operation as a delayed wave. As used herein, a delayed wave is a wave corresponding to an operation that is not currently assigned a physical wave slot. In some implementations, the flag may be included in an initial texture sampling instruction (e.g., as generated in block 340), sent to a texture processor, and received in texture mapping data received from the texture processor (e.g., as in block 350). Thus, the flag may be propagated through the texture processor.

[0069] In some embodiments, the computing device may maintain a delayed wave capacity counter to manage the number of delayed waves currently being maintained. For example, when a new delayed wave is marked, the delayed wave capacity counter may be adjusted (e.g., decremented) to indicate that an additional delayed wave is being maintained. When the processing of the sampling instruction for the delayed wave ends, the delayed wave capacity counter may be adjusted (e.g., incremented) to indicate that one less delayed wave is being maintained.

[0070] In further embodiments, the computing device may maintain a delay wave queue (e.g., in a first-in, first-out (FIFO) buffer stored in a sequencer) using a write / read pointer to save the coverage mask (i.e., the portion of pixels covered by the triangle) and the allocation status of the coverage mask. The allocation status may indicate whether a physical wave slot has been allocated or whether allocation of a physical wave slot is pending. After a delay wave is generated, allocation of a physical wave slot is pending until a physical wave slot becomes available. In some embodiments, the first delay wave in the delay wave queue may have priority for the next physical wave slot that becomes available.

[0071] In block 340, the computing device may generate an initial texture sampling instruction and send it to a texture processor. In some embodiments, the initial texture sampling instruction may be a process based on a pixel interpolation unit (e.g., a simple shader operation) and may include instructions for causing the texture processor to perform, for example, texture mapping and filtering. In other embodiments, the initial texture sampling instruction may include a flag indicating that the initial texture sampling instruction is associated with a delayed wave.

[0072] In some embodiments, when the texture processor is processing an initial sampling instruction, if a physical wave slot and / or GPR space becomes available, the computing device may allocate the available physical wave slot to the delay wave, allocate the GPR space, update the physical wave slot to the coverage mask of the delay wave, and change the allocation state in the delay wave queue to allocated.

[0073] In 350, the computing device may receive texture mapped data from a texture processor. For example, a stream processor of a GPU of the computing device may receive the data from a texture processor of the GPU. In some embodiments, the received data may include a flag indicating that the data corresponds to a delayed wave. In further embodiments, if the data is associated with an end of a sampling instruction, a delayed wave capacity counter may be adjusted.

[0074] In 355, the computing device may output texture mapping data. In some embodiments, the computing device may output the texture mapping data to a GPR, where a post-processing operation may be performed. In such an embodiment, it may be necessary to allocate GPR space and physical wave slots before the post-processing operation. Therefore, if the physical wave slots do not become available, the GPR space is not available, and / or the allocation of delayed waves remains in waiting, the computing device may have to wait until the physical wave slots and / or GPR space become available so as to allocate physical wave slots for the post-processing of the texture mapping data. In other embodiments, the texture mapping data may be output from the stream processor to other downstream components of the GPU (e.g., after the post-processing operation has been performed). In a further embodiment, the texture mapping data may correspond to an image frame output to a display of the computing device.

[0075] Returning to block 320, if the computing device determines in block 320 that GPR space and physical slots are available (block 320-yes), the process can proceed to block 360. Alternatively, returning to block 325, if the computing device determines that GPR space and physical slots are needed (block 325-yes) (e.g., the operation is a 3D operation and includes i / j / k coefficient data, calculates bias (e.g., based on input k), performs color synthesis, needs to determine w coordinates, etc.), the process can proceed to block 360, but may have to wait until GPR space and / or physical slots are available.

[0076] In blocks 360 and 370, the computing device may allocate physical slots and GPR space for texture operations. In block 360, the computing device may allocate physical slots by converting virtual slots to physical slots. For example, the computing device may update the physical slots to the coverage mask of the virtual slots.

[0077] In block 370 , the computing device may write texture attributes (eg, i / j / k coefficient data) of the texture operation into the GPRs.

[0078] In block 375, the computing device may perform a texture operation. In some embodiments, the computing device may perform the texture operation using an execution unit (e.g., an ALU) of the computing device. In other embodiments, the texture operation may be performed using texture attributes, wherein the execution unit may retrieve the texture attributes from the GPR. For example, the texture operation may be a 3D shader operation that uses i / j / k coefficient data (texture attributes retrieved from the GPR) and data from a local memory to determine u / v / w coordinates. The execution unit may then store the determined u / v / w coordinates to the GPR. Based on the texture operation, the execution unit may send a texture request corresponding to the texture operation to a texture loading unit, which may retrieve the i / j / k coefficient data and the u / v / w coordinates from the GPR. Using the retrieved data, the texture loading unit may generate a texture sampling instruction.

[0079] In block 380, the computing device may send a texture sampling instruction to the texture processor. In some embodiments, the texture sampling instruction may be an execution unit based process (eg, a more complex operation) and may include instructions that cause the texture processor to perform texture mapping and filtering.

[0080] In block 350 , the computing device may receive texture mapped data, as described above.

[0081] Figure 44 is a flow chart of an example process 400 for allocating general register space and wave slots on a stream processor consistent with the disclosed embodiments. In some embodiments, the process 400 can be performed using any type of computing device (e.g., a personal computer, a wireless communication device, a video game console, an augmented reality head mounted device, a virtual reality head mounted device, a mixed reality head mounted device, etc.). In other embodiments, the process 400 can be performed by a GPU of a computing device. In further embodiments, the process 400 can be performed using a stream processor and a texture processor of a GPU of a computing device. For example, the process 400 can be performed using a stream processor 110 and a texture processor 170 or a stream processor 210 and a texture processor 270.

[0082] When a computing device (e.g., a stream processor of a GPU of the computing device) obtains a texture operation instruction, process 400 may begin in block 405. In some embodiments, the texture operation instruction may correspond to and / or include texture attributes. In other embodiments, the texture operation instruction may be processed to determine the texture attributes (e.g., i / j for 2D, or i / j / k for 3D center of gravity coefficient data). In further embodiments, the texture operation instruction may be processed by a compiler to generate an execution thread for the computing device, generate an execution wave (of multiple threads) for the texture operation, and include a sampling instruction end indicator in the thread to indicate when the texture sampling of the wave is completed. In other embodiments, the texture operation instruction may include: a packet describing the texture operation to be performed.

[0083] In block 410 , the computing device may generate a virtual wave slot for an execution wave of a texture operation of a texture operation instruction.

[0084] In block 415, the computing device may determine whether there is GPR space and / or physical wave slots available for the texture operation. For example, the computing device may perform this determination based on the amount of available GPR space, the number of available physical wave slots, the size / number of texture attributes associated with the texture operation, the number of execution threads associated with the texture operation, the number of execution waves associated with the texture operation, and the like.

[0085] If in block 415 the computing device determines that there is not enough available GPR space and / or physical wave slots (block 415 - No), the process may proceed to block 420. In block 420, the computing device may determine whether the execution wave of the texture operation requires buffer storage space and / or wave slots.

[0086] If, in block 420, the computing device determines that buffer storage space and / or wave slots are not required to perform the wave (block 420-No), process 400 may proceed to block 425. In block 425, the computing device may perform the texture operation without initially allocating or using GPR space and / or physical wave slots. In some implementations, a pixel interpolation unit may be used in place of an execution unit of the computing device to perform simple texture operations. Thus, since the pixel interpolation unit may be used to perform the texture operation, physical wave slots and GPR space of the execution unit may not need to be allocated at the current stage, although the physical wave slots and / or GPR space may be required for the texture operation at a later stage (e.g., for a post-processing operation).

[0087] In block 430, the computing device may mark the execution wave of the texture operation as a delayed wave. In some implementations, the flag is an indication that the texture operation corresponds to a delayed wave. In other implementations, the flag may be included in an initial texture sampling instruction (e.g., as generated in block 435), sent to a texture processor, and received in texture mapping data received from the texture processor (e.g., as in block 440). Thus, the flag may be propagated through the texture processor.

[0088] In some embodiments, the computing device may maintain a delay wave capacity counter to manage the number of delay waves currently being held and maintain a delay wave queue using a write / read pointer to save the coverage mask (i.e., the portion of pixels covered by the triangle) and the allocation status of the coverage mask, as described above.

[0089] In block 435, the computing device may generate an initial texture sampling instruction and send it to the texture processor. In some embodiments, the initial texture sampling instruction may be a process based on a pixel interpolation unit (e.g., a simple shader operation) and may include instructions for causing the texture processor to perform, for example, texture mapping and filtering. In other embodiments, the initial texture sampling instruction may include a flag indicating that the initial texture sampling instruction is associated with a delayed wave.

[0090] In some embodiments, when the texture processor is processing an initial sampling instruction, if a physical wave slot and / or GPR space becomes available, the computing device may allocate the available physical wave slot to the delay wave, allocate the GPR space, update the physical wave slot to the coverage mask of the delay wave, and change the allocation state in the delay wave queue to allocated.

[0091] At 440, the computing device may receive texture mapped data from a texture processor. For example, a stream processor of a GPU of the computing device may receive the data from a texture processor of the GPU. In some embodiments, the received data may include a flag indicating that the data corresponds to a delayed wave. In other embodiments, if the data is associated with an end of a sampling instruction, a delayed wave capacity counter may be adjusted. In some implementations, the received texture mapped data may be received by a texture loading unit (e.g., Figure 2 280) is received by the texture loading unit 280 shown in FIG. For example, if the virtual slots corresponding to the texture mapped data are converted to physical slots before the stream processor receives the texture mapped data, the texture loading unit can receive the texture mapped data. In other implementations, the received texture mapped data can be received by a texture buffer (e.g., Figure 2 For example, if the virtual slots corresponding to the texture mapped data are not converted to physical slots before the stream processor receives the texture mapped data, the texture mapped data can be received and stored in the texture buffer until a physical slot becomes available.

[0092] In 445, the computing device may output the texture mapped data. In some embodiments, the computing device may output the texture mapped data to a GPR, where a post-processing operation may be performed. In such an embodiment, it may be necessary to allocate GPR space and physical wave slots before the post-processing operation. Therefore, if the physical wave slots do not become available, there is not enough GPR space available, and / or the allocation of delayed waves remains in waiting, the computing device may have to wait until the physical wave slots and / or GPR space become available so as to allocate physical wave slots for the post-processing of the texture mapped data. In other embodiments, the texture mapped data may be output from the stream processor to other downstream components of the GPU (e.g., after the post-processing operation has been performed). In a further embodiment, the texture mapped data may correspond to an image frame of the graphics content of the display output to the computing device.

[0093] Returning to block 420 , if the computing device determines that buffer storage space and wave slots are needed (block 420 —yes), the process may proceed to block 450 .

[0094] In block 450 , the computing device may store the virtual slot data in a texture buffer.

[0095] In block 455 , the computing device may write texture attributes of the texture operation into a texture buffer.

[0096] Thus, as described above, the texture buffer may allow the stream processor to continue receiving texture operations rather than waiting for a slot or GPR space for the current operation. In addition, the computing device may continue to send initial texture sampling instructions to the texture processor (eg, as in block 435).

[0097] In block 460, the computing device may perform the texture operation. In some embodiments, the computing device may perform the texture operation using an execution unit (e.g., an ALU) of the computing device. In other embodiments, the texture operation may be performed using texture attributes, where the execution unit may retrieve the texture attributes from a texture buffer. The execution unit may then store the determined u / v / w coordinates to a texture buffer or GPR (if space is available). Based on the texture operation, the execution unit may send a texture request corresponding to the texture operation to a texture loading unit, which may retrieve the texture attributes and coordinates stored by the execution unit from the texture buffer (or GPR). Using the retrieved data, the texture loading unit may determine a texture sampling instruction.

[0098] In block 470, the computing device may determine a texture sampling instruction and send it to the texture processor. In some embodiments, the texture sampling instruction may be an execution unit-based process (e.g., a more complex operation) and may include instructions to cause the texture processor to perform texture mapping and filtering. In various embodiments, the virtual slots may be converted to physical slots and / or texture attributes in the texture buffer may be written to the GPRs before block 460, when block 460 is executed, after block 460, before block 470, when block 470 is executed, after block 470, after block 440 when texture mapped data is received from the texture processor, and so on.

[0099] Returning to block 415 , if the computing device determines in block 415 that the GPR space and physical slots are available (block 415 —Yes), the process may proceed to block 480 .

[0100] In blocks 480 and 485, the computing device may allocate physical slots and GPR space for texture operations. In block 480, the computing device may allocate physical slots by converting virtual slots to physical slots. For example, the computing device may update the physical slots to the coverage mask of the virtual slots.

[0101] In block 485 , the computing device may write texture attributes (eg, i / j / k coefficient data) of the texture operation into the GPRs.

[0102] In block 490, the computing device may perform the texture operation. In some embodiments, the computing device may use an execution unit (e.g., an ALU) of the computing device to perform the texture operation. The execution unit may then store the determined coordinates in a GPR. Based on the texture operation, the execution unit may send a texture request corresponding to the texture operation to a texture load unit.

[0103] In block 495, at the texture loading unit, the computing device may determine and send a texture sampling instruction to the texture processor. In some embodiments, the texture sampling instruction may be based on the coordinates stored by the execution unit (e.g., a more complex operation) and may include instructions that cause the texture processor to perform texture mapping and filtering.

[0104] In block 440 , the computing device may receive texture mapped data, as described above.

[0105] Figure 5 is a flow chart of an example process 500 for asynchronously converting a virtual slot to a physical slot consistent with the disclosed embodiments. In some embodiments, process 500 may be performed using any type of computing device (e.g., a personal computer, a wireless communication device, a video game console, an augmented reality head mounted device, a virtual reality head mounted device, a mixed reality head mounted device, etc.). In other embodiments, process 500 may be performed by a GPU of a computing device. In further embodiments, process 500 may be performed using a stream processor and a texture processor of a GPU of a computing device. For example, process 500 may be performed using stream processor 110 and texture processor 170 or stream processor 210 and texture processor 270. Additionally, process 500 may be performed in combination with the stream processor 110 and texture processor 170. Figure 3 The process 300 described in and / or Figure 4 The process 500 is performed asynchronously based on the process 400 described in FIG.

[0106] The process may begin in block 510. In block 510, the computing device may determine whether the delayed wave queue is empty. If the delayed wave queue is empty (block 510-yes), the process may return to block 510. Thus, the computing device may repeatedly and / or continuously monitor the wave queue until it is no longer empty. If the delayed wave queue is not empty (block 510-no), the process may proceed to block 520.

[0107] In block 520, the computing device may determine whether there is available GPR space and / or physical wave slots for the texture operation in the priority position in the delayed wave queue (e.g., the first wave slot in the FIFO queue). For example, the computing device may perform this determination based on the amount of available GPR space, the amount of available physical wave slots, the size / amount of texture attributes associated with the texture operation, the number of execution threads associated with the texture operation, the number of execution waves associated with the texture operation, etc.

[0108] If, in block 520, the computing device determines that sufficient GPR space and / or physical slots are not available (block 520-No), the process may return to block 520. Thus, the computing device may repeatedly and / or continuously monitor the GPR space and physical slots until they are available for texture operations at the preferred locations.

[0109] If, in block 520 , the computing device determines that the GPR space and physical slots are available (block 520 —Yes), the process may proceed to block 530 .

[0110] In blocks 530 and 540, the computing device may allocate physical slots and GPR space for texture operations. In block 480, the computing device may allocate physical slots by converting virtual slots to physical slots. For example, the computing device may update the physical slots to the coverage mask of the virtual slots and remove the virtual waves from the delayed wave queue.

[0111] In block 540 , the computing device may write texture attributes (eg, i / j / k coefficient data) for the texture operation into the GPRs.

[0112] Therefore, it can be Figure 3 and Figure 4 The process described in , asynchronously, converts the delayed wave from the virtual wave slot to the physical wave slot. For example, after determining the initial texture sample and sending it to the texture processor (e.g., Figure 3 340 or Figure 4 The delayed wave may be converted to a physical wave slot before being processed by a texture processor (e.g., Figure 3 350 or Figure 4 After receiving the texture mapped data at 440 in the example, but before performing post-processing on the texture mapped data, the delayed waves can be converted to physical wave slots, and, in some examples, the texture mapped data can be stored in a texture buffer. In another example, the texture mapped data can be stored in a texture buffer in an execution unit (e.g., Figure 4 460) before performing a texture operation and / or before determining a texture sample and sending it to a texture processor (e.g., Figure 4 470) before converting the delayed wave into a physical wave slot.

[0113] In some embodiments, post-processing may require physical wave slots and GPR space. Thus, in such embodiments, post-processing of delayed wave texture operations may not occur until after blocks 530 and 540 are performed. In other embodiments (e.g., corresponding to a system that does not use a texture buffer) Figure 1 In an embodiment of the present invention, physical wave slots and GPR space may be required before performing texture operations. Therefore, in such an embodiment, texture operations for delayed waves may not be performed until after blocks 530 and 540 are executed.

[0114] Figure 6 is a block diagram illustrating an example device having a graphics processor and at least one stream processor consistent with the disclosed embodiments. Figure 6 , an example diagram of an electronic device that can perform graphics processing is depicted and is generally designated as electronic device 600. Electronic device 600 can correspond to a mobile device (e.g., a wireless communication device such as a cellular phone), a computer (e.g., a server, a laptop computer, a tablet computer, or a desktop computer), an access point, a base station, a wearable electronic device (e.g., a personal camera, a head-mounted display, a VR headset, an AR headset, smart glasses, or a smart watch), a vehicle control system or console (e.g., an advanced driver assistance system), an autonomous vehicle (e.g., a robot car or a drone), a home appliance, a set-top box, an entertainment device, a navigation device, a personal digital assistant (PDA), a television, a monitor, a tuner, a radio station (e.g., a satellite radio station), a music player (e.g., a digital music player or a portable music player), a video player (e.g., a digital video player such as a digital video disc (DVD) player or a portable digital video player), a robot, a healthcare device, other electronic devices, or a combination thereof.

[0115] The electronic device 600 includes one or more processors, such as a processor 610 and a graphics processing unit (GPU) 696. The processor 610 may include a central processing unit (CPU), a digital signal processor (DSP), another processing device, or a combination thereof. Figure 6 In the example of FIG. 6 , the GPU 696 may include a rendering engine 612 and a stream processor 604. In other embodiments, the rendering engine 612 and / or the stream processor 604 may be included in the processor 610, etc. In another embodiment, the stream processor 604 may be part of the rendering engine 612.

[0116] Processor 610 may be coupled to GPU 696. In an illustrative example, processor 610 may be configured to communicate with GPU 696 using graphics application programming interface (API) calls. For example, GPU 696 may include an API call analyzer (not shown), and processor 610 may be configured to provide API calls to the API call analyzer during graphics processing performed by GPU 696.

[0117] The electronic device 600 may also include one or more memories (e.g., memory 632). The memory 632 may be coupled to the processor 610, the GPU 696, or both. The memory 632 may include a random access memory (RAM), a magnetoresistive random access memory (MRAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), one or more registers, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), another storage device, or a combination thereof.

[0118] Memory 632 may store instructions 660. Instructions 660 may be executed by processor 610, GPU 696, or both. In some embodiments, instructions 660 may instruct processor 610 and / or GPU 696 to perform operations related to Figure 3-5 The process described.

[0119] A coder / decoder (CODEC) 634 may also be coupled to the processor 610. The CODEC 634 may be coupled to one or more microphones (e.g., microphone 638). The CODEC 634 may also be coupled to one or more speakers (e.g., speaker 636). The CODEC 634 may include a memory 690 storing instructions 695 executable by the CODEC 634.

[0120] Figure 6 Also shown is a display controller 626 coupled to the processor 610 and the display 628. In some embodiments, the electronic device 600 may also include a wireless controller 640 coupled to an antenna 642. In other embodiments, the electronic device 600 may also include a wired network controller (not shown) coupled to a computer network cable.

[0121] The electronic device 600 may also include a sensor 650 (eg, a camera). The sensor 650 may be any type of sensor configured to capture an image.

[0122] In a specific example, the processor 610, GPU 696, memory 632, display controller 626, CODEC 634, and wireless controller 640 are included in a system on chip (SoC) device 622. In addition, an input device 630 and a power supply 644 can be coupled to the SoC device 622. In addition, in a specific example, as shown in FIG. Figure 6 As shown in FIG, display 628, input device 630, speaker 636, microphone 638, antenna 642, power supply 644, and sensor 650 are external to SoC device 622. However, each of display 628, input device 630, speaker 636, microphone 638, antenna 642, power supply 644, and sensor 650 can be coupled to a component of SoC device 622 (e.g., to an interface or controller).

[0123] As used herein, "coupling" may include communicative coupling, electrical coupling, magnetic coupling, physical coupling, optical coupling, and combinations thereof. Two devices (or components) may be directly or indirectly coupled (e.g., communicative coupling, electrical coupling, or physical coupling) through one or more other devices, components, wires, buses, networks (e.g., wired networks, wireless networks, or combinations thereof), etc. Two electrically coupled devices (or components) may be included in the same device or in different devices, and may be connected through electronic devices, one or more connectors, or inductive coupling, as illustrative and non-limiting examples. In some implementations, two devices (or components) that are communicatively coupled (e.g., coupled using electrical communication) may, for example, directly or indirectly send and receive electrical signals (digital signals or analog signals) through one or more wires, buses, networks, etc.

[0124] The devices and functions disclosed above may be designed and represented using computer files (e.g., computer files in the format of Graphic Database System II (GDSII), GERBER, etc.). The computer files may be stored on a computer-readable medium. Some or all of such files may be provided to a manufacturing processor that manufactures devices based on such files. The resulting products include wafers that are then cut into dies and packaged into integrated circuits (or "chips"). These are then used in electronic devices (e.g., Figure 6 An integrated circuit is used in an electronic device 600).

[0125] Although some examples have been described separately for convenience, it should be noted that aspects of these examples may be appropriately combined without departing from the scope of protection of the present disclosure. For example, devices 100 and 200 may be configured to: Figure 3-5 Those skilled in the art will recognize other such modifications that fall within the scope of the present disclosure.

[0126] The various exemplary logic boxes, configurations, modules, circuits, and algorithm steps described in conjunction with the examples disclosed herein can be implemented as electronic hardware, computer software executed by a processor, or a combination of the two. The various exemplary components, boxes, configurations, modules, circuits, and steps are generally described above around their functions. Whether such functions are implemented as hardware or as processor executable instructions depends on the specific application and the design constraints imposed on the entire system. A skilled technician can implement the described functions in a flexible manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of the present invention.

[0127] One or more operations of the methods or algorithms described herein may be directly embodied as hardware, software modules executed by a processor, or a combination of the two. Figure 3 The process 300 Figure 4 Course 400 or Figure 5 One or more operations in the process 500 may be initiated, controlled or executed by a field programmable gate array (FPGA) device, an application specific integrated circuit (ASIC), a processing unit such as a CPU, a digital signal processor (DSP), a controller, another hardware device, a firmware device or a combination thereof. The software module may be located in RAM, MRAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, mobile hard disk, CD-ROM or any other form of non-temporary storage medium known in the art. An exemplary storage medium may be connected to a processor so that the processor can read information from the storage medium and write information to the storage medium. Additionally or alternatively, the storage medium may also be a component of the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a computing device or a user terminal. Additionally or alternatively, the processor and the storage medium may reside in a computing device or a user terminal as discrete components.

[0128] The above description is centered around the disclosed examples to enable any person of ordinary skill in the art to implement or use the disclosed examples. Various modifications to these examples will be apparent to those of ordinary skill in the art, and the general principles defined herein may also be applied to other examples without departing from the scope of protection of the present disclosure. Therefore, the present disclosure is not limited to the examples shown herein, but may be consistent with the broadest scope of the principles and novel features specified in the appended claims.

Claims

1. A device for generating graphic content, comprising: a memory including general purpose registers and wave slots; as well as a processor coupled to the memory, the processor being configured to: Obtaining a texture operation instruction corresponding to the texture operation; generating a virtual wave slot corresponding to the texture operation; determining at least one of insufficient general register space available for the texture operation or insufficient slots available for the texture operation; In response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation, generating an indication that the texture operation corresponds to a delayed wave; performing the texture operation corresponding to the delayed wave; sending an initial texture sampling instruction corresponding to the texture operation to be performed to a texture processor; and Textured mapped data corresponding to the initial texture sampling instruction is received, wherein the textured mapped data corresponds to a frame of content output to a display.

2. The device according to claim 1, wherein: The processor is further configured to: After said determining at least one of insufficient general register space available for said texture operation or insufficient slots available for said texture operation, determining that sufficient general register space is available for said texture operation and sufficient slots are available for said texture operation; converting the virtual wave slot into a wave slot; and A texture attribute corresponding to the texture operation is stored in the general register.

3. The device according to claim 2, wherein: After converting the virtual slot and storing the texture attributes, the processor is further configured to perform post-processing on the texture mapped data using the slot and the texture attributes.

4. The device according to claim 1, wherein: The processor comprises a pixel interpolation unit, and wherein, for performing the texture operation, the processor is further configured to use the pixel interpolation unit.

5. The device according to claim 1, further comprising the display, wherein: The processor is further configured to send data corresponding to the texture mapped data to a downstream component of the processor, wherein the data further corresponds to the frame of content output to the display.

6. The device according to claim 1, wherein: The processor is further configured to: repeatedly determining whether sufficient general register space and wave slots are available for the texture operation; and Upon determining that sufficient general register space is available for the texture operation and sufficient slots are available for the texture operation, the following operations are performed: converting the virtual wave slot into a wave slot; and A texture attribute corresponding to the texture operation is stored in the general register.

7. The device according to claim 1, wherein: The memory further comprises a texture buffer, wherein the processor is further configured to: Obtaining a second texture operation instruction corresponding to the second texture operation; determining at least one of insufficient general register space available for the second texture operation or insufficient wave slots available for the second texture operation; determining buffer storage space and wave slots required for the second texture operation; storing a virtual slot corresponding to the second texture operation in the texture buffer; and Texture attributes corresponding to the second texture operation are stored in the texture buffer.

8. The device according to claim 1, wherein: The device comprises a wireless communication device.

9. A method for generating graphical content, comprising: Obtaining a texture operation instruction corresponding to the texture operation; generating a virtual wave slot corresponding to the texture operation; determining at least one of insufficient general register space available for the texture operation or insufficient slots available for the texture operation; In response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation, generating an indication that the texture operation corresponds to a delayed wave; performing the texture operation corresponding to the delayed wave; sending an initial texture sampling instruction corresponding to the texture operation to be performed to a texture processor; and Textured mapped data corresponding to the initial texture sampling instruction is received, wherein the textured mapped data corresponds to a frame of content output to a display.

10. The method according to claim 9, further comprising: After said determining at least one of insufficient general register space available for said texture operation or insufficient slots available for said texture operation, determining that sufficient general register space is available for said texture operation and sufficient slots are available for said texture operation; converting the virtual wave slot into a wave slot; and A texture attribute corresponding to the texture operation is stored in the general register.

11. The method according to claim 10, wherein: After converting the virtual slot and storing the texture attributes, the method further includes performing post-processing on the texture mapping data using the slot and the texture attributes.

12. The method according to claim 9, wherein: Performing the texture operation includes using a pixel interpolation unit.

13. The method according to claim 9, further comprising: Data corresponding to the texture mapped data is sent to a downstream component of a processor, wherein the data also corresponds to the frame of content output to the display.

14. The method according to claim 9, further comprising: repeatedly determining whether sufficient general register space and wave slots are available for the texture operation; as well as Upon determining that sufficient general register space is available for the texture operation and sufficient slots are available for the texture operation, the following operations are performed: converting the virtual wave slot into a wave slot; and A texture attribute corresponding to the texture operation is stored in the general register.

15. The method according to claim 9, further comprising: Obtaining a second texture operation instruction corresponding to the second texture operation; determining at least one of insufficient general register space available for the second texture operation or insufficient wave slots available for the second texture operation; determining buffer storage space and wave slots required for the second texture operation; storing a virtual slot corresponding to the second texture operation in a texture buffer; and Texture attributes corresponding to the second texture operation are stored in the texture buffer.

16. A non-transitory computer-readable medium for generating graphical content, the non-transitory computer-readable medium storing a program comprising instructions that, when executed by a processor of a device, cause the device to perform a method comprising: Obtaining a texture operation instruction corresponding to the texture operation; generating a virtual wave slot corresponding to the texture operation; determining at least one of insufficient general register space available for the texture operation or insufficient slots available for the texture operation; In response to determining at least one of insufficient general register space available for the texture operation or insufficient wave slots available for the texture operation, generating an indication that the texture operation corresponds to a delayed wave; performing the texture operation corresponding to the delayed wave; sending an initial texture sampling instruction corresponding to the texture operation to be performed to a texture processor; and Textured mapped data corresponding to the initial texture sampling instruction is received, wherein the textured mapped data corresponds to a frame of content output to a display.

17. The non-transitory computer readable medium of claim 16, the method further comprising: After said determining at least one of insufficient general register space available for said texture operation or insufficient slots available for said texture operation, determining that sufficient general register space is available for said texture operation and sufficient slots are available for said texture operation; converting the virtual wave slot into a wave slot; storing a texture attribute corresponding to the texture operation in the general register; as well as After converting the virtual slot and storing the texture attributes, the method further includes performing post-processing on the texture mapping data using the slot and the texture attributes.

18. The non-transitory computer readable medium of claim 16, the method further comprising: Obtaining a second texture operation instruction corresponding to the second texture operation; determining at least one of insufficient general register space available for the second texture operation or insufficient wave slots available for the second texture operation; determining buffer storage space and wave slots required for the second texture operation; storing a virtual slot corresponding to the second texture operation in a texture buffer; and Texture attributes corresponding to the second texture operation are stored in the texture buffer.

Images