Pulse generator, encoder and laser radar

Abstract

The present invention discloses a pulse generating device, an encoder and a laser radar, wherein the pulse generating device comprises a rotatable encoding disk and a reference clock circuit, a phase-locked loop circuit and a signal collector connected in sequence; the edge of the encoding disk is provided with barrier strips evenly distributed in the circumference, there is a gap between two adjacent barrier strips and a coding hole is formed, and the outer surface of the barrier strip is covered with a dielectric layer; the signal collector comprises a first capacitor plate and a second capacitor plate arranged in parallel and oppositely, the barrier strip is located between the first capacitor plate and the second capacitor plate; a closed loop is formed between the phase-locked loop circuit and the signal collector; during the rotation of the encoding disk, if any barrier strip is located between the first capacitor plate and the second capacitor plate, the phase-locked loop circuit outputs a high-level signal, otherwise it outputs a low-level signal. The pulse generating device disclosed by the present invention can be applied to high-speed angle measurement and has the advantage of high measurement accuracy.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to a pulse generating device, an encoder and a laser radar. Background Art

[0002] At present, lidar systems are widely used in the field of unmanned driving. They mainly include a laser transmitting system and a detection receiving system. The transmitted laser is reflected after encountering the target and is received by the detection system. By measuring the round-trip time of the laser, the distance to the corresponding target point can be measured (such as time-of-flight method). After scanning and detecting the entire target area, three-dimensional imaging can be finally achieved.

[0003] The types of laser radar systems currently on the market are mainly solid-state laser radar and mechanical laser radar. Among them, mechanical laser radar refers to products with motors or other rotating parts, which can detect surrounding objects through 360° rotation. In order to locate the rotation angle of the mechanical laser radar in real time, it is usually necessary to use an encoder disk to measure the angle to determine the emission and reception directions of the laser.

[0004] In the related art, the measurement of the rotation angle of the mechanical laser radar is mainly achieved through a photoelectric encoder. The photoelectric encoder usually includes a light source (such as a light-emitting diode), a coding disk and a photoelectric sensor, wherein the coding disk is usually provided with light-transmitting holes, and the light beam emitted by the light source passes through the holes on the coding disk and irradiates the photoelectric sensor, generating an electrical pulse signal. The data processor can determine the rotation speed and current angle orientation of the coding disk according to the number of pulse signals provided by the photoelectric sensor, thereby realizing the measurement of the rotation angle of the mechanical laser radar.

[0005] However, this method of achieving angle measurement through a photoelectric encoder is generally only suitable for low-speed angle information measurement. The frequency of collecting angle information is generally low, between 1KHZ-100KHZ. When applied to high-speed angle information measurement, due to the high-speed rotation of the motor or the vibration of the equipment, the photoelectric encoder output pulse jitter (mainly manifested as interference pulses caused by jitter near the light-transmitting window), which will cause miscounting and reduce the accuracy of angle measurement. Summary of the invention

[0006] The main purpose of the present invention is to provide a pulse generating device, an encoder and a laser radar, aiming to solve the technical problem in the prior art that when using photoelectric sensors to perform high-speed angle measurement, interference pulses are easily generated, resulting in inaccurate angle measurement results.

[0007] To achieve the above object, the present invention provides a pulse generating device, which includes a reference clock circuit, a phase-locked loop circuit, a signal collector and a rotatable encoder disk;

[0008] The edge of the coding disk is provided with barrier strips evenly distributed in the circumferential direction, there is a gap between two adjacent barrier strips to form a coding hole, and the outer surface of the barrier strip is covered with a dielectric layer;

[0009] The signal collector comprises a first capacitor plate and a second capacitor plate which are arranged in parallel and opposite to each other, the encoding disk and the first capacitor plate are arranged in parallel with each other, and the blocking strip or the encoding hole is located between the first capacitor plate and the second capacitor plate; wherein, during the rotation of the encoding disk, when any of the encoding holes is located between the first capacitor plate and the second capacitor plate, the signal collector outputs a first feedback signal to the phase-locked loop circuit; when any of the blocking strips is located between the first capacitor plate and the second capacitor plate, the signal collector outputs a second feedback signal to the phase-locked loop circuit, and the signal strength of the first feedback signal is less than the signal strength of the second feedback signal;

[0010] The reference clock circuit is electrically connected to the first input terminal of the phase-locked loop circuit and is used to provide a reference clock signal for the phase-locked loop circuit;

[0011] The first output end of the phase-locked loop circuit is electrically connected to the second input end of the phase-locked loop circuit after passing through the signal collector; the phase-locked loop circuit is used to generate a corresponding pulse signal and a frequency signal according to the reference clock signal and the feedback signal output by the signal collector; wherein the first output end of the phase-locked loop circuit is used to output the frequency signal, the second output end of the phase-locked loop circuit is used to output the pulse signal, and when the feedback signal is the first feedback signal, the pulse signal output by the second output end of the phase-locked loop circuit is a low-level signal; when the feedback signal is the second feedback signal, the pulse signal output by the second output end of the phase-locked loop circuit is a high-level signal.

[0012] Further, the phase-locked loop circuit includes a frequency divider, a frequency detector, a phase detector, a low-pass filter, a comparator and a voltage-controlled oscillator;

[0013] The frequency divider is electrically connected to the output end of the signal collector, and is used to divide the frequency of the feedback signal output by the signal collector to obtain a frequency-divided signal;

[0014] The frequency and phase detector is electrically connected to the frequency divider and the reference clock circuit respectively, and is used to compare the frequency and phase difference between the reference clock signal and the frequency divided signal, and output a voltage pulse signal;

[0015] The low-pass filter is electrically connected to the frequency and phase detector, and is used to filter out the high-frequency components in the pulse voltage signal and output an analog voltage signal;

[0016] The comparator is electrically connected to the low-pass filter and is used to convert the analog voltage signal into the pulse signal;

[0017] The voltage-controlled oscillator is electrically connected to the comparator and the signal collector respectively, and is used to output the frequency signal of the corresponding frequency according to the analog voltage signal.

[0018] Furthermore, the pulse generating device also includes a single chip microcomputer;

[0019] The single chip microcomputer is electrically connected to the output end of the phase-locked loop circuit and is used to generate angle information according to the pulse signal.

[0020] Furthermore, the phase-locked loop circuit includes a phase-locked loop chip, a low-pass filter, a comparator and a voltage-controlled oscillator;

[0021] The phase-locked loop chip is electrically connected to the output end of the signal collector and the output end of the reference clock circuit, respectively, and is used to compare the frequency and phase difference between the reference clock signal and the feedback signal, and output a current pulse signal;

[0022] The low-pass filter is electrically connected to the phase-locked loop chip, and is used to convert the current pulse signal into an analog voltage signal and filter out high-frequency components in the analog voltage signal;

[0023] The comparator is electrically connected to the low-pass filter and is used to convert the analog voltage signal into the pulse signal;

[0024] The voltage-controlled oscillator is electrically connected to the comparator and the signal collector, respectively, and is used to output the frequency signal of the corresponding frequency according to the analog voltage signal;

[0025] The single chip microcomputer is electrically connected to the control input terminal of the phase-locked loop chip and the output terminal of the comparator respectively, and is also used to set the operating frequency of the phase-locked loop chip.

[0026] Furthermore, the low-pass filter includes a first capacitor, a first resistor and a polarity capacitor, the positive electrode of the polarity capacitor is grounded after passing through the first resistor and the first capacitor in sequence, and the negative electrode of the polarity capacitor is grounded; the connection point between the first capacitor and the first resistor is electrically connected to the output end of the phase-locked loop chip and the input end of the voltage-controlled oscillator respectively.

[0027] Furthermore, the voltage-controlled oscillator includes a separate RC element, an oscillator tube, a second resistor, a varactor diode and a third resistor. The base and collector of the oscillator tube are electrically connected to the input end of the comparator after passing through the separate RC element respectively, the emitter of the oscillator tube is electrically connected to one end of the third resistor after passing through the second resistor, the varactor diode and the separate RC element in sequence, and the other end of the third resistor is electrically connected to the input end of the signal collector.

[0028] Further, the comparator includes an operational amplifier, a fifth resistor, a sixth resistor and a seventh resistor, wherein the in-phase input terminal of the operational amplifier and the input terminal of the voltage-controlled oscillator are electrically connected to the output terminal of the low-pass filter after passing through the fifth resistor, the inverting input terminal of the operational amplifier is electrically connected to the power supply terminal VCC after passing through the sixth resistor and is grounded after passing through the seventh resistor, the positive power supply terminal of the operational amplifier is electrically connected to the power supply terminal VCC, the negative power supply terminal of the operational amplifier is grounded, and the output terminal of the operational amplifier is used to output the pulse signal.

[0029] Furthermore, the reference clock circuit is a crystal oscillator.

[0030] Furthermore, the material of the dielectric layer includes aluminum oxide.

[0031] Furthermore, when the pulse signal is a high level signal, the frequency of the frequency signal outputted by the first output terminal of the phase-locked loop circuit is greater than or equal to 900 MHZ.

[0032] Furthermore, the pulse generating device also includes a mounting plate, the signal collector is in a "concave" shape, the mounting plate is arranged parallel to the encoding disk, the signal collector is fixed on a side surface of the mounting plate facing the encoding disk, and the barrier strip or the encoding hole is located in the opening of the signal collector.

[0033] To achieve the above-mentioned purpose, the present invention also proposes an encoder, which includes a shell, a rotating shaft, a communication interface, a circuit board installed in the shell and the aforementioned pulse generating device, the rotating shaft can be rotatably inserted into the shell, the encoding disk is located in the shell and is sleeved on the rotating shaft, the reference clock circuit and the phase-locked loop circuit are both installed on the circuit board, the signal collector is installed in the shell, and the communication interface is installed on the shell and electrically connected to the circuit board.

[0034] To achieve the above-mentioned purpose, the present invention also proposes a laser radar, which includes the aforementioned pulse generating device, the axis of the center of the encoding disk coincides with the axis of the laser radar, and the pulse generating device is arranged at the bottom of the laser radar and rotates with the rotor of the laser radar to detect the rotation angle of the laser radar.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] The pulse generating device proposed by the present invention has a plurality of barrier strips evenly arranged on the edge of the encoding disk, and the outer surface of each barrier strip is covered with a dielectric layer whose dielectric constant is greater than that of the air medium. At the same time, a signal collector is arranged on the edge of the encoding disk, and the edge of the encoding disk is arranged in parallel between two parallel capacitor plates of the signal collector, so that during the rotation of the encoding disk, each barrier strip can successively pass through the gap between the two parallel capacitor plates. Since the surface of the barrier strip is covered with a dielectric layer, during the rotation of the encoding disk, the medium between the two parallel capacitor plates will alternately change between "air + dielectric layer" and "air", so that the mutual coupling capacitance and conductance between the two parallel capacitor plates will synchronously undergo corresponding changes in strength. On this basis, a phase-locked loop circuit is further arranged to communicate with the signal collector. The device forms a closed-loop circuit, and the feedback signal provided by the signal collector is used as the frequency signal of the internal feedback, and the reference clock signal provided by the reference clock circuit is used as the frequency signal of the external feedback. In this way, the phase-locked loop circuit can synchronously output a pulse signal whose voltage size corresponds to the feedback signal according to the feedback signal provided by the signal collector, thereby realizing the conversion of the capacitance and conductivity changes between the two parallel capacitor plates into directly measurable voltage changes, providing a pulse generation method different from the traditional one, and compared with the pulse generation method of the traditional photoelectric encoder, no matter whether the encoding disk rotates at high speed or low speed, since the medium changes between the two parallel capacitor plates are specific, the generated pulse signal can be effectively avoided from jittering, which is beneficial to improve the accuracy of the angle measurement result. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0038] Figure 1 A schematic diagram of the positional relationship between the encoder disk and the signal collector in one embodiment of the present invention;

[0039] Figure 2A schematic diagram of the circuit structure of a pulse generating device in one embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the circuit structure of a pulse generating device in another embodiment of the present invention;

[0041] Figure 4 for Figure 3 Specific circuit structure diagram;

[0042] Figure 5 A schematic diagram of the circuit structure of a pulse generating device in another embodiment of the present invention;

[0043] Figure 6 for Figure 5 Schematic diagram of the specific circuit structure.

[0044] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Reference Figure 1 and Figure 2 , an embodiment of the present invention provides a pulse generating device, the pulse generating device includes a reference clock circuit 1, a phase-locked loop circuit 2, a signal collector 3 and a rotatable encoding disk 4;

[0047] The edge of the coding disk 4 is provided with barrier strips 41 evenly distributed in the circumferential direction (illustratively, the barrier strips 41 are sawtooth-shaped), there is a gap between two adjacent barrier strips 41 and a coding hole 42 is formed, and the outer surface of the barrier strips 41 is covered with a dielectric layer (not shown in the figure);

[0048] The signal collector 3 includes a first capacitor C1 plate 31 and a second capacitor plate 32 which are arranged in parallel and opposite to each other, the encoding disk 4 and the first capacitor C1 plate 31 are arranged in parallel with each other, and the barrier strip 41 or the encoding hole 42 is located between the first capacitor C1 plate 31 and the second capacitor plate 32; wherein, during the rotation of the encoding disk 4, when any of the encoding holes 42 is located between the first capacitor C1 plate 31 and the second capacitor plate 32, the signal collector 3 outputs a first feedback signal to the phase-locked loop circuit 2; when any of the barrier strips 41 is located between the first capacitor C1 plate 31 and the second capacitor plate 32, the signal collector 3 outputs a second feedback signal to the phase-locked loop circuit 2, and the signal strength of the first feedback signal is less than the signal strength of the second feedback signal;

[0049] The reference clock circuit 1 is electrically connected to the first input terminal of the phase-locked loop circuit 2 and is used to provide a reference clock signal (i.e. Figure 2 Fref in );

[0050] The first output terminal of the phase-locked loop circuit 2 is electrically connected to the second input terminal of the phase-locked loop circuit 2 after passing through the signal collector 3; the phase-locked loop circuit 2 is used to generate a feedback signal (i.e. Figure 2 Ffb in the Figure 2 Fp in) and the frequency signal (i.e. Figure 2 Fout in); wherein the first output terminal of the phase-locked loop circuit 2 is used to output a frequency signal, the second output terminal of the phase-locked loop circuit 2 is used to output a pulse signal, and when the feedback signal is the first feedback signal, the pulse signal output by the second output terminal of the phase-locked loop circuit 2 is a low-level signal; when the feedback signal is the second feedback signal, the pulse signal output by the second output terminal of the phase-locked loop circuit 2 is a high-level signal.

[0051] In this embodiment, it should be noted that in some specific application scenarios, the pulse generating device of this embodiment can be used to measure the rotation angle of the laser radar, specifically, Figure 1 As shown, the encoding disk 4 is circular, and a zero-degree position 40 for determining the angular orientation of the encoding disk 4 is also provided on the edge of the encoding disk 4. When installed and used, the encoding disk 4 can be mounted on the rotor of the laser radar (generally the motor shaft), so that the encoding disk 4 can rotate synchronously with the rotor of the laser radar; wherein, the material of the encoding disk 4 can be stainless steel, plastic, etc., and the material of the above-mentioned dielectric layer can be aluminum oxide or other substances with incremental dielectric constants (the dielectric constant of the substance must be greater than that of air). In specific implementation, only the edge portion of the encoding disk 4 with the barrier strip 41 can be subjected to dielectric treatment, or the entire encoding disk 4 can be subjected to dielectric treatment (for example, the surface of the encoding disk 4 whose entire material is stainless steel is subjected to aluminum oxide treatment, so that the outer surface of each barrier strip 41 can be covered with an aluminum oxide dielectric layer).

[0052] In this embodiment, it is also necessary to explain that, in a specific implementation, a crystal oscillator can be used as the reference clock circuit 1 to provide an external feedback frequency signal for the phase-locked loop circuit 2. The concave signal collector 3 can be composed of a microstrip line with an inner layer characteristic of 50 ohms. For the convenience of analysis, the two microstrip lines in the signal collector 3 can be approximately regarded as two parallel capacitor plates. At this time, the abstract model of the signal collector 3 can be equivalent to the following: Figure 4 Or the circuit structure shown in 6 mainly consists of a capacitor C and a resistor G connected in parallel, an inductor L10 and a resistor R10 connected in series, and an inductor L20 and a resistor R20 connected in series. In order to apply the one-dimensional analysis method, it is assumed that w>d, δ<dp, and the form of the electric field and magnetic field between the two parallel capacitor plates is: Among them, e jωt represents the electric and magnetic fields changing sinusoidally with time, E z (x,z)H y (y,z) represents the spatial variation, w represents the width of the capacitor plate, d represents the distance between the two plates, δ represents the skin thickness, dp represents the thickness of the capacitor plate, μ represents the vacuum permeability value, σ cond , σ diel Represent the conductivity of the conductor and dielectric respectively. Assuming that the capacitor plate is very wide, the electromagnetic field between the two parallel capacitor plates is independent of y, then:

[0053] The surface impedance per unit length is:

[0054]

[0055] The capacitance of the lines coupling each other is:

[0056]

[0057] The inductance of the mutual coupling of the lines is:

[0058]

[0059] Conductivity in a medium:

[0060]

[0061] The above calculation formulas show that compared with the case where the medium between the two parallel capacitor plates is air, when a dielectric layer is inserted between the two parallel capacitor plates, the coupling capacitance C and the conductance G between the two parallel capacitor plates will be enhanced, thereby enhancing the feedback signal fed back to the phase-locked loop circuit 2. Based on this, in a specific implementation, in order to facilitate the conversion of the capacitance and conductance changes between the two parallel capacitor plates into directly measurable voltage changes, the circuit parameters of the phase-locked loop circuit 2 can be appropriately adjusted so that the signal strength of the feedback signal fed back to the phase-locked loop circuit 2 before the dielectric layer (such as aluminum oxide dielectric) is inserted (i.e., the signal strength of the first feedback signal) is lower than the detection signal sensitivity of the feedback signal input pin of the phase-locked loop circuit 2 (i.e., the above-mentioned second input terminal), and the signal strength of the feedback signal fed back to the phase-locked loop circuit 2 after the dielectric layer is inserted (i.e., the signal strength of the second feedback signal) is higher than the detection signal sensitivity of the feedback signal input pin of the phase-locked loop circuit 2. In this way, during the rotation of the encoder disk 4, if the medium between the two parallel capacitor plates is "air", the second input terminal of the phase-locked loop circuit 2 will not detect the internal feedback frequency signal (i.e., the above-mentioned first feedback signal), and the phase-locked loop circuit 2 is in an open-loop state at this time, and will output a low-level signal for use in calculating the angle. On the contrary, if the medium between the two parallel capacitor plates is "medium layer + air" during the rotation of the encoder disk 4, the phase-locked loop circuit 2 can be in a normal phase-locked state, and then outputs a high-level signal for angle calculation.

[0062] The pulse generating device proposed in the embodiment of the present invention has a plurality of barrier strips 41 evenly arranged on the edge of the encoding disk 4, and the outer surface of each barrier strip 41 is covered with a dielectric layer whose dielectric constant is greater than that of the air medium. At the same time, a signal collector 3 is arranged on the edge of the encoding disk, and the edge of the encoding disk 4 is arranged in parallel between two parallel capacitor plates of the signal collector 3, so that during the rotation of the encoding disk 4, each barrier strip 41 can successively pass through the gap between the two parallel capacitor plates. Since the surface of the barrier strip 41 is covered with a dielectric layer, during the rotation of the encoding disk 4, the medium between the two parallel capacitor plates will alternately change between "air + dielectric layer" and "air" (specifically, when a barrier strip 41 rotates between the two parallel capacitor plates, the medium between the two parallel capacitor plates is mainly "air + dielectric layer"; and when a coding hole 42 rotates between the two parallel capacitor plates, the medium between the two parallel capacitor plates is mainly "air"), so that the mutual coupling capacitance and conductance between the two parallel capacitor plates will synchronously undergo corresponding changes in strength (specifically, when the two parallel capacitor plates When the medium between the two parallel capacitor plates changes from "air" to "air + dielectric layer", the mutual coupling capacitance and conductance between the two parallel capacitor plates will be enhanced). On this basis, a phase-locked loop circuit 2 is further set to form a closed loop with the signal collector 3, and the feedback signal provided by the signal collector 3 is used as the internal feedback frequency signal, and the reference clock signal provided by the reference clock circuit 1 is used as the external feedback frequency signal. In this way, the phase-locked loop circuit 2 can synchronously output a pulse signal with a voltage corresponding to the feedback signal according to the feedback signal provided by the signal collector 3, thereby realizing the conversion of the capacitance and conductance changes between the two parallel capacitor plates into directly measurable voltage changes, providing a pulse generation method different from the traditional one, and compared with the pulse generation method of the traditional photoelectric encoder, no matter whether the encoding disk 4 rotates at high speed or low speed, since the medium change between the two parallel capacitor plates is specific (that is, whether the medium between the two parallel capacitor plates contains a dielectric layer), the generated pulse signal can be effectively avoided from jittering, which is beneficial to improve the accuracy of the angle measurement result. In addition, compared with the traditional pulse generation method based on photoelectric coupling, the pulse generation method based on medium change in the embodiment of the present invention is less susceptible to the influence of the external environment and has better anti-interference ability.

[0063] Further, refer to Figures 1 to 4 In an exemplary embodiment, the phase-locked loop circuit 2 includes a frequency divider 21, a frequency detector 22, a low-pass filter 23, a comparator 24 and a voltage-controlled oscillator 25;

[0064] The frequency divider 21 is electrically connected to the output end of the signal collector 3 and is used to divide the frequency of the feedback signal output by the signal collector 3 to obtain a divided frequency signal;

[0065] The frequency and phase detector 22 is electrically connected to the frequency divider 21 and the reference clock circuit 1, respectively, and is used to compare the frequency and phase difference between the reference clock signal and the frequency-divided signal, and output a voltage pulse signal;

[0066] The low-pass filter 23 is electrically connected to the frequency detector 22, and is used to filter out the high-frequency components in the pulse voltage signal and output an analog voltage signal;

[0067] The comparator 24 is electrically connected to the low-pass filter 23 and is used to convert the analog voltage signal into a pulse signal;

[0068] The voltage-controlled oscillator 25 is electrically connected to the input end of the comparator 24 and the input end of the signal collector 3, respectively, and is used to output a frequency signal of a corresponding frequency according to the analog voltage signal; wherein, when the pulse signal is a high-level signal, the frequency of the frequency signal output by the voltage-controlled oscillator 25 increases; when the pulse signal is a low-level signal, the frequency of the frequency signal output by the voltage-controlled oscillator 25 decreases.

[0069] In the present embodiment, based on the above structural design, the phase-locked loop circuit 2 can generate a pulse signal for calculating the angle and a frequency signal that ensures that the pulse signal can be continuously and stably generated. Specifically, during the rotation of the encoder disk 4, when the medium between the two parallel capacitor plates is "air", the output end of the comparator 24 can output a low-level signal with a fixed voltage (such as a low-level signal with a voltage of zero or close to zero), and the output end of the voltage-controlled oscillator 25 can output a frequency signal with a low frequency and a low level; when the medium between the two parallel capacitor plates is "dielectric layer + air", the output end of the comparator 24 can output a high-level signal with a fixed voltage, and the output end of the voltage-controlled oscillator 25 can output a frequency signal with a fixed frequency (the frequency can be set by adjusting the circuit parameters of the frequency detector, and the frequency is higher when the pulse signal is at a low level) and a high level. It should be noted here that the specific circuit structures and principles of the above-mentioned frequency divider 21, frequency detector 22 and voltage-controlled oscillator 25 are well known to those skilled in the art and will not be repeated here. Among them, in the specific implementation, such as Figure 4 As shown, the low-pass filter 23 of this embodiment includes a fourth resistor R4 and a second capacitor C2. The fourth resistor R4 is connected in series between the output end of the phase frequency detector 22 and the input end of the voltage controlled oscillator 25. One end of the second capacitor C2 is grounded, and the other end of the second capacitor C2 is connected to one end of the fourth resistor R4 adjacent to the voltage controlled oscillator 25. With such an arrangement, the low-pass filter 23 can filter out the high-frequency components in the pulse voltage signal output by the phase frequency detector 22, thereby improving the signal quality.

[0070] Further, refer to Figure 2 and Figure 5In an exemplary embodiment, the pulse generating device further includes a single chip microcomputer 5; the single chip microcomputer 5 is electrically connected to the output end of the phase-locked loop circuit 2, and is used to generate angle information according to the pulse signal.

[0071] In this embodiment, in the specific implementation, the model of the single-chip microcomputer 5 can be selected as STM32F405RGT6, and of course it can also be other models of single-chip microcomputer 5, as long as it can meet the use requirements, and this embodiment does not make specific restrictions on this. It should be noted here that the calculation algorithm of the single-chip microcomputer 5 to generate angle information according to the pulse signal is an existing algorithm well known in the art, and will not be repeated here.

[0072] Further, refer to Figure 2 and Figure 5 , in another exemplary embodiment, the phase-locked loop circuit 2 includes a phase-locked loop chip 20, a low-pass filter 23, a comparator 24 and a voltage-controlled oscillator 25;

[0073] The phase-locked loop chip 20 is electrically connected to the output end of the signal collector 3 and the output end of the reference clock circuit 1, respectively, and is used to compare the frequency and phase difference between the reference clock signal and the feedback signal, and output a current pulse signal;

[0074] A low-pass filter 23 is electrically connected to the phase-locked loop chip 20 and is used to convert the current pulse signal into an analog voltage signal and filter out high-frequency components in the analog voltage signal;

[0075] The comparator 24 is electrically connected to the low-pass filter 23 and is used to convert the analog voltage signal into a pulse signal;

[0076] The voltage controlled oscillator 25 is electrically connected to the input end of the comparator 24 and the input end of the signal collector 3, respectively, and is used to output a frequency signal of a corresponding frequency according to the analog voltage signal;

[0077] The single chip microcomputer 5 is electrically connected to the control input terminal of the phase-locked loop chip 20 and the output terminal of the comparator 24 , and is also used to set the operating frequency of the phase-locked loop chip 20 .

[0078] In this embodiment, based on the above structural design, not only can the phase-locked loop circuit 2 generate a pulse signal for calculating the angle and a frequency signal that ensures that the pulse signal can be continuously and stably generated, but also by electrically connecting the single-chip microcomputer 5 to the control input terminal of the phase-locked loop chip 20, it is convenient for the user to set the relevant parameters of the phase-locked loop chip 20 through the single-chip microcomputer 5, thereby improving the flexibility of use. For example, the operating frequency of the phase-locked loop chip 20 can be set through the single-chip microcomputer 5, so that when the pulse signal output by the comparator 24 is a high-level signal, the frequency of the frequency signal output by the voltage-controlled oscillator 25 is consistent with the set frequency. In the specific implementation, the model of the above-mentioned phase-locked loop chip 20 can be selected as FS8170, and of course it can also be other models of phase-locked loop chips 20, as long as it can meet the use requirements, and this embodiment does not make specific restrictions on this.

[0079] Further, in an exemplary embodiment, when the pulse signal output from the second output terminal of the phase-locked loop circuit 2 is a high-level signal, the frequency of the frequency signal output from the first output terminal of the phase-locked loop circuit is greater than or equal to 900MHZ (specifically, when the pulse signal output from the comparator 24 is a high-level signal, the frequency of the frequency signal output from the voltage-controlled oscillator 25 is greater than or equal to 900MHZ). In this way, the stability of the frequency signal when passing through two parallel capacitor plates can be improved, which is beneficial to further improve the stability of the pulse signal generation.

[0080] Further, refer to Figure 5 and Figure 6 In an exemplary embodiment, the low-pass filter 23 includes a first capacitor C1, a first resistor R1 and a polar capacitor E1. The positive electrode of the polar capacitor E1 is grounded after passing through the first resistor R1 and the first capacitor C1 in sequence, and the negative electrode of the polar capacitor E1 is grounded; the connection point between the first capacitor C1 and the first resistor R1 is electrically connected to the output end of the phase-locked loop chip 20 and the input end of the voltage-controlled oscillator 25 respectively.

[0081] In this embodiment, based on the above structural design, the low-pass filter 23 can convert the current pulse signal output by the phase-locked loop chip 20 into an analog voltage signal, and can filter out the high-frequency components in the analog voltage signal. It should be noted here that according to the specific circuit structure of the low-pass filter 23 disclosed in this embodiment, those skilled in the art can know the specific working principle of the low-pass filter 23, so it will not be repeated here.

[0082] Further, refer to Figure 3 , Figure 5 and Figure 6In an exemplary embodiment, the voltage-controlled oscillator 25 includes a separate RC element, an oscillator tube T1, a second resistor R2, a varactor diode VD1 and a third resistor R3. The base and collector of the oscillator tube T1 are electrically connected to the input end of the comparator 24 after passing through the separate RC element, and the emitter of the oscillator tube T1 is electrically connected to one end of the third resistor R3 after passing through the second resistor R2, the varactor diode VD1 and the separate RC element in sequence. The other end of the third resistor R3 is electrically connected to the input end of the signal collector.

[0083] In the present embodiment, based on the above structural design, the voltage-controlled oscillator 25 can output a frequency signal of a corresponding frequency under the control of an analog voltage signal, which is specifically manifested as follows: when the medium between the two parallel capacitor plates is "air", a relatively small fixed voltage value will be generated on the varactor diode VD1, and at this time, the signal output by the voltage-controlled oscillator 25 is a frequency signal with a relatively low frequency and a low level; when the medium between the two parallel capacitor plates is "dielectric layer + air", a relatively large fixed voltage value will be generated on the varactor diode VD1, and at this time, the signal output by the voltage-controlled oscillator 25 is a frequency signal with a fixed frequency and a high level. In the present embodiment, it should be noted that according to the specific circuit structure of the voltage-controlled oscillator 25 disclosed in the present embodiment, those skilled in the art can know the specific working principle of the voltage-controlled oscillator 25, so it will not be repeated here. It should also be noted here that the above-mentioned separation resistor-capacitor element is mainly a primary or multi-stage RC filter circuit structure composed of at least one capacitor and at least one resistor, which can be understood by those skilled in the art and will not be repeated here.

[0084] Further, refer to Figure 4 or Figure 6 In an exemplary embodiment, the comparator includes an operational amplifier U1, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, wherein the non-inverting input terminal of the operational amplifier U1 and the input terminal of the voltage-controlled oscillator 25 are electrically connected to the output terminal of the low-pass filter 23 after passing through the fifth resistor R5, the inverting input terminal of the operational amplifier U1 is electrically connected to the power supply terminal VCC after passing through the sixth resistor R6 and is grounded after passing through the seventh resistor R7, the positive power supply terminal of the operational amplifier U1 is electrically connected to the power supply terminal VCC, the negative power supply terminal of the operational amplifier U1 is grounded, and the output terminal of the operational amplifier U1 is used to output a pulse signal.

[0085] In this embodiment, based on the above structural design, the comparator 24 can convert the high and low level analog voltage signals output by the low pass filter 23 into high and low level pulse signals for the single chip microcomputer 5 to perform angle calculation. In this embodiment, it should be noted that according to the specific circuit structure of the comparator 24 disclosed in this embodiment, those skilled in the art can know the specific working principle of the comparator 24, so it will not be repeated here.

[0086] Further, refer to Figure 1 In an exemplary embodiment, the pulse generating device further includes a mounting plate 6, the signal collector 3 is in a "concave" shape, the mounting plate 6 is arranged parallel to the encoding disk 4, the signal collector 3 is fixed on a side surface of the mounting plate 6 facing the encoding disk 4, and the barrier strip 41 or the encoding hole 42 is located in the opening of the signal collector 3.

[0087] In this embodiment, based on the above structural design, the signal collector 3 can be easily installed and used.

[0088] Correspondingly, an embodiment of the present invention also provides an encoder, which includes a shell, a rotating shaft, a communication interface, a circuit board installed in the shell, and the aforementioned pulse generating device. The rotating shaft can be rotatably inserted into the shell (specifically, the rotating shaft can be rotatably installed in the shell by means of bearings, etc.), the encoding disk 4 is located in the shell and sleeved on the rotating shaft, the reference clock circuit 1 and the phase-locked loop circuit 2 are both installed on the circuit board, the signal collector 3 is installed in the shell (specifically, the signal collector 3 can be installed in the shell through the above-mentioned mounting plate 6), the communication interface is installed on the shell and electrically connected to the circuit board (specifically, in some embodiments, the signal output by the communication interface may be a pulse signal, and in other embodiments, the signal output by the communication interface may be angle information).

[0089] In this embodiment, the encoder can be installed on the shaft of a device that needs to measure angle or speed through a connector when in use. Thanks to the improvement of the above-mentioned pulse generating device, the encoder of this embodiment has the same technical effect as the above-mentioned pulse generating device, which will not be described in detail here.

[0090] Correspondingly, an embodiment of the present invention also provides a laser radar, which includes the aforementioned pulse generating device, the axis of the center of the encoding disk 4 coincides with the axis of the laser radar, the pulse generating device is arranged at the bottom of the laser radar and rotates with the rotor of the laser radar to detect the rotation angle of the laser radar (specifically, the rotation angle of the laser radar can be detected by the above-mentioned single-chip microcomputer 5).

[0091] In this embodiment, thanks to the improvement of the above-mentioned pulse generating device, the laser radar of this embodiment has the same technical effect as the above-mentioned pulse generating device, which will not be described in detail here. It should be noted here that other structural components of the laser radar of this embodiment can be referred to the prior art, which will not be described in detail here.

[0092] It should be noted that other contents of the pulse generating device, encoder and laser radar disclosed in the present invention can be found in the prior art and will not be described in detail here.

[0093] In addition, it should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0094] In addition, it should be noted that the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0095] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A pulse generating device, characterized in that: It includes a reference clock circuit, a phase-locked loop circuit, a signal collector and a rotatable encoding disk; The edge of the encoding disk is provided with barrier strips evenly distributed in the circumferential direction, there is a gap between two adjacent barrier strips to form a coding hole, and the outer surface of the barrier strip is covered with a dielectric layer; The signal collector comprises a first capacitor plate and a second capacitor plate which are arranged in parallel and opposite to each other, the encoding disk and the first capacitor plate are arranged in parallel with each other, and the blocking strip or the encoding hole is located between the first capacitor plate and the second capacitor plate; wherein, during the rotation of the encoding disk, when any of the encoding holes is located between the first capacitor plate and the second capacitor plate, the signal collector outputs a first feedback signal to the phase-locked loop circuit; when any of the blocking strips is located between the first capacitor plate and the second capacitor plate, the signal collector outputs a second feedback signal to the phase-locked loop circuit, and the signal strength of the first feedback signal is less than the signal strength of the second feedback signal; The reference clock circuit is electrically connected to the first input terminal of the phase-locked loop circuit and is used to provide a reference clock signal for the phase-locked loop circuit; The first output end of the phase-locked loop circuit is electrically connected to the second input end of the phase-locked loop circuit after passing through the signal collector; the phase-locked loop circuit is used to generate a corresponding pulse signal and a frequency signal according to the reference clock signal and the feedback signal output by the signal collector; wherein the first output end of the phase-locked loop circuit is used to output the frequency signal, the second output end of the phase-locked loop circuit is used to output the pulse signal, and when the feedback signal is the first feedback signal, the pulse signal output by the second output end of the phase-locked loop circuit is a low-level signal; when the feedback signal is the second feedback signal, the pulse signal output by the second output end of the phase-locked loop circuit is a high-level signal; Wherein, the phase-locked loop circuit includes a phase-locked loop chip, a low-pass filter, a comparator and a voltage-controlled oscillator; The phase-locked loop chip is electrically connected to the output end of the signal collector and the output end of the reference clock circuit, respectively, and is used to compare the frequency and phase difference between the reference clock signal and the feedback signal, and output a current pulse signal; The low-pass filter is electrically connected to the phase-locked loop chip, and is used to convert the current pulse signal into an analog voltage signal and filter out high-frequency components in the analog voltage signal; The comparator is electrically connected to the low-pass filter and is used to convert the analog voltage signal into the pulse signal; The voltage-controlled oscillator is electrically connected to the comparator and the signal collector, respectively, and is used to output the frequency signal of the corresponding frequency according to the analog voltage signal; The pulse generating device further comprises a single chip microcomputer; the single chip microcomputer is electrically connected to the second output terminal of the phase-locked loop circuit; specifically, the single chip microcomputer is electrically connected to the control input terminal of the phase-locked loop chip and the output terminal of the comparator respectively.

2. The pulse generating device according to claim 1, characterized in that: The low-pass filter includes a first capacitor, a first resistor and a polar capacitor. The positive electrode of the polar capacitor is grounded after passing through the first resistor and the first capacitor in sequence, and the negative electrode of the polar capacitor is grounded. The connection point between the first capacitor and the first resistor is electrically connected to the output end of the phase-locked loop chip and the input end of the voltage-controlled oscillator respectively.

3. The pulse generating device according to claim 1, characterized in that: The voltage-controlled oscillator includes a separate RC element, an oscillator tube, a second resistor, a varactor diode and a third resistor. The base and collector of the oscillator tube are electrically connected to the input end of the comparator after passing through the separate RC element respectively, the emitter of the oscillator tube is electrically connected to one end of the third resistor after passing through the second resistor, the varactor diode and the separate RC element in sequence, and the other end of the third resistor is electrically connected to the input end of the signal collector.

4. The pulse generating device according to claim 1, characterized in that: The comparator includes an operational amplifier, a fifth resistor, a sixth resistor and a seventh resistor, wherein the in-phase input terminal of the operational amplifier and the input terminal of the voltage-controlled oscillator are both electrically connected to the output terminal of the low-pass filter after passing through the fifth resistor, the inverting input terminal of the operational amplifier is electrically connected to the power supply terminal VCC after passing through the sixth resistor and is grounded after passing through the seventh resistor, the positive power supply terminal of the operational amplifier is electrically connected to the power supply terminal VCC, the negative power supply terminal of the operational amplifier is grounded, and the output terminal of the operational amplifier is used to output the pulse signal.

5. The pulse generating device according to any one of claims 1 to 4, characterized in that: The reference clock circuit is a crystal oscillator; and / or, the material of the dielectric layer includes aluminum oxide; and / or, when the pulse signal is a high-level signal, the frequency of the frequency signal output by the first output end of the phase-locked loop circuit is greater than or equal to 900 MHZ.

6. The pulse generating device according to claim 1, characterized in that: The pulse generating device also includes a mounting plate, the signal collector is in a "concave" shape, the mounting plate is arranged parallel to the encoding disk, the signal collector is fixed on a side surface of the mounting plate facing the encoding disk, and the barrier strip or the encoding hole is located in the opening of the signal collector.

7. An encoder, characterized in that It comprises a shell, a rotating shaft, a communication interface, a circuit board installed in the shell, and a pulse generating device as described in any one of claims 1 to 6, wherein the rotating shaft is rotatably inserted into the shell, the encoding disk is located in the shell and sleeved on the rotating shaft, the reference clock circuit and the phase-locked loop circuit are both installed on the circuit board, the signal collector is installed in the shell, and the communication interface is installed on the shell and electrically connected to the circuit board.

8. A laser radar, characterized in that: It includes the pulse generating device as described in claim 1, the axis of the center of the encoding disk coincides with the axis of the laser radar, and the pulse generating device is arranged at the bottom of the laser radar and rotates with the rotor of the laser radar to detect the rotation angle of the laser radar.

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