Processing Accelerator Architecture

Abstract

A processing accelerator can include multiple networks, multiple cores, a crossbar interconnect structure, multiple memory controllers, and scratch pad memories on an integrated circuit (IC) chip. The multiple cores can be coupled together via multiple on-chip networks. The crossbar interconnect structure can couple the network of cores to the multiple memory controllers. The multiple memory controllers can be configured to access data stored in off-chip memory. The scratch pad memories can be configured to cache portions of the accessed data. The scratch pad memories can be directly accessed by the network of processing cores or can be distributed within the multiple memory controllers. The memory controllers can be narrow channel (NC) memory controllers having a width of 4, 8, 12, 16 bits, or multiples of 4 bits.

Description

Background Art

[0001] Graph databases are utilized in many applications ranging from online shopping engines, social networking, recommendation engines, mapping engines, fault analysis, network management, search engines, etc. Graph databases can be used to determine dependencies, clustering, similarities, matching, categories, flows, costs, centralities, etc. in large data sets.

[0002] Graph databases use graph structures with nodes, edges, and attributes to represent and store data for semantic queries. Graphs connect data items to sets of nodes, edges, and attributes. Nodes, which can also be called vertices, can represent entities, instances, and the like. Edges can represent relationships between nodes and allow data to be linked directly together. Attributes can be information closely related to nodes or edges. Graph databases allow simple and fast retrieval of complex hierarchical structures that are difficult to model in relational systems. A large number of processing operations include graph traversal operations, such as pointer tracking, in which a node 105 is read to determine an edge 110 pointing to one or more other nodes 120. One or more other nodes 120 can be read to determine other edges 125, 130 pointing to other nodes 135, 140, etc., as illustrated in FIG1. ​​Graph traversal operations and other similar calculations can be characterized by random patterns of access to edges and nodes. In addition, data access associated with graph traversal operations and other similar calculations can typically be less than the standard minimum cache line access of 64 bytes. Data access in graph processing can also be characterized by intensive use of data associated with clustering of nodes and edges.

[0003] Graph processing usually causes large processing utilization and large memory access bandwidth utilization. Therefore, there is a need for an improved graph processing platform that can reduce latency associated with large processing utilization, improve memory bandwidth utilization, etc. Summary of the invention

[0004] The present technology may be best understood by referring to the following description and accompanying drawings, which are used to illustrate embodiments of the present technology directed to an accelerator for graph processing and other similar applications.

[0005] In one embodiment, a processing accelerator can include a network consisting of multiple cores, a scratch pad memory, a crossbar interconnect structure, and multiple memory controllers. The network consisting of multiple processor cores, the scratch pad memory, the crossbar interconnect structure, and the multiple memory controllers can include an integrated circuit (IC) chip. The scratch pad memory can be configured to cache data. In one implementation, the scratch pad memory can be directly accessed by multiple cores. In another implementation, the scratch pad memory can be distributed in multiple memory controllers. The crossbar interconnect structure can be configured to couple the network consisting of multiple processor cores to multiple memory controllers. Multiple memory controllers can be configured to access off-chip data through multiple memory channel interfaces.

[0006] In another embodiment, a processing accelerator can include multiple networks, multiple processor cores, multiple narrow channel (NC) memory controllers, scratch pad memories, and a crossbar interconnect structure. The multiple cores can be coupled together through the multiple networks. The crossbar interconnect structure can be configured to couple the multiple networks to the multiple narrow channel (NC) memory controllers. The multiple narrow channel (NC) memory controllers can be configured to access data stored in off-chip memory. The scratch pad memories can be coupled to the multiple memory controllers. The scratch pad memories can be configured to cache portions of data.

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present technology are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:

[0009] FIG. 1 illustrates an exemplary graph database according to conventional techniques.

[0010] Figure 2 A computing system in accordance with aspects of the present technique is shown.

[0011] Figure 3 A processing accelerator architecture in accordance with aspects of the present technique is shown.

[0012] Figure 4 A processing accelerator architecture in accordance with aspects of the present technique is shown.

[0013] Figure 5 A processing accelerator architecture in accordance with aspects of the present technique is shown.

[0014] Figure 6A narrow channel (NC) memory controller in accordance with aspects of the present technique is shown. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to embodiments of the present technology, examples of which are illustrated in the accompanying drawings. Although the present technology will be described in conjunction with these embodiments, it should be understood that they are not intended to limit the present technology to these embodiments. On the contrary, the present invention is intended to cover alternatives, modifications and equivalents that may be included within the scope of the present invention as defined by the appended claims. In addition, in the following detailed description of the present technology, many specific details are set forth in order to provide a thorough understanding of the present technology. However, it should be understood that the present technology can be practiced without these specific details. In other cases, known methods, processes, components and circuits have not yet been described in detail to avoid unnecessary confusion of various aspects of the present technology.

[0016] Some embodiments of the present technology below are presented in terms of routines, modules, logic blocks, and other symbolic representations of operations performed on data within one or more electronic devices. Description and representation are the means used by those skilled in the art to most effectively convey the essence of their work to those skilled in the art. Routine, module, logic block, and / or the like are herein and generally conceived as a self-consistent sequence of processes or instructions that lead to desired results. A process is a process that includes physical manipulation of physical quantities. Typically, although not necessarily, these physical manipulations take the form of electrical or magnetic signals that can be stored, transferred, compared, and otherwise manipulated in an electronic device. For convenience, and with reference to common usage, these signals are referred to as data, bits, values, elements, symbols, characters, terms, numbers, strings, and / or the like with reference to the embodiments of the present technology.

[0017] However, it should be kept in mind that these terms are to be interpreted as referring to physical manipulations and quantities and are merely convenient labels and will be further interpreted in light of terminology commonly used in the art. Unless specifically stated otherwise as apparent from the following discussion, it should be understood that throughout the discussion of the present technology, discussions utilizing terms such as "receiving" and / or the like refer to actions and processes of electronic devices such as electronic computing devices that manipulate and transform data. Data is represented as physical (e.g., electronic) quantities within the logic circuits, registers, memories, and / or the like of the electronic device and is transformed into other data similarly represented as physical quantities within the electronic device.

[0018] In the present application, the use of disjunctive words is intended to include conjunctions. The use of definite or indefinite articles is not intended to indicate cardinality. In particular, the reference to "the" object or "one" object is intended to also represent one of a plurality of possible such objects. The use of the terms "include", "include", "include", "include", etc. specifies the elements of the existence statement, but does not exclude the existence or addition of one or more other elements and / or its groups. It should also be understood that the result terms first, second, etc. can be used to describe various elements in this article, but such elements should not be limited by these terms. These terms are used to distinguish one element from another element in this article. For example, without departing from the scope of the embodiment, the first element can be referred to as the second element, and similarly the second element can be referred to as the first element. It should also be understood that when an element is referred to as "coupled" to another element, it can be directly or indirectly connected to another element, or there can be an intermediate element. In contrast, when an element is referred to as "directly connected" to another element, there is no intermediate element. It should also be understood that the term "and or" includes any and all combinations of one or more of the related elements. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0019] refer to Figure 2 , shows a computing system in accordance with aspects of the present technology. Computing system 200 can include, but is not limited to, one or more host processors 210, one or more processing accelerators 220, host memory 230, and accelerator memory 240. One or more processing accelerators 220 can be communicatively coupled to one or more host processors 210 via one or more communication interfaces 250 such as, but not limited to, one or more peripheral component interface express (PCIe) interfaces or one or more compute express link (CXL) interfaces.

[0020] The host memory 230 may be an off-chip memory such as a dynamic random access memory (DRAM) that is communicatively coupled to one or more host processors 210 via one or more memory channel communication interfaces 260. In one implementation, the host memory 230 can be characterized by a channel width of 64 bits. The accelerator memory 240 may be an off-chip memory such as a dynamic random access memory (DRAM) that is communicatively coupled to one or more processing accelerators 220 via a plurality of narrow memory (NC) channel communication interfaces 270. The accelerator memory 240 can be characterized by a narrower channel width and a smaller access granularity than the host memory 230. In one implementation, the accelerator memory 240 can be characterized by a channel width of 4, 8, 12, 16 bits, or a multiple of 4 bits.

[0021] One or more host processors 210 can be configured to manage the overall execution of system 200. One or more processing accelerators 220 can be configured to perform graph processing and or other similar functions.

[0022] Reference now Figure 3 , showing a processing accelerator architecture in accordance with aspects of the present technology. Processing accelerator 300 can include, but is not limited to, a network of cores 310, a scratch pad 320, a crossbar interconnect structure 330, and a memory controller 340. In one implementation, processing accelerator 300 can be fabricated as an integrated circuit (IC) chip. In one implementation, network of cores 310 can include hundreds, thousands, or even more cores 350, such as reduced instruction set computing (RISC-V) cores, advanced RISC machine (ARM) cores, and the like. Multiple cores 350 can be communicatively coupled together through one or more networks on chip (NoCs), and can include topologies such as, but not limited to, mesh, circuit, octagon, tree, ring, star, and combinations thereof.

[0023] The scratch pad 320 can be coupled to the network of cores 310. Graph processing can be characterized by a small amount of data that is used intensively, so the scratch pad 320 can be close to a cache memory shared by multiple cores. In one implementation, the scratch pad 320 can be a static random access memory (SRAM). In one implementation, the scratch pad 320 can be managed in a computing device executable instruction (e.g., a software application) that is executed on one or more cores of the network of cores 310, on one or more host processors (not shown), etc. The scratch pad 320 can be configured to service a given memory request from the network of cores 310 from within the scratch pad 320, or pass a given memory request to the memory controller 340. For example, the scratch pad 320 can receive a memory read or write instruction from the network of cores 310. If the memory read or write instruction is a hit for data cached in one of the scratch pads 320, the data can be read from the given scratch pad 320 or written to the given scratch pad 320. In one implementation, scratch pad 320 can be shared by network 310 of cores, such that any of cores 350 can access any of scratch pad 320 .

[0024] The network of cores 310 can also be coupled to a memory controller 340 through a crossbar interconnect structure 330. The crossbar interconnect structure 330 can be a collection of switches arranged in a matrix configuration. The switches of the crossbar interconnect structure 330 can be coupled between the network of cores 310 and the memory controller 340 to form a crossbar pattern of interconnections. The crossbar interconnect structure 330 can be non-blocking to allow concurrent connections that do not block other inputs from connecting to other outputs. If a memory read or write instruction is a miss in the scratch pad 320, the memory read or write instruction can be passed to the applicable memory controller through the crossbar interconnect structure 330 to appropriately access the accelerator memory (not shown). In one implementation, a portion of the memory address of the memory read or write access can be utilized by the crossbar interconnect structure 330 to route the memory read or write access to the corresponding memory controller 340.

[0025] The memory controller 340 can be configurable to be coupled to one or more off-chip accelerator memories (not shown) through one or more memory channels (not shown). In one implementation, the external memory can be a dynamic random access memory (DRAM). The memory channels of the memory controller 340 can be characterized by a relatively narrow channel (NC) width of about 4, 8, 12, 16 bits, or a multiple of 4 bits. In one implementation, the narrow channel (NC) can be implemented by multiple portions of a standard memory channel. In another implementation, the narrow channel (NC) can be implemented by reducing the burst length of the memory access.

[0026] Reference now Figure 4 , another processing accelerator architecture in accordance with aspects of the present technology is shown. Processing accelerator 400 can include, but is not limited to, a network of cores 410, a crossbar interconnect structure 420, and a memory controller 430. In one implementation, processing accelerator 400 can be fabricated as an integrated circuit (IC) chip. In one implementation, network of cores 410 can include hundreds, thousands, or even more cores 440, such as reduced instruction set computing (RISC-V) cores, advanced RISC machine (ARM) cores, and the like. Multiple cores 440 can be communicatively coupled together through one or more networks of connection (NoCs), and can include topologies such as, but not limited to, mesh, circuit, octagon, tree, ring, star, and combinations thereof.

[0027] The network of cores 410 can be coupled to a memory controller 430 through a crossbar interconnect structure 420. The crossbar interconnect structure 420 can be a collection of switches arranged in a matrix configuration. The switches of the crossbar interconnect structure 420 can be coupled between the network of cores 410 and the memory controller 430 to form a crossbar pattern of interconnections. The crossbar interconnect structure 420 can be non-blocking to allow concurrent connections that do not block other inputs from connecting to other outputs. In one implementation, a portion of a memory address of a memory read or write access can be utilized by the crossbar interconnect structure 420 to route the memory read or write access to the corresponding memory controller 430.

[0028] The memory controller 430 can be configurable to be coupled to one or more off-chip accelerator memories (not shown) through one or more memory channels (not shown). The memory channels of the memory controller can be characterized by a relatively narrow channel (NC) width of about 4, 8, 12, 16 bits, or a multiple of 4 bits. Therefore, the memory controller 430 can be configurable to implement a customizable memory channel. A given memory controller can be configured for a relatively small memory access granularity of about 64 bytes. The memory controller 430 can also include a scratch pad memory 450. In one implementation, the scratch pad memory 450 can be distributed within the memory controller 430 so that portions of the scratch pad memory 450 are incorporated into the corresponding memory controller 430.

[0029] The memory controller 430 can be configured to receive corresponding memory read and write access requests routed through the vertical and horizontal interconnect structure 420 from the network 410 composed of cores. The memory controller 430 can check to see whether the data of the read or write access request resides in the corresponding scratch pad memory 450 (e.g., scratch pad hit). In one implementation, the scratch pad memory 450 can be a static random access memory (SRAM) or the like. If the corresponding data is not in the corresponding scratch pad memory 450 (e.g., scratch pad miss), the corresponding memory controller 430 can access an external memory (e.g., an off-chip accelerator memory). In one implementation, the external memory can be a dynamic random access memory (DRAM).

[0030] Reference now Figure 5, shows a system including a processing accelerator architecture in accordance with aspects of the present technology. System 500 can include, but is not limited to, one or more host processors (not shown), host memory (not shown), one or more processing accelerators 510, and accelerator memory 515. Processing accelerator 510 can include, but is not limited to, multiple cores 520, one or more networks 525-540, a crossbar interconnect structure 545, multiple memory controllers 550, and one or more scratch pad memories 555. In one implementation, processing accelerator 510 can be fabricated as an integrated circuit (IC) chip.

[0031] One or more networks 525-540 can be configured to communicatively couple the plurality of cores 520 together. The crossbar interconnect structure 545 can be configured to communicatively couple the one or more networks 525-540 of the cores 520 to the plurality of memory controllers 550 and the one or more scratch pad memories 555. In one implementation, the one or more networks 525-540 can include one or more network communication channels 525 and one or more communication channel interfaces 530 arranged in one or more topologies such as, but not limited to, mesh, circuit, octagon, tree, ring, star, and combinations thereof. In one implementation, the one or more networks 525-540 can include a plurality of ring topology communication channels 525 configured to communicatively couple the respective core groups 520 to the crossbar interconnect structure 545, a plurality of ring channel interfaces 530, respective ring controllers 535, and respective ring buffers 540.

[0032] In one implementation, the plurality of cores 530 can include hundreds, thousands, or even more simple cores, such as reduced instruction set computing (RISC-V) cores, advanced RISC machine (ARM) cores, and the like. In one implementation, the plurality of cores 520 can be organized in core groups, and the core groups can be organized in sets. Each group of cores can be coupled to a corresponding communication channel interface. For example, the processing accelerator 510 can include twelve ring networks 525-540, each of which can include ten core groups, each of which can include eight cores coupled to a corresponding ring channel interface 530.

[0033] The crossbar interconnect structure 545 can be configured to communicatively couple the networks 525-540 composed of the cores 520 and the plurality of memory controllers 550 together. In one implementation, the crossbar interconnect structure 545 can be configured to couple the cores 520 in a given network of the plurality of networks 525-540 to the cores 520 in other networks of the plurality of networks 525-540. The crossbar interconnect structure 545 can also be configured to couple the cores 520 in the plurality of networks 525-540 to the plurality of memory controllers 550. The crossbar interconnect structure 545 can be a collection of switches arranged in a matrix configuration. The switches of the crossbar interconnect structure 545 can be coupled between the networks 525-540 of the cores 520 and the memory controllers 550 to form a cross pattern of interconnects that can establish connections therebetween. The crossbar interconnect structure 545 can be non-blocking to allow concurrent connections that do not prevent other inputs from being connected to other outputs.

[0034] Processing accelerator 510 can also include other subcircuits, such as one or more input / output interfaces 560, etc. For example, one or more input / output interfaces 560 can include one or more peripheral component interface express (PCIe) interfaces, one or more compute express link (CXL) interfaces, etc. for communicatively coupling processing accelerator 510 to one or more host processors (not shown). One or more input / output interfaces 560 can also couple processing accelerator 510 to one or more additional processing accelerators.

[0035] The crossbar interconnect structure 545 can communicatively couple the one or more input / output interfaces 560 to the one or more networks 525-540 formed by the cores 520. In one implementation, software executing on one or more host processors (not shown) can send instructions across the one or more input / output interfaces 560 to control the allocation of graph processing functions to the multiple cores 520. For example, the graph processing software can control the allocation of graph processing functions to the multiple cores 520. In another example, the operating system, alone or in conjunction with the graph processing software, can control the allocation of graph processing functions to the multiple cores 520.

[0036] Multiple memory controllers 550 can be coupled to off-chip accelerator memory 515 through one or more corresponding memory channels 570, 575. As used herein, the term off-chip is used to indicate that the accelerator memory is not fabricated on the integrated circuit (IC) chip of the processing accelerator 510. Multiple memory controllers 550 can also be coupled to corresponding scratch pad memories 555. In one implementation, the scratch pad memories 555 can be static random access memories (SRAMs) or the like. In one implementation, the memory controllers 550 and the scratch pad memories 555 can be organized in multiple sets 565. Each set 565 can include a set of memory controllers 550 and corresponding scratch pad memories 555.

[0037] The memory channels of the memory controller 550 can be characterized by relatively narrow channel (NC) widths of about 4, 8, 12, 16 bits, or multiples of 4 bits. Thus, the memory channels can be customizable. A given memory controller can be configured for a relatively small memory access granularity of about 64 bytes. In one implementation, each memory controller 550 can be coupled to a set of accelerator memories 515 via a set of data lines 570 and shared address and control lines 575.

[0038] The memory controller 550 can be configured to receive corresponding memory read and write access requests routed through the crossbar interconnect structure 545 from the networks 525-540 of the core 520. The corresponding memory controller 550 can check to see if the data of the read or write access request resides in the corresponding scratch pad memory 555 (e.g., a scratch pad hit). If the corresponding data is not in the corresponding scratch pad memory 555 (e.g., a scratch pad miss), the corresponding memory controller 550 can access the corresponding off-chip accelerator memory 515.

[0039] A processing accelerator comprising a network of cores can advantageously provide a high degree of versatility and programmability. A relatively simple core advantageously enables a processing accelerator to include a very large number of cores. A processing accelerator comprising a network of cores and a narrow channel (NC) memory controller also advantageously enables dense access to random access memory. Dense random access to memory is advantageous for large threads such as point tracking. A network of cores and a narrow channel (NC) memory controller can also advantageously reduce processing latency and memory access latency.

[0040] Reference now Figure 6, a narrow channel (NC) memory controller in accordance with aspects of the present technology is shown. The narrow channel (NC) memory controller 600 can include a memory management unit 605, a memory request demultiplexer 610, a request queue 615, a data buffer 620, a command demultiplexer 625, a plurality of finite state machines 630, a command multiplexer 635, a signal generator 640, a data demultiplexer 645, a plurality of data modules 650, and an input / output module 655. The narrow channel (NC) memory controller 600 can be coupled to a plurality of narrow channel (NC) memories 660, 665. In one implementation, the narrow channel (NC) memories 660, 665 include a plurality of memory cards 660, each memory card including a plurality of memory chips 665. In one implementation, the memory card 660 can be a dynamic random access memory (DRAM) card (e.g., a printed circuit board). In one implementation, the memory chip can be a dynamic random access memory (DRAM) integrated circuit (IC) chip that meets the commodity memory chip standard such as but not limited to the Joint Electronic Device Engineering Council (JEDEC). In one implementation, the memory chip 665 can have a data pin for transferring the data of a specified number of bits. For example, the memory chip 665 can have a data pin for inputting and outputting 2, 4, 8, 16 or 4 multiples of data. In one implementation, the memory chip 665 can be organized into rows and columns to provide a predetermined number of bytes of data, such as 2 memory chips per row and column of each chip each having a data pin for accessing 4 bits, or 1 memory chip per row and column of each chip each having a data pin for accessing 8 bits. As used herein, the term narrow channel (NC) includes a predetermined fraction of a standard memory channel and a multiple (e.g., 1 times, 2 times ...) of the bit width of a component memory integrated circuit (IC) chip. In one implementation, the width of the narrow channel (NC) can be equal to the bit width of the rows and columns of a dynamic random access memory (DRAM), wherein the rows and columns are a collection of IC chips sharing the same chip select signal.

[0041] In one implementation, a narrow channel (NC) memory controller 600 can communicate with each channel in a closed page strategy. Each memory controller 600 can control two separate channels simultaneously using a dedicated data bus 670 for each separate channel and a shared common command bus 675. In one implementation, the memory controller can replace the standard write and read commands (WR / RD) with automatic precharge write and read commands (WRA / RDA). The automatic precharge write and read commands can be configured to save time slots on the command bus and thus provide balanced command bus and data bus utilization.

[0042] A narrow channel (NC) memory controller 600 with a relatively small access granularity can advantageously improve data utilization and increase data bus throughput for a given data bus bandwidth for poor data locality applications such as graph processing. A closed page policy can provide improved random access to data for use in applications such as graph processing. The narrow channel (NC) memory controller 600 can also advantageously work with readily available commodity memory such as dynamic random access memory (DRAM).

[0043] The foregoing descriptions of specific embodiments of the present technology have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present technology to the precise form disclosed, and obviously, many modifications and variations are possible in light of the above teachings. The embodiments are chosen and described in order to best illustrate the principles of the present technology and its practical application, thereby enabling others skilled in the art to best utilize the present technology and various embodiments with various modifications as are suitable for the particular use contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. A processing accelerator, the processing accelerator comprising: One or more networks, consisting of multiple processor cores; a scratch pad memory configured to cache data for use by the plurality of processor cores, the scratch pad memory being coupled to the one or more networks, or being distributed within a plurality of memory controllers, or being coupled to a plurality of the memory controllers, the memory controllers and the scratch pad memory being organized in a plurality of sets; a crossbar interconnect structure configured to couple one or more networks comprised of the plurality of processor cores to a plurality of memory controllers; as well as the plurality of memory controllers configured to access data through a plurality of memory channel interfaces; The multiple memory controllers include multiple narrow memory channel dynamic random access memory controllers, and the memory controllers are narrow channel NC memory controllers with a width of 4, 8, 12, 16 bits or other multiples of 4 bits.

2. The processing accelerator of claim 1, wherein the scratch pad memory is coupled to the one or more networks comprised of the plurality of processor cores.

3. The processing accelerator of claim 1, wherein the scratch pad memory is distributed among the plurality of memory controllers.

4. The processing accelerator of claim 1, wherein the scratch pad memory comprises static random access memory.

5. The processing accelerator of claim 1, wherein the plurality of memory controllers comprises a narrow channel NC memory interface.

6. The processing accelerator of claim 1, wherein the one or more networks formed by the plurality of processor cores include one or more mesh networks, one or more roving networks, one or more octagonal networks, one or more tree networks, one or more ring networks, and one or more star networks.

7. The processing accelerator of claim 1 , further comprising: one or more communication interfaces configured to couple one or more networks of the plurality of processor cores to a host processor, and The crossbar interconnect structure couples the one or more communication interfaces to one or more networks of the plurality of processor cores.

8. A processing accelerator, the processing accelerator comprising: Multiple networks; a plurality of processor cores, the plurality of processor cores being coupled together via the plurality of networks; a plurality of narrow channel NC memory controllers configured to access data stored in an off-chip memory, wherein the memory controllers are narrow channel NC memory controllers having a width of 4, 8, 12, 16 bits or other multiples of 4 bits; a scratch pad memory coupled to the plurality of narrow channel NC memory controllers, wherein the scratch pad memory is configured to cache a portion of the data, the scratch pad memory being coupled to one or more networks, or being distributed within a plurality of memory controllers, or being coupled to a plurality of memory controllers, the memory controllers and the scratch pad memory being organized in a plurality of sets; and A crossbar interconnect structure is configured to couple the plurality of networks to the plurality of narrow channel NC memory controllers.

9. The processing accelerator of claim 8, wherein the plurality of networks comprises: Multiple two-way communication channels; a plurality of communication channel interfaces configured to couple the plurality of processor cores to corresponding bidirectional communication channels and to couple the corresponding bidirectional communication channels to corresponding network controllers; as well as A network buffer is configured to couple the corresponding network controller to the crossbar interconnect structure.

10. The processing accelerator of claim 9, wherein the plurality of networks comprises a plurality of ring networks; The corresponding set of processor cores includes a group of processor cores coupled to a corresponding ring network among the plurality of ring networks.

11. The processing accelerator of claim 8, wherein the plurality of narrow channel NC memory controllers and the scratch pad memory are configured in a set of the plurality of narrow channel NC memory controllers and the scratch pad memory.

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