Structure of High Electron Mobility Transistor and Related Methods

Abstract

Structure of a high electron mobility transistor and method of forming the structure of a high electron mobility transistor. The high electron mobility transistor has a first semiconductor layer, a second semiconductor layer adjacent to the first semiconductor layer along an interface, a gate electrode, and source / drain regions. Insulating regions are provided in the first semiconductor layer and the second semiconductor layer. The insulating regions extend through the interface at positions that are laterally located between the gate electrode and the source / drain regions.

Description

Technical Field

[0001] The present invention generally relates to the fabrication of integrated circuits and semiconductor devices, and more particularly to the structure of high-electron-mobility transistors and methods of forming the structure of high-electron-mobility transistors. Background Art

[0002] High-voltage power electronic devices, such as high-electron-mobility transistors, can be fabricated using III-V compound semiconductors to take advantage of their material properties, such as carrier mobility greater than that of silicon. III-V compound semiconductors are formed by combining group III elements (aluminum, gallium, indium) with group V elements (nitrogen, phosphorus, arsenic, antimony). A high-electron-mobility transistor can include a heterojunction between III-V compound semiconductor materials having different bandgaps, such as a heterojunction between binary gallium nitride and trinary aluminum gallium nitride. During operation, a two-dimensional electron gas is formed near the interface at the heterojunction of the high-electron-mobility transistor. The two-dimensional electron gas defines the channel of the high-electron-mobility transistor.

[0003] Due to the high electron mobility of the two-dimensional electron gas, high-electron-mobility transistors (HEMTs) have high conductivity and low losses compared to other types of transistors. However, in power switching applications, the gate dielectric layer near the gate edge is prone to premature breakdown under high drain bias.

[0004] There is a need for improved structures of high-electron-mobility transistors and methods of forming the structures of high-electron-mobility transistors. Summary of the Invention

[0005] In one embodiment of the present invention, a structure includes a high-electron-mobility transistor having a first semiconductor layer, a second semiconductor layer adjacent to the first semiconductor layer along an interface, a gate electrode, and source / drain regions. The structure further includes insulating regions in the first semiconductor layer and the second semiconductor layer. The insulating regions extend through the interface transversely at a position between the gate electrode and the source / drain regions.

[0006] In one embodiment of the present invention, a method includes forming a high-electron-mobility transistor including a first semiconductor layer and a second semiconductor layer adjacent to the first semiconductor layer along an interface, forming insulating regions in the first semiconductor layer and the second semiconductor layer, forming a gate electrode of the high-electron-mobility transistor, and forming source / drain regions of the high-electron-mobility transistor. The insulating regions extend through the interface transversely at a position between the gate electrode and the source / drain regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings incorporated in and forming a part of this specification illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to the same features in various views.

[0008] Figure 1 FIG. is a top view of the structure of a high electron mobility transistor according to an embodiment of the present invention.

[0009] Figure 2 is along Figure 1 A cross-sectional view taken along line 2-2 in.

[0010] Figure 2A is along Figure 1 A cross-sectional view taken along line 2A-2A in.

[0011] Figure 3 is Figure 1 A top view of the structure in a later manufacturing stage.

[0012] Figure 4 is along Figure 3 A cross-sectional view taken along line 4-4 in.

[0013] Figure 4A is along Figure 3 A cross-sectional view taken along line 4A-4A in.

[0014] Figure 5 is Figure 3 A top view of the structure in a later manufacturing stage.

[0015] Figure 6 is along Figure 5 A cross-sectional view taken along line 6-6 in.

[0016] Figure 6A is along Figure 5 A cross-sectional view taken along line 6A-6A in.

[0017] Figure 7 FIG. is a cross-sectional view of the structure of a high electron mobility transistor according to an alternative embodiment of the present invention.

[0018] Figure 8 、 Figure 8A FIG. is a cross-sectional view of the structure of a high electron mobility transistor according to an alternative embodiment of the present invention.

[0019] Figure 9 、 Figure 9A FIG. is a cross-sectional view of the structure of a high electron mobility transistor according to an alternative embodiment of the present invention.

[0020] Description of Reference Numerals

[0021] 10 Structure

[0022] 12 Semiconductor substrate

[0023] 16 strips

[0024] 18 Semiconductor layer

[0025] 19 Interface

[0026] 20 Semiconductor layer

[0027] 22 Dielectric layer

[0028] 24 Grooves

[0029] 25 end

[0030] 26 Gate Window

[0031] 27 end

[0032] 28 Conformal dielectric layer

[0033] 29 Edge

[0034] 30 Gate electrode

[0035] 31 Edge

[0036] 32 Source / Drain Region

[0037] 34 Source / Drain Region

[0038] 36 Insulation Area

[0039] 38 Implantation Mask

[0040] 40 additional layers DETAILED DESCRIPTION

[0041] refer to Figure 1 , Figure 2 , Figure 2A According to an embodiment of the present invention, a structure 10 for a high electron mobility transistor is formed on a top surface of a semiconductor substrate 12. The semiconductor substrate 12 may be composed of a single crystalline semiconductor material (e.g., single crystalline silicon). The semiconductor substrate 12 may be a bulk substrate composed of a single crystalline semiconductor material (e.g., single crystalline silicon), and the bulk substrate may be lightly doped to have p-type conductivity.

[0042] The semiconductor layer 18, semiconductor layer 20, and dielectric layer 22 are formed in a layer stack on the semiconductor substrate 12. The semiconductor layers 18, 20 can be formed continuously using an epitaxial growth process (such as metalorganic chemical vapor deposition), and the semiconductor layers 18, 20 can each include a single-crystalline material. The semiconductor layer 18 can include a plurality of sub-layers customized according to the material and layer thickness to accommodate the lattice mismatch between the crystal structure of the semiconductor substrate 12 and the crystal structure of the portion of the semiconductor layer 18 adjacent to the semiconductor layer 20. The semiconductor layer 18 can be composed of a group III-V compound semiconductor material (such as gallium nitride). The semiconductor layer 20 can be composed of a group III-V compound semiconductor material (such as aluminum gallium nitride). The semiconductor layers 18, 20 are adjacent along an interface 19 that can define a heterojunction. During device operation, a two-dimensional electron gas filled with high-mobility electrons and electron-rich may be generated near the interface 19. The dielectric layer 22 can be composed of a dielectric material (such as silicon nitride, silicon dioxide, or aluminum oxide), and can be deposited by chemical vapor deposition.

[0043] The semiconductor layer 18, semiconductor layer 20, and dielectric layer 22 are patterned by one or more lithography and etching processes to define the trenches 24 and the gate windows 26 as depressions interconnecting adjacent trenches 24. Each trench 24 terminates at opposite ends 25, 27 along its length, and the gate windows 26 are spaced apart from the opposite ends 25, 27 of the trenches 24. Strips 16 of the materials of the semiconductor layer 18, semiconductor layer 20, and dielectric layer 22 are provided between adjacent trenches 24, and the gate windows 26 extend through the strips 16 to connect adjacent trenches 24. The trenches 24 completely penetrate the dielectric layer 22 and the semiconductor layer 20, and the trenches 24 extend to a shallower depth into the semiconductor layer 18. The gate windows 26 completely penetrate the dielectric layer 22 and the semiconductor layer 20 to reach the semiconductor layer 18. The trenches 24 have a length L in the longitudinal direction, and the gate windows have a width w1 in the longitudinal direction.

[0044] Reference Figure 3 、 Figure 4 、 Figure 4A wherein like reference numerals identify Figure 1 、 Figure 2 、 Figure 2A like features in

[0045] The gate electrode 30 is formed in the gate windows 26 and on portions of the trenches 24 that are laterally disposed between the gate windows 26. The portion of the gate electrode 30 within the gate window 26 is directly on the conformal dielectric layer 28 on the semiconductor layer 20. The gate electrode 30 also slightly overlaps the strip 16 adjacent to the gate window 26. The gate electrode 30 may be composed of a metal (such as a metal nitride) and may be patterned using photolithography and etching processes to define its shape. The gate electrode 30 is indirectly on the semiconductor layer 18 with the conformal dielectric layer 28 as an intermediate coating to prevent direct contact. The portion of the conformal dielectric layer 28 located between the gate electrode 30 and the semiconductor layers 18, 20 provides the gate dielectric layer.

[0046] In addition to completely filling the gate windows 26, the gate electrode 30 only partially fills the trenches 24. The gate electrode 30 has a gap within each trench 24 between its opposite ends 25, 27 of the trench 24. Specifically, the gate electrode 30 includes an edge 29 and an edge 31 opposite to the edge 29. The edge 31 of the portion of the gate electrode 30 within each trench 24 has a gap G from the end 27 of each trench 24. The edge 29 of the portion of the gate electrode 30 within each trench 24 also has a gap from the end 25 of each trench 24.

[0047] The source / drain regions 32, 34 are formed by patterning openings using photolithography and etching processes in the dielectric layer 22 and depositing a metal (such as a metal nitride), and the metal can be patterned using photolithography and etching processes. The source / drain regions 32, 34 can directly contact the semiconductor layer 20. As used herein, the term "source / drain region" refers to a conductive region that can serve as a source or a drain of a high electron mobility transistor. In one embodiment, the source / drain region 32 can provide a source in the structure 10, and the source / drain region 34 can provide a drain in the structure 10.

[0048] Reference Figure 5 、 Figure 6 、 Figure 6A wherein, like reference numerals identify Figure 3 、 Figure 4 、 Figure 4ASimilar features in. In a subsequent manufacturing stage of the processing method, an insulating region 36 is formed at the semiconductor layers 18, 20, near the end 27 of each trench 24, and thus is formed between the source / drain region 34 and the portion of the gate electrode 30 within the trench 24. The insulating region 36 may extend or penetrate the interface 19 between the semiconductor layer 18 and the semiconductor layer 20. The lower portion of each insulating region 36 is located in the semiconductor layer 18, the upper portion of each insulating region 36 is located in the semiconductor layer 20, and the interface 19 is located between different portions of each insulating region 36. In one embodiment, the insulating region 36 may extend to a depth d2, where the depth d2 is greater than the depth d1 of the bottom of the trench 24. Thus, the lower portion of each insulating region 36 may be located below the gate electrode 30 relative to the semiconductor substrate 12. The semiconductor layer 18 is not modified at a depth greater than the depth d2.

[0049] The insulating region 36 may be formed, for example, by an ion implantation process, and an implantation mask 38 determines the implantation location. The implantation mask 38 may include a dielectric material layer such as silicon nitride, and the dielectric material layer may be patterned by photolithography and etching processes to define openings at predetermined positions of the insulating region 36. Alternatively, the implantation mask 38 may be composed of a photoresist, and the photoresist is patterned by photolithography and etching processes to define openings at predetermined positions of the insulating region 36. In an alternative embodiment, the insulating region 36 may be formed by introducing elemental species using a plasma process.

[0050] As indicated by the single-headed arrow, the ion implantation process introduces energetic ions of elemental species, and these elemental species stop in local portions of the semiconductor layer 18 and the semiconductor layer 20 to form the insulating region 36. The ions may be generated from a suitable source gas and implanted using an ion implantation tool under one or more implantation conditions. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the characteristics of the insulating region 36. In one embodiment, the implanted ions may be ions of the elemental species nitrogen. In one embodiment, the implanted ions may be ions of the elemental species fluorine. In one embodiment, the implanted ions may be ions of the elemental species iron. The implanted portions of the dielectric layer 22 may also be included in the insulating region 36, although it represents local portions of the modified dielectric material rather than the modified semiconductor material, because these portions of the dielectric layer 22 may contain concentrations of implanted atomic species.

[0051] The atomic concentration of the implanted species is sufficient to convert the implanted semiconductor material of the implanted portions of the semiconductor layer 18 and the semiconductor layer 20 within the insulating region 36 into an electrically insulating material. In one embodiment, multiple ion implantation processes may be employed to form the insulating region 36. For example, nitrogen may be implanted at an energy of 20 keV to 30 keV, and the ion dose ranges from per square centimeter (cm2 ) 5 x 10 13 ions up to 1 x 10 per square centimeter 14 ions, implanted with an energy in the range of 40 keV to 50 keV, and an ion dose range of 8 x 10 per square centimeter 13 ions up to 1.5 x 10 per square centimeter 14 ions, and implanted with an energy in the range of 60 keV to 70 keV, and an ion dose range of 5 x 10 per square centimeter 13 ions up to 1 x 10 per square centimeter 14 ions. In the example, the average atomic concentration of the implanted species nitrogen in the semiconductor layers 18, 20 can be in the range of (cm per cubic centimeter 3 ) 5 x 10 18 atoms to 1.5 x 10 19 atoms per cubic centimeter.

[0052] The implantation mask 38 has a thickness and a stopping ability sufficient to prevent the masked area from being implanted. As a result, the masked portions of the semiconductor materials of the semiconductor layers 18, 20 in the strip 16 between the trenches 24 are not altered by the implantation process. Additionally, during implantation, the space between the end 25 of the masked trench 24 and the source / drain region 32 causes the insulating region 36 to form only in a local position adjacent to the end 27 of the trench 24. Thus, the insulating region 36 is surrounded by the semiconductor materials of the semiconductor layers 18, 20 on at least three sides, and the semiconductor materials are not altered by the introduction of the implanted atomic species. After implantation, the implantation mask 38 can be removed.

[0053] Each insulating region 36 is laterally located at a position between the end 27 of one of the trenches 24 and the source / drain region 34. The non-implanted portions of the semiconductor layers 18, 20 and the intact portions of the interface 19 are located between each insulating region 36 and the source / drain region 34. In one embodiment, the trenches 24 and the insulating regions 36 can have the same or approximately the same width w2, in which case the non-implanted portions of the semiconductor layers 18, 20 located between adjacent insulating regions 36 have the same width as the strip 16. In one embodiment, the insulating region 36 can overlap with the end 27 of the trench 24.

[0054] Compared with the unimplanted volume of the semiconductor material of the semiconductor layers 18, 20, the insulating regions 36 provide a local volume of semiconductor material with low conductivity in the semiconductor layers 18, 20. During device operation, each insulating region 36 effectively laterally displaces the two-dimensional electron gas from the ends 27 of its associated trench 24 and the edges 31 of the gate electrode 30 within each trench 24. Since the interface 19 between the semiconductor layers 18, 20 is interrupted, and the high electric field occurring near the edges 31 of the gate electrode 30 is laterally shifted towards the source / drain regions 34 and away from the edges 31. The lateral displacement of the two-dimensional electron gas reduces the sensitivity of the conformal dielectric layer 28 at the end 27 of each trench 24 near the edge 31 of the gate electrode 30 to dielectric breakdown, which improves the reliability of the gate. The insulating regions 36 can be added without reducing the ON-resistance of the high electron mobility transistor because the local ion implantation regions of the semiconductor layers 28, 30 near the ends 27 of the trenches 24 are generally non-conductive.

[0055] Reference Figure 7 , wherein like reference numerals represent Figure 6 like features in, an alternative embodiment of the present invention, the gate electrode 30 can be modified to completely occupy the space between the end 27 of each trench 24 and the gate window 26, such that the edge 31 of the gate electrode 30 directly contacts the dielectric layer 22 at the end 27 of each trench 24, and the gap between the end 27 and the edge 31 is eliminated. The gate electrode 30 can also include a portion that extends beyond the end 27 of each trench 24 and protrudes from the dielectric layer 22 to define a field plate. In one embodiment, the insulating regions 36 can be formed before forming the gate electrode 30 because the gate electrode 30 overlaps the dielectric layer 22 adjacent to the end 27 of the trench 24.

[0056] Reference Figure 8 , Figure 8A , wherein like reference numerals represent Figure 6 , Figure 6A like features in, according to an alternative embodiment of the present invention, the structure 10 can omit the trenches 24 and include a single gate window 26 that is laterally disposed between the source / drain regions 32 and the source / drain regions 34. The edge 31 of the gate electrode 30 directly contacts the dielectric layer 22 at the side edge of the gate window 26. The insulating regions 36 are located near different portions of the gate electrode 30 and the source / drain regions 34, and the unmodified strips 16 of the semiconductor layers 18, 20 are located between adjacent insulating regions 36.

[0057] Reference Figure 9 , Figure 9A , wherein like reference numerals represent Figure 6 , Figure 6ASimilar features in. According to an alternative embodiment of the present invention, the structure 10 may omit the trench 24 and be configured as a planar high electron mobility transistor. An additional layer 40 of a compound semiconductor material (e.g., p-type gallium nitride or p-type aluminum gallium nitride) may be located between the gate electrode 30 and the dielectric layer 22. As shown by the dashed line, a portion of each insulating region 36 may also be located in the layer 40. The insulating region 36 is located between different portions of the gate electrode 30 and the source / drain regions 34. Unmodified strips 16 of the semiconductor layers 18, 20 are located between adjacent insulating regions 36.

[0058] The above method is used to manufacture integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in a packaged form. The chips may be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product or a final product. The final product may be any product that includes an integrated circuit chip, such as a computer product or a smartphone having a central processor.

[0059] Terms modified by approximate language as cited herein, such as "about", "approximately", and "substantially", are not limited to the specified exact value. The approximate language may correspond to the precision of the instrument used to measure the value and may represent + / - 10% of the specified value unless otherwise determined by the precision of the instrument.

[0060] References herein to terms such as "vertical", "horizontal", etc. for injection are by way of example rather than by way of limitation to establish a reference framework. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to a direction perpendicular to the horizontal direction as just defined. The term "lateral" refers to a direction in the horizontal plane.

[0061] A feature "connected" or "coupled" to another feature may be directly connected or coupled to another feature or coupled to another feature, or there may be one or more intermediate features. If there are no intermediate features, the feature may be "directly connected" or "directly coupled" to another feature or coupled to another feature. If there is at least one intermediate feature, the feature may be "indirectly connected" or "indirectly coupled" to another feature. A feature located on or in contact with another feature may be directly located on or in direct contact with another feature, or conversely, there may be one or more intermediate features. If there are no intermediate features, a feature may be directly located on or in direct contact with another feature. If there is at least one intermediate feature, a feature may be indirectly located on or in indirect contact with another feature.

[0062] The description of the various embodiments of the present invention is provided for illustrative purposes but is not intended to be exhaustive or limiting to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable a person of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, characterized in that, Comprising: A high electron mobility transistor, which includes a first semiconductor layer, a second semiconductor layer adjacent to the first semiconductor layer along an interface, and source / drain regions; A first trench and a second trench, which are located in the first semiconductor layer and the second semiconductor layer, wherein the second trench is adjacent to the first trench; A gate window, which is located in the first semiconductor layer, wherein the gate window connects the first trench and the second trench; A gate electrode, which is located in the first trench, the second trench, and the gate window; and A first insulating region and a second insulating region, which are located in the first semiconductor layer and the second semiconductor layer, wherein the first insulating region extends through the interface at a first position laterally between the gate electrode and the source / drain regions, and the second insulating region extends through the interface at a second position laterally between the gate electrode and the source / drain regions, wherein the first insulating region is located between the first trench and the source / drain regions, and the second insulating region is located between the second trench and the source / drain regions, wherein the first semiconductor layer and the second semiconductor layer include respective portions that are laterally located between the first insulating region and the second insulating region.

2. The semiconductor structure according to claim 1, wherein, The first semiconductor layer is composed of a first semiconductor material, the second semiconductor layer is composed of a second semiconductor material having a composition different from that of the first semiconductor material, and the first insulating region includes a portion of the first semiconductor material and a portion of the second semiconductor material containing atoms of one elemental species.

3. The semiconductor structure according to claim 2, wherein The first semiconductor material is aluminum gallium nitride, the second semiconductor material is gallium nitride, and the elemental species is fluorine.

4. The semiconductor structure according to claim 2, characterized in that, The first semiconductor material is aluminum gallium nitride, the second semiconductor material is gallium nitride, and the elemental species is fluorine, nitrogen, or iron.

5. The semiconductor structure according to claim 1, characterized in that, The first trench includes an end, and the first insulating region is located near the end of the first trench.

6. The semiconductor structure according to claim 5, wherein, The structure further includes: A conformal dielectric layer, which is located on the first semiconductor layer and the second semiconductor layer at the end of the first trench, and the conformal dielectric layer is located between the first insulating region and the end of the first trench, wherein the gate electrode includes a first portion located in the first trench, and there is a gap between the first portion of the gate electrode and the conformal dielectric layer at the end of the first trench.

7. The semiconductor structure according to claim 5, wherein The structure further includes: A conformal dielectric layer, which is located on the first semiconductor layer and the second semiconductor layer at the end of the first trench, and the conformal dielectric layer is located between the first insulating region and the end of the first trench, wherein the gate electrode includes a first portion located in the first trench, and the first portion of the gate electrode is in direct contact with the conformal dielectric layer at the end of the first trench.

8. The semiconductor structure according to claim 1, wherein, The gate electrode includes a first portion located in the first trench, the first trench extends through the interface into the second semiconductor layer to a first depth through the first semiconductor layer, the first insulating region extends into the second semiconductor layer to a second depth, and the second depth is greater than the first depth.

9. A method for forming a semiconductor structure, characterized in that, Comprising: Forming a high electron mobility transistor, which includes a first semiconductor layer and a second semiconductor layer adjacent to the first semiconductor layer along an interface; A first trench and a second trench are formed in the first semiconductor layer and the second semiconductor layer, wherein the second trench is adjacent to the first trench; A gate window is formed in the first semiconductor layer, wherein the gate window connects the first trench and the second trench; A gate electrode of the high electron mobility transistor is formed, wherein the gate electrode is located in the first trench, the second trench and the gate window; Source / drain regions of the high electron mobility transistor are formed; and A first insulating region and a second insulating region are formed in the first semiconductor layer and the second semiconductor layer; wherein the first insulating region extends through the interface at a first position laterally between the gate electrode and the source / drain regions, and the second insulating region extends through the interface at a second position laterally between the gate electrode and the source / drain regions, wherein the first insulating region is located between the first trench and the source / drain region, and the second insulating region is located between the second trench and the source / drain region, wherein the first semiconductor layer and the second semiconductor layer include respective portions disposed laterally between the first insulating region and the second insulating region.

10. The method according to claim 9, characterized in that, Forming the first insulating region in the first semiconductor layer and the second semiconductor layer includes: Introducing an elemental species into a portion of the first semiconductor layer and a portion of the second semiconductor layer.

11. The method according to claim 10, wherein The first semiconductor layer contains aluminum gallium nitride, the second semiconductor layer contains gallium nitride, and the elemental species is fluorine, nitrogen or iron.

12. The method according to claim 9, wherein The trench includes an end, the first insulating region is located near the end of the trench, and the gate electrode includes a portion located in the trench.

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