3-D NAND die

Abstract

A method of manufacturing a memory device is provided. The method reduces the thickness of a first layer and increases the thickness of a second layer. A semiconductor device is described as having: a film stack in a first portion of the device, including alternating nitride layers and a second layer, the alternating nitride layers and the second layer of the film stack having a nitride:oxide thickness ratio (N f ∶O f ); and a memory stack in a second portion of the device, including alternating word line layers and a second layer, the alternating word line layers and the second layer of the memory stack having a word line:oxide thickness ratio (W m ∶O m ), where 0.1(W m ∶O m ) < N f ∶O f < 0.95(W m ∶O m ).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatuses for manufacturing such electronic devices. More specifically, embodiments of the present disclosure provide methods for forming 3D-NAND die stacks. Background Art

[0002] Semiconductor technology has advanced rapidly, and as technology has progressed, device sizes have been reduced to provide faster processing and storage per unit of space. In NAND devices, the string current needs to be high enough to obtain sufficient current to distinguish ON and OFF cells. The string current depends on the carrier mobility, which is increased by enlarging the grain size of the silicon channel.

[0003] Existing 3D-NAND memory stacks with alternating oxide and nitride layers require a replacement metal gate (RMG) process to construct word lines. The silicon nitride layer is mechanically unstable because a large amount of residual hydrogen is left. The hydrogen adversely affects pattern deformation and / or process controllability or the memory via etching process.

[0004] Therefore, there is a need in the art for 3D-NAND devices with lower residual hydrogen levels. Additionally, there is a need in the art for methods and apparatuses for forming 3D-NAND devices. Summary of the Invention

[0005] One or more embodiments of the present disclosure relate to methods of forming memory devices. In one embodiment, a method of forming an electronic device includes: removing one or more first layers from a film stack including alternating second layers and first layers, the one or more first layers being removed from a first side of the first layer to leave an opening defined on a second side by one or more films including a polysilicon layer, the opening having a first thickness; trimming an adjacent second layer through the opening to increase the thickness of the opening from the first thickness to a second thickness and to reduce a first oxide layer thickness to a second oxide layer thickness smaller than the first oxide layer thickness; and depositing a word line replacement material in the opening.

[0006] Additional embodiments of the present disclosure relate to semiconductor memory devices. In one embodiment, a semiconductor memory device includes: a film stack in a first portion of the device, including alternating nitride layers and oxide layers, the alternating nitride layers and oxide layers of the film stack having a nitride:oxide thickness ratio (N f :O f); and a memory stack in a second portion of the device, the memory stack including alternating word line layers and oxide layers, the alternating word line layers and oxide layers of the memory stack having a word line:oxide thickness ratio (W m :O m ), where 0.1 (W m :O m ) < N f :O f < 0.95 (W m :O m ).

[0007] Additional embodiments of the present disclosure relate to a processing tool. In one embodiment, a processing tool includes: a central transfer station including a robotic arm configured to move wafers; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separate from the processing areas of adjacent processing stations, the plurality of processing stations including an oxide layer thinning chamber and a word line deposition chamber; and a controller connected to the central transfer station and the plurality of processing stations, the controller configured to activate the robotic arm to move the wafer between the processing stations and control the processes occurring in each of the processing stations. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more particular description of the features briefly summarized above, reference may be made to the embodiments, some of which are illustrated in the drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit other equivalent embodiments. The embodiments described herein are shown by way of example and not limitation in the figures, where like reference numerals indicate similar elements.

[0009] Figure 1 A process flow diagram depicting one embodiment of a method of forming a memory device in accordance with embodiments described herein;

[0010] Figure 2 A cross-sectional view of a device having a memory stack in accordance with one or more embodiments;

[0011] Figure 3 A cross-sectional view of a substrate after forming a stepped pattern of a memory stack in accordance with one or more embodiments;

[0012] Figure 4A A cross-sectional view of a substrate after forming memory holes in accordance with one or more embodiments;

[0013] Figure 4B shows a cross-sectional view of region 103 of a substrate according to one or more embodiments; Figure 4A

[0014] Figure 5A shows a cross-sectional view of a substrate after selectively oxidizing a nitride layer according to one or more embodiments;

[0015] Figure 5B shows an enlarged view of region 101 according to one or more embodiments;

[0016] Figure 6A shows a cross-sectional view of a substrate according to one or more embodiments;

[0017] Figure 6B shows an enlarged view of region 101 according to one or more embodiments;

[0018] Figure 7 shows a cross-sectional view of a substrate after forming a bit line pad according to one or more embodiments;

[0019] Figure 8 shows a cross-sectional view of a substrate after depositing an interlayer dielectric according to one or more embodiments;

[0020] Figure 9 shows a cross-sectional view of a substrate after slit patterning according to one or more embodiments;

[0021] Figure 10 shows a cross-sectional view of a substrate after removing a sacrificial layer according to one or more embodiments;

[0022] Figure 11 shows a cross-sectional view of a substrate according to one or more embodiments;

[0023] Figure 12 shows a cross-sectional view of a substrate according to one or more embodiments;

[0024] Figure 13A shows a cross-sectional view of a substrate after etching a nitride according to one or more embodiments;

[0025] Figure 13B shows Figure 13A an enlarged view of region 201;

[0026] Figure 14A shows a cross-sectional view of a substrate according to one or more embodiments;

[0027] Figure 14B shows Figure 14A an enlarged view of region 201;

[0028] Figure 15A shows a cross-sectional view of a substrate in accordance with one or more embodiments;

[0029] Figure 15B shows Figure 15A an enlarged view of region 201;

[0030] Figure 16 shows a cross-sectional view of a substrate in accordance with one or more embodiments;

[0031] Figure 17 shows a cross-sectional view of a substrate in accordance with one or more embodiments;

[0032] Figure 18 shows a cross-sectional view of a substrate in accordance with one or more embodiments; and

[0033] Figure 19 shows a cluster tool in accordance with one or more embodiments. DETAILED DESCRIPTION

[0034] Before describing several exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0035] Existing 3D-NAND memory stacks having alternating oxide and nitride layers require a replacement metal gate (RMG) process to build word lines. Since a large amount of residual hydrogen is left, the silicon nitride layer is mechanically unstable. Hydrogen adversely affects pattern deformation and / or process controllability or the memory via etch process. Accordingly, embodiments of the present disclosure provide methods of reducing the thickness of the nitride layer and increasing the thickness of the oxide layer. Thus, an oxide / nitride die of one or more embodiments can achieve a desired thickness of the oxide / nitride die with a reduced SiN thickness and an increased oxide thickness. In one or more embodiments, the alternating layers are not limited to alternating layers of nitride and oxide, but may include alternating layers of a first material and a second material.

[0036] To control the surface between polysilicon and metal, metal deposition and other processes may be performed in an isolation environment (e.g., a cluster processing tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system having associated process modules to implement the methods.

[0037] Figure 1FIG. 0 shows a flow chart of an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 may include any or all of the processes shown. Additionally, for some portions, the order of the individual processes may be different. Without departing from the present disclosure, method 10 may begin with any one of the recited processes. Referring to Figure 1 , at operation 15, a memory stack is formed. At operation 20, a word line ladder is formed in the memory stack. At operation 25, the memory hole channels are patterned into the word line ladder. At operation 30, optionally, the first layer (e.g., a nitride layer) may be selectively oxidized through the memory hole channels. At operation 35, a transistor layer is deposited. At operation 40, bit line pads are formed. At operation 45, an interlayer dielectric is deposited. At operation 50, the memory ladder is slit patterned. At operation 55, the sacrificial layer is removed. At operation 60, a semiconductor material is deposited. At operation 65, the first layer (e.g., a nitride layer) is removed. At operation 70, the second layer (e.g., an oxide layer) is trimmed. At operation 75, a word line replacement material is deposited. At operation 80, the slit is filled, and at operation 85, word line contacts are formed.

[0038] Figures 2 to 18 FIG. shows a portion of a memory device 100 following the process flow shown for method 10 in Figure 1 .

[0039] Figure 2 FIG. shows an initial or starting memory stack of an electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, Figure 2 the electronic device 100 shown is formed in layers on a bare substrate 105, as shown. Figure 2 The electronic device of consists of a substrate 105, a semiconductor layer 110, a sacrificial layer 120, a memory stack 130, and an oxide layer 140.

[0040] The substrate 105 may be any suitable material known to those skilled in the art. As used in this specification and the appended claims, the term "substrate" refers to the surface or a portion of the surface on which a process acts. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, a reference to a substrate may refer only to a portion of the substrate. Additionally, a reference to depositing on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0041] As used herein, "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during a manufacturing process. For example, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material (such as metals, metal nitrides, metal alloys, and other conductive materials), depending on the application. The substrate includes, but is not limited to, semiconductor wafers. The substrate can be exposed to a pre-treatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, when a film / layer or a portion of a film / layer has been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0042] The semiconductor layer 110 is located on the substrate 105. The semiconductor layer 110 can also be referred to as a common source line. The semiconductor layer 110 can be formed by any suitable technique known to those skilled in the art and can be made of any suitable material including, but not limited to, polysilicon (polycrystalline Si). In some embodiments, the semiconductor layer 110 is a common source line made of a conductive or semiconductor material.

[0043] The sacrificial layer 120 is formed on the semiconductor layer 110 and can be made of any suitable material. In some embodiments, the sacrificial layer 120 is removed and replaced in a subsequent process. In some embodiments, the sacrificial layer 120 is not removed and remains within the memory device 100. In this case, the term "sacrificial" has an extended meaning that includes a permanent layer and can be referred to as a conductive layer. In the illustrated embodiment, as further described below, in operation 55, the sacrificial layer 120 is removed. In one or more embodiments, the sacrificial layer 120 includes a material that can be selectively removed relative to the adjacent semiconductor layer 110 and the oxide layer 132.

[0044] A memory stack 130 is formed on a sacrificial layer 120. The memory stack 130 in the illustrated embodiment includes a plurality of alternating second layers 132 and first layers 134. In one or more embodiments, the first layer 134 includes a nitride layer, and the second layer 132 includes an oxide layer. In some embodiments, the memory stack 130 includes a non-replaceable gate, such as alternating oxide and polysilicon (OP), or oxide and metal, or oxide and sacrificial layer. The first layer 134 includes a material that is etch-selective with respect to the second layer 132 such that the first layer 134 can be removed without substantially affecting the second layer 132. In one or more embodiments, the first layer 134 includes silicon nitride. In one or more embodiments, the second layer 132 includes silicon oxide.

[0045] The individual alternating layers can be formed to any suitable thickness. In some embodiments, the thickness of each second layer 132 is approximately equal. In one or more embodiments, each second layer 132 has a first second layer thickness. In some embodiments, the thickness of each first layer 134 is approximately equal. As used in this regard, approximately equal thicknesses are within + / - 5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second layer 132 and the first layer 134. The thickness of the silicon layer can be relatively thin compared to the layer thicknesses of the second layer 132 or the first layer 134. In one or more embodiments, the first layer 134 has a thickness in the range from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the nitride layer 134 has a thickness in the range from about 0.5 nm to about 40 nm.

[0046] Referring Figure 3 , at operation 20 of method 10, a stepped structure 131 is formed. The stepped structure 131 exposes the top surface 135 of the second layer 132. The top surface 135 can be used to provide space for word line contacts to be formed, as described below. A suitable fill material 137 can be deposited to occupy the space outside the stepped structure 131. Those skilled in the art will understand that the suitable fill material 137 can be any material that prevents electrical short circuits between adjacent word lines. In the stepped structure 131, each word line has a smaller width than the word line below it (shown from left to right in the figures). The use of relative terms such as "above" and "below" should not be construed as limiting the scope of the present disclosure to a physical orientation in space.

[0047] Referring Figure 4A and Figure 4B, at operation 25, a memory via channel 150 is opened through the memory stack 130. In some embodiments, opening the memory via channel 150 includes etching through the oxide layer 140, the memory stack 130, the sacrificial layer 120, and into the semiconductor layer 110. Referring to Figure 4B , which is an enlarged view of region 103, the memory via channel 150 has sidewalls that extend through the memory stack 130, the exposed surface 138 of the second layer 132, and the surface 139 of the first layer 134.

[0048] The sacrificial layer 120 has a surface 122 that is exposed as the sidewall of the memory via channel 150. The memory trench via 150 extends a distance into the semiconductor layer 110 such that the sidewall surface 112 and the bottom 114 of the memory via channel 150 are formed within the semiconductor layer 110. The bottom 114 of the memory via channel 150 can be formed at any point within the thickness of the semiconductor layer 110. In some embodiments, the memory via channel 150 extends into the semiconductor layer 110 by a thickness in the range from about 10% to about 90% of the thickness of the semiconductor layer 110, or from about 20% to about 80% of the thickness, or from about 30% to about 70% of the thickness, or from about 40% to about 60% of the thickness. In some embodiments, the memory via channel 150 extends into the semiconductor layer 110 by a distance greater than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70%, or 80% of the thickness of the semiconductor layer 110.

[0049] Figure 5A Operation 30 is shown, in which the first layer 134 (e.g., a nitride layer) is selectively oxidized through the memory via channel 150. In one or more embodiments, the selective oxidation of the first layer 134 (e.g., a nitride layer) is optional. Figure 5B is Figure 5A an enlarged view of region 101. In one or more embodiments, the first layer 134 (e.g., a nitride layer) is selectively oxidized by in situ steam generation (ISSG) oxidation or radical plasma oxidation (RPO) at a temperature in the range from about 700 °C to about 900 °C in an atmosphere of hydrogen (H2) gas and oxygen (O2) gas at ambient pressure. The ISSG oxide layer 155 is formed adjacent to the memory via channel 150 in the first layer 134 (e.g., a nitride layer). Without being bound by theory, it is believed that the ISSG oxide layer 155 protects the blocking oxide layer 176 from etching during the thermal phosphorous pullback of the nitride. In one or more embodiments, the ISSG oxide layer 155 or the RPO oxide layer 155 has a thickness of about 2 nm.

[0050] Figure 6A and Figure 6BOperation 35 is shown, in which a transistor layer 165 is conformally deposited into a memory hole channel 150 adjacent to a second layer 132 and an ISSG oxide layer 155 or an RPO oxide layer 155. The transistor layer 165 can be formed by any suitable technique known to those skilled in the art. In some embodiments, the transistor layer 165 is formed by a conformal deposition process. In some embodiments, the transistor layer 165 is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0051] In one or more embodiments, the deposition of the transistor layer 165 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer having a thickness that is substantially the same everywhere (e.g., at the top, middle, and bottom of the sidewall and on the bottom of the memory hole channel 150). The variation in the thickness of a substantially conformal layer is less than or equal to about 5%, 2%, 1%, or 0.5%.

[0052] Referring to Figure 6B , which is an enlarged view of region 101, in one or more embodiments, the transistor layer 165 includes a barrier oxide layer 176 (or a first oxide layer 176), a nitride well layer 174 on the first oxide layer 176, a second oxide layer 172 (or a tunneling oxide layer 172) on the nitride well layer 174, and a polysilicon layer 170 in the memory hole channel 150 on the second oxide layer 172. In one or more embodiments, the barrier oxide layer 176, the charge trap nitride (SiN) layer 174, and the tunneling oxide layer 172 are deposited on the sidewalls of the memory hole channel 150 in the memory hole channel 150 or on the semiconductor layer 110.

[0053] In one or more embodiments, a polysilicon (polycrystalline Si) layer 170 is formed adjacent to the transistor layer 165 in the memory hole channel 150. The polysilicon layer 170 can be formed directly on the transistor layer 165. The polysilicon layer 170 can be deposited by any suitable technique known to those skilled in the art, including but not limited to atomic layer deposition and chemical vapor deposition. In some embodiments, the polysilicon layer 170 is deposited as a conformal layer such that the polysilicon layer forms on the sidewalls and exposed surfaces 138, 139, 122, 112, and bottom 114 (see Figure 4B ).

[0054] The polysilicon layer 170 may have any suitable thickness, depending on, for example, the dimensions of the memory via channel 150. In some embodiments, the polysilicon layer 170 has a thickness in the range from about 0.5 nm to about 50 nm, or from about 0.75 nm to about 35 nm, or from about 1 nm to about 20 nm. In some embodiments, the polysilicon layer 170 is a continuous film. In one or more embodiments, a conformal deposition on the tunnel oxide layer 172 is utilized to form the polysilicon layer 170 in a macaroni-type, and the polysilicon layer 170 has a thickness in the range from about 1 nm to about 20 nm. Then, the memory via channel 150 is filled with the dielectric material 160.

[0055] Figure 7 Operation 40 of method 10 is shown, where the bit line pad 180 is formed in the polysilicon (polycrystalline Si) layer 160. The bit line pad 180 can be any suitable material known to those skilled in the art, including but not limited to polysilicon.

[0056] Figure 8 Operation 45 of method 10 is shown, where the interlayer dielectric 185 is deposited on the top surfaces of the oxide layer 140 and the bit line pad 180. The interlayer dielectric (ILD) 185 can be deposited by any suitable technique known to those skilled in the art. The interlayer dielectric 185 can include any suitable material known to those skilled in the art. In one or more embodiments, the interlayer dielectric 185 is a low-k dielectric, including but not limited to materials such as, for example, silicon dioxide, silicon oxide, carbon-doped oxide ("CDO") (e.g., carbon-doped silicon dioxide), porous silicon dioxide (SiO2), silicon nitride (SiN), or any combination thereof. Although the term "silicon oxide" may be used to describe the interlayer dielectric 185, those skilled in the art will recognize that the present disclosure is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe materials having any suitable stoichiometric ratio of silicon and oxygen atoms. The same is true for the other materials listed in the present disclosure (e.g., silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and the like).

[0057] Figure 9 Operation 50 of method 10 is shown, where the slit patterned memory stack 130 is patterned to form a slit pattern opening 190 extending from the top surface of the interlayer dielectric 185 to the substrate 105.

[0058] Figure 10 Operation 55 of method 10 is shown, where the sacrificial layer 120 and a portion 165 of the polysilicon layer 160 are removed. The sacrificial layer 120 can be removed by any suitable technique known to those skilled in the art, including but not limited to selective etching.

[0059] Figure 11 Illustrates operation 60 of method 10, where a semiconductor material (e.g., nitride and polysilicon filler) 195 is deposited in slit pattern opening 190. The semiconductor material can be any suitable material known to those skilled in the art.

[0060] Figure 12 Illustrates the removal of semiconductor material 195 from the sidewalls of slit pattern opening 190. Without being bound by theory, slit pattern opening 190 should be larger than the height of the common source line 110 (semiconductor layer 110) such that there can be an opening in slit pattern opening 190 for removing semiconductor material 195 from the sidewalls. In one or more embodiments, semiconductor material 195 is removed from the sidewalls of slit pattern opening 190 by an isotropic etching process (e.g., wet etching using TMAH or the like).

[0061] Figure 13A and Figure 13B Illustrates operation 65 of method 10, where one or more of the first layers 134 (e.g., nitride layers) are removed to form opening 210 and slit pattern opening 190. In one or more embodiments, opening 210 has a first thickness t1 in the range from about 1 nm to about 50 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, about 30 nm, about 32 nm, about 35 nm, about 37 nm, about 40 nm, about 42 nm, about 45 nm, about 47 nm, about 50 nm. Figure 13B is Figure 13A An enlarged view of a portion 201 of the substrate in. In one or more embodiments, when one or more of the first layers 134 (e.g., nitride layers) are removed, a first side of the first layer 134 (e.g., nitride layer) is exposed to slit pattern opening 190, and the first side of the first layer 134 (e.g., nitride layer) is exposed to an etchant through slit pattern opening 190.

[0062] Figure 14A and Figure 14BIllustrates operation 70 of method 10, where the second layer 132 (e.g., oxide layer) is trimmed through opening 210 to increase the thickness of opening 210 from a first thickness t1 to a second thickness t2. In one or more embodiments, the second thickness t2 is approximately 50% to about 75% greater than the first thickness t1. In one or more embodiments, the second thickness t2 is approximately 50%, or about 55%, or about 60%, or about 65%, or about 70%, or about 75% greater than the first thickness t1. In one or more embodiments, when trimming the second layer 132 (e.g., oxide layer), the thickness of the second layer 132 is reduced to a second thickness of the second layer, and the second thickness of the second layer is less than the first thickness of the second layer. In one or more embodiments, the second layer 132 (e.g., oxide layer) of the memory stack 130 has an average thickness, i.e., the second thickness of the second layer 132, which ranges from about 5 nm to about 30 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the oxide layer 132 of the memory stack 130 has an average thickness, i.e., the second oxide layer thickness, which ranges from about 5 nm to about 30 nm, including about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.

[0063] In one or more embodiments, the second layer 132 (e.g., oxide layer) is trimmed by exposing the second layer 132 to a fluorine-based gas-phase dry cleaning process or a diluted hydrogen fluoride (HF) solution via the slit pattern opening 190. In one or more embodiments, trimming the second layer 132 includes exposing the second layer 132 to a fluorine-based gas-phase dry cleaning chemistry or a diluted hydrogen fluoride (HF) chemistry via the slit pattern opening 190. Without being bound by theory, it is believed that since dry chemical etching does not involve any liquid, oxide collapse due to surface tension during oxide removal can be avoided. When trimming the second layer 132 (e.g., oxide layer), the thickness of the second layer 132 (e.g., oxide layer) is reduced, and the thickness of opening 210 increases / widens. In one or more embodiments, the thickness of opening 210 increases from a first thickness t1 to a second thickness t2, and the thickness of the second layer 132 (e.g., oxide layer) is reduced to a second thickness of the second layer 132 that is less than the first thickness of the second layer 132.

[0064] Figure 15A and Figure 15BIllustrates operation 75 of method 10, where an aluminum oxide layer 215 and a word line replacement material 225 are deposited in opening 210. Figure 15B is Figure 15A an enlarged view of portion 201 of the device. In one or more embodiments, the word line replacement material 225 includes a nitride liner 220 (e.g., titanium nitride, tantalum nitride, or the like) and a bulk metal, the bulk metal including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the bulk metal includes tungsten (W). In other embodiments, the bulk metal layer includes ruthenium (Ru).

[0065] Figure 16 Illustrates operation 80 of method 10, where slit pattern opening 190 is filled with a fill material 230. The fill material 230 can be any suitable material known to those skilled in the art. In one or more embodiments, the fill material 230 includes one or more of a dielectric material or a conductor material. As used herein, the term "dielectric material" refers to a material layer that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric material includes one or more of an oxide, a carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, a carbide, a carbon oxide, a nitride, a nitrogen oxide, a carbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH).

[0066] Figure 17 Illustrates operation 85 of method 10, where word line contacts 235 are formed. The word line contacts 235 extend through the memory stack 130 a distance sufficient to terminate at one of the word lines 225. In one or more embodiments, the word line contacts 235 can include any suitable material known to those skilled in the art. In one or more embodiments, the word line contacts 235 include one or more of a metal, a metal silicide, polysilicon, amorphous silicon, or epitaxial (EPI) silicon. In one or more embodiments, the word line contacts are doped with an N-type dopant or a P-type dopant to reduce contact resistance. In one or more embodiments, the metal of the word line contacts 235 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0067] Figure 18illustrates a semiconductor memory device according to one or more embodiments. The memory device 100 includes: a film stack 120 in a first portion 300 of the device 100, including alternating first layers 134 (e.g., nitride layers) and second layers 132 (e.g., oxide layers), the alternating first layers 134 (e.g., nitride layers) and second layers 132 (e.g., oxide layers) of the film stack 120 having a nitride:oxide thickness ratio (N f ∶O f ). A memory stack 130 is in a second portion 400 of the device 100 and includes alternating word line layers 225 and second layers 132 (e.g., oxide layers), the alternating word line layers 225 and second layers 132 (e.g., oxide layers) of the memory stack 130 having a word line:oxide thickness ratio (W m ∶O m ), where 0.1 (W m ∶O m ) < N f ∶O f < 0.95 (W m ∶O m ). In one or more embodiments, 0.2 (W m ∶O m ) < N f ∶O f < 0.9 (W m ∶O m ). In other embodiments, 0.5 (W m ∶O m ) < N f ∶O f < 0.75 (W m ∶O m ). In one or more embodiments, the first layer 134 (e.g., nitride layer) of the film stack 120 has a thickness in the range from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, W m ∶O m is in the range from about 2.5∶2 to about 3.5∶2.

[0068] In one or more embodiments, the first layer 134 (e.g., a nitride layer) of the film stack 120 has a thickness in the range from about 0.5 to about 50 nm, including the range from about 1 nm to about 50 nm and the range from 1 nm to about 30 nm. In one or more embodiments, the second layer 132 (e.g., an oxide layer) of the memory stack 130 has an average thickness in the range from about 10 nm to about 20 nm.

[0069] In one or more embodiments, a method of forming an electronic device includes: removing one or more first layers from a film stack including alternating second layers and first layers, the first layers being removed from a first side of the first layer to leave an opening defined on a second side by one or more films including a polysilicon layer, the opening having a first thickness; trimming the second layer through the opening to increase the thickness of the opening from the first thickness to a second thickness and to reduce a first second layer thickness to a second oxide layer thickness smaller than the first second layer thickness; and depositing word line replacement material in the opening.

[0070] Additional embodiments of the present disclosure relate to a processing tool 900 for forming the described memory devices and methods, as Figure 19 shown.

[0071] The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Manipulators 925, 935 are positioned within the central transfer stations 921, 931 and are configured to move manipulator blades and wafers to each of the plurality of sides.

[0072] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918 connected to the central transfer station, which are also referred to as processing stations. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chamber can be any suitable chamber, including but not limited to a pre-cleaning chamber, a buffer chamber, a transfer space, a wafer orienter / degassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective oxidation chamber, an oxide layer thinning chamber, or a word line deposition chamber. The specific arrangement of the processing chambers and components can vary according to the cluster tool and should not be considered as limiting the scope of the present disclosure.

[0073] In some embodiments, the cluster tool 900 includes an oxide layer thinning chamber. The oxide layer thinning chamber of some embodiments includes one or more fluorine-based dry cleaning chambers. In some embodiments, the cluster tool 900 includes a pre-cleaning chamber connected to the central transfer station.

[0074] In Figure 19In the illustrated embodiment, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a load chamber 954 and an unload chamber 956 on the front portion 951 of the factory interface 950. Although the load chamber 954 is shown on the left side and the unload chamber 956 is shown on the right side, those skilled in the art will understand that this represents only one possible configuration.

[0075] The size and shape of the load chamber 954 and the unload chamber 956 can vary depending on, for example, the substrates processed in the cluster tool 900. In the illustrated embodiment, the load chamber 954 and the unload chamber 956 are sized to hold a wafer cassette in which a plurality of wafers are positioned.

[0076] The robot 952 is located within the factory interface 950 and is movable between the load chamber 954 and the unload chamber 956. The robot 952 is capable of transferring wafers from a cassette in the load chamber 954 through the factory interface 950 to the load lock chamber 960. The robot 952 is also capable of transferring wafers from the load lock chamber 962 through the factory interface 950 to a cassette in the unload chamber 956. As those skilled in the art will understand, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot for transferring wafers between the load chamber 954 and the load lock chamber 960 and a second robot for transferring wafers between the load chamber 962 and the unload chamber 956.

[0077] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through the load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is positioned. The robot 925 is also referred to as a robot wafer transfer mechanism. The first transfer chamber 921 is centered relative to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 in some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 includes more than one robot wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between the chambers surrounding the first transfer chamber 921. Individual wafers are carried on wafer transfer blades located at the distal end of the first robot mechanism.

[0078] After processing the wafer in the first section 920, the wafer can be transferred to the second section 930 through a pass-through chamber. For example, chambers 922, 924 can be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 can be used, for example, to cryo-cool the wafer before processing in the second section 930, or to allow the wafer to cool or be post-processed before being moved back to the first section 920.

[0079] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component that can control the processing chambers and the robots. For example, the system controller 990 can be a computer including a central processing unit, a memory, suitable circuitry, and a storage device.

[0080] The process can generally be stored as a software program in the memory of the system controller 990, and the software program, when executed by a processor, causes the processing chamber to perform the processes of the present disclosure. The software program can also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Thus, the process can be implemented in software and executed using a computer system, can be implemented in hardware (e.g., an application-specific integrated circuit or other type of hardware implementation), or can be implemented as a combination of software and hardware. The software program, when executed by a processor, transforms a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber to perform the process.

[0081] In some embodiments, the system controller 990 has a configuration for controlling a selective oxidation chamber to selectively oxidize a first layer (e.g., a nitride layer) on a wafer at a temperature in the range of from about 400 °C to about 900 °C in an atmosphere of hydrogen (H2) gas and oxygen (O2) gas at ambient pressure. In some embodiments, the controller 990 has a configuration for activating an oxide layer thinning chamber to remove portions of an oxide layer from a wafer using a fluorine-based dry etch in an etch based on a hydrogen fluoride (HF) solution.

[0082] In one or more embodiments, a processing tool includes: a central transfer station including a robot configured to move wafers; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separate from the processing areas of adjacent processing stations, the plurality of processing stations including an oxide layer thinning chamber and a word line deposition chamber; and a controller connected to the central transfer station and the plurality of processing stations, the controller configured to activate the robot to move wafers between the processing stations and control the processes occurring in each of the processing stations.

[0083] Unless otherwise specified herein or clearly contradicted by the context, the terms "a / an" and "the" and similar references used in the context of describing the materials and methods discussed herein (especially in the context of the appended claims) will be understood to cover both the singular and the plural. Unless otherwise specified herein, a statement of a range of values herein is merely intended to be a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise specified herein or clearly contradicted by the context. Unless otherwise claimed herein, the use of any and all examples or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and does not pose a limitation on the scope. The language in the specification should not be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0084] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment," or "in an embodiment" throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Moreover, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0085] Although the present disclosure has been described with reference to specific embodiments, it will be understood that these embodiments merely illustrate the principles and applications of the present disclosure. Those skilled in the art will appreciate that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A method of forming an electronic device, the method comprising: Removing one or more nitride layers from a film stack including alternating oxide layers and nitride layers, the nitride layers being removed from a first side of the nitride layers to leave an opening defined by one or more films including a polysilicon layer on a second side opposite the first side, the one or more films extending in a direction of the stack of the nitride layer and the oxide layer, the opening having a first thickness; Trimming the oxide layer through the opening to increase the thickness of the opening from the first thickness to a second thickness and to reduce the first thickness of the oxide layer to a second thickness of the oxide layer that is less than the first thickness of the oxide layer; And Depositing a word line replacement material in the opening to form a word line having a thickness greater than the first thickness of the opening, thereby forming a memory stack including alternating word lines and the oxide layer; wherein the alternating nitride and oxide layers of the film stack have a f :O f Expressed as nitride:oxide thickness ratio; The alternating word lines and oxide layers of the memory stack have a word line:oxide thickness ratio represented by W m :O m and 0.1x(W m : O m ) <N f : O f <0.95x(W m : O m )。 2. The method of claim 1, wherein the oxide layer comprises silicon oxide and the nitride layer comprises silicon nitride.

3. The method of claim 1, wherein the second thickness of the opening is 50% or more greater than the first thickness of the opening.

4. The method of claim 1, wherein the first thickness of the opening is in the range from 1 nm to 50 nm.

5. The method of claim 1, wherein removing the one or more nitride layers further comprises: Forming a slit pattern opening through the film stack, the first side of the nitride layer being exposed to the slit pattern opening; And Exposing the first side of the nitride layer to an etchant through the slit pattern opening.

6. The method of claim 5, wherein trimming the oxide layer comprises exposing the oxide layer to a fluorine-based vapor dry cleaning chemical or a diluted HF chemical through the slit pattern opening.

7. The method of claim 1, wherein the word line replacement material comprises tungsten.

8. The method of claim 7, wherein the word line replacement material further comprises a titanium nitride liner between the tungsten and the oxide layer.

9. The method of claim 1, further comprising: Forming a memory hole channel through the film stack; Depositing a first oxide channel layer; Depositing a nitride channel layer on the first oxide channel layer; Depositing a second oxide channel layer on the nitride channel layer; and Forming the polysilicon layer in the memory hole channel on the second oxide channel layer.

10. The method of claim 1, further comprising exposing the opening to an in-situ steam process to form an in-situ steam generation (ISSG) oxide layer at the second side of the opening, or to form a radical plasma oxidation (RPO) oxide layer at the second side of the opening.

11. The method of claim 10, wherein the in-situ steam generation (ISSG) oxide layer is formed at a temperature in the range from 700 °C to 900 °C in an atmosphere of hydrogen (H2) gas and oxygen (O2) gas at ambient pressure.

12. The method according to claim 11, wherein while trimming the oxide layer, the oxide layer at the second side of the opening is removed from the second side of the opening.

13. The method according to claim 11, wherein the in-situ steam generated oxide layer or the radical plasma oxidized oxide layer has a thickness of 2 nm.

14. A semiconductor memory device, comprising: A film stack, which is in the first part of the semiconductor memory device, includes alternating nitride layers and oxide layers, and the alternating nitride layers and oxide layers of the film stack have a nitride:oxide thickness ratio represented by N f :O f ; and A memory stack, which is in the second part of the semiconductor memory device, includes alternating word lines and oxide layers. The word lines are formed by depositing word line replacement material. The alternating word lines and oxide layers of the memory stack have a word line:oxide thickness ratio represented by W m :O m . where 0.1x(W m : O m ) < N f : O f <0.95x(W m : O m )。 15. The semiconductor memory device according to claim 14, wherein the nitride layer of the film stack has a thickness in the range from 1 nm to 50 nm.

16. The semiconductor memory device according to claim 14, wherein the oxide layer of the memory stack has an average thickness in the range from 10 nm to 20 nm.

17. The semiconductor memory device according to claim 14, wherein W m : O m is in the range from 2.5:2 to 3.5:

2.

18. A processing tool, comprising: a central transfer station including a robot configured to move wafers; a plurality of processing stations, each processing station being connected to the central transfer station and providing a processing area separate from the processing areas of adjacent processing stations, the plurality of processing stations including an oxide layer thinning chamber and a word line deposition chamber; and a controller connected to the central transfer station and the plurality of processing stations, the controller being configured to activate the robot to move the wafer between the processing stations and control the processes occurring in each of the processing stations, wherein the processes include the method of forming an electronic device according to any one of claims 1 to 13.

19. The processing tool according to claim 18, wherein the oxide layer thinning chamber is a fluorine-based dry cleaning chamber.

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